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Commit 6560491fe5acd2f150853efdd5d9bd714a93374c

Authored by Erik van Luijk
Committed by Andreas Bießmann
1 parent 0c01c3e876
Exists in v2017.01-smarct4x and in 33 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf-6.6.52-2.2.0, emb_lf_v2022.04, emb_lf_v2023.04, emb_lf_v2024.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

arm: at91: at91sam9m10g45ek/corvus remove useless chip select 1 init 

On these boards the DDR is connected to a dedicated controller and not
to chip select 1 of the EBI.

Signed-off-by: Erik van Luijk <evanluijk@interact.nl>
Tested-by: Erik van Luijk <evanluijk@interact.nl>

Showing 2 changed files with 0 additions and 16 deletions Inline Diff

board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
Diff comments   View file @ 6560491
1 /* 1 /*
2 * (C) Copyright 2007-2008 2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian@popies.net> 3 * Stelian Pop <stelian@popies.net>
4 * Lead Tech Design <www.leadtechdesign.com> 4 * Lead Tech Design <www.leadtechdesign.com>
5 * 5 *
6 * SPDX-License-Identifier: GPL-2.0+ 6 * SPDX-License-Identifier: GPL-2.0+
7 */ 7 */
8 8
9 #include <common.h> 9 #include <common.h>
10 #include <asm/io.h> 10 #include <asm/io.h>
11 #include <asm/arch/clk.h> 11 #include <asm/arch/clk.h>
12 #include <asm/arch/at91sam9g45_matrix.h> 12 #include <asm/arch/at91sam9g45_matrix.h>
13 #include <asm/arch/at91sam9_smc.h> 13 #include <asm/arch/at91sam9_smc.h>
14 #include <asm/arch/at91_common.h> 14 #include <asm/arch/at91_common.h>
15 #include <asm/arch/at91_pmc.h> 15 #include <asm/arch/at91_pmc.h>
16 #include <asm/arch/gpio.h> 16 #include <asm/arch/gpio.h>
17 #include <asm/arch/clk.h> 17 #include <asm/arch/clk.h>
18 #include <lcd.h> 18 #include <lcd.h>
19 #include <linux/mtd/nand.h> 19 #include <linux/mtd/nand.h>
20 #include <atmel_lcdc.h> 20 #include <atmel_lcdc.h>
21 #include <atmel_mci.h> 21 #include <atmel_mci.h>
22 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) 22 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
23 #include <net.h> 23 #include <net.h>
24 #endif 24 #endif
25 #include <netdev.h> 25 #include <netdev.h>
26 26
27 DECLARE_GLOBAL_DATA_PTR; 27 DECLARE_GLOBAL_DATA_PTR;
28 28
29 /* ------------------------------------------------------------------------- */ 29 /* ------------------------------------------------------------------------- */
30 /* 30 /*
31 * Miscelaneous platform dependent initialisations 31 * Miscelaneous platform dependent initialisations
32 */ 32 */
33 33
34 #ifdef CONFIG_CMD_NAND 34 #ifdef CONFIG_CMD_NAND
35 void at91sam9m10g45ek_nand_hw_init(void) 35 void at91sam9m10g45ek_nand_hw_init(void)
36 { 36 {
37 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 37 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
38 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 38 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
39 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 39 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
40 unsigned long csa; 40 unsigned long csa;
41 41
42 /* Enable CS3 */ 42 /* Enable CS3 */
43 csa = readl(&matrix->ebicsa); 43 csa = readl(&matrix->ebicsa);
44 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; 44 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
45 writel(csa, &matrix->ebicsa); 45 writel(csa, &matrix->ebicsa);
46 46
47 /* Configure SMC CS3 for NAND/SmartMedia */ 47 /* Configure SMC CS3 for NAND/SmartMedia */
48 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | 48 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
49 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), 49 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
50 &smc->cs[3].setup); 50 &smc->cs[3].setup);
51 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) | 51 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
52 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2), 52 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
53 &smc->cs[3].pulse); 53 &smc->cs[3].pulse);
54 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4), 54 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
55 &smc->cs[3].cycle); 55 &smc->cs[3].cycle);
56 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 56 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
57 AT91_SMC_MODE_EXNW_DISABLE | 57 AT91_SMC_MODE_EXNW_DISABLE |
58 #ifdef CONFIG_SYS_NAND_DBW_16 58 #ifdef CONFIG_SYS_NAND_DBW_16
59 AT91_SMC_MODE_DBW_16 | 59 AT91_SMC_MODE_DBW_16 |
60 #else /* CONFIG_SYS_NAND_DBW_8 */ 60 #else /* CONFIG_SYS_NAND_DBW_8 */
61 AT91_SMC_MODE_DBW_8 | 61 AT91_SMC_MODE_DBW_8 |
62 #endif 62 #endif
63 AT91_SMC_MODE_TDF_CYCLE(3), 63 AT91_SMC_MODE_TDF_CYCLE(3),
64 &smc->cs[3].mode); 64 &smc->cs[3].mode);
65 65
66 writel(1 << ATMEL_ID_PIOC, &pmc->pcer); 66 writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
67 67
68 /* Configure RDY/BSY */ 68 /* Configure RDY/BSY */
69 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); 69 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
70 70
71 /* Enable NandFlash */ 71 /* Enable NandFlash */
72 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 72 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
73 } 73 }
74 #endif 74 #endif
75 75
76 #if defined(CONFIG_SPL_BUILD) 76 #if defined(CONFIG_SPL_BUILD)
77 #include <spl.h> 77 #include <spl.h>
78 #include <nand.h> 78 #include <nand.h>
79 79
80 void at91_spl_board_init(void) 80 void at91_spl_board_init(void)
81 { 81 {
82 /* 82 /*
83 * On the at91sam9m10g45ek board, the chip wm9711 stays in the 83 * On the at91sam9m10g45ek board, the chip wm9711 stays in the
84 * test mode, so it needs do some action to exit test mode. 84 * test mode, so it needs do some action to exit test mode.
85 */ 85 */
86 at91_periph_clk_enable(ATMEL_ID_PIODE); 86 at91_periph_clk_enable(ATMEL_ID_PIODE);
87 at91_set_gpio_output(AT91_PIN_PD7, 0); 87 at91_set_gpio_output(AT91_PIN_PD7, 0);
88 at91_set_gpio_output(AT91_PIN_PD8, 0); 88 at91_set_gpio_output(AT91_PIN_PD8, 0);
89 at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1); 89 at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1);
90 at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1); 90 at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1);
91 91
92 #ifdef CONFIG_SYS_USE_MMC 92 #ifdef CONFIG_SYS_USE_MMC
93 at91_mci_hw_init(); 93 at91_mci_hw_init();
94 #elif CONFIG_SYS_USE_NANDFLASH 94 #elif CONFIG_SYS_USE_NANDFLASH
95 at91sam9m10g45ek_nand_hw_init(); 95 at91sam9m10g45ek_nand_hw_init();
96 #endif 96 #endif
97 } 97 }
98 98
99 #include <asm/arch/atmel_mpddrc.h> 99 #include <asm/arch/atmel_mpddrc.h>
100 static void ddr2_conf(struct atmel_mpddr *ddr2) 100 static void ddr2_conf(struct atmel_mpddr *ddr2)
101 { 101 {
102 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); 102 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
103 103
104 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 104 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
105 ATMEL_MPDDRC_CR_NR_ROW_14 | 105 ATMEL_MPDDRC_CR_NR_ROW_14 |
106 ATMEL_MPDDRC_CR_DQMS_SHARED | 106 ATMEL_MPDDRC_CR_DQMS_SHARED |
107 ATMEL_MPDDRC_CR_CAS_DDR_CAS3); 107 ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
108 108
109 ddr2->rtr = 0x24b; 109 ddr2->rtr = 0x24b;
110 110
111 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */ 111 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
112 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */ 112 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
113 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */ 113 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
114 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */ 114 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */
115 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */ 115 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
116 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/ 116 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
117 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */ 117 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
118 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */ 118 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
119 119
120 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */ 120 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
121 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | 121 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
122 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | 122 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
123 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); 123 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
124 124
125 ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | 125 ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
126 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | 126 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
127 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | 127 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
128 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); 128 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
129 } 129 }
130 130
131 void mem_init(void) 131 void mem_init(void)
132 { 132 {
133 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 133 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
134 struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
135 struct atmel_mpddr ddr2; 134 struct atmel_mpddr ddr2;
136 unsigned long csa;
137 135
138 ddr2_conf(&ddr2); 136 ddr2_conf(&ddr2);
139 137
140 /* enable DDR2 clock */ 138 /* enable DDR2 clock */
141 writel(0x4, &pmc->scer); 139 writel(0x4, &pmc->scer);
142
143 /* Chip select 1 is for DDR2/SDRAM */
144 csa = readl(&mat->ebicsa);
145 csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
146 csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V;
147 writel(csa, &mat->ebicsa);
148 140
149 /* DDRAM2 Controller initialize */ 141 /* DDRAM2 Controller initialize */
150 ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2); 142 ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
151 } 143 }
152 #endif 144 #endif
153 145
154 #ifdef CONFIG_CMD_USB 146 #ifdef CONFIG_CMD_USB
155 static void at91sam9m10g45ek_usb_hw_init(void) 147 static void at91sam9m10g45ek_usb_hw_init(void)
156 { 148 {
157 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 149 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
158 150
159 writel(1 << ATMEL_ID_PIODE, &pmc->pcer); 151 writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
160 152
161 at91_set_gpio_output(AT91_PIN_PD1, 0); 153 at91_set_gpio_output(AT91_PIN_PD1, 0);
162 at91_set_gpio_output(AT91_PIN_PD3, 0); 154 at91_set_gpio_output(AT91_PIN_PD3, 0);
163 } 155 }
164 #endif 156 #endif
165 157
166 #ifdef CONFIG_MACB 158 #ifdef CONFIG_MACB
167 static void at91sam9m10g45ek_macb_hw_init(void) 159 static void at91sam9m10g45ek_macb_hw_init(void)
168 { 160 {
169 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 161 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
170 struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; 162 struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
171 163
172 /* Enable clock */ 164 /* Enable clock */
173 writel(1 << ATMEL_ID_EMAC, &pmc->pcer); 165 writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
174 166
175 /* 167 /*
176 * Disable pull-up on: 168 * Disable pull-up on:
177 * RXDV (PA15) => PHY normal mode (not Test mode) 169 * RXDV (PA15) => PHY normal mode (not Test mode)
178 * ERX0 (PA12) => PHY ADDR0 170 * ERX0 (PA12) => PHY ADDR0
179 * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0 171 * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
180 * 172 *
181 * PHY has internal pull-down 173 * PHY has internal pull-down
182 */ 174 */
183 writel(pin_to_mask(AT91_PIN_PA15) | 175 writel(pin_to_mask(AT91_PIN_PA15) |
184 pin_to_mask(AT91_PIN_PA12) | 176 pin_to_mask(AT91_PIN_PA12) |
185 pin_to_mask(AT91_PIN_PA13), 177 pin_to_mask(AT91_PIN_PA13),
186 &pioa->pudr); 178 &pioa->pudr);
187 179
188 at91_phy_reset(); 180 at91_phy_reset();
189 181
190 /* Re-enable pull-up */ 182 /* Re-enable pull-up */
191 writel(pin_to_mask(AT91_PIN_PA15) | 183 writel(pin_to_mask(AT91_PIN_PA15) |
192 pin_to_mask(AT91_PIN_PA12) | 184 pin_to_mask(AT91_PIN_PA12) |
193 pin_to_mask(AT91_PIN_PA13), 185 pin_to_mask(AT91_PIN_PA13),
194 &pioa->puer); 186 &pioa->puer);
195 187
196 /* And the pins. */ 188 /* And the pins. */
197 at91_macb_hw_init(); 189 at91_macb_hw_init();
198 } 190 }
199 #endif 191 #endif
200 192
201 #ifdef CONFIG_LCD 193 #ifdef CONFIG_LCD
202 194
203 vidinfo_t panel_info = { 195 vidinfo_t panel_info = {
204 .vl_col = 480, 196 .vl_col = 480,
205 .vl_row = 272, 197 .vl_row = 272,
206 .vl_clk = 9000000, 198 .vl_clk = 9000000,
207 .vl_sync = ATMEL_LCDC_INVLINE_NORMAL | 199 .vl_sync = ATMEL_LCDC_INVLINE_NORMAL |
208 ATMEL_LCDC_INVFRAME_NORMAL, 200 ATMEL_LCDC_INVFRAME_NORMAL,
209 .vl_bpix = 3, 201 .vl_bpix = 3,
210 .vl_tft = 1, 202 .vl_tft = 1,
211 .vl_hsync_len = 45, 203 .vl_hsync_len = 45,
212 .vl_left_margin = 1, 204 .vl_left_margin = 1,
213 .vl_right_margin = 1, 205 .vl_right_margin = 1,
214 .vl_vsync_len = 1, 206 .vl_vsync_len = 1,
215 .vl_upper_margin = 40, 207 .vl_upper_margin = 40,
216 .vl_lower_margin = 1, 208 .vl_lower_margin = 1,
217 .mmio = ATMEL_BASE_LCDC, 209 .mmio = ATMEL_BASE_LCDC,
218 }; 210 };
219 211
220 212
221 void lcd_enable(void) 213 void lcd_enable(void)
222 { 214 {
223 at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */ 215 at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */
224 } 216 }
225 217
226 void lcd_disable(void) 218 void lcd_disable(void)
227 { 219 {
228 at91_set_A_periph(AT91_PIN_PE6, 0); /* power down */ 220 at91_set_A_periph(AT91_PIN_PE6, 0); /* power down */
229 } 221 }
230 222
231 static void at91sam9m10g45ek_lcd_hw_init(void) 223 static void at91sam9m10g45ek_lcd_hw_init(void)
232 { 224 {
233 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 225 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
234 226
235 at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */ 227 at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
236 at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */ 228 at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
237 at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */ 229 at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
238 at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */ 230 at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
239 at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */ 231 at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
240 232
241 at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */ 233 at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
242 at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */ 234 at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
243 at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */ 235 at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
244 at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */ 236 at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
245 at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */ 237 at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
246 at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */ 238 at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
247 at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */ 239 at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
248 at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */ 240 at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
249 at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */ 241 at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
250 at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */ 242 at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
251 at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */ 243 at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
252 at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */ 244 at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
253 at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */ 245 at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
254 at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */ 246 at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */
255 at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */ 247 at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
256 at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */ 248 at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
257 at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */ 249 at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
258 at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */ 250 at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
259 at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */ 251 at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
260 at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */ 252 at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
261 at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */ 253 at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
262 at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */ 254 at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */
263 at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */ 255 at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
264 at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */ 256 at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
265 257
266 writel(1 << ATMEL_ID_LCDC, &pmc->pcer); 258 writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
267 259
268 gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE; 260 gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
269 } 261 }
270 262
271 #ifdef CONFIG_LCD_INFO 263 #ifdef CONFIG_LCD_INFO
272 #include <nand.h> 264 #include <nand.h>
273 #include <version.h> 265 #include <version.h>
274 266
275 void lcd_show_board_info(void) 267 void lcd_show_board_info(void)
276 { 268 {
277 ulong dram_size, nand_size; 269 ulong dram_size, nand_size;
278 int i; 270 int i;
279 char temp[32]; 271 char temp[32];
280 272
281 lcd_printf ("%s\n", U_BOOT_VERSION); 273 lcd_printf ("%s\n", U_BOOT_VERSION);
282 lcd_printf ("(C) 2008 ATMEL Corp\n"); 274 lcd_printf ("(C) 2008 ATMEL Corp\n");
283 lcd_printf ("at91support@atmel.com\n"); 275 lcd_printf ("at91support@atmel.com\n");
284 lcd_printf ("%s CPU at %s MHz\n", 276 lcd_printf ("%s CPU at %s MHz\n",
285 ATMEL_CPU_NAME, 277 ATMEL_CPU_NAME,
286 strmhz(temp, get_cpu_clk_rate())); 278 strmhz(temp, get_cpu_clk_rate()));
287 279
288 dram_size = 0; 280 dram_size = 0;
289 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 281 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
290 dram_size += gd->bd->bi_dram[i].size; 282 dram_size += gd->bd->bi_dram[i].size;
291 nand_size = 0; 283 nand_size = 0;
292 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 284 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
293 nand_size += nand_info[i].size; 285 nand_size += nand_info[i].size;
294 lcd_printf (" %ld MB SDRAM, %ld MB NAND\n", 286 lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
295 dram_size >> 20, 287 dram_size >> 20,
296 nand_size >> 20 ); 288 nand_size >> 20 );
297 } 289 }
298 #endif /* CONFIG_LCD_INFO */ 290 #endif /* CONFIG_LCD_INFO */
299 #endif 291 #endif
300 292
301 #ifdef CONFIG_GENERIC_ATMEL_MCI 293 #ifdef CONFIG_GENERIC_ATMEL_MCI
302 int board_mmc_init(bd_t *bis) 294 int board_mmc_init(bd_t *bis)
303 { 295 {
304 at91_mci_hw_init(); 296 at91_mci_hw_init();
305 297
306 return atmel_mci_init((void *)ATMEL_BASE_MCI0); 298 return atmel_mci_init((void *)ATMEL_BASE_MCI0);
307 } 299 }
308 #endif 300 #endif
309 301
310 int board_early_init_f(void) 302 int board_early_init_f(void)
311 { 303 {
312 at91_seriald_hw_init(); 304 at91_seriald_hw_init();
313 return 0; 305 return 0;
314 } 306 }
315 307
316 int board_init(void) 308 int board_init(void)
317 { 309 {
318 /* arch number of AT91SAM9M10G45EK-Board */ 310 /* arch number of AT91SAM9M10G45EK-Board */
319 #ifdef CONFIG_AT91SAM9M10G45EK 311 #ifdef CONFIG_AT91SAM9M10G45EK
320 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK; 312 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK;
321 #elif defined CONFIG_AT91SAM9G45EKES 313 #elif defined CONFIG_AT91SAM9G45EKES
322 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES; 314 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES;
323 #endif 315 #endif
324 316
325 /* adress of boot parameters */ 317 /* adress of boot parameters */
326 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 318 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
327 319
328 #ifdef CONFIG_CMD_NAND 320 #ifdef CONFIG_CMD_NAND
329 at91sam9m10g45ek_nand_hw_init(); 321 at91sam9m10g45ek_nand_hw_init();
330 #endif 322 #endif
331 #ifdef CONFIG_CMD_USB 323 #ifdef CONFIG_CMD_USB
332 at91sam9m10g45ek_usb_hw_init(); 324 at91sam9m10g45ek_usb_hw_init();
333 #endif 325 #endif
334 #ifdef CONFIG_HAS_DATAFLASH 326 #ifdef CONFIG_HAS_DATAFLASH
335 at91_spi0_hw_init(1 << 0); 327 at91_spi0_hw_init(1 << 0);
336 #endif 328 #endif
337 #ifdef CONFIG_ATMEL_SPI 329 #ifdef CONFIG_ATMEL_SPI
338 at91_spi0_hw_init(1 << 4); 330 at91_spi0_hw_init(1 << 4);
339 #endif 331 #endif
340 #ifdef CONFIG_MACB 332 #ifdef CONFIG_MACB
341 at91sam9m10g45ek_macb_hw_init(); 333 at91sam9m10g45ek_macb_hw_init();
342 #endif 334 #endif
343 #ifdef CONFIG_LCD 335 #ifdef CONFIG_LCD
344 at91sam9m10g45ek_lcd_hw_init(); 336 at91sam9m10g45ek_lcd_hw_init();
345 #endif 337 #endif
346 return 0; 338 return 0;
347 } 339 }
348 340
349 int dram_init(void) 341 int dram_init(void)
350 { 342 {
351 gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE, 343 gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
352 CONFIG_SYS_SDRAM_SIZE); 344 CONFIG_SYS_SDRAM_SIZE);
353 return 0; 345 return 0;
354 } 346 }
355 347
356 #ifdef CONFIG_RESET_PHY_R 348 #ifdef CONFIG_RESET_PHY_R
357 void reset_phy(void) 349 void reset_phy(void)
358 { 350 {
359 } 351 }
360 #endif 352 #endif
361 353
362 int board_eth_init(bd_t *bis) 354 int board_eth_init(bd_t *bis)
363 { 355 {
364 int rc = 0; 356 int rc = 0;
365 #ifdef CONFIG_MACB 357 #ifdef CONFIG_MACB
366 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); 358 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
367 #endif 359 #endif
368 return rc; 360 return rc;
369 } 361 }
370 362
371 /* SPI chip select control */ 363 /* SPI chip select control */
372 #ifdef CONFIG_ATMEL_SPI 364 #ifdef CONFIG_ATMEL_SPI
373 #include <spi.h> 365 #include <spi.h>
374 366
375 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 367 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
376 { 368 {
377 return bus == 0 && cs < 2; 369 return bus == 0 && cs < 2;
378 } 370 }
379 371
380 void spi_cs_activate(struct spi_slave *slave) 372 void spi_cs_activate(struct spi_slave *slave)
381 { 373 {
382 switch(slave->cs) { 374 switch(slave->cs) {
383 case 1: 375 case 1:
384 at91_set_gpio_output(AT91_PIN_PB18, 0); 376 at91_set_gpio_output(AT91_PIN_PB18, 0);
385 break; 377 break;
386 case 0: 378 case 0:
387 default: 379 default:
388 at91_set_gpio_output(AT91_PIN_PB3, 0); 380 at91_set_gpio_output(AT91_PIN_PB3, 0);
389 break; 381 break;
390 } 382 }
391 } 383 }
392 384
393 void spi_cs_deactivate(struct spi_slave *slave) 385 void spi_cs_deactivate(struct spi_slave *slave)
394 { 386 {
395 switch(slave->cs) { 387 switch(slave->cs) {
396 case 1: 388 case 1:
397 at91_set_gpio_output(AT91_PIN_PB18, 1); 389 at91_set_gpio_output(AT91_PIN_PB18, 1);
398 break; 390 break;
399 case 0: 391 case 0:
400 default: 392 default:
401 at91_set_gpio_output(AT91_PIN_PB3, 1); 393 at91_set_gpio_output(AT91_PIN_PB3, 1);
402 break; 394 break;
403 } 395 }
404 } 396 }
405 #endif /* CONFIG_ATMEL_SPI */ 397 #endif /* CONFIG_ATMEL_SPI */
406 398
board/siemens/corvus/board.c
Diff comments   View file @ 6560491
1 /* 1 /*
2 * Board functions for Siemens CORVUS (AT91SAM9G45) based board 2 * Board functions for Siemens CORVUS (AT91SAM9G45) based board
3 * (C) Copyright 2013 Siemens AG 3 * (C) Copyright 2013 Siemens AG
4 * 4 *
5 * Based on: 5 * Based on:
6 * U-Boot file: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c 6 * U-Boot file: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
7 * (C) Copyright 2007-2008 7 * (C) Copyright 2007-2008
8 * Stelian Pop <stelian@popies.net> 8 * Stelian Pop <stelian@popies.net>
9 * Lead Tech Design <www.leadtechdesign.com> 9 * Lead Tech Design <www.leadtechdesign.com>
10 * 10 *
11 * SPDX-License-Identifier: GPL-2.0+ 11 * SPDX-License-Identifier: GPL-2.0+
12 */ 12 */
13 13
14 14
15 #include <common.h> 15 #include <common.h>
16 #include <asm/io.h> 16 #include <asm/io.h>
17 #include <asm/arch/at91sam9g45_matrix.h> 17 #include <asm/arch/at91sam9g45_matrix.h>
18 #include <asm/arch/at91sam9_smc.h> 18 #include <asm/arch/at91sam9_smc.h>
19 #include <asm/arch/at91_common.h> 19 #include <asm/arch/at91_common.h>
20 #include <asm/arch/at91_pmc.h> 20 #include <asm/arch/at91_pmc.h>
21 #include <asm/arch/at91_rstc.h> 21 #include <asm/arch/at91_rstc.h>
22 #include <asm/arch/gpio.h> 22 #include <asm/arch/gpio.h>
23 #include <asm/arch/clk.h> 23 #include <asm/arch/clk.h>
24 #include <lcd.h> 24 #include <lcd.h>
25 #include <atmel_lcdc.h> 25 #include <atmel_lcdc.h>
26 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) 26 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
27 #include <net.h> 27 #include <net.h>
28 #endif 28 #endif
29 #include <netdev.h> 29 #include <netdev.h>
30 #include <spi.h> 30 #include <spi.h>
31 31
32 DECLARE_GLOBAL_DATA_PTR; 32 DECLARE_GLOBAL_DATA_PTR;
33 33
34 static void corvus_nand_hw_init(void) 34 static void corvus_nand_hw_init(void)
35 { 35 {
36 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 36 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
37 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 37 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
38 unsigned long csa; 38 unsigned long csa;
39 39
40 /* Enable CS3 */ 40 /* Enable CS3 */
41 csa = readl(&matrix->ebicsa); 41 csa = readl(&matrix->ebicsa);
42 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; 42 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
43 writel(csa, &matrix->ebicsa); 43 writel(csa, &matrix->ebicsa);
44 44
45 /* Configure SMC CS3 for NAND/SmartMedia */ 45 /* Configure SMC CS3 for NAND/SmartMedia */
46 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | 46 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
47 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), 47 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
48 &smc->cs[3].setup); 48 &smc->cs[3].setup);
49 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) | 49 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
50 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4), 50 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
51 &smc->cs[3].pulse); 51 &smc->cs[3].pulse);
52 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7), 52 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
53 &smc->cs[3].cycle); 53 &smc->cs[3].cycle);
54 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 54 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
55 AT91_SMC_MODE_EXNW_DISABLE | 55 AT91_SMC_MODE_EXNW_DISABLE |
56 #ifdef CONFIG_SYS_NAND_DBW_16 56 #ifdef CONFIG_SYS_NAND_DBW_16
57 AT91_SMC_MODE_DBW_16 | 57 AT91_SMC_MODE_DBW_16 |
58 #else /* CONFIG_SYS_NAND_DBW_8 */ 58 #else /* CONFIG_SYS_NAND_DBW_8 */
59 AT91_SMC_MODE_DBW_8 | 59 AT91_SMC_MODE_DBW_8 |
60 #endif 60 #endif
61 AT91_SMC_MODE_TDF_CYCLE(3), 61 AT91_SMC_MODE_TDF_CYCLE(3),
62 &smc->cs[3].mode); 62 &smc->cs[3].mode);
63 63
64 at91_periph_clk_enable(ATMEL_ID_PIOC); 64 at91_periph_clk_enable(ATMEL_ID_PIOC);
65 at91_periph_clk_enable(ATMEL_ID_PIOA); 65 at91_periph_clk_enable(ATMEL_ID_PIOA);
66 66
67 /* Enable NandFlash */ 67 /* Enable NandFlash */
68 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 68 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
69 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); 69 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
70 } 70 }
71 71
72 #if defined(CONFIG_SPL_BUILD) 72 #if defined(CONFIG_SPL_BUILD)
73 #include <spl.h> 73 #include <spl.h>
74 #include <nand.h> 74 #include <nand.h>
75 75
76 void at91_spl_board_init(void) 76 void at91_spl_board_init(void)
77 { 77 {
78 /* 78 /*
79 * For on the sam9m10g45ek board, the chip wm9711 stay in the test 79 * For on the sam9m10g45ek board, the chip wm9711 stay in the test
80 * mode, so it need do some action to exit mode. 80 * mode, so it need do some action to exit mode.
81 */ 81 */
82 at91_set_gpio_output(AT91_PIN_PD7, 0); 82 at91_set_gpio_output(AT91_PIN_PD7, 0);
83 at91_set_gpio_output(AT91_PIN_PD8, 0); 83 at91_set_gpio_output(AT91_PIN_PD8, 0);
84 at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1); 84 at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1);
85 at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1); 85 at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1);
86 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1); 86 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
87 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1); 87 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);
88 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1); 88 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
89 89
90 corvus_nand_hw_init(); 90 corvus_nand_hw_init();
91 91
92 /* Configure recovery button PINs */ 92 /* Configure recovery button PINs */
93 at91_set_gpio_input(AT91_PIN_PB7, 1); 93 at91_set_gpio_input(AT91_PIN_PB7, 1);
94 94
95 /* check if button is pressed */ 95 /* check if button is pressed */
96 if (at91_get_gpio_value(AT91_PIN_PB7) == 0) { 96 if (at91_get_gpio_value(AT91_PIN_PB7) == 0) {
97 u32 boot_device; 97 u32 boot_device;
98 98
99 debug("Recovery button pressed\n"); 99 debug("Recovery button pressed\n");
100 boot_device = spl_boot_device(); 100 boot_device = spl_boot_device();
101 switch (boot_device) { 101 switch (boot_device) {
102 #ifdef CONFIG_SPL_NAND_SUPPORT 102 #ifdef CONFIG_SPL_NAND_SUPPORT
103 case BOOT_DEVICE_NAND: 103 case BOOT_DEVICE_NAND:
104 nand_init(); 104 nand_init();
105 spl_nand_erase_one(0, 0); 105 spl_nand_erase_one(0, 0);
106 break; 106 break;
107 #endif 107 #endif
108 } 108 }
109 } 109 }
110 } 110 }
111 111
112 #include <asm/arch/atmel_mpddrc.h> 112 #include <asm/arch/atmel_mpddrc.h>
113 static void ddr2_conf(struct atmel_mpddr *ddr2) 113 static void ddr2_conf(struct atmel_mpddr *ddr2)
114 { 114 {
115 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); 115 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
116 116
117 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 117 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
118 ATMEL_MPDDRC_CR_NR_ROW_14 | 118 ATMEL_MPDDRC_CR_NR_ROW_14 |
119 ATMEL_MPDDRC_CR_DIC_DS | 119 ATMEL_MPDDRC_CR_DIC_DS |
120 ATMEL_MPDDRC_CR_DQMS_SHARED | 120 ATMEL_MPDDRC_CR_DQMS_SHARED |
121 ATMEL_MPDDRC_CR_CAS_DDR_CAS3); 121 ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
122 ddr2->rtr = 0x24b; 122 ddr2->rtr = 0x24b;
123 123
124 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */ 124 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
125 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */ 125 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
126 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */ 126 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
127 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 75 ns */ 127 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 75 ns */
128 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */ 128 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
129 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/ 129 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
130 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */ 130 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
131 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */ 131 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
132 132
133 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */ 133 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
134 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | 134 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
135 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | 135 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
136 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); 136 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
137 137
138 ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | 138 ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
139 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | 139 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
140 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | 140 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
141 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); 141 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
142 } 142 }
143 143
144 void mem_init(void) 144 void mem_init(void)
145 { 145 {
146 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 146 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
147 struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
148 struct atmel_mpddr ddr2; 147 struct atmel_mpddr ddr2;
149 unsigned long csa;
150 148
151 ddr2_conf(&ddr2); 149 ddr2_conf(&ddr2);
152 150
153 /* enable DDR2 clock */ 151 /* enable DDR2 clock */
154 writel(0x4, &pmc->scer); 152 writel(0x4, &pmc->scer);
155
156 /* Chip select 1 is for DDR2/SDRAM */
157 csa = readl(&mat->ebicsa);
158 csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
159 csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V;
160 writel(csa, &mat->ebicsa);
161 153
162 /* DDRAM2 Controller initialize */ 154 /* DDRAM2 Controller initialize */
163 ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2); 155 ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
164 } 156 }
165 #endif 157 #endif
166 158
167 #ifdef CONFIG_CMD_USB 159 #ifdef CONFIG_CMD_USB
168 static void taurus_usb_hw_init(void) 160 static void taurus_usb_hw_init(void)
169 { 161 {
170 at91_periph_clk_enable(ATMEL_ID_PIODE); 162 at91_periph_clk_enable(ATMEL_ID_PIODE);
171 163
172 at91_set_gpio_output(AT91_PIN_PD1, 0); 164 at91_set_gpio_output(AT91_PIN_PD1, 0);
173 at91_set_gpio_output(AT91_PIN_PD3, 0); 165 at91_set_gpio_output(AT91_PIN_PD3, 0);
174 } 166 }
175 #endif 167 #endif
176 168
177 #ifdef CONFIG_MACB 169 #ifdef CONFIG_MACB
178 static void corvus_macb_hw_init(void) 170 static void corvus_macb_hw_init(void)
179 { 171 {
180 /* Enable clock */ 172 /* Enable clock */
181 at91_periph_clk_enable(ATMEL_ID_EMAC); 173 at91_periph_clk_enable(ATMEL_ID_EMAC);
182 174
183 /* 175 /*
184 * Disable pull-up on: 176 * Disable pull-up on:
185 * RXDV (PA15) => PHY normal mode (not Test mode) 177 * RXDV (PA15) => PHY normal mode (not Test mode)
186 * ERX0 (PA12) => PHY ADDR0 178 * ERX0 (PA12) => PHY ADDR0
187 * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0 179 * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
188 * 180 *
189 * PHY has internal pull-down 181 * PHY has internal pull-down
190 */ 182 */
191 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0); 183 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0);
192 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 0); 184 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 0);
193 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 0); 185 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 0);
194 186
195 at91_phy_reset(); 187 at91_phy_reset();
196 188
197 /* Re-enable pull-up */ 189 /* Re-enable pull-up */
198 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1); 190 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
199 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1); 191 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
200 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1); 192 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);
201 193
202 /* And the pins. */ 194 /* And the pins. */
203 at91_macb_hw_init(); 195 at91_macb_hw_init();
204 } 196 }
205 #endif 197 #endif
206 198
207 int board_early_init_f(void) 199 int board_early_init_f(void)
208 { 200 {
209 at91_seriald_hw_init(); 201 at91_seriald_hw_init();
210 return 0; 202 return 0;
211 } 203 }
212 204
213 int board_init(void) 205 int board_init(void)
214 { 206 {
215 /* address of boot parameters */ 207 /* address of boot parameters */
216 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 208 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
217 209
218 #ifdef CONFIG_CMD_NAND 210 #ifdef CONFIG_CMD_NAND
219 corvus_nand_hw_init(); 211 corvus_nand_hw_init();
220 #endif 212 #endif
221 #ifdef CONFIG_ATMEL_SPI 213 #ifdef CONFIG_ATMEL_SPI
222 at91_spi0_hw_init(1 << 4); 214 at91_spi0_hw_init(1 << 4);
223 #endif 215 #endif
224 #ifdef CONFIG_HAS_DATAFLASH 216 #ifdef CONFIG_HAS_DATAFLASH
225 at91_spi0_hw_init(1 << 0); 217 at91_spi0_hw_init(1 << 0);
226 #endif 218 #endif
227 #ifdef CONFIG_MACB 219 #ifdef CONFIG_MACB
228 corvus_macb_hw_init(); 220 corvus_macb_hw_init();
229 #endif 221 #endif
230 #ifdef CONFIG_CMD_USB 222 #ifdef CONFIG_CMD_USB
231 taurus_usb_hw_init(); 223 taurus_usb_hw_init();
232 #endif 224 #endif
233 return 0; 225 return 0;
234 } 226 }
235 227
236 int dram_init(void) 228 int dram_init(void)
237 { 229 {
238 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 230 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
239 CONFIG_SYS_SDRAM_SIZE); 231 CONFIG_SYS_SDRAM_SIZE);
240 return 0; 232 return 0;
241 } 233 }
242 234
243 int board_eth_init(bd_t *bis) 235 int board_eth_init(bd_t *bis)
244 { 236 {
245 int rc = 0; 237 int rc = 0;
246 #ifdef CONFIG_MACB 238 #ifdef CONFIG_MACB
247 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); 239 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
248 #endif 240 #endif
249 return rc; 241 return rc;
250 } 242 }
251 243
252 /* SPI chip select control */ 244 /* SPI chip select control */
253 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 245 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
254 { 246 {
255 return bus == 0 && cs < 2; 247 return bus == 0 && cs < 2;
256 } 248 }
257 249
258 void spi_cs_activate(struct spi_slave *slave) 250 void spi_cs_activate(struct spi_slave *slave)
259 { 251 {
260 switch (slave->cs) { 252 switch (slave->cs) {
261 case 1: 253 case 1:
262 at91_set_gpio_output(AT91_PIN_PB18, 0); 254 at91_set_gpio_output(AT91_PIN_PB18, 0);
263 break; 255 break;
264 case 0: 256 case 0:
265 default: 257 default:
266 at91_set_gpio_output(AT91_PIN_PB3, 0); 258 at91_set_gpio_output(AT91_PIN_PB3, 0);
267 break; 259 break;
268 } 260 }
269 } 261 }
270 262
271 void spi_cs_deactivate(struct spi_slave *slave) 263 void spi_cs_deactivate(struct spi_slave *slave)
272 { 264 {
273 switch (slave->cs) { 265 switch (slave->cs) {
274 case 1: 266 case 1:
275 at91_set_gpio_output(AT91_PIN_PB18, 1); 267 at91_set_gpio_output(AT91_PIN_PB18, 1);
276 break; 268 break;
277 case 0: 269 case 0:
278 default: 270 default:
279 at91_set_gpio_output(AT91_PIN_PB3, 1); 271 at91_set_gpio_output(AT91_PIN_PB3, 1);
280 break; 272 break;
281 } 273 }
282 } 274 }
283 275