tny_a9260/tny_a9g20: update board to the new AT91 organization

Cc: Albin Tonnerre <tonnerrealbin@gmail.com> CC: Gregory Hermant <gregory.hermant@calao-systems.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

tny_a9260/tny_a9g20: update board to the new AT91 organization
Cc: Albin Tonnerre <tonnerrealbin@gmail.com> CC: Gregory Hermant <gregory.hermant@calao-systems.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Thomas Petazzoni · Albert ARIBAUD
1 parent 6785c7c84a
Showing 5 changed files with 73 additions and 83 deletions Side-by-side Diff
MAKEALL
Makefile
board/calao/tny_a9260/tny_a9260.c
boards.cfg
include/configs/tny_a9260.h
@@ -446,8 +446,6 @@
 LIST_at91="$(boards_by_soc at91)\
 	at91sam9m10g45ek	\
 	pm9g45			\
-	TNY_A9260		\
-	TNY_A9G20		\
 "
  
 #########################################################################
@@ -827,16 +827,6 @@
 	@mkdir -p $(obj)include
 	@$(MKCONFIG) -a pm9g45 arm arm926ejs pm9g45 ronetix at91
  
-TNY_A9G20_NANDFLASH_config \
-TNY_A9G20_EEPROM_config \
-TNY_A9G20_config \
-TNY_A9260_NANDFLASH_config \
-TNY_A9260_EEPROM_config \
-TNY_A9260_config	:	unconfig
-	@mkdir -p $(obj)include
-	@echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h
-	@$(MKCONFIG) -n $@ -a tny_a9260 arm arm926ejs tny_a9260 calao at91
-
 ########################################################################
 ## ARM Integrator boards - see doc/README-integrator for more info.
 integratorap_config	\
@@ -26,14 +26,12 @@
  */
  
 #include <common.h>
-#include <asm/arch/at91sam9260.h>
 #include <asm/arch/at91sam9_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
 #include <asm/arch/hardware.h>
  
 DECLARE_GLOBAL_DATA_PTR;
  
  
  
  
  
  
@@ -45,33 +43,36 @@
  
 static void tny_a9260_nand_hw_init(void)
 {
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
 	unsigned long csa;
  
-	/* Enable CS3 */
-	csa = at91_sys_read(AT91_MATRIX_EBICSA);
-	at91_sys_write(AT91_MATRIX_EBICSA,
-		       csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+	/* Assign CS3 to NAND/SmartMedia Interface */
+	csa = readl(&matrix->ebicsa);
+	csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+	writel(csa, &matrix->ebicsa);
  
 	/* Configure SMC CS3 for NAND/SmartMedia */
-	at91_sys_write(AT91_SMC_SETUP(3),
-		       AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
-		       AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
-	at91_sys_write(AT91_SMC_PULSE(3),
-		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
-		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
-	at91_sys_write(AT91_SMC_CYCLE(3),
-		       AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
-	at91_sys_write(AT91_SMC_MODE(3),
-		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
-		       AT91_SMC_EXNWMODE_DISABLE |
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+		&smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+		&smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
 #ifdef CONFIG_SYS_NAND_DBW_16
-		       AT91_SMC_DBW_16 |
+		AT91_SMC_MODE_DBW_16 |
 #else /* CONFIG_SYS_NAND_DBW_8 */
-		       AT91_SMC_DBW_8 |
+		AT91_SMC_MODE_DBW_8 |
 #endif
-		       AT91_SMC_TDF_(2));
+		AT91_SMC_MODE_TDF_CYCLE(2),
+		&smc->cs[3].mode);
  
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
+	writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
  
 	/* Configure RDY/BSY */
 	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  
@@ -91,9 +92,9 @@
 	gd->bd->bi_arch_number = MACH_TYPE_TNY_A9G20;
 #endif
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  
-	at91_serial_hw_init();
+	at91_seriald_hw_init();
 	tny_a9260_nand_hw_init();
 	at91_spi0_hw_init(1 << 5);
 	return 0;
@@ -101,11 +102,9 @@
  
 int dram_init(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM;
-	if(get_ram_size((long *) PHYS_SDRAM, PHYS_SDRAM_SIZE) != PHYS_SDRAM_SIZE)
-		return -1;
-
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	gd->ram_size = get_ram_size(
+		(void *)CONFIG_SYS_SDRAM_BASE,
+		CONFIG_SYS_SDRAM_SIZE);
 	return 0;
 }
@@ -104,6 +104,10 @@
 snapper9g20                  arm         arm926ejs   snapper9260         bluewater      at91        snapper9260:AT91SAM9G20
 sbc35_a9g20_nandflash        arm         arm926ejs   sbc35_a9g20         calao          at91        sbc35_a9g20:AT91SAM9G20,SYS_USE_NANDFLASH
 sbc35_a9g20_eeprom           arm         arm926ejs   sbc35_a9g20         calao          at91        sbc35_a9g20:AT91SAM9G20,SYS_USE_EEPROM
+tny_a9g20_nandflash          arm         arm926ejs   tny_a9260           calao          at91        tny_a9260:AT91SAM9G20,SYS_USE_NANDFLASH
+tny_a9g20_eeprom             arm         arm926ejs   tny_a9260           calao          at91        tny_a9260:AT91SAM9G20,SYS_USE_EEPROM
+tny_a9260_nandflash          arm         arm926ejs   tny_a9260           calao          at91        tny_a9260:AT91SAM9260,SYS_USE_NANDFLASH
+tny_a9260_eeprom             arm         arm926ejs   tny_a9260           calao          at91        tny_a9260:AT91SAM9260,SYS_USE_EEPROM
 cpu9260                      arm         arm926ejs   cpu9260             eukrea         at91        cpu9260:CPU9260
 cpu9260_nand                 arm         arm926ejs   cpu9260             eukrea         at91        cpu9260:CPU9260,NANDBOOT
 cpu9260_128M                 arm         arm926ejs   cpu9260             eukrea         at91        cpu9260:CPU9260,CPU9260_128M
@@ -30,50 +30,49 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
  
-#define CONFIG_AT91_LEGACY
+/*
+ * SoC must be defined first, before hardware.h is included.
+ * In this case SoC is defined in boards.cfg.
+ */
+#include <asm/hardware.h>
  
-#if defined(CONFIG_TNY_A9260_NANDFLASH) || defined(CONFIG_TNY_A9260_EEPROM)
-#define CONFIG_TNY_A9260
-#elif defined(CONFIG_TNY_A9G20_NANDFLASH) || defined(CONFIG_TNY_A9G20_EEPROM)
-#define CONFIG_TNY_A9G20
-#endif
-
-#ifdef CONFIG_TNY_A9260
-#define CONFIG_AT91SAM9260
-#else
-#define CONFIG_AT91SAM9G20
-#endif
-
 #if defined(CONFIG_TNY_A9260_NANDFLASH) || defined(CONFIG_TNY_A9G20_NANDFLASH)
 #define CONFIG_ENV_IS_IN_NAND
 #else
 #define CONFIG_ENV_IS_IN_EEPROM
 #endif
  
+/* Define actual evaluation board type from used processor type */
+#ifdef CONFIG_AT91SAM9G20
+# define CONFIG_TNY_A9G20
+#else
+# define CONFIG_TNY_A9260
+#endif
+
 /* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
 #define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* 12 MHz crystal */
-#define CONFIG_SYS_HZ		1000
+#define CONFIG_SYS_HZ		        1000
  
-#define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core */
 #define CONFIG_ARCH_CPU_INIT
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
-
-#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG	1
-
+#define CONFIG_CMDLINE_TAG	        /* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
 #define CONFIG_SKIP_LOWLEVEL_INIT
  
 /*
  * Hardware drivers
  */
-#define CONFIG_AT91_GPIO	1
-#define CONFIG_ATMEL_USART	1
-#undef CONFIG_USART0
-#undef CONFIG_USART1
-#undef CONFIG_USART2
-#define CONFIG_USART3		1	/* USART 3 is DBGU */
+#define CONFIG_ATMEL_LEGACY
+#define CONFIG_AT91_GPIO
  
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define	CONFIG_USART_ID			ATMEL_ID_SYS
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
+
 #define CONFIG_BOOTDELAY	3
  
 /*
  
@@ -86,13 +85,16 @@
 #undef CONFIG_CMD_IMLS
 #undef CONFIG_CMD_LOADS
 #undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
 #undef CONFIG_CMD_SOURCE
 #undef CONFIG_CMD_USB
  
 /* SDRAM */
 #define CONFIG_NR_DRAM_BANKS		1
-#define PHYS_SDRAM			0x20000000
-#define PHYS_SDRAM_SIZE			0x04000000	/* 64 megs */
+#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
+#define CONFIG_SYS_SDRAM_SIZE		0x04000000	/* 64 megs */
+# define CONFIG_SYS_INIT_SP_ADDR \
+	(ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
  
 /* SPI EEPROM */
 #define CONFIG_SPI
@@ -109,8 +111,8 @@
 #define CONFIG_CMD_NAND
 #define CONFIG_NAND_ATMEL
 #define CONFIG_SYS_MAX_NAND_DEVICE		1
-#define CONFIG_SYS_NAND_BASE			0x40000000
-#define CONFIG_SYS_NAND_DBW_8			1
+#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_DBW_8
 /* our ALE is AD21 */
 #define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
 /* our CLE is AD22 */
  
  
  
  
@@ -119,27 +121,27 @@
 #define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PC13
  
 /* NOR flash - no real flash on this board */
-#define CONFIG_SYS_NO_FLASH			1
+#define CONFIG_SYS_NO_FLASH
  
-#define CONFIG_DOS_PARTITION		1
-#define CONFIG_CMD_FAT			1
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
  
 #define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */
  
-#define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_START		CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_MEMTEST_END			0x23e00000
  
 /* Env in EEPROM, bootstrap + u-boot in NAND*/
 #ifdef CONFIG_ENV_IS_IN_EEPROM
 #define CONFIG_ENV_OFFSET		0x20
-#define CONFIG_ENV_SIZE		0x1000
+#define CONFIG_ENV_SIZE		        0x1000
 #endif
  
 /* Env, bootstrap and u-boot in NAND */
 #ifdef CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET 0x60000
-#define CONFIG_ENV_OFFSET_REDUND 0x80000
-#define CONFIG_ENV_SIZE 0x20000
+#define CONFIG_ENV_OFFSET               0x60000
+#define CONFIG_ENV_OFFSET_REDUND        0x80000
+#define CONFIG_ENV_SIZE                 0x20000
 #endif
  
 #define CONFIG_BOOTCOMMAND	"nboot 0x21000000 0 400000"
  
@@ -149,15 +151,12 @@
 				"120M(rootfs),-(other) " \
 				"rw rootfstype=jffs2"
  
-#define CONFIG_BAUDRATE		115200
-#define CONFIG_SYS_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
-
 #define CONFIG_SYS_PROMPT	"U-Boot> "
 #define CONFIG_SYS_CBSIZE	256
 #define CONFIG_SYS_MAXARGS	16
 #define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_LONGHELP	1
-#define CONFIG_CMDLINE_EDITING	1
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
  
 /*
  * Size of malloc() pool
...	...	@@ -446,8 +446,6 @@
446	446	LIST_at91="$(boards_by_soc at91)\
447	447	at91sam9m10g45ek \
448	448	pm9g45 \
449		- TNY_A9260 \
450		- TNY_A9G20 \
451	449	"
452	450
453	451	#########################################################################
...	...	@@ -827,16 +827,6 @@
827	827	@mkdir -p $(obj)include
828	828	@$(MKCONFIG) -a pm9g45 arm arm926ejs pm9g45 ronetix at91
829	829
830		-TNY_A9G20_NANDFLASH_config \
831		-TNY_A9G20_EEPROM_config \
832		-TNY_A9G20_config \
833		-TNY_A9260_NANDFLASH_config \
834		-TNY_A9260_EEPROM_config \
835		-TNY_A9260_config : unconfig
836		- @mkdir -p $(obj)include
837		- @echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h
838		- @$(MKCONFIG) -n $@ -a tny_a9260 arm arm926ejs tny_a9260 calao at91
839		-
840	830	########################################################################
841	831	## ARM Integrator boards - see doc/README-integrator for more info.
842	832	integratorap_config \
...	...	@@ -26,14 +26,12 @@
26	26	*/
27	27
28	28	#include <common.h>
29		-#include <asm/arch/at91sam9260.h>
30	29	#include <asm/arch/at91sam9_matrix.h>
31	30	#include <asm/arch/at91sam9_smc.h>
32	31	#include <asm/arch/at91_common.h>
33	32	#include <asm/arch/at91_pmc.h>
34	33	#include <asm/arch/at91_rstc.h>
35	34	#include <asm/arch/gpio.h>
36		-#include <asm/arch/io.h>
37	35	#include <asm/arch/hardware.h>
38	36
39	37	DECLARE_GLOBAL_DATA_PTR;
40	38
41	39
42	40
43	41
44	42
45	43
...	...	@@ -45,33 +43,36 @@
45	43
46	44	static void tny_a9260_nand_hw_init(void)
47	45	{
	46	+ struct at91_pmc pmc = (struct at91_pmc )ATMEL_BASE_PMC;
	47	+ struct at91_smc smc = (struct at91_smc )ATMEL_BASE_SMC;
	48	+ struct at91_matrix matrix = (struct at91_matrix )ATMEL_BASE_MATRIX;
48	49	unsigned long csa;
49	50
50		- /* Enable CS3 */
51		- csa = at91_sys_read(AT91_MATRIX_EBICSA);
52		- at91_sys_write(AT91_MATRIX_EBICSA,
53		- csa \| AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
	51	+ /* Assign CS3 to NAND/SmartMedia Interface */
	52	+ csa = readl(&matrix->ebicsa);
	53	+ csa \|= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
	54	+ writel(csa, &matrix->ebicsa);
54	55
55	56	/* Configure SMC CS3 for NAND/SmartMedia */
56		- at91_sys_write(AT91_SMC_SETUP(3),
57		- AT91_SMC_NWESETUP_(1) \| AT91_SMC_NCS_WRSETUP_(0) \|
58		- AT91_SMC_NRDSETUP_(1) \| AT91_SMC_NCS_RDSETUP_(0));
59		- at91_sys_write(AT91_SMC_PULSE(3),
60		- AT91_SMC_NWEPULSE_(3) \| AT91_SMC_NCS_WRPULSE_(3) \|
61		- AT91_SMC_NRDPULSE_(3) \| AT91_SMC_NCS_RDPULSE_(3));
62		- at91_sys_write(AT91_SMC_CYCLE(3),
63		- AT91_SMC_NWECYCLE_(5) \| AT91_SMC_NRDCYCLE_(5));
64		- at91_sys_write(AT91_SMC_MODE(3),
65		- AT91_SMC_READMODE \| AT91_SMC_WRITEMODE \|
66		- AT91_SMC_EXNWMODE_DISABLE \|
	57	+ writel(AT91_SMC_SETUP_NWE(1) \| AT91_SMC_SETUP_NCS_WR(0) \|
	58	+ AT91_SMC_SETUP_NRD(1) \| AT91_SMC_SETUP_NCS_RD(0),
	59	+ &smc->cs[3].setup);
	60	+ writel(AT91_SMC_PULSE_NWE(3) \| AT91_SMC_PULSE_NCS_WR(3) \|
	61	+ AT91_SMC_PULSE_NRD(3) \| AT91_SMC_PULSE_NCS_RD(3),
	62	+ &smc->cs[3].pulse);
	63	+ writel(AT91_SMC_CYCLE_NWE(5) \| AT91_SMC_CYCLE_NRD(5),
	64	+ &smc->cs[3].cycle);
	65	+ writel(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \|
	66	+ AT91_SMC_MODE_EXNW_DISABLE \|
67	67	#ifdef CONFIG_SYS_NAND_DBW_16
68		- AT91_SMC_DBW_16 \|
	68	+ AT91_SMC_MODE_DBW_16 \|
69	69	#else /* CONFIG_SYS_NAND_DBW_8 */
70		- AT91_SMC_DBW_8 \|
	70	+ AT91_SMC_MODE_DBW_8 \|
71	71	#endif
72		- AT91_SMC_TDF_(2));
	72	+ AT91_SMC_MODE_TDF_CYCLE(2),
	73	+ &smc->cs[3].mode);
73	74
74		- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
	75	+ writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
75	76
76	77	/* Configure RDY/BSY */
77	78	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
78	79
...	...	@@ -91,9 +92,9 @@
91	92	gd->bd->bi_arch_number = MACH_TYPE_TNY_A9G20;
92	93	#endif
93	94	/* adress of boot parameters */
94		- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	95	+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
95	96
96		- at91_serial_hw_init();
	97	+ at91_seriald_hw_init();
97	98	tny_a9260_nand_hw_init();
98	99	at91_spi0_hw_init(1 << 5);
99	100	return 0;
...	...	@@ -101,11 +102,9 @@
101	102
102	103	int dram_init(void)
103	104	{
104		- gd->bd->bi_dram[0].start = PHYS_SDRAM;
105		- if(get_ram_size((long *) PHYS_SDRAM, PHYS_SDRAM_SIZE) != PHYS_SDRAM_SIZE)
106		- return -1;
107		-
108		- gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
	105	+ gd->ram_size = get_ram_size(
	106	+ (void *)CONFIG_SYS_SDRAM_BASE,
	107	+ CONFIG_SYS_SDRAM_SIZE);
109	108	return 0;
110	109	}
...	...	@@ -104,6 +104,10 @@
104	104	snapper9g20 arm arm926ejs snapper9260 bluewater at91 snapper9260:AT91SAM9G20
105	105	sbc35_a9g20_nandflash arm arm926ejs sbc35_a9g20 calao at91 sbc35_a9g20:AT91SAM9G20,SYS_USE_NANDFLASH
106	106	sbc35_a9g20_eeprom arm arm926ejs sbc35_a9g20 calao at91 sbc35_a9g20:AT91SAM9G20,SYS_USE_EEPROM
	107	+tny_a9g20_nandflash arm arm926ejs tny_a9260 calao at91 tny_a9260:AT91SAM9G20,SYS_USE_NANDFLASH
	108	+tny_a9g20_eeprom arm arm926ejs tny_a9260 calao at91 tny_a9260:AT91SAM9G20,SYS_USE_EEPROM
	109	+tny_a9260_nandflash arm arm926ejs tny_a9260 calao at91 tny_a9260:AT91SAM9260,SYS_USE_NANDFLASH
	110	+tny_a9260_eeprom arm arm926ejs tny_a9260 calao at91 tny_a9260:AT91SAM9260,SYS_USE_EEPROM
107	111	cpu9260 arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260
108	112	cpu9260_nand arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260,NANDBOOT
109	113	cpu9260_128M arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260,CPU9260_128M
...	...	@@ -30,50 +30,49 @@
30	30	#ifndef __CONFIG_H
31	31	#define __CONFIG_H
32	32
33		-#define CONFIG_AT91_LEGACY
	33	+/*
	34	+ * SoC must be defined first, before hardware.h is included.
	35	+ * In this case SoC is defined in boards.cfg.
	36	+ */
	37	+#include <asm/hardware.h>
34	38
35		-#if defined(CONFIG_TNY_A9260_NANDFLASH) \|\| defined(CONFIG_TNY_A9260_EEPROM)
36		-#define CONFIG_TNY_A9260
37		-#elif defined(CONFIG_TNY_A9G20_NANDFLASH) \|\| defined(CONFIG_TNY_A9G20_EEPROM)
38		-#define CONFIG_TNY_A9G20
39		-#endif
40		-
41		-#ifdef CONFIG_TNY_A9260
42		-#define CONFIG_AT91SAM9260
43		-#else
44		-#define CONFIG_AT91SAM9G20
45		-#endif
46		-
47	39	#if defined(CONFIG_TNY_A9260_NANDFLASH) \|\| defined(CONFIG_TNY_A9G20_NANDFLASH)
48	40	#define CONFIG_ENV_IS_IN_NAND
49	41	#else
50	42	#define CONFIG_ENV_IS_IN_EEPROM
51	43	#endif
52	44
	45	+/* Define actual evaluation board type from used processor type */
	46	+#ifdef CONFIG_AT91SAM9G20
	47	+# define CONFIG_TNY_A9G20
	48	+#else
	49	+# define CONFIG_TNY_A9260
	50	+#endif
	51	+
53	52	/* ARM asynchronous clock */
	53	+#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
54	54	#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
55		-#define CONFIG_SYS_HZ 1000
	55	+#define CONFIG_SYS_HZ 1000
56	56
57		-#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
58	57	#define CONFIG_ARCH_CPU_INIT
59	58	#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
60		-
61		-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
62		-#define CONFIG_SETUP_MEMORY_TAGS 1
63		-#define CONFIG_INITRD_TAG 1
64		-
	59	+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	60	+#define CONFIG_SETUP_MEMORY_TAGS
	61	+#define CONFIG_INITRD_TAG
65	62	#define CONFIG_SKIP_LOWLEVEL_INIT
66	63
67	64	/*
68	65	* Hardware drivers
69	66	*/
70		-#define CONFIG_AT91_GPIO 1
71		-#define CONFIG_ATMEL_USART 1
72		-#undef CONFIG_USART0
73		-#undef CONFIG_USART1
74		-#undef CONFIG_USART2
75		-#define CONFIG_USART3 1 /* USART 3 is DBGU */
	67	+#define CONFIG_ATMEL_LEGACY
	68	+#define CONFIG_AT91_GPIO
76	69
	70	+#define CONFIG_ATMEL_USART
	71	+#define CONFIG_USART_BASE ATMEL_BASE_DBGU
	72	+#define CONFIG_USART_ID ATMEL_ID_SYS
	73	+#define CONFIG_BAUDRATE 115200
	74	+#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
	75	+
77	76	#define CONFIG_BOOTDELAY 3
78	77
79	78	/*
80	79
...	...	@@ -86,13 +85,16 @@
86	85	#undef CONFIG_CMD_IMLS
87	86	#undef CONFIG_CMD_LOADS
88	87	#undef CONFIG_CMD_NET
	88	+#undef CONFIG_CMD_NFS
89	89	#undef CONFIG_CMD_SOURCE
90	90	#undef CONFIG_CMD_USB
91	91
92	92	/* SDRAM */
93	93	#define CONFIG_NR_DRAM_BANKS 1
94		-#define PHYS_SDRAM 0x20000000
95		-#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
	94	+#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
	95	+#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */
	96	+# define CONFIG_SYS_INIT_SP_ADDR \
	97	+ (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
96	98
97	99	/* SPI EEPROM */
98	100	#define CONFIG_SPI
...	...	@@ -109,8 +111,8 @@
109	111	#define CONFIG_CMD_NAND
110	112	#define CONFIG_NAND_ATMEL
111	113	#define CONFIG_SYS_MAX_NAND_DEVICE 1
112		-#define CONFIG_SYS_NAND_BASE 0x40000000
113		-#define CONFIG_SYS_NAND_DBW_8 1
	114	+#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
	115	+#define CONFIG_SYS_NAND_DBW_8
114	116	/* our ALE is AD21 */
115	117	#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
116	118	/* our CLE is AD22 */
117	119
118	120
119	121
120	122
...	...	@@ -119,27 +121,27 @@
119	121	#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
120	122
121	123	/* NOR flash - no real flash on this board */
122		-#define CONFIG_SYS_NO_FLASH 1
	124	+#define CONFIG_SYS_NO_FLASH
123	125
124		-#define CONFIG_DOS_PARTITION 1
125		-#define CONFIG_CMD_FAT 1
	126	+#define CONFIG_DOS_PARTITION
	127	+#define CONFIG_CMD_FAT
126	128
127	129	#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
128	130
129		-#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
	131	+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
130	132	#define CONFIG_SYS_MEMTEST_END 0x23e00000
131	133
132	134	/* Env in EEPROM, bootstrap + u-boot in NAND*/
133	135	#ifdef CONFIG_ENV_IS_IN_EEPROM
134	136	#define CONFIG_ENV_OFFSET 0x20
135		-#define CONFIG_ENV_SIZE 0x1000
	137	+#define CONFIG_ENV_SIZE 0x1000
136	138	#endif
137	139
138	140	/* Env, bootstrap and u-boot in NAND */
139	141	#ifdef CONFIG_ENV_IS_IN_NAND
140		-#define CONFIG_ENV_OFFSET 0x60000
141		-#define CONFIG_ENV_OFFSET_REDUND 0x80000
142		-#define CONFIG_ENV_SIZE 0x20000
	142	+#define CONFIG_ENV_OFFSET 0x60000
	143	+#define CONFIG_ENV_OFFSET_REDUND 0x80000
	144	+#define CONFIG_ENV_SIZE 0x20000
143	145	#endif
144	146
145	147	#define CONFIG_BOOTCOMMAND "nboot 0x21000000 0 400000"
146	148
...	...	@@ -149,15 +151,12 @@
149	151	"120M(rootfs),-(other) " \
150	152	"rw rootfstype=jffs2"
151	153
152		-#define CONFIG_BAUDRATE 115200
153		-#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
154		-
155	154	#define CONFIG_SYS_PROMPT "U-Boot> "
156	155	#define CONFIG_SYS_CBSIZE 256
157	156	#define CONFIG_SYS_MAXARGS 16
158	157	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
159		-#define CONFIG_SYS_LONGHELP 1
160		-#define CONFIG_CMDLINE_EDITING 1
	158	+#define CONFIG_SYS_LONGHELP
	159	+#define CONFIG_CMDLINE_EDITING
161	160
162	161	/*
163	162	* Size of malloc() pool