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Commit 665e4caf02e4e835c5ec50d616512c6c7d99f1c0

Authored by Marek Vasut
1 parent de6da9255a
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

arm: socfpga: sysmgr: Clean up system manager 

Clean up the system manager register definition and add the missing
register definitions in place.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

Showing 2 changed files with 86 additions and 34 deletions Side-by-side Diff

arch/arm/cpu/armv7/socfpga/system_manager.c
Diff comments   View file @ 665e4ca
1 1 /*
2   - * Copyright (C) 2013 Altera Corporation <www.altera.com>
  2 + * Copyright (C) 2013 Altera Corporation <www.altera.com>
3 3 *
4 4 * SPDX-License-Identifier: GPL-2.0+
5 5 */
6 6  
7 7  
8 8  
... ... @@ -7,22 +7,24 @@
7 7 #include <common.h>
8 8 #include <asm/io.h>
9 9 #include <asm/arch/system_manager.h>
  10 +#include <asm/arch/fpga_manager.h>
10 11  
11 12 DECLARE_GLOBAL_DATA_PTR;
12 13  
  14 +static struct socfpga_system_manager *sysmgr_regs =
  15 + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  16 +
13 17 /*
14 18 * Configure all the pin muxes
15 19 */
16 20 void sysmgr_pinmux_init(void)
17 21 {
18   - unsigned long offset = CONFIG_SYSMGR_PINMUXGRP_OFFSET;
  22 + uint32_t regs = (uint32_t)&sysmgr_regs->emacio[0];
  23 + int i;
19 24  
20   - const unsigned long *pval = sys_mgr_init_table;
21   - unsigned long i;
22   -
23   - for (i = 0; i < ARRAY_SIZE(sys_mgr_init_table);
24   - i++, offset += sizeof(unsigned long)) {
25   - writel(*pval++, (SOCFPGA_SYSMGR_ADDRESS + offset));
  25 + for (i = 0; i < ARRAY_SIZE(sys_mgr_init_table); i++) {
  26 + writel(sys_mgr_init_table[i], regs);
  27 + regs += sizeof(regs);
26 28 }
27 29 }
arch/arm/include/asm/arch-socfpga/system_manager.h
Diff comments   View file @ 665e4ca
1 1 /*
2   - * Copyright (C) 2013 Altera Corporation <www.altera.com>
  2 + * Copyright (C) 2013 Altera Corporation <www.altera.com>
3 3 *
4 4 * SPDX-License-Identifier: GPL-2.0+
5 5 */
6 6  
7 7  
8 8  
9 9  
10 10  
11 11  
12 12  
13 13  
14 14  
15 15  
16 16  
17 17  
18 18  
19 19  
20 20  
21 21  
22 22  
23 23  
24 24  
25 25  
26 26  
... ... @@ -16,73 +16,123 @@
16 16  
17 17 #endif
18 18  
19   -
20   -#define CONFIG_SYSMGR_PINMUXGRP_OFFSET (0x400)
21   -
22   -#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
23   - ((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38))
24   -
25 19 struct socfpga_system_manager {
26   - u32 siliconid1;
  20 + /* System Manager Module */
  21 + u32 siliconid1; /* 0x00 */
27 22 u32 siliconid2;
28 23 u32 _pad_0x8_0xf[2];
29   - u32 wddbg;
  24 + u32 wddbg; /* 0x10 */
30 25 u32 bootinfo;
31 26 u32 hpsinfo;
32 27 u32 parityinj;
33   - u32 fpgaintfgrp_gbl;
  28 + /* FPGA Interface Group */
  29 + u32 fpgaintfgrp_gbl; /* 0x20 */
34 30 u32 fpgaintfgrp_indiv;
35 31 u32 fpgaintfgrp_module;
36 32 u32 _pad_0x2c_0x2f;
37   - u32 scanmgrgrp_ctrl;
  33 + /* Scan Manager Group */
  34 + u32 scanmgrgrp_ctrl; /* 0x30 */
38 35 u32 _pad_0x34_0x3f[3];
39   - u32 frzctrl_vioctrl;
  36 + /* Freeze Control Group */
  37 + u32 frzctrl_vioctrl; /* 0x40 */
40 38 u32 _pad_0x44_0x4f[3];
41   - u32 frzctrl_hioctrl;
  39 + u32 frzctrl_hioctrl; /* 0x50 */
42 40 u32 frzctrl_src;
43 41 u32 frzctrl_hwctrl;
44 42 u32 _pad_0x5c_0x5f;
45   - u32 emacgrp_ctrl;
  43 + /* EMAC Group */
  44 + u32 emacgrp_ctrl; /* 0x60 */
46 45 u32 emacgrp_l3master;
47 46 u32 _pad_0x68_0x6f[2];
48   - u32 dmagrp_ctrl;
  47 + /* DMA Controller Group */
  48 + u32 dmagrp_ctrl; /* 0x70 */
49 49 u32 dmagrp_persecurity;
50 50 u32 _pad_0x78_0x7f[2];
51   - u32 iswgrp_handoff[8];
52   - u32 _pad_0xa0_0xbf[8];
53   - u32 romcodegrp_ctrl;
  51 + /* Preloader (initial software) Group */
  52 + u32 iswgrp_handoff[8]; /* 0x80 */
  53 + u32 _pad_0xa0_0xbf[8]; /* 0xa0 */
  54 + /* Boot ROM Code Register Group */
  55 + u32 romcodegrp_ctrl; /* 0xc0 */
54 56 u32 romcodegrp_cpu1startaddr;
55 57 u32 romcodegrp_initswstate;
56 58 u32 romcodegrp_initswlastld;
57   - u32 romcodegrp_bootromswstate;
  59 + u32 romcodegrp_bootromswstate; /* 0xd0 */
58 60 u32 __pad_0xd4_0xdf[3];
59   - u32 romcodegrp_warmramgrp_enable;
  61 + /* Warm Boot from On-Chip RAM Group */
  62 + u32 romcodegrp_warmramgrp_enable; /* 0xe0 */
60 63 u32 romcodegrp_warmramgrp_datastart;
61 64 u32 romcodegrp_warmramgrp_length;
62 65 u32 romcodegrp_warmramgrp_execution;
63   - u32 romcodegrp_warmramgrp_crc;
  66 + u32 romcodegrp_warmramgrp_crc; /* 0xf0 */
64 67 u32 __pad_0xf4_0xff[3];
65   - u32 romhwgrp_ctrl;
  68 + /* Boot ROM Hardware Register Group */
  69 + u32 romhwgrp_ctrl; /* 0x100 */
66 70 u32 _pad_0x104_0x107;
  71 + /* SDMMC Controller Group */
67 72 u32 sdmmcgrp_ctrl;
68 73 u32 sdmmcgrp_l3master;
69   - u32 nandgrp_bootstrap;
  74 + /* NAND Flash Controller Register Group */
  75 + u32 nandgrp_bootstrap; /* 0x110 */
70 76 u32 nandgrp_l3master;
  77 + /* USB Controller Group */
71 78 u32 usbgrp_l3master;
72 79 u32 _pad_0x11c_0x13f[9];
73   - u32 eccgrp_l2;
  80 + /* ECC Management Register Group */
  81 + u32 eccgrp_l2; /* 0x140 */
74 82 u32 eccgrp_ocram;
75 83 u32 eccgrp_usb0;
76 84 u32 eccgrp_usb1;
77   - u32 eccgrp_emac0;
  85 + u32 eccgrp_emac0; /* 0x150 */
78 86 u32 eccgrp_emac1;
79 87 u32 eccgrp_dma;
80 88 u32 eccgrp_can0;
81   - u32 eccgrp_can1;
  89 + u32 eccgrp_can1; /* 0x160 */
82 90 u32 eccgrp_nand;
83 91 u32 eccgrp_qspi;
84 92 u32 eccgrp_sdmmc;
  93 + u32 _pad_0x170_0x3ff[164];
  94 + /* Pin Mux Control Group */
  95 + u32 emacio[20]; /* 0x400 */
  96 + u32 flashio[12]; /* 0x450 */
  97 + u32 generalio[28]; /* 0x480 */
  98 + u32 _pad_0x4f0_0x4ff[4];
  99 + u32 mixed1io[22]; /* 0x500 */
  100 + u32 mixed2io[8]; /* 0x558 */
  101 + u32 gplinmux[23]; /* 0x578 */
  102 + u32 gplmux[71]; /* 0x5d4 */
  103 + u32 nandusefpga; /* 0x6f0 */
  104 + u32 _pad_0x6f4;
  105 + u32 rgmii1usefpga; /* 0x6f8 */
  106 + u32 _pad_0x6fc_0x700[2];
  107 + u32 i2c0usefpga; /* 0x704 */
  108 + u32 sdmmcusefpga; /* 0x708 */
  109 + u32 _pad_0x70c_0x710[2];
  110 + u32 rgmii0usefpga; /* 0x714 */
  111 + u32 _pad_0x718_0x720[3];
  112 + u32 i2c3usefpga; /* 0x724 */
  113 + u32 i2c2usefpga; /* 0x728 */
  114 + u32 i2c1usefpga; /* 0x72c */
  115 + u32 spim1usefpga; /* 0x730 */
  116 + u32 _pad_0x734;
  117 + u32 spim0usefpga; /* 0x738 */
85 118 };
  119 +
  120 +#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX (1 << 0)
  121 +#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO (1 << 1)
  122 +#define SYSMGR_ECC_OCRAM_EN (1 << 0)
  123 +#define SYSMGR_ECC_OCRAM_SERR (1 << 3)
  124 +#define SYSMGR_ECC_OCRAM_DERR (1 << 4)
  125 +#define SYSMGR_FPGAINTF_USEFPGA 0x1
  126 +#define SYSMGR_FPGAINTF_SPIM0 (1 << 0)
  127 +#define SYSMGR_FPGAINTF_SPIM1 (1 << 1)
  128 +#define SYSMGR_FPGAINTF_EMAC0 (1 << 2)
  129 +#define SYSMGR_FPGAINTF_EMAC1 (1 << 3)
  130 +#define SYSMGR_FPGAINTF_NAND (1 << 4)
  131 +#define SYSMGR_FPGAINTF_SDMMC (1 << 5)
  132 +
  133 +/* FIXME: This is questionable macro. */
  134 +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
  135 + ((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38))
86 136  
87 137 #endif /* _SYSTEM_MANAGER_H_ */