clock_am43xx:Set the MAC clock to /5 for OPP100

When EMAC is in the boot order, the boot ROM sets OPP50 and the MAC clock is set to /2. SPL needs to change it to /5 for Ethernet to generate the correct txclk. This patch sets it correctly. Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>

clock_am43xx:Set the MAC clock to /5 for OPP100
When EMAC is in the boot order, the boot ROM sets OPP50 and the MAC clock is set to /2. SPL needs to change it to /5 for Ethernet to generate the correct txclk. This patch sets it correctly. Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Steve Kipisz · Tom Rini
1 parent 1860d10196
Showing 2 changed files with 5 additions and 0 deletions Side-by-side Diff
arch/arm/cpu/armv7/am33xx/clock_am43xx.c
arch/arm/include/asm/arch-am33xx/cpu.h
@@ -118,5 +118,8 @@
  
 	/* Select the Master osc clk as Timer2 clock source */
 	writel(0x1, &cmdpll->clktimer2clk);
+
+	/* For OPP100 the mac clock should be /5. */
+	writel(0x4, &cmdpll->clkselmacclk);
 }
@@ -400,6 +400,8 @@
 struct cm_dpll {
 	unsigned int resv1;
 	unsigned int clktimer2clk;	/* offset 0x04 */
+	unsigned int resv2[11];
+	unsigned int clkselmacclk;	/* offset 0x34 */ 
 };
 #endif /* CONFIG_AM43XX */
...	...	@@ -118,5 +118,8 @@
118	118
119	119	/* Select the Master osc clk as Timer2 clock source */
120	120	writel(0x1, &cmdpll->clktimer2clk);
	121	+
	122	+ /* For OPP100 the mac clock should be /5. */
	123	+ writel(0x4, &cmdpll->clkselmacclk);
121	124	}
...	...	@@ -400,6 +400,8 @@
400	400	struct cm_dpll {
401	401	unsigned int resv1;
402	402	unsigned int clktimer2clk; /* offset 0x04 */
	403	+ unsigned int resv2[11];
	404	+ unsigned int clkselmacclk; /* offset 0x34 */
403	405	};
404	406	#endif /* CONFIG_AM43XX */
405	407