Eric Lee / smarc-uboot

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Commit 6a402cfcea13b6d34f9c9adb036ecc1bcf161139

Authored by Ye Li
1 parent 9df950e799
Exists in smarc_8mq_lf_v2020.04 and in 4 other branches pitx_8mp_lf_v2020.04, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mp_lf_v2020.04

MLK-24958-4 DTS: imx8dxl-evk: Add dedicated DTS for LCD enablemennt 

Because LCDIF has lots of pinmux conflict with modules like eQOS, SPI,
ADC, LPUART1, etc. We can't support it by default.
Introduce a new DTS for LCDIF enablement and disable conflicted nodes.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 39840421d4e2d805df1420658629e78925f41490)

Showing 2 changed files with 84 additions and 0 deletions Side-by-side Diff

arch/arm/dts/Makefile
Diff comments   View file @ 6a402cf
... ... @@ -778,6 +778,7 @@
778 778 fsl-imx8dx-mek.dtb \
779 779 fsl-imx8dxl-phantom-mek.dtb \
780 780 fsl-imx8dxl-evk.dtb \
  781 + fsl-imx8dxl-evk-lcdif.dtb \
781 782 fsl-imx8dxl-ddr3-evk.dtb \
782 783 imx8-deneb.dtb \
783 784 imx8-giedi.dtb
arch/arm/dts/fsl-imx8dxl-evk-lcdif.dts
Diff comments   View file @ 6a402cf
  1 +// SPDX-License-Identifier: GPL-2.0
  2 +/*
  3 + * Copyright 2020 NXP.
  4 + */
  5 +
  6 +#include "fsl-imx8dxl-evk.dts"
  7 +#include "fsl-imx8dxl-evk-u-boot.dtsi"
  8 +
  9 +&eqos {
  10 + status = "disabled";
  11 +};
  12 +
  13 +&lpspi3 {
  14 + status = "disabled";
  15 +};
  16 +
  17 +&iomuxc {
  18 + pinctrl_lcdif: lcdifgrp {
  19 + fsl,pins = <
  20 + SC_P_SPI3_SCK_ADMA_LCDIF_D00 0x00000060
  21 + SC_P_SPI3_SDO_ADMA_LCDIF_D01 0x00000060
  22 + SC_P_SPI3_SDI_ADMA_LCDIF_D02 0x00000060
  23 + SC_P_ENET1_RGMII_TXD3_ADMA_LCDIF_D03 0x00000060
  24 + SC_P_UART1_TX_ADMA_LCDIF_D04 0x00000060
  25 + SC_P_UART1_RX_ADMA_LCDIF_D05 0x00000060
  26 + SC_P_UART1_RTS_B_ADMA_LCDIF_D06 0x00000060
  27 + SC_P_UART1_CTS_B_ADMA_LCDIF_D07 0x00000060
  28 + SC_P_SPI0_SCK_ADMA_LCDIF_D08 0x00000060
  29 + SC_P_SPI0_SDI_ADMA_LCDIF_D09 0x00000060
  30 + SC_P_SPI0_SDO_ADMA_LCDIF_D10 0x00000060
  31 + SC_P_SPI0_CS1_ADMA_LCDIF_D11 0x00000060
  32 + SC_P_SPI0_CS0_ADMA_LCDIF_D12 0x00000060
  33 + SC_P_ADC_IN1_ADMA_LCDIF_D13 0xc600004c
  34 + SC_P_ADC_IN0_ADMA_LCDIF_D14 0xc600004c
  35 + SC_P_ADC_IN3_ADMA_LCDIF_D15 0xc600004c
  36 + SC_P_SPI3_CS0_ADMA_LCDIF_HSYNC 0x00000060
  37 + SC_P_SPI3_CS1_ADMA_LCDIF_RESET 0x00000060
  38 + SC_P_MCLK_IN1_ADMA_LCDIF_EN 0x00000060
  39 + SC_P_MCLK_IN0_ADMA_LCDIF_VSYNC 0x00000060
  40 + SC_P_MCLK_OUT0_ADMA_LCDIF_CLK 0x00000060
  41 + >;
  42 + };
  43 +};
  44 +
  45 +&adma_lcdif {
  46 + pinctrl-names = "default";
  47 + pinctrl-0 = <&pinctrl_lcdif>;
  48 + status = "okay";
  49 +
  50 + assigned-clocks = <&clk IMX8QXP_LCD_SEL>,
  51 + <&clk IMX8QXP_LCD_PXL_SEL>,
  52 + <&clk IMX8QXP_ELCDIF_PLL_DIV>;
  53 + assigned-clock-parents = <&clk IMX8QXP_ELCDIF_PLL_DIV>,
  54 + <&clk IMX8QXP_LCD_PXL_BYPASS_DIV>;
  55 + assigned-clock-rates = <0>, <0>, <711000000>;
  56 +
  57 + display = <&display0>;
  58 +
  59 + display0: display@0 {
  60 + bits-per-pixel = <18>;
  61 + bus-width = <24>;
  62 +
  63 + display-timings {
  64 + native-mode = <&timing0>;
  65 + timing0: timing0 {
  66 + clock-frequency = <71100000>;
  67 + hactive = <1280>;
  68 + vactive = <800>;
  69 + hfront-porch = <70>;
  70 + hback-porch = <80>;
  71 + hsync-len = <10>;
  72 + vback-porch = <10>;
  73 + vfront-porch = <10>;
  74 + vsync-len = <3>;
  75 +
  76 + hsync-active = <0>;
  77 + vsync-active = <0>;
  78 + de-active = <1>;
  79 + pixelclk-active = <0>;
  80 + };
  81 + };
  82 + };
  83 +};