Eric Lee / smarc-uboot

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Commit 9df950e79963c328b1b04d6eb42f43f41217e752

Authored by Ye Li
1 parent dafd6bc77f
Exists in smarc_8mq_lf_v2020.04 and in 4 other branches pitx_8mp_lf_v2020.04, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mp_lf_v2020.04

MLK-24958-3 video: mxsfb: Add iMX8DXL support to LCDIF driver 

Support iMX8DXL in mxsfb driver by below changes:
1. Enable iMX8 in lcdif registers file
2. Add u-boot clock driver support for iMX8
3. Change the FB buffer alignment to align it at allocation. So
   it won't overlay with other memory at mmu_set_region_dcache_behaviour

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 6f02d6894509e0aa79df9d1bdf5029136e1493b5)

Showing 3 changed files with 67 additions and 8 deletions Side-by-side Diff

arch/arm/include/asm/arch-imx8/imx-regs.h
Diff comments   View file @ 9df950e
... ... @@ -6,6 +6,8 @@
6 6 #ifndef __ASM_ARCH_IMX8_REGS_H__
7 7 #define __ASM_ARCH_IMX8_REGS_H__
8 8  
  9 +#include <asm/mach-imx/regs-lcdif.h>
  10 +
9 11 #define ARCH_MXC
10 12  
11 13 #define LPUART_BASE 0x5A060000
arch/arm/include/asm/mach-imx/regs-lcdif.h
Diff comments   View file @ 9df950e
... ... @@ -22,7 +22,7 @@
22 22 defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
23 23 defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
24 24 defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
25   - defined(CONFIG_IMX8M)
  25 + defined(CONFIG_IMX8M) || defined(CONFIG_IMX8)
26 26 mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */
27 27 #endif
28 28 mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */
... ... @@ -61,7 +61,7 @@
61 61 defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
62 62 defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
63 63 defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
64   - defined(CONFIG_IMX8M)
  64 + defined(CONFIG_IMX8M) || defined(CONFIG_IMX8)
65 65 mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */
66 66 #endif
67 67 mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */
... ... @@ -73,7 +73,7 @@
73 73 defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
74 74 defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
75 75 defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
76   - defined(CONFIG_IMX8M)
  76 + defined(CONFIG_IMX8M) || defined(CONFIG_IMX8)
77 77 mxs_reg_32(hw_lcdif_thres)
78 78 mxs_reg_32(hw_lcdif_as_ctrl)
79 79 mxs_reg_32(hw_lcdif_as_buf)
drivers/video/mxsfb.c
Diff comments   View file @ 9df950e
... ... @@ -14,8 +14,11 @@
14 14 #include <malloc.h>
15 15 #include <video.h>
16 16 #include <video_fb.h>
17   -
  17 +#if CONFIG_IS_ENABLED(CLK) && IS_ENABLED(CONFIG_IMX8)
  18 +#include <clk.h>
  19 +#else
18 20 #include <asm/arch/clock.h>
  21 +#endif
19 22 #include <asm/arch/imx-regs.h>
20 23 #include <asm/arch/sys_proto.h>
21 24 #include <asm/mach-imx/dma.h>
22 25  
... ... @@ -74,8 +77,9 @@
74 77 uint8_t valid_data = 0;
75 78  
76 79 /* Kick in the LCDIF clock */
  80 +#if !(CONFIG_IS_ENABLED(CLK) && IS_ENABLED(CONFIG_IMX8))
77 81 mxs_set_lcdclk((u32)reg_base, PS2KHZ(mode->pixclock));
78   -
  82 +#endif
79 83 /* Restart the LCDIF block */
80 84 mxs_reset_block(&regs->hw_lcdif_ctrl_reg);
81 85  
... ... @@ -365,6 +369,12 @@
365 369 struct reset_ctl_bulk soft_resetn;
366 370 struct reset_ctl_bulk clk_enable;
367 371 #endif
  372 +
  373 +#if CONFIG_IS_ENABLED(CLK) && IS_ENABLED(CONFIG_IMX8)
  374 + struct clk lcdif_pix;
  375 + struct clk lcdif_disp_axi;
  376 + struct clk lcdif_axi;
  377 +#endif
368 378 };
369 379  
370 380 #if IS_ENABLED(CONFIG_DM_RESET)
... ... @@ -499,6 +509,38 @@
499 509 if (ret)
500 510 return ret;
501 511  
  512 +#if CONFIG_IS_ENABLED(CLK) && IS_ENABLED(CONFIG_IMX8)
  513 + ret = clk_get_by_name(dev, "pix", &priv->lcdif_pix);
  514 + if (ret) {
  515 + printf("Failed to get pix clk\n");
  516 + return ret;
  517 + }
  518 +
  519 + ret = clk_get_by_name(dev, "disp_axi", &priv->lcdif_disp_axi);
  520 + if (ret) {
  521 + printf("Failed to get disp_axi clk\n");
  522 + return ret;
  523 + }
  524 +
  525 + ret = clk_get_by_name(dev, "axi", &priv->lcdif_axi);
  526 + if (ret) {
  527 + printf("Failed to get axi clk\n");
  528 + return ret;
  529 + }
  530 +
  531 + ret = clk_enable(&priv->lcdif_axi);
  532 + if (ret) {
  533 + printf("unable to enable lcdif_axi clock\n");
  534 + return ret;
  535 + }
  536 +
  537 + ret = clk_enable(&priv->lcdif_disp_axi);
  538 + if (ret) {
  539 + printf("unable to enable lcdif_disp_axi clock\n");
  540 + return ret;
  541 + }
  542 +#endif
  543 +
502 544 #if IS_ENABLED(CONFIG_DM_RESET)
503 545 ret = lcdif_of_parse_resets(dev);
504 546 if (!ret) {
... ... @@ -560,6 +602,20 @@
560 602 mode.vsync_len = timings.vsync_len.typ;
561 603 mode.pixclock = HZ2PS(timings.pixelclock.typ);
562 604  
  605 +#if CONFIG_IS_ENABLED(CLK) && IS_ENABLED(CONFIG_IMX8)
  606 + ret = clk_set_rate(&priv->lcdif_pix, timings.pixelclock.typ);
  607 + if (ret < 0) {
  608 + printf("Failed to set pix clk rate\n");
  609 + return ret;
  610 + }
  611 +
  612 + ret = clk_enable(&priv->lcdif_pix);
  613 + if (ret) {
  614 + printf("unable to enable lcdif_pix clock\n");
  615 + return ret;
  616 + }
  617 +#endif
  618 +
563 619 ret = mxs_probe_common(priv->reg_base, &mode, bpp, plat->base, enable_bridge, enable_pol);
564 620 if (ret)
565 621 return ret;
566 622  
... ... @@ -585,9 +641,9 @@
585 641 uc_priv->ysize = mode.yres;
586 642  
587 643 /* Enable dcache for the frame buffer */
588   - fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
  644 + fb_start = plat->base;
589 645 fb_end = plat->base + plat->size;
590   - fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
  646 +
591 647 mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
592 648 DCACHE_WRITEBACK);
593 649 video_set_flush_dcache(dev, true);
... ... @@ -601,7 +657,8 @@
601 657 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
602 658  
603 659 /* Max size supported by LCDIF, because in bind, we can't probe panel */
604   - plat->size = 1920 * 1080 *4 * 2;
  660 + plat->size = ALIGN(1920 * 1080 *4 * 2, MMU_SECTION_SIZE);
  661 + plat->align = MMU_SECTION_SIZE;
605 662  
606 663 return 0;
607 664 }