driver/ddr: Add 256 byte interleaving support

Freescale LayerScape SoCs support controller interleaving on 256 byte size. This interleaving is mandoratory. Signed-off-by: York Sun <yorksun@freescale.com>

driver/ddr: Add 256 byte interleaving support
Freescale LayerScape SoCs support controller interleaving on 256 byte size. This interleaving is mandoratory. Signed-off-by: York Sun <yorksun@freescale.com>
York Sun · Tom Rini
1 parent 6b9e309a8a
Showing 6 changed files with 26 additions and 2 deletions Side-by-side Diff
README
drivers/ddr/fsl/ctrl_regs.c
drivers/ddr/fsl/main.c
drivers/ddr/fsl/options.c
drivers/ddr/fsl/util.c
include/fsl_ddr_sdram.h
@@ -497,6 +497,11 @@
 		same as CONFIG_SYS_DDR_SDRAM_BASE for  all Power SoCs. But
 		it could be different for ARM SoCs.
  
+		CONFIG_SYS_FSL_DDR_INTLV_256B
+		DDR controller interleaving on 256-byte. This is a special
+		interleaving mode, handled by Dickens for Freescale layerscape
+		SoCs with ARM core.
+
 - Intel Monahans options:
 		CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
  
@@ -145,6 +145,7 @@
 			if (!popts->memctl_interleaving)
 				break;
 			switch (popts->memctl_interleaving_mode) {
+			case FSL_DDR_256B_INTERLEAVING:
 			case FSL_DDR_CACHE_LINE_INTERLEAVING:
 			case FSL_DDR_PAGE_INTERLEAVING:
 			case FSL_DDR_BANK_INTERLEAVING:
@@ -291,6 +291,7 @@
 		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 			if (pinfo->memctl_opts[i].memctl_interleaving) {
 				switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
+				case FSL_DDR_256B_INTERLEAVING:
 				case FSL_DDR_CACHE_LINE_INTERLEAVING:
 				case FSL_DDR_PAGE_INTERLEAVING:
 				case FSL_DDR_BANK_INTERLEAVING:
@@ -818,21 +818,33 @@
 	 * If memory controller interleaving is enabled, then the data
 	 * bus widths must be programmed identically for all memory controllers.
 	 *
-	 * XXX: Attempt to set all controllers to the same chip select
+	 * Attempt to set all controllers to the same chip select
 	 * interleaving mode. It will do a best effort to get the
 	 * requested ranks interleaved together such that the result
 	 * should be a subset of the requested configuration.
+	 *
+	 * if CONFIG_SYS_FSL_DDR_INTLV_256B is defined, mandatory interleaving
+	 * with 256 Byte is enabled.
 	 */
 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
 	if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf))
+#ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
+		;
+#else
 		goto done;
-
+#endif
 	if (pdimm[0].n_ranks == 0) {
 		printf("There is no rank on CS0 for controller %d.\n", ctrl_num);
 		popts->memctl_interleaving = 0;
 		goto done;
 	}
 	popts->memctl_interleaving = 1;
+#ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
+	popts->memctl_interleaving_mode = FSL_DDR_256B_INTERLEAVING;
+	popts->memctl_interleaving = 1;
+	debug("256 Byte interleaving\n");
+	goto done;
+#endif
 	/*
 	 * test null first. if CONFIG_HWCONFIG is not defined
 	 * hwconfig_arg_cmp returns non-zero
@@ -1085,6 +1097,7 @@
 			"Memory controller interleaving disabled.\n");
 	} else {
 		switch (check_intlv) {
+		case FSL_DDR_256B_INTERLEAVING:
 		case FSL_DDR_CACHE_LINE_INTERLEAVING:
 		case FSL_DDR_PAGE_INTERLEAVING:
 		case FSL_DDR_BANK_INTERLEAVING:
@@ -228,6 +228,9 @@
 		puts("       DDR Controller Interleaving Mode: ");
  
 		switch ((cs0_config >> 24) & 0xf) {
+		case FSL_DDR_256B_INTERLEAVING:
+			puts("256B");
+			break;
 		case FSL_DDR_CACHE_LINE_INTERLEAVING:
 			puts("cache line");
 			break;
@@ -76,6 +76,7 @@
 #define FSL_DDR_PAGE_INTERLEAVING	0x1
 #define FSL_DDR_BANK_INTERLEAVING	0x2
 #define FSL_DDR_SUPERBANK_INTERLEAVING	0x3
+#define FSL_DDR_256B_INTERLEAVING	0x8
 #define FSL_DDR_3WAY_1KB_INTERLEAVING	0xA
 #define FSL_DDR_3WAY_4KB_INTERLEAVING	0xC
 #define FSL_DDR_3WAY_8KB_INTERLEAVING	0xD
...	...	@@ -497,6 +497,11 @@
497	497	same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But
498	498	it could be different for ARM SoCs.
499	499
	500	+ CONFIG_SYS_FSL_DDR_INTLV_256B
	501	+ DDR controller interleaving on 256-byte. This is a special
	502	+ interleaving mode, handled by Dickens for Freescale layerscape
	503	+ SoCs with ARM core.
	504	+
500	505	- Intel Monahans options:
501	506	CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
502	507
...	...	@@ -145,6 +145,7 @@
145	145	if (!popts->memctl_interleaving)
146	146	break;
147	147	switch (popts->memctl_interleaving_mode) {
	148	+ case FSL_DDR_256B_INTERLEAVING:
148	149	case FSL_DDR_CACHE_LINE_INTERLEAVING:
149	150	case FSL_DDR_PAGE_INTERLEAVING:
150	151	case FSL_DDR_BANK_INTERLEAVING:
...	...	@@ -291,6 +291,7 @@
291	291	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
292	292	if (pinfo->memctl_opts[i].memctl_interleaving) {
293	293	switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
	294	+ case FSL_DDR_256B_INTERLEAVING:
294	295	case FSL_DDR_CACHE_LINE_INTERLEAVING:
295	296	case FSL_DDR_PAGE_INTERLEAVING:
296	297	case FSL_DDR_BANK_INTERLEAVING:
...	...	@@ -818,21 +818,33 @@
818	818	* If memory controller interleaving is enabled, then the data
819	819	* bus widths must be programmed identically for all memory controllers.
820	820	*
821		- * XXX: Attempt to set all controllers to the same chip select
	821	+ * Attempt to set all controllers to the same chip select
822	822	* interleaving mode. It will do a best effort to get the
823	823	* requested ranks interleaved together such that the result
824	824	* should be a subset of the requested configuration.
	825	+ *
	826	+ * if CONFIG_SYS_FSL_DDR_INTLV_256B is defined, mandatory interleaving
	827	+ * with 256 Byte is enabled.
825	828	*/
826	829	#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
827	830	if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf))
	831	+#ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
	832	+ ;
	833	+#else
828	834	goto done;
829		-
	835	+#endif
830	836	if (pdimm[0].n_ranks == 0) {
831	837	printf("There is no rank on CS0 for controller %d.\n", ctrl_num);
832	838	popts->memctl_interleaving = 0;
833	839	goto done;
834	840	}
835	841	popts->memctl_interleaving = 1;
	842	+#ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
	843	+ popts->memctl_interleaving_mode = FSL_DDR_256B_INTERLEAVING;
	844	+ popts->memctl_interleaving = 1;
	845	+ debug("256 Byte interleaving\n");
	846	+ goto done;
	847	+#endif
836	848	/*
837	849	* test null first. if CONFIG_HWCONFIG is not defined
838	850	* hwconfig_arg_cmp returns non-zero
...	...	@@ -1085,6 +1097,7 @@
1085	1097	"Memory controller interleaving disabled.\n");
1086	1098	} else {
1087	1099	switch (check_intlv) {
	1100	+ case FSL_DDR_256B_INTERLEAVING:
1088	1101	case FSL_DDR_CACHE_LINE_INTERLEAVING:
1089	1102	case FSL_DDR_PAGE_INTERLEAVING:
1090	1103	case FSL_DDR_BANK_INTERLEAVING:
...	...	@@ -228,6 +228,9 @@
228	228	puts(" DDR Controller Interleaving Mode: ");
229	229
230	230	switch ((cs0_config >> 24) & 0xf) {
	231	+ case FSL_DDR_256B_INTERLEAVING:
	232	+ puts("256B");
	233	+ break;
231	234	case FSL_DDR_CACHE_LINE_INTERLEAVING:
232	235	puts("cache line");
233	236	break;
...	...	@@ -76,6 +76,7 @@
76	76	#define FSL_DDR_PAGE_INTERLEAVING 0x1
77	77	#define FSL_DDR_BANK_INTERLEAVING 0x2
78	78	#define FSL_DDR_SUPERBANK_INTERLEAVING 0x3
	79	+#define FSL_DDR_256B_INTERLEAVING 0x8
79	80	#define FSL_DDR_3WAY_1KB_INTERLEAVING 0xA
80	81	#define FSL_DDR_3WAY_4KB_INTERLEAVING 0xC
81	82	#define FSL_DDR_3WAY_8KB_INTERLEAVING 0xD