Eric Lee / smarc-uboot | Embedian Git Server

Commit 6c0bbdccd379f5c8702af9e0765294c2fb7472a6

Authored by Nobuhiro Iwamatsu 2007-09-23 01:31:13 +0800

Exists in master and in 54 other branches

sh: Add support Renesas sh7722 processor and Hitachi MS7722SE01 board

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Showing 7 changed files with 2016 additions and 0 deletions Side-by-side Diff

board/ms7722se/Makefile
board/ms7722se/config.mk
board/ms7722se/lowlevel_init.S
board/ms7722se/ms7722se.c
board/ms7722se/u-boot.lds
include/asm-sh/cpu_sh7722.h
include/configs/ms7722se.h

board/ms7722se/Makefile

Diff comments View file @ 6c0bbdc

	1	+#
	2	+# Copyright (C) 2007
	3	+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
	4	+#
	5	+# Copyright (C) 2007
	6	+# Kenati Technologies, Inc.
	7	+#
	8	+# board/ms7722se/Makefile
	9	+#
	10	+# This program is free software; you can redistribute it and/or
	11	+# modify it under the terms of the GNU General Public License as
	12	+# published by the Free Software Foundation; either version 2 of
	13	+# the License, or (at your option) any later version.
	14	+#
	15	+# This program is distributed in the hope that it will be useful,
	16	+# but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	+# GNU General Public License for more details.
	19	+#
	20	+# You should have received a copy of the GNU General Public License
	21	+# along with this program; if not, write to the Free Software
	22	+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	+# MA 02111-1307 USA
	24	+
	25	+include $(TOPDIR)/config.mk
	26	+
	27	+LIB = lib$(BOARD).a
	28	+
	29	+OBJS := ms7722se.o
	30	+SOBJS := lowlevel_init.o
	31	+
	32	+$(LIB): $(OBJS) $(SOBJS)
	33	+ $(AR) crv $@ $(OBJS) $(SOBJS)
	34	+
	35	+clean:
	36	+ rm -f $(SOBJS) $(OBJS)
	37	+
	38	+distclean: clean
	39	+ rm -f $(LIB) core *.bak .depend
	40	+
	41	+#########################################################################
	42	+
	43	+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
	44	+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
	45	+
	46	+-include .depend
	47	+
	48	+#########################################################################

board/ms7722se/config.mk

Diff comments View file @ 6c0bbdc

	1	+#
	2	+# Copyright (C) 2007
	3	+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
	4	+#
	5	+# Copyright (C) 2007
	6	+# Kenati Technologies, Inc.
	7	+#
	8	+# board/ms7722se/config.mk
	9	+#
	10	+# This program is free software; you can redistribute it and/or
	11	+# modify it under the terms of the GNU General Public License as
	12	+# published by the Free Software Foundation; either version 2 of
	13	+# the License, or (at your option) any later version.
	14	+#
	15	+# This program is distributed in the hope that it will be useful,
	16	+# but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	+# GNU General Public License for more details.
	19	+#
	20	+# You should have received a copy of the GNU General Public License
	21	+# along with this program; if not, write to the Free Software
	22	+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	+# MA 02111-1307 USA
	24	+
	25	+#
	26	+# TEXT_BASE refers to image _after_ relocation.
	27	+#
	28	+# NOTE: Must match value used in u-boot.lds (in this directory).
	29	+#
	30	+
	31	+TEXT_BASE = 0x8FFC0000

board/ms7722se/lowlevel_init.S

Diff comments View file @ 6c0bbdc

	1	+/*
	2	+ * Copyright (C) 2007
	3	+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
	4	+ *
	5	+ * Copyright (C) 2007
	6	+ * Kenati Technologies, Inc.
	7	+ *
	8	+ * board/ms7722se/lowlevel_init.S
	9	+ *
	10	+ * This program is free software; you can redistribute it and/or
	11	+ * modify it under the terms of the GNU General Public License as
	12	+ * published by the Free Software Foundation; either version 2 of
	13	+ * the License, or (at your option) any later version.
	14	+ *
	15	+ * This program is distributed in the hope that it will be useful,
	16	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	+ * GNU General Public License for more details.
	19	+ *
	20	+ * You should have received a copy of the GNU General Public License
	21	+ * along with this program; if not, write to the Free Software
	22	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	+ * MA 02111-1307 USA
	24	+ */
	25	+
	26	+#include <config.h>
	27	+#include <version.h>
	28	+
	29	+#include <asm/processor.h>
	30	+
	31	+/*
	32	+ * Board specific low level init code, called _very_ early in the
	33	+ * startup sequence. Relocation to SDRAM has not happened yet, no
	34	+ * stack is available, bss section has not been initialised, etc.
	35	+ *
	36	+ * (Note: As no stack is available, no subroutines can be called...).
	37	+ */
	38	+
	39	+ .global lowlevel_init
	40	+
	41	+ .text
	42	+ .align 2
	43	+
	44	+lowlevel_init:
	45	+
	46	+ mov.l CCR_A, r1 ! Address of Cache Control Register
	47	+ mov.l CCR_D, r0 ! Instruction Cache Invalidate
	48	+ mov.l r0, @r1
	49	+
	50	+ mov.l MMUCR_A, r1 ! Address of MMU Control Register
	51	+ mov.l MMUCR_D, r0 ! TI == TLB Invalidate bit
	52	+ mov.l r0, @r1
	53	+
	54	+ mov.l MSTPCR0_A, r1 ! Address of Power Control Register 0
	55	+ mov.l MSTPCR0_D, r0 !
	56	+ mov.l r0, @r1
	57	+
	58	+ mov.l MSTPCR2_A, r1 ! Address of Power Control Register 2
	59	+ mov.l MSTPCR2_D, r0 !
	60	+ mov.l r0, @r1
	61	+
	62	+ mov.l SBSCR_A, r1 !
	63	+ mov.w SBSCR_D, r0 !
	64	+ mov.w r0, @r1
	65	+
	66	+ mov.l PSCR_A, r1 !
	67	+ mov.w PSCR_D, r0 !
	68	+ mov.w r0, @r1
	69	+
	70	+! mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register)
	71	+! mov.w RWTCSR_D_1, r0 ! 0xA507 -> timer_STOP/WDT_CLK=max
	72	+! mov.w r0, @r1
	73	+
	74	+ mov.l RWTCNT_A, r1 ! 0xA4520000 (Watchdog Count Register)
	75	+ mov.w RWTCNT_D, r0 ! 0x5A00 -> Clear
	76	+ mov.w r0, @r1
	77	+
	78	+ mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register)
	79	+ mov.w RWTCSR_D_2, r0 ! 0xA504 -> timer_STOP/CLK=500ms
	80	+ mov.w r0, @r1
	81	+
	82	+ mov.l FRQCR_A, r1 ! 0xA4150000 Frequency control register
	83	+ mov.l FRQCR_D, r0 !
	84	+ mov.l r0, @r1
	85	+
	86	+ mov.l CCR_A, r1 ! Address of Cache Control Register
	87	+ mov.l CCR_D_2, r0 ! ??
	88	+ mov.l r0, @r1
	89	+
	90	+bsc_init:
	91	+
	92	+ mov.l PSELA_A, r1
	93	+ mov.w PSELA_D, r0
	94	+ mov.w r0, @r1
	95	+
	96	+ mov.l DRVCR_A, r1
	97	+ mov.w DRVCR_D, r0
	98	+ mov.w r0, @r1
	99	+
	100	+ mov.l PCCR_A, r1
	101	+ mov.w PCCR_D, r0
	102	+ mov.w r0, @r1
	103	+
	104	+ mov.l PECR_A, r1
	105	+ mov.w PECR_D, r0
	106	+ mov.w r0, @r1
	107	+
	108	+ mov.l PJCR_A, r1
	109	+ mov.w PJCR_D, r0
	110	+ mov.w r0, @r1
	111	+
	112	+ mov.l PXCR_A, r1
	113	+ mov.w PXCR_D, r0
	114	+ mov.w r0, @r1
	115	+
	116	+ mov.l CMNCR_A, r1 ! CMNCR address -> R1
	117	+ mov.l CMNCR_D, r0 ! CMNCR data -> R0
	118	+ mov.l r0, @r1 ! CMNCR set
	119	+
	120	+ mov.l CS0BCR_A, r1 ! CS0BCR address -> R1
	121	+ mov.l CS0BCR_D, r0 ! CS0BCR data -> R0
	122	+ mov.l r0, @r1 ! CS0BCR set
	123	+
	124	+ mov.l CS2BCR_A, r1 ! CS2BCR address -> R1
	125	+ mov.l CS2BCR_D, r0 ! CS2BCR data -> R0
	126	+ mov.l r0, @r1 ! CS2BCR set
	127	+
	128	+ mov.l CS4BCR_A, r1 ! CS4BCR address -> R1
	129	+ mov.l CS4BCR_D, r0 ! CS4BCR data -> R0
	130	+ mov.l r0, @r1 ! CS4BCR set
	131	+
	132	+ mov.l CS5ABCR_A, r1 ! CS5ABCR address -> R1
	133	+ mov.l CS5ABCR_D, r0 ! CS5ABCR data -> R0
	134	+ mov.l r0, @r1 ! CS5ABCR set
	135	+
	136	+ mov.l CS5BBCR_A, r1 ! CS5BBCR address -> R1
	137	+ mov.l CS5BBCR_D, r0 ! CS5BBCR data -> R0
	138	+ mov.l r0, @r1 ! CS5BBCR set
	139	+
	140	+ mov.l CS6ABCR_A, r1 ! CS6ABCR address -> R1
	141	+ mov.l CS6ABCR_D, r0 ! CS6ABCR data -> R0
	142	+ mov.l r0, @r1 ! CS6ABCR set
	143	+
	144	+ mov.l CS0WCR_A, r1 ! CS0WCR address -> R1
	145	+ mov.l CS0WCR_D, r0 ! CS0WCR data -> R0
	146	+ mov.l r0, @r1 ! CS0WCR set
	147	+
	148	+ mov.l CS2WCR_A, r1 ! CS2WCR address -> R1
	149	+ mov.l CS2WCR_D, r0 ! CS2WCR data -> R0
	150	+ mov.l r0, @r1 ! CS2WCR set
	151	+
	152	+ mov.l CS4WCR_A, r1 ! CS4WCR address -> R1
	153	+ mov.l CS4WCR_D, r0 ! CS4WCR data -> R0
	154	+ mov.l r0, @r1 ! CS4WCR set
	155	+
	156	+ mov.l CS5AWCR_A, r1 ! CS5AWCR address -> R1
	157	+ mov.l CS5AWCR_D, r0 ! CS5AWCR data -> R0
	158	+ mov.l r0, @r1 ! CS5AWCR set
	159	+
	160	+ mov.l CS5BWCR_A, r1 ! CS5BWCR address -> R1
	161	+ mov.l CS5BWCR_D, r0 ! CS5BWCR data -> R0
	162	+ mov.l r0, @r1 ! CS5BWCR set
	163	+
	164	+ mov.l CS6AWCR_A, r1 ! CS6AWCR address -> R1
	165	+ mov.l CS6AWCR_D, r0 ! CS6AWCR data -> R0
	166	+ mov.l r0, @r1 ! CS6AWCR set
	167	+
	168	+ ! SDRAM initialization
	169	+ mov.l SDCR_A, r1 ! SB_SDCR address -> R1
	170	+ mov.l SDCR_D, r0 ! SB_SDCR data -> R0
	171	+ mov.l r0, @r1 ! SB_SDCR set
	172	+
	173	+ mov.l SDWCR_A, r1 ! SB_SDWCR address -> R1
	174	+ mov.l SDWCR_D, r0 ! SB_SDWCR data -> R0
	175	+ mov.l r0, @r1 ! SB_SDWCR set
	176	+
	177	+ mov.l SDPCR_A, r1 ! SB_SDPCR address -> R1
	178	+ mov.l SDPCR_D, r0 ! SB_SDPCR data -> R0
	179	+ mov.l r0, @r1 ! SB_SDPCR set
	180	+
	181	+ mov.l RTCOR_A, r1 ! SB_RTCOR address -> R1
	182	+ mov.l RTCOR_D, r0 ! SB_RTCOR data -> R0
	183	+ mov.l r0, @r1 ! SB_RTCOR set
	184	+
	185	+ mov.l RTCSR_A, r1 ! SB_RTCSR address -> R1
	186	+ mov.l RTCSR_D, r0 ! SB_RTCSR data -> R0
	187	+ mov.l r0, @r1 ! SB_RTCSR set
	188	+
	189	+ mov.l SDMR3_A, r1 ! SDMR3 address -> R1
	190	+ mov #0x00, r0 ! SDMR3 data -> R0
	191	+ mov.b r0, @r1 ! SDMR3 set
	192	+
	193	+ ! BL bit off (init = ON) (?!?)
	194	+
	195	+ stc sr, r0 ! BL bit off(init=ON)
	196	+ mov.l SR_MASK_D, r1
	197	+ and r1, r0
	198	+ ldc r0, sr
	199	+
	200	+ rts
	201	+ mov #0, r0
	202	+
	203	+
	204	+
	205	+ .align 2
	206	+
	207	+CCR_A: .long CCR
	208	+MMUCR_A: .long MMUCR
	209	+MSTPCR0_A: .long MSTPCR0
	210	+MSTPCR2_A: .long MSTPCR2
	211	+SBSCR_A: .long SBSCR
	212	+PSCR_A: .long PSCR
	213	+RWTCSR_A: .long RWTCSR
	214	+RWTCNT_A: .long RWTCNT
	215	+FRQCR_A: .long FRQCR
	216	+
	217	+CCR_D: .long 0x00000800
	218	+CCR_D_2: .long 0x00000103
	219	+MMUCR_D: .long 0x00000004
	220	+MSTPCR0_D: .long 0x00001001
	221	+MSTPCR2_D: .long 0xffffffff
	222	+FRQCR_D: .long 0x07022538
	223	+
	224	+PSELA_A: .long 0xa405014E
	225	+PSELA_D: .word 0x0A10
	226	+ .align 2
	227	+
	228	+DRVCR_A: .long 0xa405018A
	229	+DRVCR_D: .word 0x0554
	230	+ .align 2
	231	+
	232	+PCCR_A: .long 0xa4050104
	233	+PCCR_D: .word 0x8800
	234	+ .align 2
	235	+
	236	+PECR_A: .long 0xa4050108
	237	+PECR_D: .word 0x0000
	238	+ .align 2
	239	+
	240	+PJCR_A: .long 0xa4050110
	241	+PJCR_D: .word 0x1000
	242	+ .align 2
	243	+
	244	+PXCR_A: .long 0xa4050148
	245	+PXCR_D: .word 0x0AAA
	246	+ .align 2
	247	+
	248	+CMNCR_A: .long CMNCR
	249	+CMNCR_D: .long 0x00000013
	250	+CS0BCR_A: .long CS0BCR ! Flash bank 1
	251	+CS0BCR_D: .long 0x24920400
	252	+CS2BCR_A: .long CS2BCR ! SRAM
	253	+CS2BCR_D: .long 0x24920400
	254	+CS4BCR_A: .long CS4BCR ! FPGA, PCMCIA, USB, ext slot
	255	+CS4BCR_D: .long 0x24920400
	256	+CS5ABCR_A: .long CS5ABCR ! Ext slot
	257	+CS5ABCR_D: .long 0x24920400
	258	+CS5BBCR_A: .long CS5BBCR ! USB controller
	259	+CS5BBCR_D: .long 0x24920400
	260	+CS6ABCR_A: .long CS6ABCR ! Ethernet
	261	+CS6ABCR_D: .long 0x24920400
	262	+
	263	+CS0WCR_A: .long CS0WCR
	264	+CS0WCR_D: .long 0x00000300
	265	+CS2WCR_A: .long CS2WCR
	266	+CS2WCR_D: .long 0x00000300
	267	+CS4WCR_A: .long CS4WCR
	268	+CS4WCR_D: .long 0x00000300
	269	+CS5AWCR_A: .long CS5AWCR
	270	+CS5AWCR_D: .long 0x00000300
	271	+CS5BWCR_A: .long CS5BWCR
	272	+CS5BWCR_D: .long 0x00000300
	273	+CS6AWCR_A: .long CS6AWCR
	274	+CS6AWCR_D: .long 0x00000300
	275	+
	276	+SDCR_A: .long SBSC_SDCR
	277	+SDCR_D: .long 0x00020809
	278	+SDWCR_A: .long SBSC_SDWCR
	279	+SDWCR_D: .long 0x00164d0d
	280	+SDPCR_A: .long SBSC_SDPCR
	281	+SDPCR_D: .long 0x00000087
	282	+RTCOR_A: .long SBSC_RTCOR
	283	+RTCOR_D: .long 0xA55A0034
	284	+RTCSR_A: .long SBSC_RTCSR
	285	+RTCSR_D: .long 0xA55A0010
	286	+SDMR3_A: .long 0xFE500180
	287	+
	288	+ .align 1
	289	+
	290	+SBSCR_D: .word 0x0040
	291	+PSCR_D: .word 0x0000
	292	+RWTCSR_D_1: .word 0xA507
	293	+RWTCSR_D_2: .word 0xA507
	294	+RWTCNT_D: .word 0x5A00
	295	+
	296	+SR_MASK_D: .long 0xEFFFFF0F

board/ms7722se/ms7722se.c

Diff comments View file @ 6c0bbdc

	1	+/*
	2	+ * Copyright (C) 2007
	3	+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
	4	+ *
	5	+ * Copyright (C) 2007
	6	+ * Kenati Technologies, Inc.
	7	+ *
	8	+ * board/ms7722se/ms7722se.c
	9	+ *
	10	+ * This program is free software; you can redistribute it and/or
	11	+ * modify it under the terms of the GNU General Public License as
	12	+ * published by the Free Software Foundation; either version 2 of
	13	+ * the License, or (at your option) any later version.
	14	+ *
	15	+ * This program is distributed in the hope that it will be useful,
	16	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	+ * GNU General Public License for more details.
	19	+ *
	20	+ * You should have received a copy of the GNU General Public License
	21	+ * along with this program; if not, write to the Free Software
	22	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	+ * MA 02111-1307 USA
	24	+ */
	25	+
	26	+#include <common.h>
	27	+#include <asm/io.h>
	28	+#include <asm/processor.h>
	29	+
	30	+#define LED_BASE 0xB0800000
	31	+
	32	+int checkboard(void)
	33	+{
	34	+ puts("BOARD: Hitachi UL MS7722SE\n");
	35	+ return 0;
	36	+}
	37	+
	38	+int board_init(void)
	39	+{
	40	+ /* Setup PTXMD[1:0] for /CS6A */
	41	+ outw(inw(PXCR) & ~0xf000, PXCR);
	42	+
	43	+ return 0;
	44	+}
	45	+
	46	+int dram_init (void)
	47	+{
	48	+ DECLARE_GLOBAL_DATA_PTR;
	49	+
	50	+ gd->bd->bi_memstart = CFG_SDRAM_BASE;
	51	+ gd->bd->bi_memsize = CFG_SDRAM_SIZE;
	52	+ printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
	53	+ return 0;
	54	+}
	55	+
	56	+void led_set_state (unsigned short value)
	57	+{
	58	+ ((volatile unsigned short ) LED_BASE) = (value & 0xFF);
	59	+}

board/ms7722se/u-boot.lds

Diff comments View file @ 6c0bbdc

	1	+/*
	2	+ * Copyrigth (c) 2007
	3	+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+
	24	+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
	25	+OUTPUT_ARCH(sh)
	26	+ENTRY(_start)
	27	+
	28	+SECTIONS
	29	+{
	30	+ /*
	31	+ Base address of internal SDRAM is 0x0C000000.
	32	+ Although size of SDRAM can be either 16 or 32 MBytes,
	33	+ we assume 16 MBytes (ie ignore upper half if the full
	34	+ 32 MBytes is present).
	35	+
	36	+ NOTE: This address must match with the definition of
	37	+ TEXT_BASE in config.mk (in this directory).
	38	+
	39	+ */
	40	+ . = 0x8C000000 + (6410241024) - (256*1024);
	41	+
	42	+ PROVIDE (reloc_dst = .);
	43	+
	44	+ PROVIDE (_ftext = .);
	45	+ PROVIDE (_fcode = .);
	46	+ PROVIDE (_start = .);
	47	+
	48	+ .text :
	49	+ {
	50	+ cpu/sh4/start.o (.text)
	51	+ . = ALIGN(8192);
	52	+ common/environment.o (.ppcenv)
	53	+ . = ALIGN(8192);
	54	+ common/environment.o (.ppcenvr)
	55	+ . = ALIGN(8192);
	56	+ *(.text)
	57	+ . = ALIGN(4);
	58	+ } =0xFF
	59	+ PROVIDE (_ecode = .);
	60	+ .rodata :
	61	+ {
	62	+ *(.rodata)
	63	+ . = ALIGN(4);
	64	+ }
	65	+ PROVIDE (_etext = .);
	66	+
	67	+
	68	+ PROVIDE (_fdata = .);
	69	+ .data :
	70	+ {
	71	+ *(.data)
	72	+ . = ALIGN(4);
	73	+ }
	74	+ PROVIDE (_edata = .);
	75	+
	76	+ PROVIDE (_fgot = .);
	77	+ .got :
	78	+ {
	79	+ *(.got)
	80	+ . = ALIGN(4);
	81	+ }
	82	+ PROVIDE (_egot = .);
	83	+
	84	+ PROVIDE (__u_boot_cmd_start = .);
	85	+ .u_boot_cmd :
	86	+ {
	87	+ *(.u_boot_cmd)
	88	+ . = ALIGN(4);
	89	+ }
	90	+ PROVIDE (__u_boot_cmd_end = .);
	91	+
	92	+ PROVIDE (reloc_dst_end = .);
	93	+ /* _reloc_dst_end = .; */
	94	+
	95	+ PROVIDE (bss_start = .);
	96	+ PROVIDE (__bss_start = .);
	97	+ .bss :
	98	+ {
	99	+ *(.bss)
	100	+ . = ALIGN(4);
	101	+ }
	102	+ PROVIDE (bss_end = .);
	103	+
	104	+ PROVIDE (_end = .);
	105	+}

include/asm-sh/cpu_sh7722.h

Diff comments View file @ 6c0bbdc

Changes suppressed. Click to show

	1	+/*
	2	+ * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
	3	+ *
	4	+ * SH7722 Internal I/O register
	5	+ *
	6	+ * This program is free software; you can redistribute it and/or
	7	+ * modify it under the terms of the GNU General Public License as
	8	+ * published by the Free Software Foundation; either version 2 of
	9	+ * the License, or (at your option) any later version.
	10	+ *
	11	+ * This program is distributed in the hope that it will be useful,
	12	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	+ * GNU General Public License for more details.
	15	+ *
	16	+ * You should have received a copy of the GNU General Public License
	17	+ * along with this program; if not, write to the Free Software
	18	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	19	+ * MA 02111-1307 USA
	20	+ */
	21	+
	22	+#ifndef _ASM_CPU_SH7722_H_
	23	+#define _ASM_CPU_SH7722_H_
	24	+
	25	+#define CACHE_OC_NUM_WAYS 4
	26	+#define CCR_CACHE_INIT 0x0000090d
	27	+
	28	+/* EXP */
	29	+#define TRA 0xFF000020
	30	+#define EXPEVT 0xFF000024
	31	+#define INTEVT 0xFF000028
	32	+
	33	+/* MMU */
	34	+#define PTEH 0xFF000000
	35	+#define PTEL 0xFF000004
	36	+#define TTB 0xFF000008
	37	+#define TEA 0xFF00000C
	38	+#define MMUCR 0xFF000010
	39	+#define PASCR 0xFF000070
	40	+#define IRMCR 0xFF000078
	41	+
	42	+/* CACHE */
	43	+#define CCR 0xFF00001C
	44	+#define RAMCR 0xFF000074
	45	+
	46	+/* XY MEMORY */
	47	+#define XSA 0xFF000050
	48	+#define YSA 0xFF000054
	49	+#define XDA 0xFF000058
	50	+#define YDA 0xFF00005C
	51	+#define XPR 0xFF000060
	52	+#define YPR 0xFF000064
	53	+#define XEA 0xFF000068
	54	+#define YEA 0xFF00006C
	55	+
	56	+/* INTC */
	57	+#define ICR0 0xA4140000
	58	+#define ICR1 0xA414001C
	59	+#define INTPRI0 0xA4140010
	60	+#define INTREQ0 0xA4140024
	61	+#define INTMSK0 0xA4140044
	62	+#define INTMSKCLR0 0xA4140064
	63	+#define NMIFCR 0xA41400C0
	64	+#define USERIMASK 0xA4700000
	65	+#define IPRA 0xA4080000
	66	+#define IPRB 0xA4080004
	67	+#define IPRC 0xA4080008
	68	+#define IPRD 0xA408000C
	69	+#define IPRE 0xA4080010
	70	+#define IPRF 0xA4080014
	71	+#define IPRG 0xA4080018
	72	+#define IPRH 0xA408001C
	73	+#define IPRI 0xA4080020
	74	+#define IPRJ 0xA4080024
	75	+#define IPRK 0xA4080028
	76	+#define IPRL 0xA408002C
	77	+#define IMR0 0xA4080080
	78	+#define IMR1 0xA4080084
	79	+#define IMR2 0xA4080088
	80	+#define IMR3 0xA408008C
	81	+#define IMR4 0xA4080090
	82	+#define IMR5 0xA4080094
	83	+#define IMR6 0xA4080098
	84	+#define IMR7 0xA408009C
	85	+#define IMR8 0xA40800A0
	86	+#define IMR9 0xA40800A4
	87	+#define IMR10 0xA40800A8
	88	+#define IMR11 0xA40800AC
	89	+#define IMCR0 0xA40800C0
	90	+#define IMCR1 0xA40800C4
	91	+#define IMCR2 0xA40800C8
	92	+#define IMCR3 0xA40800CC
	93	+#define IMCR4 0xA40800D0
	94	+#define IMCR5 0xA40800D4
	95	+#define IMCR6 0xA40800D8
	96	+#define IMCR7 0xA40800DC
	97	+#define IMCR8 0xA40800E0
	98	+#define IMCR9 0xA40800E4
	99	+#define IMCR10 0xA40800E8
	100	+#define IMCR11 0xA40800EC
	101	+#define MFI_IPRA 0xA40B0000
	102	+#define MFI_IPRB 0xA40B0004
	103	+#define MFI_IPRC 0xA40B0008
	104	+#define MFI_IPRD 0xA40B000C
	105	+#define MFI_IPRE 0xA40B0010
	106	+#define MFI_IPRF 0xA40B0014
	107	+#define MFI_IPRG 0xA40B0018
	108	+#define MFI_IPRH 0xA40B001C
	109	+#define MFI_IPRI 0xA40B0020
	110	+#define MFI_IPRJ 0xA40B0024
	111	+#define MFI_IPRK 0xA40B0028
	112	+#define MFI_IPRL 0xA40B002C
	113	+#define MFI_IMR0 0xA40B0080
	114	+#define MFI_IMR1 0xA40B0084
	115	+#define MFI_IMR2 0xA40B0088
	116	+#define MFI_IMR3 0xA40B008C
	117	+#define MFI_IMR4 0xA40B0090
	118	+#define MFI_IMR5 0xA40B0094
	119	+#define MFI_IMR6 0xA40B0098
	120	+#define MFI_IMR7 0xA40B009C
	121	+#define MFI_IMR8 0xA40B00A0
	122	+#define MFI_IMR9 0xA40B00A4
	123	+#define MFI_IMR10 0xA40B00A8
	124	+#define MFI_IMR11 0xA40B00AC
	125	+#define MFI_IMCR0 0xA40B00C0
	126	+#define MFI_IMCR1 0xA40B00C4
	127	+#define MFI_IMCR2 0xA40B00C8
	128	+#define MFI_IMCR3 0xA40B00CC
	129	+#define MFI_IMCR4 0xA40B00D0
	130	+#define MFI_IMCR5 0xA40B00D4
	131	+#define MFI_IMCR6 0xA40B00D8
	132	+#define MFI_IMCR7 0xA40B00DC
	133	+#define MFI_IMCR8 0xA40B00E0
	134	+#define MFI_IMCR9 0xA40B00E4
	135	+#define MFI_IMCR10 0xA40B00E8
	136	+#define MFI_IMCR11 0xA40B00EC
	137	+
	138	+/* BSC */
	139	+#define CMNCR 0xFEC10000
	140	+#define CS0BCR 0xFEC10004
	141	+#define CS2BCR 0xFEC10008
	142	+#define CS4BCR 0xFEC10010
	143	+#define CS5ABCR 0xFEC10014
	144	+#define CS5BBCR 0xFEC10018
	145	+#define CS6ABCR 0xFEC1001C
	146	+#define CS6BBCR 0xFEC10020
	147	+#define CS0WCR 0xFEC10024
	148	+#define CS2WCR 0xFEC10028
	149	+#define CS4WCR 0xFEC10030
	150	+#define CS5AWCR 0xFEC10034
	151	+#define CS5BWCR 0xFEC10038
	152	+#define CS6AWCR 0xFEC1003C
	153	+#define CS6BWCR 0xFEC10040
	154	+#define RBWTCNT 0xFEC10054
	155	+
	156	+/* SBSC */
	157	+#define SBSC_SDCR 0xFE400008
	158	+#define SBSC_SDWCR 0xFE40000C
	159	+#define SBSC_SDPCR 0xFE400010
	160	+#define SBSC_RTCSR 0xFE400014
	161	+#define SBSC_RTCNT 0xFE400018
	162	+#define SBSC_RTCOR 0xFE40001C
	163	+#define SBSC_RFCR 0xFE400020
	164	+
	165	+/* DMAC */
	166	+#define SAR_0 0xFE008020
	167	+#define DAR_0 0xFE008024
	168	+#define TCR_0 0xFE008028
	169	+#define CHCR_0 0xFE00802C
	170	+#define SAR_1 0xFE008030
	171	+#define DAR_1 0xFE008034
	172	+#define TCR_1 0xFE008038
	173	+#define CHCR_1 0xFE00803C
	174	+#define SAR_2 0xFE008040
	175	+#define DAR_2 0xFE008044
	176	+#define TCR_2 0xFE008048
	177	+#define CHCR_2 0xFE00804C
	178	+#define SAR_3 0xFE008050
	179	+#define DAR_3 0xFE008054
	180	+#define TCR_3 0xFE008058
	181	+#define CHCR_3 0xFE00805C
	182	+#define SAR_4 0xFE008070
	183	+#define DAR_4 0xFE008074
	184	+#define TCR_4 0xFE008078
	185	+#define CHCR_4 0xFE00807C
	186	+#define SAR_5 0xFE008080
	187	+#define DAR_5 0xFE008084
	188	+#define TCR_5 0xFE008088
	189	+#define CHCR_5 0xFE00808C
	190	+#define SARB_0 0xFE008120
	191	+#define DARB_0 0xFE008124
	192	+#define TCRB_0 0xFE008128
	193	+#define SARB_1 0xFE008130
	194	+#define DARB_1 0xFE008134
	195	+#define TCRB_1 0xFE008138
	196	+#define SARB_2 0xFE008140
	197	+#define DARB_2 0xFE008144
	198	+#define TCRB_2 0xFE008148
	199	+#define SARB_3 0xFE008150
	200	+#define DARB_3 0xFE008154
	201	+#define TCRB_3 0xFE008158
	202	+#define DMAOR 0xFE008060
	203	+#define DMARS_0 0xFE009000
	204	+#define DMARS_1 0xFE009004
	205	+#define DMARS_2 0xFE009008
	206	+
	207	+/* CPG */
	208	+#define FRQCR 0xA4150000
	209	+#define VCLKCR 0xA4150004
	210	+#define SCLKACR 0xA4150008
	211	+#define SCLKBCR 0xA415000C
	212	+#define PLLCR 0xA4150024
	213	+#define DLLFRQ 0xA4150050
	214	+
	215	+/* LOW POWER MODE */
	216	+#define STBCR 0xA4150020
	217	+#define MSTPCR0 0xA4150030
	218	+#define MSTPCR1 0xA4150034
	219	+#define MSTPCR2 0xA4150038
	220	+#define BAR 0xA4150040
	221	+
	222	+/* RWDT */
	223	+#define RWTCNT 0xA4520000
	224	+#define RWTCSR 0xA4520004
	225	+#define WTCNT RWTCNT
	226	+
	227	+
	228	+/* TMU */
	229	+#define TSTR 0xFFD80004
	230	+#define TCOR0 0xFFD80008
	231	+#define TCNT0 0xFFD8000C
	232	+#define TCR0 0xFFD80010
	233	+#define TCOR1 0xFFD80014
	234	+#define TCNT1 0xFFD80018
	235	+#define TCR1 0xFFD8001C
	236	+#define TCOR2 0xFFD80020
	237	+#define TCNT2 0xFFD80024
	238	+#define TCR2 0xFFD80028
	239	+
	240	+/* TPU */
	241	+#define TPU_TSTR 0xA4C90000
	242	+#define TPU_TCR0 0xA4C90010
	243	+#define TPU_TMDR0 0xA4C90014
	244	+#define TPU_TIOR0 0xA4C90018
	245	+#define TPU_TIER0 0xA4C9001C
	246	+#define TPU_TSR0 0xA4C90020
	247	+#define TPU_TCNT0 0xA4C90024
	248	+#define TPU_TGR0A 0xA4C90028
	249	+#define TPU_TGR0B 0xA4C9002C
	250	+#define TPU_TGR0C 0xA4C90030
	251	+#define TPU_TGR0D 0xA4C90034
	252	+#define TPU_TCR1 0xA4C90050
	253	+#define TPU_TMDR1 0xA4C90054
	254	+#define TPU_TIER1 0xA4C9005C
	255	+#define TPU_TSR1 0xA4C90060
	256	+#define TPU_TCNT1 0xA4C90064
	257	+#define TPU_TGR1A 0xA4C90068
	258	+#define TPU_TGR1B 0xA4C9006C
	259	+#define TPU_TGR1C 0xA4C90070
	260	+#define TPU_TGR1D 0xA4C90074
	261	+#define TPU_TCR2 0xA4C90090
	262	+#define TPU_TMDR2 0xA4C90094
	263	+#define TPU_TIER2 0xA4C9009C
	264	+#define TPU_TSR2 0xA4C900A0
	265	+#define TPU_TCNT2 0xA4C900A4
	266	+#define TPU_TGR2A 0xA4C900A8
	267	+#define TPU_TGR2B 0xA4C900AC
	268	+#define TPU_TGR2C 0xA4C900B0
	269	+#define TPU_TGR2D 0xA4C900B4
	270	+#define TPU_TCR3 0xA4C900D0
	271	+#define TPU_TMDR3 0xA4C900D4
	272	+#define TPU_TIER3 0xA4C900DC
	273	+#define TPU_TSR3 0xA4C900E0
	274	+#define TPU_TCNT3 0xA4C900E4
	275	+#define TPU_TGR3A 0xA4C900E8
	276	+#define TPU_TGR3B 0xA4C900EC
	277	+#define TPU_TGR3C 0xA4C900F0
	278	+#define TPU_TGR3D 0xA4C900F4
	279	+
	280	+/* CMT */
	281	+#define CMSTR 0xA44A0000
	282	+#define CMCSR 0xA44A0060
	283	+#define CMCNT 0xA44A0064
	284	+#define CMCOR 0xA44A0068
	285	+
	286	+/* SIO */
	287	+#define SIOMDR 0xA4500000
	288	+#define SIOCTR 0xA4500004
	289	+#define SIOSTBCR0 0xA4500008
	290	+#define SIOSTBCR1 0xA450000C
	291	+#define SIOTDR 0xA4500014
	292	+#define SIORDR 0xA4500018
	293	+#define SIOSTR 0xA450001C
	294	+#define SIOIER 0xA4500020
	295	+#define SIOSCR 0xA4500024
	296	+
	297	+/* SIOF */
	298	+#define SIMDR0 0xA4410000
	299	+#define SISCR0 0xA4410002
	300	+#define SITDAR0 0xA4410004
	301	+#define SIRDAR0 0xA4410006
	302	+#define SICDAR0 0xA4410008
	303	+#define SICTR0 0xA441000C
	304	+#define SIFCTR0 0xA4410010
	305	+#define SISTR0 0xA4410014
	306	+#define SIIER0 0xA4410016
	307	+#define SITDR0 0xA4410020
	308	+#define SIRDR0 0xA4410024
	309	+#define SITCR0 0xA4410028
	310	+#define SIRCR0 0xA441002C
	311	+#define SPICR0 0xA4410030
	312	+#define SIMDR1 0xA4420000
	313	+#define SISCR1 0xA4420002
	314	+#define SITDAR1 0xA4420004
	315	+#define SIRDAR1 0xA4420006
	316	+#define SICDAR1 0xA4420008
	317	+#define SICTR1 0xA442000C
	318	+#define SIFCTR1 0xA4420010
	319	+#define SISTR1 0xA4420014
	320	+#define SIIER1 0xA4420016
	321	+#define SITDR1 0xA4420020
	322	+#define SIRDR1 0xA4420024
	323	+#define SITCR1 0xA4420028
	324	+#define SIRCR1 0xA442002C
	325	+#define SPICR1 0xA4420030
	326	+
	327	+/* SCIF */
	328	+/*
	329	+#define SCSMR 0xFFE00000
	330	+#define SCBRR 0xFFE00004
	331	+#define SCSCR 0xFFE00008
	332	+#define SCFTDR 0xFFE0000C
	333	+#define SCFSR 0xFFE00010
	334	+#define SCFRDR 0xFFE00014
	335	+#define SCFCR 0xFFE00018
	336	+#define SCFDR 0xFFE0001C
	337	+#define SCLSR 0xFFE00024
	338	+#define SCSMR1 0xFFE10000
	339	+#define SCBRR1 0xFFE10004
	340	+#define SCSCR1 0xFFE10008
	341	+#define SCFTDR1 0xFFE1000C
	342	+#define SCFSR1 0xFFE10010
	343	+#define SCFRDR1 0xFFE10014
	344	+#define SCFCR1 0xFFE10018
	345	+#define SCFDR1 0xFFE1001C
	346	+#define SCLSR1 0xFFE10024
	347	+#define SCSMR2 0xFFE20000
	348	+#define SCBRR2 0xFFE20004
	349	+#define SCSCR2 0xFFE20008
	350	+#define SCFTDR2 0xFFE2000C
	351	+#define SCFSR2 0xFFE20010
	352	+#define SCFRDR2 0xFFE20014
	353	+#define SCFCR2 0xFFE20018
	354	+#define SCFDR2 0xFFE2001C
	355	+#define SCLSR2 0xFFE20024
	356	+#define SCSMR3 0xFFE30000
	357	+#define SCBRR3 0xFFE30004
	358	+#define SCSCR3 0xFFE30008
	359	+#define SCFTDR3 0xFFE3000C
	360	+#define SCFSR3 0xFFE30010
	361	+#define SCFRDR3 0xFFE30014
	362	+#define SCFCR3 0xFFE30018
	363	+#define SCFDR3 0xFFE3001C
	364	+#define SCLSR3 0xFFE30024
	365	+*/
	366	+#define SCIF0_BASE 0xFFE00000
	367	+
	368	+/* SIM */
	369	+#define SIM_SCSMR 0xA4490000
	370	+#define SIM_SCBRR 0xA4490002
	371	+#define SIM_SCSCR 0xA4490004
	372	+#define SIM_SCTDR 0xA4490006
	373	+#define SIM_SCSSR 0xA4490008
	374	+#define SIM_SCRDR 0xA449000A
	375	+#define SIM_SCSCMR 0xA449000C
	376	+#define SIM_SCSC2R 0xA449000E
	377	+#define SIM_SCWAIT 0xA4490010
	378	+#define SIM_SCGRD 0xA4490012
	379	+#define SIM_SCSMPL 0xA4490014
	380	+#define SIM_SCDMAEN 0xA4490016
	381	+
	382	+/* IrDA */
	383	+#define IRIF_INIT1 0xA45D0012
	384	+#define IRIF_INIT2 0xA45D0014
	385	+#define IRIF_RINTCLR 0xA45D0016
	386	+#define IRIF_TINTCLR 0xA45D0018
	387	+#define IRIF_SIR0 0xA45D0020
	388	+#define IRIF_SIR1 0xA45D0022
	389	+#define IRIF_SIR2 0xA45D0024
	390	+#define IRIF_SIR3 0xA45D0026
	391	+#define IRIF_SIR_FRM 0xA45D0028
	392	+#define IRIF_SIR_EOF 0xA45D002A
	393	+#define IRIF_SIR_FLG 0xA45D002C
	394	+#define IRIF_SIR_STS2 0xA45D002E
	395	+#define IRIF_UART0 0xA45D0030
	396	+#define IRIF_UART1 0xA45D0032
	397	+#define IRIF_UART2 0xA45D0034
	398	+#define IRIF_UART3 0xA45D0036
	399	+#define IRIF_UART4 0xA45D0038
	400	+#define IRIF_UART5 0xA45D003A
	401	+#define IRIF_UART6 0xA45D003C
	402	+#define IRIF_UART7 0xA45D003E
	403	+#define IRIF_CRC0 0xA45D0040
	404	+#define IRIF_CRC1 0xA45D0042
	405	+#define IRIF_CRC2 0xA45D0044
	406	+#define IRIF_CRC3 0xA45D0046
	407	+#define IRIF_CRC4 0xA45D0048
	408	+
	409	+/* IIC */
	410	+#define ICDR0 0xA4470000
	411	+#define ICCR0 0xA4470004
	412	+#define ICSR0 0xA4470008
	413	+#define ICIC0 0xA447000C
	414	+#define ICCL0 0xA4470010
	415	+#define ICCH0 0xA4470014
	416	+#define ICDR1 0xA4750000
	417	+#define ICCR1 0xA4750004
	418	+#define ICSR1 0xA4750008
	419	+#define ICIC1 0xA475000C
	420	+#define ICCL1 0xA4750010
	421	+#define ICCH1 0xA4750014
	422	+
	423	+/* FLCTL */
	424	+#define FLCMNCR 0xA4530000
	425	+#define FLCMDCR 0xA4530004
	426	+#define FLCMCDR 0xA4530008
	427	+#define FLADR 0xA453000C
	428	+#define FLDATAR 0xA4530010
	429	+#define FLDTCNTR 0xA4530014
	430	+#define FLINTDMACR 0xA4530018
	431	+#define FLBSYTMR 0xA453001C
	432	+#define FLBSYCNT 0xA4530020
	433	+#define FLDTFIFO 0xA4530024
	434	+#define FLECFIFO 0xA4530028
	435	+#define FLTRCR 0xA453002C
	436	+#define FLADR2 0xA453003C
	437	+
	438	+/* MFI */
	439	+#define MFIIDX 0xA4C10000
	440	+#define MFIGSR 0xA4C10004
	441	+#define MFISCR 0xA4C10008
	442	+#define MFIMCR 0xA4C1000C
	443	+#define MFIIICR 0xA4C10010
	444	+#define MFIEICR 0xA4C10014
	445	+#define MFIADR 0xA4C10018
	446	+#define MFIDATA 0xA4C1001C
	447	+#define MFIRCR 0xA4C10020
	448	+#define MFIINTEVT 0xA4C1002C
	449	+#define MFIIMASK 0xA4C10030
	450	+#define MFIBCR 0xA4C10040
	451	+#define MFIADRW 0xA4C10044
	452	+#define MFIADRR 0xA4C10048
	453	+#define MFIDATAW 0xA4C1004C
	454	+#define MFIDATAR 0xA4C10050
	455	+#define MFIMCRW 0xA4C10054
	456	+#define MFIMCRR 0xA4C10058
	457	+#define MFIDNRW 0xA4C1005C
	458	+#define MFIDNRR 0xA4C10060
	459	+#define MFISIZEW 0xA4C10064
	460	+#define MFISIZER 0xA4C10068
	461	+#define MFIDEVCR 0xA4C10038
	462	+#define MFISM4 0xA4C10080
	463	+
	464	+/* VPU */
	465	+#define VP4_CTRL 0xFE900000
	466	+#define VP4_VOL_CTRL 0xFE900004
	467	+#define VP4_IMAGE_SIZE 0xFE900008
	468	+#define VP4_MB_NUM 0xFE90000C
	469	+#define VP4_DWY_ADDR 0xFE900010
	470	+#define VP4_DWC_ADDR 0xFE900014
	471	+#define VP4_D2WY_ADDR 0xFE900018
	472	+#define VP4_D2WC_ADDR 0xFE90001C
	473	+#define VP4_DP1_ADDR 0xFE900020
	474	+#define VP4_DP2_ADDR 0xFE900024
	475	+#define VP4_STRS_ADDR 0xFE900028
	476	+#define VP4_STRE_ADDR 0xFE90002C
	477	+#define VP4_VOP_CTRL 0xFE900030
	478	+#define VP4_VOP_TIME 0xFE900034
	479	+#define VP4_263_CTRL 0xFE900038
	480	+#define VP4_264_CTRL 0xFE90003C
	481	+#define VP4_VLC_CTRL 0xFE900040
	482	+#define VP4_ENDIAN 0xFE900044
	483	+#define VP4_CMD 0xFE900048
	484	+#define VP4_ME_TH1 0xFE90004C
	485	+#define VP4_ME_TH2 0xFE900050
	486	+#define VP4_ME_COSTMB 0xFE900054
	487	+#define VP4_ME_SKIP 0xFE900058
	488	+#define VP4_ME_CTRL 0xFE90005C
	489	+#define VP4_MBRF_CTRL 0xFE900060
	490	+#define VP4_MC_CTRL 0xFE900064
	491	+#define VP4_PRED_CTRL 0xFE900068
	492	+#define VP4_SLC_SIZE 0xFE90006C
	493	+#define VP4_VOP_MINBIT 0xFE900070
	494	+#define VP4_MB_MAXBIT 0xFE900074
	495	+#define VP4_MB_TBIT 0xFE900078
	496	+#define VP4_RCQNT 0xFE90007C
	497	+#define VP4_RCRP 0xFE900080
	498	+#define VP4_RCDJ 0xFE900084
	499	+#define VP4_RCWQ 0xFE900088
	500	+#define VP4_FWD_TIME 0xFE900094
	501	+#define VP4_BWD_TIME 0xFE900098
	502	+#define VP4_PST_TIME 0xFE90009C
	503	+#define VP4_ILTFRAME 0xFE9000A0
	504	+#define VP4_EC_REF 0xFE9000A4
	505	+#define VP4_STATUS 0xFE900100
	506	+#define VP4_IRQ_ENB 0xFE900104
	507	+#define VP4_IRQ_STA 0xFE900108
	508	+#define VP4_VOP_BIT 0xFE90010C
	509	+#define VP4_PRV_BIT 0xFE900110
	510	+#define VP4_SLC_MB 0xFE900114
	511	+#define VP4_QSUM 0xFE900118
	512	+#define VP4_DEC_ERR 0xFE90011C
	513	+#define VP4_ERR_AREA 0xFE900120
	514	+#define VP4_NEXT_CODE 0xFE900124
	515	+#define VP4_MB_ATTR 0xFE900128
	516	+#define VP4_DBMON 0xFE90012C
	517	+#define VP4_DEBUG 0xFE900130
	518	+#define VP4_ERR_DET 0xFE900134
	519	+#define VP4_CLK_STOP 0xFE900138
	520	+#define VP4_MB_SADA 0xFE90013C
	521	+#define VP4_MB_SADR 0xFE900140
	522	+#define VP4_MAT_RAM 0xFE901000
	523	+#define VP4_NC_RAM 0xFE902000
	524	+#define WT 0xFE9020CC
	525	+#define VP4_CPY_ADDR 0xFE902264
	526	+#define VP4_CPC_ADDR 0xFE902268
	527	+#define VP4_R0Y_ADDR 0xFE90226C
	528	+#define VP4_R0C_ADDR 0xFE902270
	529	+#define VP4_R1Y_ADDR 0xFE902274
	530	+#define VP4_R1C_ADDR 0xFE902278
	531	+#define VP4_R2Y_ADDR 0xFE90227C
	532	+#define VP4_R2C_ADDR 0xFE902280
	533	+#define VP4_R3Y_ADDR 0xFE902284
	534	+#define VP4_R3C_ADDR 0xFE902288
	535	+#define VP4_R4Y_ADDR 0xFE90228C
	536	+#define VP4_R4C_ADDR 0xFE902290
	537	+#define VP4_R5Y_ADDR 0xFE902294
	538	+#define VP4_R5C_ADDR 0xFE902298
	539	+#define VP4_R6Y_ADDR 0xFE90229C
	540	+#define VP4_R6C_ADDR 0xFE9022A0
	541	+#define VP4_R7Y_ADDR 0xFE9022A4
	542	+#define VP4_R7C_ADDR 0xFE9022A8
	543	+#define VP4_R8Y_ADDR 0xFE9022AC
	544	+#define VP4_R8C_ADDR 0xFE9022B0
	545	+#define VP4_R9Y_ADDR 0xFE9022B4
	546	+#define VP4_R9C_ADDR 0xFE9022B8
	547	+#define VP4_RAY_ADDR 0xFE9022BC
	548	+#define VP4_RAC_ADDR 0xFE9022C0
	549	+#define VP4_RBY_ADDR 0xFE9022C4
	550	+#define VP4_RBC_ADDR 0xFE9022C8
	551	+#define VP4_RCY_ADDR 0xFE9022CC
	552	+#define VP4_RCC_ADDR 0xFE9022D0
	553	+#define VP4_RDY_ADDR 0xFE9022D4
	554	+#define VP4_RDC_ADDR 0xFE9022D8
	555	+#define VP4_REY_ADDR 0xFE9022DC
	556	+#define VP4_REC_ADDR 0xFE9022E0
	557	+#define VP4_RFY_ADDR 0xFE9022E4
	558	+#define VP4_RFC_ADDR 0xFE9022E8
	559	+
	560	+/* VIO(CEU) */
	561	+#define CAPSR 0xFE910000
	562	+#define CAPCR 0xFE910004
	563	+#define CAMCR 0xFE910008
	564	+#define CMCYR 0xFE91000C
	565	+#define CAMOR 0xFE910010
	566	+#define CAPWR 0xFE910014
	567	+#define CAIFR 0xFE910018
	568	+#define CSTCR 0xFE910020
	569	+#define CSECR 0xFE910024
	570	+#define CRCNTR 0xFE910028
	571	+#define CRCMPR 0xFE91002C
	572	+#define CFLCR 0xFE910030
	573	+#define CFSZR 0xFE910034
	574	+#define CDWDR 0xFE910038
	575	+#define CDAYR 0xFE91003C
	576	+#define CDACR 0xFE910040
	577	+#define CDBYR 0xFE910044
	578	+#define CDBCR 0xFE910048
	579	+#define CBDSR 0xFE91004C
	580	+#define CLFCR 0xFE910060
	581	+#define CDOCR 0xFE910064
	582	+#define CDDCR 0xFE910068
	583	+#define CDDAR 0xFE91006C
	584	+#define CEIER 0xFE910070
	585	+#define CETCR 0xFE910074
	586	+#define CSTSR 0xFE91007C
	587	+#define CSRTR 0xFE910080
	588	+#define CDAYR2 0xFE910090
	589	+#define CDACR2 0xFE910094
	590	+#define CDBYR2 0xFE910098
	591	+#define CDBCR2 0xFE91009C
	592	+
	593	+/* VIO(VEU) */
	594	+#define VESTR 0xFE920000
	595	+#define VESWR 0xFE920010
	596	+#define VESSR 0xFE920014
	597	+#define VSAYR 0xFE920018
	598	+#define VSACR 0xFE92001C
	599	+#define VBSSR 0xFE920020
	600	+#define VEDWR 0xFE920030
	601	+#define VDAYR 0xFE920034
	602	+#define VDACR 0xFE920038
	603	+#define VTRCR 0xFE920050
	604	+#define VRFCR 0xFE920054
	605	+#define VRFSR 0xFE920058
	606	+#define VENHR 0xFE92005C
	607	+#define VFMCR 0xFE920070
	608	+#define VVTCR 0xFE920074
	609	+#define VHTCR 0xFE920078
	610	+#define VAPCR 0xFE920080
	611	+#define VECCR 0xFE920084
	612	+#define VAFXR 0xFE920090
	613	+#define VSWPR 0xFE920094
	614	+#define VEIER 0xFE9200A0
	615	+#define VEVTR 0xFE9200A4
	616	+#define VSTAR 0xFE9200B0
	617	+#define VBSRR 0xFE9200B4
	618	+
	619	+/* VIO(BEU) */
	620	+#define BESTR 0xFE930000
	621	+#define BSMWR1 0xFE930010
	622	+#define BSSZR1 0xFE930014
	623	+#define BSAYR1 0xFE930018
	624	+#define BSACR1 0xFE93001C
	625	+#define BSAAR1 0xFE930020
	626	+#define BSIFR1 0xFE930024
	627	+#define BSMWR2 0xFE930028
	628	+#define BSSZR2 0xFE93002C
	629	+#define BSAYR2 0xFE930030
	630	+#define BSACR2 0xFE930034
	631	+#define BSAAR2 0xFE930038
	632	+#define BSIFR2 0xFE93003C
	633	+#define BSMWR3 0xFE930040
	634	+#define BSSZR3 0xFE930044
	635	+#define BSAYR3 0xFE930048
	636	+#define BSACR3 0xFE93004C
	637	+#define BSAAR3 0xFE930050
	638	+#define BSIFR3 0xFE930054
	639	+#define BTPSR 0xFE930058
	640	+#define BMSMWR1 0xFE930070
	641	+#define BMSSZR1 0xFE930074
	642	+#define BMSAYR1 0xFE930078
	643	+#define BMSACR1 0xFE93007C
	644	+#define BMSMWR2 0xFE930080
	645	+#define BMSSZR2 0xFE930084
	646	+#define BMSAYR2 0xFE930088
	647	+#define BMSACR2 0xFE93008C
	648	+#define BMSMWR3 0xFE930090
	649	+#define BMSSZR3 0xFE930094
	650	+#define BMSAYR3 0xFE930098
	651	+#define BMSACR3 0xFE93009C
	652	+#define BMSMWR4 0xFE9300A0
	653	+#define BMSSZR4 0xFE9300A4
	654	+#define BMSAYR4 0xFE9300A8
	655	+#define BMSACR4 0xFE9300AC
	656	+#define BMSIFR 0xFE9300F0
	657	+#define BBLCR0 0xFE930100
	658	+#define BBLCR1 0xFE930104
	659	+#define BPROCR 0xFE930108
	660	+#define BMWCR0 0xFE93010C
	661	+#define BLOCR1 0xFE930114
	662	+#define BLOCR2 0xFE930118
	663	+#define BLOCR3 0xFE93011C
	664	+#define BMLOCR1 0xFE930120
	665	+#define BMLOCR2 0xFE930124
	666	+#define BMLOCR3 0xFE930128
	667	+#define BMLOCR4 0xFE93012C
	668	+#define BMPCCR1 0xFE930130
	669	+#define BMPCCR2 0xFE930134
	670	+#define BPKFR 0xFE930140
	671	+#define BPCCR0 0xFE930144
	672	+#define BPCCR11 0xFE930148
	673	+#define BPCCR12 0xFE93014C
	674	+#define BPCCR21 0xFE930150
	675	+#define BPCCR22 0xFE930154
	676	+#define BPCCR31 0xFE930158
	677	+#define BPCCR32 0xFE93015C
	678	+#define BDMWR 0xFE930160
	679	+#define BDAYR 0xFE930164
	680	+#define BDACR 0xFE930168
	681	+#define BAFXR 0xFE930180
	682	+#define BSWPR 0xFE930184
	683	+#define BEIER 0xFE930188
	684	+#define BEVTR 0xFE93018C
	685	+#define BRCNTR 0xFE930194
	686	+#define BSTAR 0xFE930198
	687	+#define BBRSTR 0xFE93019C
	688	+#define BRCHR 0xFE9301A0
	689	+#define CLUT 0xFE933000
	690	+
	691	+/* JPU */
	692	+#define JCMOD 0xFEA00000
	693	+#define JCCMD 0xFEA00004
	694	+#define JCSTS 0xFEA00008
	695	+#define JCQTN 0xFEA0000C
	696	+#define JCHTN 0xFEA00010
	697	+#define JCDRIU 0xFEA00014
	698	+#define JCDRID 0xFEA00018
	699	+#define JCVSZU 0xFEA0001C
	700	+#define JCVSZD 0xFEA00020
	701	+#define JCHSZU 0xFEA00024
	702	+#define JCHSZD 0xFEA00028
	703	+#define JCDTCU 0xFEA0002C
	704	+#define JCDTCM 0xFEA00030
	705	+#define JCDTCD 0xFEA00034
	706	+#define JINTE 0xFEA00038
	707	+#define JINTS 0xFEA0003C
	708	+#define JCDERR 0xFEA00040
	709	+#define JCRST 0xFEA00044
	710	+#define JIFCNT 0xFEA00060
	711	+#define JIFECNT 0xFEA00070
	712	+#define JIFESYA1 0xFEA00074
	713	+#define JIFESCA1 0xFEA00078
	714	+#define JIFESYA2 0xFEA0007C
	715	+#define JIFESCA2 0xFEA00080
	716	+#define JIFESMW 0xFEA00084
	717	+#define JIFESVSZ 0xFEA00088
	718	+#define JIFESHSZ 0xFEA0008C
	719	+#define JIFEDA1 0xFEA00090
	720	+#define JIFEDA2 0xFEA00094
	721	+#define JIFEDRSZ 0xFEA00098
	722	+#define JIFDCNT 0xFEA000A0
	723	+#define JIFDSA1 0xFEA000A4
	724	+#define JIFDSA2 0xFEA000A8
	725	+#define JIFDDRSZ 0xFEA000AC
	726	+#define JIFDDMW 0xFEA000B0
	727	+#define JIFDDVSZ 0xFEA000B4
	728	+#define JIFDDHSZ 0xFEA000B8
	729	+#define JIFDDYA1 0xFEA000BC
	730	+#define JIFDDCA1 0xFEA000C0
	731	+#define JIFDDYA2 0xFEA000C4
	732	+#define JIFDDCA2 0xFEA000C8
	733	+#define JCQTBL0 0xFEA10000
	734	+#define JCQTBL1 0xFEA10040
	735	+#define JCQTBL2 0xFEA10080
	736	+#define JCQTBL3 0xFEA100C0
	737	+#define JCHTBD0 0xFEA10100
	738	+#define JCHTBA0 0xFEA10120
	739	+#define JCHTBD1 0xFEA10200
	740	+#define JCHTBA1 0xFEA10220
	741	+
	742	+/* LCDC */
	743	+#define MLDDCKPAT1R 0xFE940400
	744	+#define MLDDCKPAT2R 0xFE940404
	745	+#define SLDDCKPAT1R 0xFE940408
	746	+#define SLDDCKPAT2R 0xFE94040C
	747	+#define LDDCKR 0xFE940410
	748	+#define LDDCKSTPR 0xFE940414
	749	+#define MLDMT1R 0xFE940418
	750	+#define MLDMT2R 0xFE94041C
	751	+#define MLDMT3R 0xFE940420
	752	+#define MLDDFR 0xFE940424
	753	+#define MLDSM1R 0xFE940428
	754	+#define MLDSM2R 0xFE94042C
	755	+#define MLDSA1R 0xFE940430
	756	+#define MLDSA2R 0xFE940434
	757	+#define MLDMLSR 0xFE940438
	758	+#define MLDWBFR 0xFE94043C
	759	+#define MLDWBCNTR 0xFE940440
	760	+#define MLDWBAR 0xFE940444
	761	+#define MLDHCNR 0xFE940448
	762	+#define MLDHSYNR 0xFE94044C
	763	+#define MLDVLNR 0xFE940450
	764	+#define MLDVSYNR 0xFE940454
	765	+#define MLDHPDR 0xFE940458
	766	+#define MLDVPDR 0xFE94045C
	767	+#define MLDPMR 0xFE940460
	768	+#define LDPALCR 0xFE940464
	769	+#define LDINTR 0xFE940468
	770	+#define LDSR 0xFE94046C
	771	+#define LDCNT1R 0xFE940470
	772	+#define LDCNT2R 0xFE940474
	773	+#define LDRCNTR 0xFE940478
	774	+#define LDDDSR 0xFE94047C
	775	+#define LDRCR 0xFE940484
	776	+#define LDCMRKRGBR 0xFE9404C4
	777	+#define LDCMRKCMYR 0xFE9404C8
	778	+#define LDCMRK1R 0xFE9404CC
	779	+#define LDCMRK2R 0xFE9404D0
	780	+#define LDCMGKRGBR 0xFE9404D4
	781	+#define LDCMGKCMYR 0xFE9404D8
	782	+#define LDCMGK1R 0xFE9404DC
	783	+#define LDCMGK2R 0xFE9404E0
	784	+#define LDCMBKRGBR 0xFE9404E4
	785	+#define LDCMBKCMYR 0xFE9404E8
	786	+#define LDCMBK1R 0xFE9404EC
	787	+#define LDCMBK2R 0xFE9404F0
	788	+#define LDCMHKPR 0xFE9404F4
	789	+#define LDCMHKQR 0xFE9404F8
	790	+#define LDCMSELR 0xFE9404FC
	791	+#define LDCMTVR 0xFE940500
	792	+#define LDCMTVSELR 0xFE940504
	793	+#define LDCMDTHR 0xFE940508
	794	+#define LDCMCNTR 0xFE94050C
	795	+#define SLDMT1R 0xFE940600
	796	+#define SLDMT2R 0xFE940604
	797	+#define SLDMT3R 0xFE940608
	798	+#define SLDDFR 0xFE94060C
	799	+#define SLDSM1R 0xFE940610
	800	+#define SLDSM2R 0xFE940614
	801	+#define SLDSA1R 0xFE940618
	802	+#define SLDSA2R 0xFE94061C
	803	+#define SLDMLSR 0xFE940620
	804	+#define SLDHCNR 0xFE940624
	805	+#define SLDHSYNR 0xFE940628
	806	+#define SLDVLNR 0xFE94062C
	807	+#define SLDVSYNR 0xFE940630
	808	+#define SLDHPDR 0xFE940634
	809	+#define SLDVPDR 0xFE940638
	810	+#define SLDPMR 0xFE94063C
	811	+#define LDDWD0R 0xFE940800
	812	+#define LDDWD1R 0xFE940804
	813	+#define LDDWD2R 0xFE940808
	814	+#define LDDWD3R 0xFE94080C
	815	+#define LDDWD4R 0xFE940810
	816	+#define LDDWD5R 0xFE940814
	817	+#define LDDWD6R 0xFE940818
	818	+#define LDDWD7R 0xFE94081C
	819	+#define LDDWD8R 0xFE940820
	820	+#define LDDWD9R 0xFE940824
	821	+#define LDDWDAR 0xFE940828
	822	+#define LDDWDBR 0xFE94082C
	823	+#define LDDWDCR 0xFE940830
	824	+#define LDDWDDR 0xFE940834
	825	+#define LDDWDER 0xFE940838
	826	+#define LDDWDFR 0xFE94083C
	827	+#define LDDRDR 0xFE940840
	828	+#define LDDWAR 0xFE940900
	829	+#define LDDRAR 0xFE940904
	830	+#define LDPR00 0xFE940000
	831	+
	832	+/* VOU */
	833	+#define VOUER 0xFE960000
	834	+#define VOUCR 0xFE960004
	835	+#define VOUSTR 0xFE960008
	836	+#define VOUVCR 0xFE96000C
	837	+#define VOUISR 0xFE960010
	838	+#define VOUBCR 0xFE960014
	839	+#define VOUDPR 0xFE960018
	840	+#define VOUDSR 0xFE96001C
	841	+#define VOUVPR 0xFE960020
	842	+#define VOUIR 0xFE960024
	843	+#define VOUSRR 0xFE960028
	844	+#define VOUMSR 0xFE96002C
	845	+#define VOUHIR 0xFE960030
	846	+#define VOUDFR 0xFE960034
	847	+#define VOUAD1R 0xFE960038
	848	+#define VOUAD2R 0xFE96003C
	849	+#define VOUAIR 0xFE960040
	850	+#define VOUSWR 0xFE960044
	851	+#define VOURCR 0xFE960048
	852	+#define VOURPR 0xFE960050
	853	+
	854	+/* TSIF */
	855	+#define TSCTLR 0xA4C80000
	856	+#define TSPIDR 0xA4C80004
	857	+#define TSCMDR 0xA4C80008
	858	+#define TSSTR 0xA4C8000C
	859	+#define TSTSDR 0xA4C80010
	860	+#define TSBUFCLRR 0xA4C80014
	861	+#define TSINTER 0xA4C80018
	862	+#define TSPSCALER 0xA4C80020
	863	+#define TSPSCALERR 0xA4C80024
	864	+#define TSPCRADCMDR 0xA4C80028
	865	+#define TSPCRADCR 0xA4C8002C
	866	+#define TSTRPCRADCR 0xA4C80030
	867	+#define TSDPCRADCR 0xA4C80034
	868	+
	869	+/* SIU */
	870	+#define IFCTL 0xA454C000
	871	+#define SRCTL 0xA454C004
	872	+#define SFORM 0xA454C008
	873	+#define CKCTL 0xA454C00C
	874	+#define TRDAT 0xA454C010
	875	+#define STFIFO 0xA454C014
	876	+#define DPAK 0xA454C01C
	877	+#define CKREV 0xA454C020
	878	+#define EVNTC 0xA454C028
	879	+#define SBCTL 0xA454C040
	880	+#define SBPSET 0xA454C044
	881	+#define SBBUS 0xA454C048
	882	+#define SBWFLG 0xA454C058
	883	+#define SBRFLG 0xA454C05C
	884	+#define SBWDAT 0xA454C060
	885	+#define SBRDAT 0xA454C064
	886	+#define SBFSTS 0xA454C068
	887	+#define SBDVCA 0xA454C06C
	888	+#define SBDVCB 0xA454C070
	889	+#define SBACTIV 0xA454C074
	890	+#define DMAIA 0xA454C090
	891	+#define DMAIB 0xA454C094
	892	+#define DMAOA 0xA454C098
	893	+#define DMAOB 0xA454C09C
	894	+#define SPLRI 0xA454C0B8
	895	+#define SPRRI 0xA454C0BC
	896	+#define SPURI 0xA454C0C4
	897	+#define SPTIS 0xA454C0C8
	898	+#define SPSTS 0xA454C0CC
	899	+#define SPCTL 0xA454C0D0
	900	+#define SPIRI 0xA454C0D4
	901	+#define SPQCF 0xA454C0D8
	902	+#define SPQCS 0xA454C0DC
	903	+#define SPQCT 0xA454C0E0
	904	+#define DPEAK 0xA454C0F0
	905	+#define DSLPD 0xA454C0F4
	906	+#define DSLLV 0xA454C0F8
	907	+#define BRGASEL 0xA454C100
	908	+#define BRRA 0xA454C104
	909	+#define BRGBSEL 0xA454C108
	910	+#define BRRB 0xA454C10C
	911	+
	912	+/* USB */
	913	+#define IFR0 0xA4480000
	914	+#define ISR0 0xA4480010
	915	+#define IER0 0xA4480020
	916	+#define EPDR0I 0xA4480030
	917	+#define EPDR0O 0xA4480034
	918	+#define EPDR0S 0xA4480038
	919	+#define EPDR1 0xA448003C
	920	+#define EPDR2 0xA4480040
	921	+#define EPDR3 0xA4480044
	922	+#define EPDR4 0xA4480048
	923	+#define EPDR5 0xA448004C
	924	+#define EPDR6 0xA4480050
	925	+#define EPDR7 0xA4480054
	926	+#define EPDR8 0xA4480058
	927	+#define EPDR9 0xA448005C
	928	+#define EPSZ0O 0xA4480080
	929	+#define EPSZ3 0xA4480084
	930	+#define EPSZ6 0xA4480088
	931	+#define EPSZ9 0xA448008C
	932	+#define TRG 0xA44800A0
	933	+#define DASTS 0xA44800A4
	934	+#define FCLR 0xA44800AA
	935	+#define DMA 0xA44800AC
	936	+#define EPSTL 0xA44800B2
	937	+#define CVR 0xA44800B4
	938	+#define TSR 0xA44800B8
	939	+#define CTLR 0xA44800BC
	940	+#define EPIR 0xA44800C0
	941	+#define XVERCR 0xA44800D0
	942	+#define STLMR 0xA44800D4
	943	+
	944	+/* KEYSC */
	945	+#define KYCR1 0xA44B0000
	946	+#define KYCR2 0xA44B0004
	947	+#define KYINDR 0xA44B0008
	948	+#define KYOUTDR 0xA44B000C
	949	+
	950	+/* MMCIF */
	951	+#define CMDR0 0xA4448000
	952	+#define CMDR1 0xA4448001
	953	+#define CMDR2 0xA4448002
	954	+#define CMDR3 0xA4448003
	955	+#define CMDR4 0xA4448004
	956	+#define CMDR5 0xA4448005
	957	+#define CMDSTRT 0xA4448006
	958	+#define OPCR 0xA444800A
	959	+#define CSTR 0xA444800B
	960	+#define INTCR0 0xA444800C
	961	+#define INTCR1 0xA444800D
	962	+#define INTSTR0 0xA444800E
	963	+#define INTSTR1 0xA444800F
	964	+#define CLKON 0xA4448010
	965	+#define CTOCR 0xA4448011
	966	+#define VDCNT 0xA4448012
	967	+#define TBCR 0xA4448014
	968	+#define MODER 0xA4448016
	969	+#define CMDTYR 0xA4448018
	970	+#define RSPTYR 0xA4448019
	971	+#define TBNCR 0xA444801A
	972	+#define RSPR0 0xA4448020
	973	+#define RSPR1 0xA4448021
	974	+#define RSPR2 0xA4448022
	975	+#define RSPR3 0xA4448023
	976	+#define RSPR4 0xA4448024
	977	+#define RSPR5 0xA4448025
	978	+#define RSPR6 0xA4448026
	979	+#define RSPR7 0xA4448027
	980	+#define RSPR8 0xA4448028
	981	+#define RSPR9 0xA4448029
	982	+#define RSPR10 0xA444802A
	983	+#define RSPR11 0xA444802B
	984	+#define RSPR12 0xA444802C
	985	+#define RSPR13 0xA444802D
	986	+#define RSPR14 0xA444802E
	987	+#define RSPR15 0xA444802F
	988	+#define RSPR16 0xA4448030
	989	+#define RSPRD 0xA4448031
	990	+#define DTOUTR 0xA4448032
	991	+#define DR 0xA4448040
	992	+#define FIFOCLR 0xA4448042
	993	+#define DMACR 0xA4448044
	994	+#define INTCR2 0xA4448046
	995	+#define INTSTR2 0xA4448048
	996	+
	997	+/* Z3D3 */
	998	+#define DLBI 0xFD980000
	999	+#define DLBD0 0xFD980080
	1000	+#define DLBD1 0xFD980100
	1001	+#define GEWM 0xFD984000
	1002	+#define ICD0 0xFD988000
	1003	+#define ICD1 0xFD989000
	1004	+#define ICT 0xFD98A000
	1005	+#define ILM 0xFD98C000
	1006	+#define FLM0 0xFD98C800
	1007	+#define FLM1 0xFD98D000
	1008	+#define FLUT 0xFD98D800
	1009	+#define Z3D_PC 0xFD98E400
	1010	+#define Z3D_PCSP 0xFD98E404
	1011	+#define Z3D_PAR 0xFD98E408
	1012	+#define Z3D_IMADR 0xFD98E40C
	1013	+#define Z3D_BTR0 0xFD98E410
	1014	+#define Z3D_BTR1 0xFD98E414
	1015	+#define Z3D_BTR2 0xFD98E418
	1016	+#define Z3D_BTR3 0xFD98E41C
	1017	+#define Z3D_LC0 0xFD98E420
	1018	+#define Z3D_LC1 0xFD98E424
	1019	+#define Z3D_LC2 0xFD98E428
	1020	+#define Z3D_LC3 0xFD98E42C
	1021	+#define Z3D_FR0 0xFD98E430
	1022	+#define Z3D_FR1 0xFD98E434
	1023	+#define Z3D_FR2 0xFD98E438
	1024	+#define Z3D_SR 0xFD98E440
	1025	+#define Z3D_SMDR 0xFD98E444
	1026	+#define Z3D_PBIR 0xFD98E448
	1027	+#define Z3D_DMDR 0xFD98E44C
	1028	+#define Z3D_IREG 0xFD98E460
	1029	+#define Z3D_AR00 0xFD98E480
	1030	+#define Z3D_AR01 0xFD98E484
	1031	+#define Z3D_AR02 0xFD98E488
	1032	+#define Z3D_AR03 0xFD98E48C
	1033	+#define Z3D_BR00 0xFD98E490
	1034	+#define Z3D_BR01 0xFD98E494
	1035	+#define Z3D_IXR00 0xFD98E4A0
	1036	+#define Z3D_IXR01 0xFD98E4A4
	1037	+#define Z3D_IXR02 0xFD98E4A8
	1038	+#define Z3D_IXR03 0xFD98E4AC
	1039	+#define Z3D_AR10 0xFD98E4C0
	1040	+#define Z3D_AR11 0xFD98E4C4
	1041	+#define Z3D_AR12 0xFD98E4C8
	1042	+#define Z3D_AR13 0xFD98E4CC
	1043	+#define Z3D_BR10 0xFD98E4D0
	1044	+#define Z3D_BR11 0xFD98E4D4
	1045	+#define Z3D_IXR10 0xFD98E4E0
	1046	+#define Z3D_IXR11 0xFD98E4E4
	1047	+#define Z3D_IXR12 0xFD98E4E8
	1048	+#define Z3D_IXR13 0xFD98E4EC
	1049	+#define Z3D_AR20 0xFD98E500
	1050	+#define Z3D_AR21 0xFD98E504
	1051	+#define Z3D_AR22 0xFD98E508
	1052	+#define Z3D_AR23 0xFD98E50C
	1053	+#define Z3D_BR20 0xFD98E510
	1054	+#define Z3D_BR21 0xFD98E514
	1055	+#define Z3D_IXR20 0xFD98E520
	1056	+#define Z3D_IXR21 0xFD98E524
	1057	+#define Z3D_IXR22 0xFD98E528
	1058	+#define Z3D_IXR23 0xFD98E52C
	1059	+#define Z3D_MR0 0xFD98E540
	1060	+#define Z3D_MR1 0xFD98E544
	1061	+#define Z3D_MR2 0xFD98E548
	1062	+#define Z3D_MR3 0xFD98E54C
	1063	+#define Z3D_WORKRST 0xFD98E558
	1064	+#define Z3D_WORKWST 0xFD98E55C
	1065	+#define Z3D_DBADR 0xFD98E560
	1066	+#define Z3D_DLBPRST 0xFD98E564
	1067	+#define Z3D_DLBRST 0xFD98E568
	1068	+#define Z3D_DLBWST 0xFD98E56C
	1069	+#define Z3D_UDR0 0xFD98E570
	1070	+#define Z3D_UDR1 0xFD98E574
	1071	+#define Z3D_UDR2 0xFD98E578
	1072	+#define Z3D_UDR3 0xFD98E57C
	1073	+#define Z3D_CCR0 0xFD98E580
	1074	+#define Z3D_CCR1 0xFD98E584
	1075	+#define Z3D_EXPR 0xFD98E588
	1076	+#define Z3D_V0_X 0xFD9A0000
	1077	+#define Z3D_V0_Y 0xFD9A0004
	1078	+#define Z3D_V0_Z 0xFD9A0008
	1079	+#define Z3D_V0_W 0xFD9A000C
	1080	+#define Z3D_V0_A 0xFD9A0010
	1081	+#define Z3D_V0_R 0xFD9A0014
	1082	+#define Z3D_V0_G 0xFD9A0018
	1083	+#define Z3D_V0_B 0xFD9A001C
	1084	+#define Z3D_V0_F 0xFD9A0020
	1085	+#define Z3D_V0_SR 0xFD9A0024
	1086	+#define Z3D_V0_SG 0xFD9A0028
	1087	+#define Z3D_V0_SB 0xFD9A002C
	1088	+#define Z3D_V0_U0 0xFD9A0030
	1089	+#define Z3D_V0_V0 0xFD9A0034
	1090	+#define Z3D_V0_U1 0xFD9A0038
	1091	+#define Z3D_V0_V1 0xFD9A003C
	1092	+#define Z3D_V1_X 0xFD9A0080
	1093	+#define Z3D_V1_Y 0xFD9A0084
	1094	+#define Z3D_V1_Z 0xFD9A0088
	1095	+#define Z3D_V1_W 0xFD9A008C
	1096	+#define Z3D_V1_A 0xFD9A0090
	1097	+#define Z3D_V1_R 0xFD9A0094
	1098	+#define Z3D_V1_G 0xFD9A0098
	1099	+#define Z3D_V1_B 0xFD9A009C
	1100	+#define Z3D_V1_F 0xFD9A00A0
	1101	+#define Z3D_V1_SR 0xFD9A00A4
	1102	+#define Z3D_V1_SG 0xFD9A00A8
	1103	+#define Z3D_V1_SB 0xFD9A00AC
	1104	+#define Z3D_V1_U0 0xFD9A00B0
	1105	+#define Z3D_V1_V0 0xFD9A00B4
	1106	+#define Z3D_V1_U1 0xFD9A00B8
	1107	+#define Z3D_V1_V1 0xFD9A00BC
	1108	+#define Z3D_V2_X 0xFD9A0100
	1109	+#define Z3D_V2_Y 0xFD9A0104
	1110	+#define Z3D_V2_Z 0xFD9A0108
	1111	+#define Z3D_V2_W 0xFD9A010C
	1112	+#define Z3D_V2_A 0xFD9A0110
	1113	+#define Z3D_V2_R 0xFD9A0114
	1114	+#define Z3D_V2_G 0xFD9A0118
	1115	+#define Z3D_V2_B 0xFD9A011C
	1116	+#define Z3D_V2_F 0xFD9A0120
	1117	+#define Z3D_V2_SR 0xFD9A0124
	1118	+#define Z3D_V2_SG 0xFD9A0128
	1119	+#define Z3D_V2_SB 0xFD9A012C
	1120	+#define Z3D_V2_U0 0xFD9A0130
	1121	+#define Z3D_V2_V0 0xFD9A0134
	1122	+#define Z3D_V2_U1 0xFD9A0138
	1123	+#define Z3D_V2_V1 0xFD9A013C
	1124	+#define Z3D_RENDER 0xFD9A0180
	1125	+#define Z3D_POLYGON_OFFSET 0xFD9A0184
	1126	+#define Z3D_VERTEX_CONTROL 0xFD9A0200
	1127	+#define Z3D_STATE_MODE 0xFD9A0204
	1128	+#define Z3D_FPU_MODE 0xFD9A0318
	1129	+#define Z3D_SCISSOR_MIN 0xFD9A0400
	1130	+#define Z3D_SCISSOR_MAX 0xFD9A0404
	1131	+#define Z3D_TEXTURE_MODE_A 0xFD9A0408
	1132	+#define Z3D_TEXTURE_MODE_B 0xFD9A040C
	1133	+#define Z3D_TEXTURE_BASE_HI_A 0xFD9A0418
	1134	+#define Z3D_TEXTURE_BASE_LO_A 0xFD9A041C
	1135	+#define Z3D_TEXTURE_BASE_HI_B 0xFD9A0420
	1136	+#define Z3D_TEXTURE_BASE_LO_B 0xFD9A0424
	1137	+#define Z3D_TEXTURE_ALPHA_A0 0xFD9A0438
	1138	+#define Z3D_TEXTURE_ALPHA_A1 0xFD9A043C
	1139	+#define Z3D_TEXTURE_ALPHA_A2 0xFD9A0440
	1140	+#define Z3D_TEXTURE_ALPHA_A3 0xFD9A0444
	1141	+#define Z3D_TEXTURE_ALPHA_A4 0xFD9A0448
	1142	+#define Z3D_TEXTURE_ALPHA_A5 0xFD9A044C
	1143	+#define Z3D_TEXTURE_ALPHA_B0 0xFD9A0450
	1144	+#define Z3D_TEXTURE_ALPHA_B1 0xFD9A0454
	1145	+#define Z3D_TEXTURE_ALPHA_B2 0xFD9A0458
	1146	+#define Z3D_TEXTURE_ALPHA_B3 0xFD9A045C
	1147	+#define Z3D_TEXTURE_ALPHA_B4 0xFD9A0460
	1148	+#define Z3D_TEXTURE_ALPHA_B5 0xFD9A0464
	1149	+#define Z3D_TEXTURE_FLUSH 0xFD9A0498
	1150	+#define Z3D_GAMMA_TABLE0 0xFD9A049C
	1151	+#define Z3D_GAMMA_TABLE1 0xFD9A04A0
	1152	+#define Z3D_GAMMA_TABLE2 0xFD9A04A4
	1153	+#define Z3D_ALPHA_TEST 0xFD9A0800
	1154	+#define Z3D_STENCIL_TEST 0xFD9A0804
	1155	+#define Z3D_DEPTH_ROP_BLEND_DITHER 0xFD9A0808
	1156	+#define Z3D_MASK 0xFD9A080C
	1157	+#define Z3D_FBUS_MODE 0xFD9A0810
	1158	+#define Z3D_GNT_SET 0xFD9A0814
	1159	+#define Z3D_BETWEEN_TEST 0xFD9A0818
	1160	+#define Z3D_FB_BASE 0xFD9A081C
	1161	+#define Z3D_LCD_SIZE 0xFD9A0820
	1162	+#define Z3D_FB_FLUSH 0xFD9A0824
	1163	+#define Z3D_CACHE_INVALID 0xFD9A0828
	1164	+#define Z3D_SC_MODE 0xFD9A0830
	1165	+#define Z3D_SC0_MIN 0xFD9A0834
	1166	+#define Z3D_SC0_MAX 0xFD9A0838
	1167	+#define Z3D_SC1_MIN 0xFD9A083C
	1168	+#define Z3D_SC1_MAX 0xFD9A0840
	1169	+#define Z3D_SC2_MIN 0xFD9A0844
	1170	+#define Z3D_SC2_MAX 0xFD9A0848
	1171	+#define Z3D_SC3_MIN 0xFD9A084C
	1172	+#define Z3D_SC3_MAX 0xFD9A0850
	1173	+#define Z3D_READRESET 0xFD9A0854
	1174	+#define Z3D_DET_MIN 0xFD9A0858
	1175	+#define Z3D_DET_MAX 0xFD9A085C
	1176	+#define Z3D_FB_BASE_SR 0xFD9A0860
	1177	+#define Z3D_LCD_SIZE_SR 0xFD9A0864
	1178	+#define Z3D_2D_CTRL_STATUS 0xFD9A0C00
	1179	+#define Z3D_2D_SIZE 0xFD9A0C04
	1180	+#define Z3D_2D_SRCLOC 0xFD9A0C08
	1181	+#define Z3D_2D_DSTLOC 0xFD9A0C0C
	1182	+#define Z3D_2D_DMAPORT 0xFD9A0C10
	1183	+#define Z3D_2D_CONSTANT_SOURCE0 0xFD9A0C14
	1184	+#define Z3D_2D_CONSTANT_SOURCE1 0xFD9A0C18
	1185	+#define Z3D_2D_STPCOLOR0 0xFD9A0C1C
	1186	+#define Z3D_2D_STPCOLOR1 0xFD9A0C20
	1187	+#define Z3D_2D_STPPARAMETER_SET0 0xFD9A0C24
	1188	+#define Z3D_2D_STPPARAMETER_SET1 0xFD9A0C28
	1189	+#define Z3D_2D_STPPAT_0 0xFD9A0C40
	1190	+#define Z3D_2D_STPPAT_1 0xFD9A0C44
	1191	+#define Z3D_2D_STPPAT_2 0xFD9A0C48
	1192	+#define Z3D_2D_STPPAT_3 0xFD9A0C4C
	1193	+#define Z3D_2D_STPPAT_4 0xFD9A0C50
	1194	+#define Z3D_2D_STPPAT_5 0xFD9A0C54
	1195	+#define Z3D_2D_STPPAT_6 0xFD9A0C58
	1196	+#define Z3D_2D_STPPAT_7 0xFD9A0C5C
	1197	+#define Z3D_2D_STPPAT_8 0xFD9A0C60
	1198	+#define Z3D_2D_STPPAT_9 0xFD9A0C64
	1199	+#define Z3D_2D_STPPAT_10 0xFD9A0C68
	1200	+#define Z3D_2D_STPPAT_11 0xFD9A0C6C
	1201	+#define Z3D_2D_STPPAT_12 0xFD9A0C70
	1202	+#define Z3D_2D_STPPAT_13 0xFD9A0C74
	1203	+#define Z3D_2D_STPPAT_14 0xFD9A0C78
	1204	+#define Z3D_2D_STPPAT_15 0xFD9A0C7C
	1205	+#define Z3D_2D_STPPAT_16 0xFD9A0C80
	1206	+#define Z3D_2D_STPPAT_17 0xFD9A0C84
	1207	+#define Z3D_2D_STPPAT_18 0xFD9A0C88
	1208	+#define Z3D_2D_STPPAT_19 0xFD9A0C8C
	1209	+#define Z3D_2D_STPPAT_20 0xFD9A0C90
	1210	+#define Z3D_2D_STPPAT_21 0xFD9A0C94
	1211	+#define Z3D_2D_STPPAT_22 0xFD9A0C98
	1212	+#define Z3D_2D_STPPAT_23 0xFD9A0C9C
	1213	+#define Z3D_2D_STPPAT_24 0xFD9A0CA0
	1214	+#define Z3D_2D_STPPAT_25 0xFD9A0CA4
	1215	+#define Z3D_2D_STPPAT_26 0xFD9A0CA8
	1216	+#define Z3D_2D_STPPAT_27 0xFD9A0CAC
	1217	+#define Z3D_2D_STPPAT_28 0xFD9A0CB0
	1218	+#define Z3D_2D_STPPAT_29 0xFD9A0CB4
	1219	+#define Z3D_2D_STPPAT_30 0xFD9A0CB8
	1220	+#define Z3D_2D_STPPAT_31 0xFD9A0CBC
	1221	+#define Z3D_WR_CTRL 0xFD9A1000
	1222	+#define Z3D_WR_P0 0xFD9A1004
	1223	+#define Z3D_WR_P1 0xFD9A1008
	1224	+#define Z3D_WR_P2 0xFD9A100C
	1225	+#define Z3D_WR_FGC 0xFD9A1010
	1226	+#define Z3D_WR_BGC 0xFD9A1014
	1227	+#define Z3D_WR_SZ 0xFD9A1018
	1228	+#define Z3D_WR_PATPARAM 0xFD9A101C
	1229	+#define Z3D_WR_PAT 0xFD9A1020
	1230	+#define Z3D_SYS_STATUS 0xFD9A1400
	1231	+#define Z3D_SYS_RESET 0xFD9A1404
	1232	+#define Z3D_SYS_CLK 0xFD9A1408
	1233	+#define Z3D_SYS_CONF 0xFD9A140C
	1234	+#define Z3D_SYS_VERSION 0xFD9A1410
	1235	+#define Z3D_SYS_DBINV 0xFD9A1418
	1236	+#define Z3D_SYS_I2F_FMT 0xFD9A1420
	1237	+#define Z3D_SYS_I2F_SRC 0xFD9A1424
	1238	+#define Z3D_SYS_I2F_DST 0xFD9A1428
	1239	+#define Z3D_SYS_GBCNT 0xFD9A1430
	1240	+#define Z3D_SYS_BSYCNT 0xFD9A1434
	1241	+#define Z3D_SYS_INT_STATUS 0xFD9A1450
	1242	+#define Z3D_SYS_INT_MASK 0xFD9A1454
	1243	+#define Z3D_SYS_INT_CLEAR 0xFD9A1458
	1244	+#define TCD0 0xFD9C0000
	1245	+#define TCD1 0xFD9C0400
	1246	+#define TCD2 0xFD9C0800
	1247	+#define TCD3 0xFD9C0C00
	1248	+#define TCT0 0xFD9C1000
	1249	+#define TCT1 0xFD9C1400
	1250	+#define TCT2 0xFD9C1800
	1251	+#define TCT3 0xFD9C1C00
	1252	+
	1253	+/* PFC */
	1254	+#define PACR 0xA4050100
	1255	+#define PBCR 0xA4050102
	1256	+#define PCCR 0xA4050104
	1257	+#define PDCR 0xA4050106
	1258	+#define PECR 0xA4050108
	1259	+#define PFCR 0xA405010A
	1260	+#define PGCR 0xA405010C
	1261	+#define PHCR 0xA405010E
	1262	+#define PJCR 0xA4050110
	1263	+#define PKCR 0xA4050112
	1264	+#define PLCR 0xA4050114
	1265	+#define PMCR 0xA4050116
	1266	+#define PNCR 0xA4050118
	1267	+#define PQCR 0xA405011A
	1268	+#define PRCR 0xA405011C
	1269	+#define PSCR 0xA405011E
	1270	+#define PTCR 0xA4050140
	1271	+#define PUCR 0xA4050142
	1272	+#define PVCR 0xA4050144
	1273	+#define PWCR 0xA4050146
	1274	+#define PXCR 0xA4050148
	1275	+#define PYCR 0xA405014A
	1276	+#define PZCR 0xA405014C
	1277	+#define PSELA 0xA405014E
	1278	+#define PSELB 0xA4050150
	1279	+#define PSELC 0xA4050152
	1280	+#define PSELD 0xA4050154
	1281	+#define PSELE 0xA4050156
	1282	+#define HIZCRA 0xA4050158
	1283	+#define HIZCRB 0xA405015A
	1284	+#define HIZCRC 0xA405015C
	1285	+#define MSELCR 0xA405015C
	1286	+#define PULCR 0xA405015E
	1287	+#define DRVCR 0xA4050180
	1288	+#define SBSCR 0xA4050182
	1289	+#define AUDTHCR 0xA4050184
	1290	+#define PSELF 0xA4050186
	1291	+
	1292	+/* I/O Port */
	1293	+#define PADR 0xA4050120
	1294	+#define PBDR 0xA4050122
	1295	+#define PCDR 0xA4050124
	1296	+#define PDDR 0xA4050126
	1297	+#define PEDR 0xA4050128
	1298	+#define PFDR 0xA405012A
	1299	+#define PGDR 0xA405012C
	1300	+#define PHDR 0xA405012E
	1301	+#define PJDR 0xA4050130
	1302	+#define PKDR 0xA4050132
	1303	+#define PLDR 0xA4050134
	1304	+#define PMDR 0xA4050136
	1305	+#define PNDR 0xA4050138
	1306	+#define PQDR 0xA405013A
	1307	+#define PRDR 0xA405013C
	1308	+#define PSDR 0xA405013E
	1309	+#define PTDR 0xA4050160
	1310	+#define PUDR 0xA4050162
	1311	+#define PVDR 0xA4050164
	1312	+#define PWDR 0xA4050166
	1313	+#define PYDR 0xA4050168
	1314	+#define PZDR 0xA405016A
	1315	+
	1316	+/* UBC */
	1317	+#define CBR0 0xFF200000
	1318	+#define CRR0 0xFF200004
	1319	+#define CAR0 0xFF200008
	1320	+#define CAMR0 0xFF20000C
	1321	+#define CBR1 0xFF200020
	1322	+#define CRR1 0xFF200024
	1323	+#define CAR1 0xFF200028
	1324	+#define CAMR1 0xFF20002C
	1325	+#define CDR1 0xFF200030
	1326	+#define CDMR1 0xFF200034
	1327	+#define CETR1 0xFF200038
	1328	+#define CCMFR 0xFF200600
	1329	+#define CBCR 0xFF200620
	1330	+
	1331	+/* H-UDI */
	1332	+#define SDIR 0xFC110000
	1333	+#define SDDRH 0xFC110008
	1334	+#define SDDRL 0xFC11000A
	1335	+#define SDINT 0xFC110018
	1336	+
	1337	+#endif /* _ASM_CPU_SH7722_H_ */

include/configs/ms7722se.h

Diff comments View file @ 6c0bbdc

	1	+/*
	2	+ * Configuation settings for the Hitachi Solution Engine 7722
	3	+ *
	4	+ * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
	5	+ *
	6	+ * See file CREDITS for list of people who contributed to this
	7	+ * project.
	8	+ *
	9	+ * This program is free software; you can redistribute it and/or
	10	+ * modify it under the terms of the GNU General Public License as
	11	+ * published by the Free Software Foundation; either version 2 of
	12	+ * the License, or (at your option) any later version.
	13	+ *
	14	+ * This program is distributed in the hope that it will be useful,
	15	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	+ * GNU General Public License for more details.
	18	+ *
	19	+ * You should have received a copy of the GNU General Public License
	20	+ * along with this program; if not, write to the Free Software
	21	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	+ * MA 02111-1307 USA
	23	+ */
	24	+
	25	+#ifndef __MS7722SE_H
	26	+#define __MS7722SE_H
	27	+
	28	+#undef DEBUG
	29	+#define CONFIG_SH 1
	30	+#define CONFIG_SH4 1
	31	+#define CONFIG_CPU_SH7722 1
	32	+#define CONFIG_MS7722SE 1
	33	+
	34	+#define CONFIG_CMD_FLASH
	35	+#define CONFIG_CMD_NET
	36	+#define CONFIG_CMD_PING
	37	+#define CONFIG_CMD_DFL
	38	+#define CONFIG_CMD_SDRAM
	39	+#define CONFIG_CMD_ENV
	40	+
	41	+#define CONFIG_BAUDRATE 115200
	42	+#define CONFIG_BOOTDELAY 3
	43	+#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01"
	44	+#define CONFIG_NETMASK 255.255.255.0
	45	+#define CONFIG_IPADDR 192.168.0.22
	46	+#define CONFIG_SERVERIP 192.168.0.1
	47	+#define CONFIG_GATEWAYIP 192.168.0.1
	48	+
	49	+#define CONFIG_VERSION_VARIABLE
	50	+#undef CONFIG_SHOW_BOOT_PROGRESS
	51	+
	52	+/* SMC9111 */
	53	+#define CONFIG_DRIVER_SMC91111
	54	+#define CONFIG_SMC91111_BASE (0xB8000000)
	55	+
	56	+/* MEMORY */
	57	+#define MS7722SE_SDRAM_BASE (0x8C000000)
	58	+#define MS7722SE_FLASH_BASE_1 (0xA0000000)
	59	+//#define MS7722SE_FLASH_BASE_1 (0xA1000000)
	60	+#define MS7722SE_FLASH_BANK_SIZE (81024 1024)
	61	+
	62	+#define CFG_LONGHELP /* undef to save memory */
	63	+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	64	+#define CFG_CBSIZE 256 /* Buffer size for input from the Console */
	65	+#define CFG_PBSIZE 256 /* Buffer size for Console output */
	66	+#define CFG_MAXARGS 16 /* max args accepted for monitor commands */
	67	+#define CFG_BARGSIZE 512 /* Buffer size for Boot Arguments passed to kernel */
	68	+#define CFG_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */
	69	+
	70	+/* SCIF */
	71	+#define CFG_SCIF_CONSOLE 1
	72	+#define CONFIG_CONS_SCIF0 1
	73	+#undef CFG_CONSOLE_INFO_QUIET /* Suppress display of console information at boot */
	74	+#undef CFG_CONSOLE_OVERWRITE_ROUTINE
	75	+#undef CFG_CONSOLE_ENV_OVERWRITE
	76	+
	77	+#define CFG_MEMTEST_START (MS7722SE_SDRAM_BASE)
	78	+#define CFG_MEMTEST_END (CFG_MEMTEST_START + (60 * 1024 * 1024))
	79	+
	80	+#undef CFG_ALT_MEMTEST /* Enable alternate, more extensive, memory test */
	81	+#undef CFG_MEMTEST_SCRATCH /* Scratch address used by the alternate memory test */
	82	+
	83	+#undef CFG_LOADS_BAUD_CHANGE /* Enable temporary baudrate change while serial download */
	84	+
	85	+#define CFG_SDRAM_BASE (MS7722SE_SDRAM_BASE)
	86	+#define CFG_SDRAM_SIZE (64 * 1024 * 1024) /* maybe more, but if so u-boot doesn't know about it... */
	87	+
	88	+#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 4 * 1024 * 1024) /* default load address for scripts ?!? */
	89	+
	90	+#define CFG_MONITOR_BASE (MS7722SE_FLASH_BASE_1) /* Address of u-boot image
	91	+ in Flash (NOT run time address in SDRAM) ?!? */
	92	+#define CFG_MONITOR_LEN (128 * 1024) /* */
	93	+#define CFG_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */
	94	+#define CFG_GBL_DATA_SIZE (256) /* size in bytes reserved for initial data */
	95	+#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
	96	+
	97	+/* FLASH */
	98	+#define CFG_FLASH_CFI
	99	+#define CFG_FLASH_CFI_DRIVER
	100	+#undef CFG_FLASH_QUIET_TEST
	101	+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
	102	+
	103	+#define CFG_FLASH_BASE (MS7722SE_FLASH_BASE_1) /* Physical start address of Flash memory */
	104	+
	105	+#define CFG_MAX_FLASH_SECT 150 /* Max number of sectors on each
	106	+ Flash chip */
	107	+
	108	+/* if you use all NOR Flash , you change dip-switch. Please see MS7722SE01 Manual. */
	109	+#define CFG_MAX_FLASH_BANKS 2
	110	+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE + (0 * MS7722SE_FLASH_BANK_SIZE), \
	111	+ CFG_FLASH_BASE + (1 * MS7722SE_FLASH_BANK_SIZE), \
	112	+ }
	113	+
	114	+#define CFG_FLASH_ERASE_TOUT (3 * 1000) /* Timeout for Flash erase operations (in ms) */
	115	+#define CFG_FLASH_WRITE_TOUT (3 * 1000) /* Timeout for Flash write operations (in ms) */
	116	+#define CFG_FLASH_LOCK_TOUT (3 * 1000) /* Timeout for Flash set sector lock bit operations (in ms) */
	117	+#define CFG_FLASH_UNLOCK_TOUT (3 * 1000) /* Timeout for Flash clear lock bit operations (in ms) */
	118	+
	119	+#undef CFG_FLASH_PROTECTION /* Use hardware flash sectors protection instead of U-Boot software protection */
	120	+
	121	+#undef CFG_DIRECT_FLASH_TFTP
	122	+
	123	+#define CFG_ENV_IS_IN_FLASH
	124	+#define CONFIG_ENV_OVERWRITE 1
	125	+#define CFG_ENV_SECT_SIZE (8 * 1024)
	126	+#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
	127	+#define CFG_ENV_ADDR (CFG_FLASH_BASE + (1 * CFG_ENV_SECT_SIZE))
	128	+#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE) /* Offset of env Flash sector relative to CFG_FLASH_BASE */
	129	+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SECT_SIZE)
	130	+#define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + (2 * CFG_ENV_SECT_SIZE))
	131	+
	132	+/* Board Clock */
	133	+#define CONFIG_SYS_CLK_FREQ 33333333
	134	+#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
	135	+#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
	136	+
	137	+#endif /* __MS7722SE_H */