Commit 6d8abe6a8a5981685687a0f2fd660e034d974824
Committed by
Tom Rini
Tom Rini
1 parent
9b4d65f918
Exists in
v2017.01-smarct4x
and in
37 other branches
ARM: OMAP: Change set_pl310_ctrl_reg to be generic
set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup PL310 control register, however, that is something that is generic enough to be used for OMAP5 generation of processors as well. The only difference being the service being invoked for the function. So, convert the service to a macro and use a generic name (same as that used in Linux for some consistency). While at that, also add a data barrier which is necessary as per recommendation. While at this, smc #0 is maintained as handcoded assembly thanks to various gcc version eccentricities, discussion thread: http://marc.info/?t=142542166800001&r=1&w=2 Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Showing 4 changed files with 18 additions and 10 deletions Side-by-side Diff
arch/arm/cpu/armv7/omap-common/lowlevel_init.S
| ... | ... | @@ -22,12 +22,16 @@ |
| 22 | 22 | b save_boot_params_ret |
| 23 | 23 | ENDPROC(save_boot_params) |
| 24 | 24 | |
| 25 | -ENTRY(set_pl310_ctrl_reg) | |
| 26 | - PUSH {r4-r11, lr} @ save registers - ROM code may pollute | |
| 25 | +ENTRY(omap_smc1) | |
| 26 | + PUSH {r4-r12, lr} @ save registers - ROM code may pollute | |
| 27 | 27 | @ our registers |
| 28 | - LDR r12, =0x102 @ Set PL310 control register - value in R0 | |
| 29 | - .word 0xe1600070 @ SMC #0 - hand assembled because -march=armv5 | |
| 30 | - @ call ROM Code API to set control register | |
| 31 | - POP {r4-r11, pc} | |
| 32 | -ENDPROC(set_pl310_ctrl_reg) | |
| 28 | + MOV r12, r0 @ Service | |
| 29 | + MOV r0, r1 @ Argument | |
| 30 | + DSB | |
| 31 | + DMB | |
| 32 | + .word 0xe1600070 @ SMC #0 - hand assembled for GCC versions | |
| 33 | + @ call ROM Code API for the service requested | |
| 34 | + | |
| 35 | + POP {r4-r12, pc} | |
| 36 | +ENDPROC(omap_smc1) |
arch/arm/cpu/armv7/omap4/hwinit.c
| ... | ... | @@ -159,12 +159,12 @@ |
| 159 | 159 | #ifndef CONFIG_SYS_L2CACHE_OFF |
| 160 | 160 | void v7_outer_cache_enable(void) |
| 161 | 161 | { |
| 162 | - set_pl310_ctrl_reg(1); | |
| 162 | + omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 1); | |
| 163 | 163 | } |
| 164 | 164 | |
| 165 | 165 | void v7_outer_cache_disable(void) |
| 166 | 166 | { |
| 167 | - set_pl310_ctrl_reg(0); | |
| 167 | + omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 0); | |
| 168 | 168 | } |
| 169 | 169 | #endif /* !CONFIG_SYS_L2CACHE_OFF */ |
arch/arm/include/asm/arch-omap4/sys_proto.h
| ... | ... | @@ -37,7 +37,6 @@ |
| 37 | 37 | void set_muxconf_regs_essential(void); |
| 38 | 38 | u32 wait_on_value(u32, u32, void *, u32); |
| 39 | 39 | void sdelay(unsigned long); |
| 40 | -void set_pl310_ctrl_reg(u32 val); | |
| 41 | 40 | void setup_clocks_for_console(void); |
| 42 | 41 | void prcm_init(void); |
| 43 | 42 | void bypass_dpll(u32 const base); |
| ... | ... | @@ -57,5 +56,8 @@ |
| 57 | 56 | u32 warm_reset(void); |
| 58 | 57 | void force_emif_self_refresh(void); |
| 59 | 58 | void setup_warmreset_time(void); |
| 59 | + | |
| 60 | +#define OMAP4_SERVICE_PL310_CONTROL_REG_SET 0x102 | |
| 61 | + | |
| 60 | 62 | #endif |
arch/arm/include/asm/omap_common.h