* Patches by Martin Krause, 14 Jul 2003:

- add I2C support for s3c2400 systems (trab board) - (re-) add "ping" to command table * Fix handling of "slow" POST routines

* Patches by Martin Krause, 14 Jul 2003:
- add I2C support for s3c2400 systems (trab board) - (re-) add "ping" to command table * Fix handling of "slow" POST routines
wdenk
1 parent 8564acf936
Showing 11 changed files with 110 additions and 39 deletions Side-by-side Diff
CHANGELOG
README
board/lwmon/lwmon.c
board/trab/trab.c
common/cmd_net.c
drivers/s3c24x0_i2c.c
include/asm-ppc/global_data.h
include/configs/trab.h
lib_i386/board.c
lib_ppc/board.c
post/post.c
@@ -2,6 +2,12 @@
 Changes for U-Boot 0.4.3:
 ======================================================================
  
+* Patches by Martin Krause, 14 Jul 2003:
+  - add I2C support for s3c2400 systems (trab board)
+  - (re-) add "ping" to command table
+
+* Fix handling of "slow" POST routines
+
 * Patches by Yuli Barcohen, 13 Jul 2003:
   - Correct flash and JFFS2 support for MPC8260ADS
   - fix PVR values and clock generation for PowerQUICC II family
@@ -3048,6 +3048,11 @@
   version of diff does not support these options, then get the latest
   version of GNU diff.
  
+  The current directory when running this command shall be the top
+  level directory of the U-Boot source tree, or it's parent directory
+  (i. e. please make sure that your patch includes sufficient
+  directory information for the affected files).
+
   We accept patches as plain text, MIME attachments or as uuencoded
   gzipped text.
  
@@ -1087,8 +1087,7 @@
 	i2c_write (kbd_addr, 0, 0, &val, 1);
 	i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
  
-	return (gd->post_hotkeys_latch = 
-			(compare_magic(kbd_data, CONFIG_POST_KEY_MAGIC) == 0));
+	return (compare_magic(kbd_data, CONFIG_POST_KEY_MAGIC) == 0);
 }
 #endif
@@ -130,6 +130,11 @@
 	}
 #endif	/* CONFIG_MODEM_SUPPORT */
  
+#ifdef CONFIG_DRIVER_S3C24X0_I2C
+	/* Configure I/O ports PG5 und PG6 for I2C */
+ 	gpio->PGCON = (gpio->PGCON & 0x003c00) | 0x003c00;
+#endif /* CONFIG_DRIVER_S3C24X0_I2C */
+
 	return 0;
 }
  
@@ -210,6 +210,12 @@
  
 	return 0;
 }
+
+U_BOOT_CMD(
+	ping,	2,	1,	do_ping,
+	"ping    - send ICMP ECHO_REQUEST to network host\n",
+	"pingAddress\n"
+);
 #endif	/* CFG_CMD_PING */
  
 #endif	/* CFG_CMD_NET */
@@ -63,7 +63,12 @@
 {
 	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
  
+#ifdef CONFIG_S3C2410
 	return (gpio->GPEDAT & 0x8000) >> 15;
+#endif
+#ifdef CONFIG_S3C2400
+	return (gpio->PGDAT & 0x0020) >> 5;
+#endif
 }
  
 #if 0
  
@@ -77,7 +82,12 @@
 {
 	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
  
+#ifdef CONFIG_S3C2410
 	gpio->GPEDAT = (gpio->GPEDAT & ~0x4000) | (x&1) << 14;
+#endif
+#ifdef CONFIG_S3C2400
+	gpio->PGDAT = (gpio->PGDAT & ~0x0040) | (x&1) << 6;
+#endif
 }
  
  
  
  
  
@@ -129,11 +139,22 @@
     }
  
     if ((status & I2CSTAT_BSY) || GetI2CSDA() == 0) {
+#ifdef CONFIG_S3C2410
 	ulong old_gpecon = gpio->GPECON;
+#endif
+#ifdef CONFIG_S3C2400
+	ulong old_gpecon = gpio->PGCON;
+#endif
 	/* bus still busy probably by (most) previously interrupted transfer */
  
+#ifdef CONFIG_S3C2410
 	/* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
 	gpio->GPECON = (gpio->GPECON & ~0xF0000000) | 0x10000000;
+#endif
+#ifdef CONFIG_S3C2400
+	/* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */
+	gpio->PGCON = (gpio->PGCON & ~0x00003c00) | 0x00000c00;
+#endif
  
 	/* toggle I2CSCL until bus idle */
 	SetI2CSCL(0); udelay(1000);
  
@@ -146,7 +167,12 @@
 	SetI2CSCL(1); udelay(1000);
  
 	/* restore pin functions */
+#ifdef CONFIG_S3C2410
 	gpio->GPECON = old_gpecon;
+#endif
+#ifdef CONFIG_S3C2400
+	gpio->PGCON = old_gpecon;
+#endif
     }
  
     /* calculate prescaler and divisor values */
@@ -73,7 +73,6 @@
 #ifdef CONFIG_POST
 	unsigned long	post_log_word;  /* Record POST activities */
 	unsigned long	post_init_f_time;  /* When post_init_f started */
-	unsigned long	post_hotkeys_latch; /* If the post hotkeys pressed */
 #endif
 #ifdef CONFIG_BOARD_TYPES
 	unsigned long	board_type;
@@ -37,9 +37,9 @@
  * (easy to change)
  */
 #define CONFIG_ARM920T		1	/* This is an arm920t CPU	*/
-#define CONFIG_S3C2400		1	/* in a SAMSUNG S3C2400 SoC     */
-#define CONFIG_TRAB		1	/* on a TRAB Board      */
-#undef CONFIG_TRAB_50MHZ		/* run the CPU at 50 MHz */
+#define CONFIG_S3C2400		1	/* in a SAMSUNG S3C2400 SoC	*/
+#define CONFIG_TRAB		1	/* on a TRAB Board		*/
+#undef CONFIG_TRAB_50MHZ		/* run the CPU at 50 MHz	*/
  
 /* input clock of PLL */
 #define CONFIG_SYS_CLK_FREQ	12000000 /* TRAB has 12 MHz input clock */
@@ -50,6 +50,23 @@
 #define CONFIG_SETUP_MEMORY_TAGS 1
 #define CONFIG_INITRD_TAG	 1
  
+
+/***********************************************************
+ * I2C stuff:
+ * the TRAB is equipped with an ATMEL 24C04 EEPROM at
+ * address 0x54 with 8bit addressing
+ ***********************************************************/
+#define CONFIG_HARD_I2C			/* I2C with hardware support */
+#define CFG_I2C_SPEED 		100000	/* I2C speed */
+#define CFG_I2C_SLAVE 		0x7F	/* I2C slave addr */
+
+#define CFG_I2C_EEPROM_ADDR	0x54	/* EEPROM address */
+#define CFG_I2C_EEPROM_ADDR_LEN	1	/* 1 address byte */
+
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
+#define CFG_EEPROM_PAGE_WRITE_BITS 3	/* 8 bytes page write mode on 24C04 */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
 /*
  * Size of malloc() pool
  */
  
@@ -62,13 +79,15 @@
 #define CS8900_BASE		0x07000300 /* agrees with WIN CE PA */
 #define CS8900_BUS16		1 /* the Linux driver does accesses as shorts */
  
+#define CONFIG_DRIVER_S3C24X0_I2C 1	/* we use the buildin I2C controller */
+
 #define CONFIG_VFD		1	/* VFD linear frame buffer driver */
 #define VFD_TEST_LOGO		1	/* output a test logo to the VFDs */
  
 /*
  * select serial console configuration
  */
-#define CONFIG_SERIAL1          1	/* we use SERIAL 1 on TRAB */
+#define CONFIG_SERIAL1		1	/* we use SERIAL 1 on TRAB */
  
 #define CONFIG_HWFLOW			/* include RTS/CTS flow control support	*/
  
  
  
@@ -105,18 +124,30 @@
 #define CONFIG_COMMANDS_ADD_VFD		0
 #endif
  
+#ifdef CONFIG_DRIVER_S3C24X0_I2C
+#define CONFIG_COMMANDS_ADD_EEPROM	CFG_CMD_EEPROM
+#define CONFIG_COMMANDS_I2C		CFG_CMD_I2C
+#else
+#define CONFIG_COMMANDS_ADD_EEPROM	0
+#define CONFIG_COMMANDS_I2C		0
+#endif
+
 #ifndef USE_920T_MMU
 #define CONFIG_COMMANDS		((CONFIG_CMD_DFL & ~CFG_CMD_CACHE) | \
 				 CFG_CMD_BSP			| \
 				 CFG_CMD_DATE			| \
 				 CONFIG_COMMANDS_ADD_HWFLOW	| \
-				 CONFIG_COMMANDS_ADD_VFD	)
+				 CONFIG_COMMANDS_ADD_VFD	| \
+				 CONFIG_COMMANDS_ADD_EEPROM	| \
+				 CONFIG_COMMANDS_I2C		)
 #else
 #define CONFIG_COMMANDS		(CONFIG_CMD_DFL			| \
 				 CFG_CMD_BSP			| \
 				 CFG_CMD_DATE			| \
 				 CONFIG_COMMANDS_ADD_HWFLOW	| \
-				 CONFIG_COMMANDS_ADD_VFD	)
+				 CONFIG_COMMANDS_ADD_VFD	| \
+				 CONFIG_COMMANDS_ADD_EEPROM	| \
+				 CONFIG_COMMANDS_I2C		)
 #endif
  
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
@@ -125,8 +156,8 @@
 #define CONFIG_BOOTDELAY	5
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* allow to break in always */
 #define CONFIG_PREBOOT		"echo;echo *** booting ***;echo"
-#define CONFIG_BOOTARGS    	"console=ttyS0"
-#define CONFIG_NETMASK          255.255.0.0
+#define CONFIG_BOOTARGS		"console=ttyS0"
+#define CONFIG_NETMASK		255.255.0.0
 #define CONFIG_IPADDR		192.168.3.68
 #define CONFIG_HOSTNAME		trab
 #define CONFIG_SERVERIP		192.168.3.1
@@ -192,6 +223,11 @@
  */
 #define	CFG_LONGHELP				/* undef to save memory		*/
 #define	CFG_PROMPT		"TRAB # "	/* Monitor Command Prompt	*/
+/* #define CFG_HUSH_PARSER		1 */	/* use "hush" command parser	*/
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
 #define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
 #define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 #define	CFG_MAXARGS		16		/* max number of command args	*/
@@ -200,7 +236,7 @@
 #define CFG_MEMTEST_START	0x0c000000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0d000000	/* 16 MB in DRAM	*/
  
-#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#undef CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
  
 #define	CFG_LOAD_ADDR		0x0cf00000	/* default load address	*/
  
  
@@ -235,11 +271,11 @@
 /*-----------------------------------------------------------------------
  * Physical Memory Map
  */
-#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		0x0c000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	0x01000000 /* 16 MB */
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0x0c000000	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x01000000	/* 16 MB */
  
-#define CFG_FLASH_BASE		0x00000000 /* Flash Bank #1 */
+#define CFG_FLASH_BASE		0x00000000	/* Flash Bank #1 */
  
 /* The following #defines are needed to get flash environment right */
 #define	CFG_MONITOR_BASE	CFG_FLASH_BASE
@@ -418,10 +418,6 @@
  
 #ifdef CONFIG_POST
 	post_run (NULL, POST_RAM | post_bootmode_get(0));
-	if (post_bootmode_get(0) & POST_SLOWTEST) {
-		post_bootmode_clear();
-		board_poweroff();
-	}
 #endif
  
  
@@ -526,10 +526,7 @@
  
 #ifdef CONFIG_POST
 	post_bootmode_init();
-	if (post_hotkeys_pressed(gd)) /* Force the long-running tests (memory) */
-		post_run (NULL, POST_ROM | POST_SLOWTEST);
-	else
-		post_run (NULL, POST_ROM | post_bootmode_get(0));
+	post_run (NULL, POST_ROM | post_bootmode_get(0));
 #endif
  
 	WATCHDOG_RESET();
@@ -900,14 +897,7 @@
 #endif
  
 #ifdef CONFIG_POST
-	if (gd->post_hotkeys_latch)
-		post_run (NULL, POST_RAM | POST_SLOWTEST);
-	else
-		post_run (NULL, POST_RAM | post_bootmode_get(0));
-	if (post_bootmode_get(0) & POST_SLOWTEST) {
-		post_bootmode_clear();
-		board_poweroff();
-	}
+	post_run (NULL, POST_RAM | post_bootmode_get(0));
 #endif
  
 #if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) && !(CONFIG_COMMANDS & CFG_CMD_IDE)
@@ -65,9 +65,11 @@
 	DECLARE_GLOBAL_DATA_PTR;
 	int bootmode = post_bootmode_get (0);
  
-	if (bootmode == 0) {
+	if (post_hotkeys_pressed(gd) && !(bootmode & POST_POWERTEST)) {
+		bootmode = POST_SLOWTEST;
+	} else if (bootmode == 0) {
 		bootmode = POST_POWERON;
-	} else if (bootmode == POST_POWERON) {
+	} else if (bootmode == POST_POWERON || bootmode == POST_SLOWTEST) {
 		bootmode = POST_NORMAL;
 	} else {
 		return;
@@ -96,11 +98,6 @@
 	return bootmode;
 }
  
-void post_bootmode_clear (void)
-{
-	post_word_store (0);
-}
-
 /* POST tests run before relocation only mark status bits .... */
 static void post_log_mark_start ( unsigned long testid )
 {
@@ -201,6 +198,12 @@
 			}
  
 			name = s + 1;
+		}
+	}
+
+	for (j = 0; j < post_list_size; j++) {
+		if (test_flags[j] & POST_POWERON) {
+			test_flags[j] |= POST_SLOWTEST;
 		}
 	}
 }
...	...	@@ -2,6 +2,12 @@
2	2	Changes for U-Boot 0.4.3:
3	3	======================================================================
4	4
	5	+* Patches by Martin Krause, 14 Jul 2003:
	6	+ - add I2C support for s3c2400 systems (trab board)
	7	+ - (re-) add "ping" to command table
	8	+
	9	+* Fix handling of "slow" POST routines
	10	+
5	11	* Patches by Yuli Barcohen, 13 Jul 2003:
6	12	- Correct flash and JFFS2 support for MPC8260ADS
7	13	- fix PVR values and clock generation for PowerQUICC II family
...	...	@@ -3048,6 +3048,11 @@
3048	3048	version of diff does not support these options, then get the latest
3049	3049	version of GNU diff.
3050	3050
	3051	+ The current directory when running this command shall be the top
	3052	+ level directory of the U-Boot source tree, or it's parent directory
	3053	+ (i. e. please make sure that your patch includes sufficient
	3054	+ directory information for the affected files).
	3055	+
3051	3056	We accept patches as plain text, MIME attachments or as uuencoded
3052	3057	gzipped text.
3053	3058
...	...	@@ -1087,8 +1087,7 @@
1087	1087	i2c_write (kbd_addr, 0, 0, &val, 1);
1088	1088	i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
1089	1089
1090		- return (gd->post_hotkeys_latch =
1091		- (compare_magic(kbd_data, CONFIG_POST_KEY_MAGIC) == 0));
	1090	+ return (compare_magic(kbd_data, CONFIG_POST_KEY_MAGIC) == 0);
1092	1091	}
1093	1092	#endif
...	...	@@ -130,6 +130,11 @@
130	130	}
131	131	#endif /* CONFIG_MODEM_SUPPORT */
132	132
	133	+#ifdef CONFIG_DRIVER_S3C24X0_I2C
	134	+ /* Configure I/O ports PG5 und PG6 for I2C */
	135	+ gpio->PGCON = (gpio->PGCON & 0x003c00) \| 0x003c00;
	136	+#endif /* CONFIG_DRIVER_S3C24X0_I2C */
	137	+
133	138	return 0;
134	139	}
135	140
...	...	@@ -210,6 +210,12 @@
210	210
211	211	return 0;
212	212	}
	213	+
	214	+U_BOOT_CMD(
	215	+ ping, 2, 1, do_ping,
	216	+ "ping - send ICMP ECHO_REQUEST to network host\n",
	217	+ "pingAddress\n"
	218	+);
213	219	#endif /* CFG_CMD_PING */
214	220
215	221	#endif /* CFG_CMD_NET */
...	...	@@ -63,7 +63,12 @@
63	63	{
64	64	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
65	65
	66	+#ifdef CONFIG_S3C2410
66	67	return (gpio->GPEDAT & 0x8000) >> 15;
	68	+#endif
	69	+#ifdef CONFIG_S3C2400
	70	+ return (gpio->PGDAT & 0x0020) >> 5;
	71	+#endif
67	72	}
68	73
69	74	#if 0
70	75
...	...	@@ -77,7 +82,12 @@
77	82	{
78	83	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
79	84
	85	+#ifdef CONFIG_S3C2410
80	86	gpio->GPEDAT = (gpio->GPEDAT & ~0x4000) \| (x&1) << 14;
	87	+#endif
	88	+#ifdef CONFIG_S3C2400
	89	+ gpio->PGDAT = (gpio->PGDAT & ~0x0040) \| (x&1) << 6;
	90	+#endif
81	91	}
82	92
83	93
84	94
85	95
86	96
...	...	@@ -129,11 +139,22 @@
129	139	}
130	140
131	141	if ((status & I2CSTAT_BSY) \|\| GetI2CSDA() == 0) {
	142	+#ifdef CONFIG_S3C2410
132	143	ulong old_gpecon = gpio->GPECON;
	144	+#endif
	145	+#ifdef CONFIG_S3C2400
	146	+ ulong old_gpecon = gpio->PGCON;
	147	+#endif
133	148	/* bus still busy probably by (most) previously interrupted transfer */
134	149
	150	+#ifdef CONFIG_S3C2410
135	151	/* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
136	152	gpio->GPECON = (gpio->GPECON & ~0xF0000000) \| 0x10000000;
	153	+#endif
	154	+#ifdef CONFIG_S3C2400
	155	+ /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */
	156	+ gpio->PGCON = (gpio->PGCON & ~0x00003c00) \| 0x00000c00;
	157	+#endif
137	158
138	159	/* toggle I2CSCL until bus idle */
139	160	SetI2CSCL(0); udelay(1000);
140	161
...	...	@@ -146,7 +167,12 @@
146	167	SetI2CSCL(1); udelay(1000);
147	168
148	169	/* restore pin functions */
	170	+#ifdef CONFIG_S3C2410
149	171	gpio->GPECON = old_gpecon;
	172	+#endif
	173	+#ifdef CONFIG_S3C2400
	174	+ gpio->PGCON = old_gpecon;
	175	+#endif
150	176	}
151	177
152	178	/* calculate prescaler and divisor values */
...	...	@@ -73,7 +73,6 @@
73	73	#ifdef CONFIG_POST
74	74	unsigned long post_log_word; /* Record POST activities */
75	75	unsigned long post_init_f_time; /* When post_init_f started */
76		- unsigned long post_hotkeys_latch; /* If the post hotkeys pressed */
77	76	#endif
78	77	#ifdef CONFIG_BOARD_TYPES
79	78	unsigned long board_type;
...	...	@@ -37,9 +37,9 @@
37	37	* (easy to change)
38	38	*/
39	39	#define CONFIG_ARM920T 1 /* This is an arm920t CPU */
40		-#define CONFIG_S3C2400 1 /* in a SAMSUNG S3C2400 SoC */
41		-#define CONFIG_TRAB 1 /* on a TRAB Board */
42		-#undef CONFIG_TRAB_50MHZ /* run the CPU at 50 MHz */
	40	+#define CONFIG_S3C2400 1 /* in a SAMSUNG S3C2400 SoC */
	41	+#define CONFIG_TRAB 1 /* on a TRAB Board */
	42	+#undef CONFIG_TRAB_50MHZ /* run the CPU at 50 MHz */
43	43
44	44	/* input clock of PLL */
45	45	#define CONFIG_SYS_CLK_FREQ 12000000 /* TRAB has 12 MHz input clock */
...	...	@@ -50,6 +50,23 @@
50	50	#define CONFIG_SETUP_MEMORY_TAGS 1
51	51	#define CONFIG_INITRD_TAG 1
52	52
	53	+
	54	+/***********************************************************
	55	+ * I2C stuff:
	56	+ * the TRAB is equipped with an ATMEL 24C04 EEPROM at
	57	+ * address 0x54 with 8bit addressing
	58	+ ***********************************************************/
	59	+#define CONFIG_HARD_I2C /* I2C with hardware support */
	60	+#define CFG_I2C_SPEED 100000 /* I2C speed */
	61	+#define CFG_I2C_SLAVE 0x7F /* I2C slave addr */
	62	+
	63	+#define CFG_I2C_EEPROM_ADDR 0x54 /* EEPROM address */
	64	+#define CFG_I2C_EEPROM_ADDR_LEN 1 /* 1 address byte */
	65	+
	66	+#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
	67	+#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* 8 bytes page write mode on 24C04 */
	68	+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
	69	+
53	70	/*
54	71	* Size of malloc() pool
55	72	*/
56	73
...	...	@@ -62,13 +79,15 @@
62	79	#define CS8900_BASE 0x07000300 /* agrees with WIN CE PA */
63	80	#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
64	81
	82	+#define CONFIG_DRIVER_S3C24X0_I2C 1 /* we use the buildin I2C controller */
	83	+
65	84	#define CONFIG_VFD 1 /* VFD linear frame buffer driver */
66	85	#define VFD_TEST_LOGO 1 /* output a test logo to the VFDs */
67	86
68	87	/*
69	88	* select serial console configuration
70	89	*/
71		-#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on TRAB */
	90	+#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on TRAB */
72	91
73	92	#define CONFIG_HWFLOW /* include RTS/CTS flow control support */
74	93
75	94
76	95
...	...	@@ -105,18 +124,30 @@
105	124	#define CONFIG_COMMANDS_ADD_VFD 0
106	125	#endif
107	126
	127	+#ifdef CONFIG_DRIVER_S3C24X0_I2C
	128	+#define CONFIG_COMMANDS_ADD_EEPROM CFG_CMD_EEPROM
	129	+#define CONFIG_COMMANDS_I2C CFG_CMD_I2C
	130	+#else
	131	+#define CONFIG_COMMANDS_ADD_EEPROM 0
	132	+#define CONFIG_COMMANDS_I2C 0
	133	+#endif
	134	+
108	135	#ifndef USE_920T_MMU
109	136	#define CONFIG_COMMANDS ((CONFIG_CMD_DFL & ~CFG_CMD_CACHE) \| \
110	137	CFG_CMD_BSP \| \
111	138	CFG_CMD_DATE \| \
112	139	CONFIG_COMMANDS_ADD_HWFLOW \| \
113		- CONFIG_COMMANDS_ADD_VFD )
	140	+ CONFIG_COMMANDS_ADD_VFD \| \
	141	+ CONFIG_COMMANDS_ADD_EEPROM \| \
	142	+ CONFIG_COMMANDS_I2C )
114	143	#else
115	144	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| \
116	145	CFG_CMD_BSP \| \
117	146	CFG_CMD_DATE \| \
118	147	CONFIG_COMMANDS_ADD_HWFLOW \| \
119		- CONFIG_COMMANDS_ADD_VFD )
	148	+ CONFIG_COMMANDS_ADD_VFD \| \
	149	+ CONFIG_COMMANDS_ADD_EEPROM \| \
	150	+ CONFIG_COMMANDS_I2C )
120	151	#endif
121	152
122	153	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
...	...	@@ -125,8 +156,8 @@
125	156	#define CONFIG_BOOTDELAY 5
126	157	#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow to break in always */
127	158	#define CONFIG_PREBOOT "echo;echo * booting *;echo"
128		-#define CONFIG_BOOTARGS "console=ttyS0"
129		-#define CONFIG_NETMASK 255.255.0.0
	159	+#define CONFIG_BOOTARGS "console=ttyS0"
	160	+#define CONFIG_NETMASK 255.255.0.0
130	161	#define CONFIG_IPADDR 192.168.3.68
131	162	#define CONFIG_HOSTNAME trab
132	163	#define CONFIG_SERVERIP 192.168.3.1
...	...	@@ -192,6 +223,11 @@
192	223	*/
193	224	#define CFG_LONGHELP /* undef to save memory */
194	225	#define CFG_PROMPT "TRAB # " /* Monitor Command Prompt */
	226	+/* #define CFG_HUSH_PARSER 1 / / use "hush" command parser */
	227	+#ifdef CFG_HUSH_PARSER
	228	+#define CFG_PROMPT_HUSH_PS2 "> "
	229	+#endif
	230	+
195	231	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
196	232	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
197	233	#define CFG_MAXARGS 16 /* max number of command args */
...	...	@@ -200,7 +236,7 @@
200	236	#define CFG_MEMTEST_START 0x0c000000 /* memtest works on */
201	237	#define CFG_MEMTEST_END 0x0d000000 /* 16 MB in DRAM */
202	238
203		-#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
	239	+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
204	240
205	241	#define CFG_LOAD_ADDR 0x0cf00000 /* default load address */
206	242
207	243
...	...	@@ -235,11 +271,11 @@
235	271	/*-----------------------------------------------------------------------
236	272	* Physical Memory Map
237	273	*/
238		-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
239		-#define PHYS_SDRAM_1 0x0c000000 /* SDRAM Bank #1 */
240		-#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */
	274	+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
	275	+#define PHYS_SDRAM_1 0x0c000000 /* SDRAM Bank #1 */
	276	+#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */
241	277
242		-#define CFG_FLASH_BASE 0x00000000 /* Flash Bank #1 */
	278	+#define CFG_FLASH_BASE 0x00000000 /* Flash Bank #1 */
243	279
244	280	/* The following #defines are needed to get flash environment right */
245	281	#define CFG_MONITOR_BASE CFG_FLASH_BASE
...	...	@@ -418,10 +418,6 @@
418	418
419	419	#ifdef CONFIG_POST
420	420	post_run (NULL, POST_RAM \| post_bootmode_get(0));
421		- if (post_bootmode_get(0) & POST_SLOWTEST) {
422		- post_bootmode_clear();
423		- board_poweroff();
424		- }
425	421	#endif
426	422
427	423
...	...	@@ -526,10 +526,7 @@
526	526
527	527	#ifdef CONFIG_POST
528	528	post_bootmode_init();
529		- if (post_hotkeys_pressed(gd)) /* Force the long-running tests (memory) */
530		- post_run (NULL, POST_ROM \| POST_SLOWTEST);
531		- else
532		- post_run (NULL, POST_ROM \| post_bootmode_get(0));
	529	+ post_run (NULL, POST_ROM \| post_bootmode_get(0));
533	530	#endif
534	531
535	532	WATCHDOG_RESET();
...	...	@@ -900,14 +897,7 @@
900	897	#endif
901	898
902	899	#ifdef CONFIG_POST
903		- if (gd->post_hotkeys_latch)
904		- post_run (NULL, POST_RAM \| POST_SLOWTEST);
905		- else
906		- post_run (NULL, POST_RAM \| post_bootmode_get(0));
907		- if (post_bootmode_get(0) & POST_SLOWTEST) {
908		- post_bootmode_clear();
909		- board_poweroff();
910		- }
	900	+ post_run (NULL, POST_RAM \| post_bootmode_get(0));
911	901	#endif
912	902
913	903	#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) && !(CONFIG_COMMANDS & CFG_CMD_IDE)