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Commit 71bdfcb21d755435a8e99f0ff66b853a3759f4b7

Authored by Marcus Comstedt
Committed by Andes
1 parent f379fa6406
Exists in smarc_8mq_lf_v2020.04 and in 9 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

riscv: tools: Handle addend to absolute reloc in prelink-riscv 

Previously the handling of R_RISCV_32 and R_RISCV_64 would simply
insert the value of the symbol and ignore any addend.  However, there
exist relocs where the addend is non-zero:

0000000080250900 R_RISCV_64        efi_runtime_services+0x0000000000000068
0000000080250910 R_RISCV_64        efi_runtime_services+0x0000000000000038
0000000080250920 R_RISCV_64        efi_runtime_services+0x0000000000000018
0000000080250930 R_RISCV_64        efi_runtime_services+0x0000000000000020
0000000080250980 R_RISCV_64        efi_runtime_services+0x0000000000000048
0000000080250990 R_RISCV_64        efi_runtime_services+0x0000000000000050
00000000802509a0 R_RISCV_64        efi_runtime_services+0x0000000000000058
0000000080250940 R_RISCV_64        systab+0x0000000000000030
0000000080250950 R_RISCV_64        systab+0x0000000000000040
0000000080250960 R_RISCV_64        systab+0x0000000000000050
0000000080250970 R_RISCV_64        systab+0x0000000000000060

In these cases the addend needs to be added to the symbol value to get
the correct value for the reloc.

Signed-off-by: Marcus Comstedt <marcus@mc.pp.se>
Cc: Rick Chen <rick@andestech.com>

Showing 1 changed file with 6 additions and 2 deletions Side-by-side Diff

tools/prelink-riscv.inc
Diff comments   View file @ 71bdfcb
... ... @@ -27,6 +27,8 @@
27 27 #define target32_to_cpu CONCAT(PRELINK_BYTEORDER, 32_to_cpu)
28 28 #define target64_to_cpu CONCAT(PRELINK_BYTEORDER, 64_to_cpu)
29 29 #define targetnn_to_cpu CONCAT3(PRELINK_BYTEORDER, PRELINK_INC_BITS, _to_cpu)
  30 +#define cpu_to_target32 CONCAT3(cpu_to_, PRELINK_BYTEORDER, 32)
  31 +#define cpu_to_target64 CONCAT3(cpu_to_, PRELINK_BYTEORDER, 64)
30 32  
31 33 static void* get_offset_bonn (void* data, Elf_Phdr* phdrs, size_t phnum, Elf_Addr addr)
32 34 {
33 35  
... ... @@ -92,9 +94,9 @@
92 94 if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_RELATIVE)
93 95 *((uintnn_t*) buf) = r->r_addend;
94 96 else if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_32)
95   - *((uint32_t*) buf) = dynsym[ELF_R_SYM(targetnn_to_cpu(r->r_info))].st_value;
  97 + *((uint32_t*) buf) = cpu_to_target32(targetnn_to_cpu(dynsym[ELF_R_SYM(targetnn_to_cpu(r->r_info))].st_value) + targetnn_to_cpu(r->r_addend));
96 98 else if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_64)
97   - *((uint64_t*) buf) = dynsym[ELF_R_SYM(targetnn_to_cpu(r->r_info))].st_value;
  99 + *((uint64_t*) buf) = cpu_to_target64(targetnn_to_cpu(dynsym[ELF_R_SYM(targetnn_to_cpu(r->r_info))].st_value) + targetnn_to_cpu(r->r_addend));
98 100 }
99 101 }
100 102  
... ... @@ -113,6 +115,8 @@
113 115 #undef target32_to_cpu
114 116 #undef target64_to_cpu
115 117 #undef targetnn_to_cpu
  118 +#undef cpu_to_target32
  119 +#undef cpu_to_target64
116 120  
117 121 #undef CONCAT_IMPL
118 122 #undef CONCAT