Eric Lee / smarc-uboot

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Commit 7769776a603f76ab1b7c1478f6cf8388b3cb5464

Authored by Ashish Kumar
Committed by York Sun
1 parent e84a324ba7
Exists in smarc_8mq_lf_v2020.04 and in 20 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf-6.6.52-2.2.0, emb_lf_v2022.04, emb_lf_v2023.04, emb_lf_v2024.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

armv8: ls1088aqds: Add support of LS1088AQDS 

This patch add support of LS1088AQDS platform.

The LS1088A QorIQTM Development System (QDS) is a high-performance
computing, evaluation, and development platform that supports the
LS1088A QorIQ Architecture processor.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

Showing 14 changed files with 1372 additions and 7 deletions Inline Diff

1 menu "ARM architecture" 1 menu "ARM architecture"
2 depends on ARM 2 depends on ARM
3 3
4 config SYS_ARCH 4 config SYS_ARCH
5 default "arm" 5 default "arm"
6 6
7 config ARM64 7 config ARM64
8 bool 8 bool
9 select PHYS_64BIT 9 select PHYS_64BIT
10 select SYS_CACHE_SHIFT_6 10 select SYS_CACHE_SHIFT_6
11 11
12 config DMA_ADDR_T_64BIT 12 config DMA_ADDR_T_64BIT
13 bool 13 bool
14 default y if ARM64 14 default y if ARM64
15 15
16 config HAS_VBAR 16 config HAS_VBAR
17 bool 17 bool
18 18
19 config HAS_THUMB2 19 config HAS_THUMB2
20 bool 20 bool
21 21
22 # Used for compatibility with asm files copied from the kernel 22 # Used for compatibility with asm files copied from the kernel
23 config ARM_ASM_UNIFIED 23 config ARM_ASM_UNIFIED
24 bool 24 bool
25 default y 25 default y
26 26
27 # Used for compatibility with asm files copied from the kernel 27 # Used for compatibility with asm files copied from the kernel
28 config THUMB2_KERNEL 28 config THUMB2_KERNEL
29 bool 29 bool
30 30
31 # If set, the workarounds for these ARM errata are applied early during U-Boot 31 # If set, the workarounds for these ARM errata are applied early during U-Boot
32 # startup. Note that in general these options force the workarounds to be 32 # startup. Note that in general these options force the workarounds to be
33 # applied; no CPU-type/version detection exists, unlike the similar options in 33 # applied; no CPU-type/version detection exists, unlike the similar options in
34 # the Linux kernel. Do not set these options unless they apply! Also note that 34 # the Linux kernel. Do not set these options unless they apply! Also note that
35 # the following can be machine specific errata. These do have ability to 35 # the following can be machine specific errata. These do have ability to
36 # provide rudimentary version and machine specific checks, but expect no 36 # provide rudimentary version and machine specific checks, but expect no
37 # product checks: 37 # product checks:
38 # CONFIG_ARM_ERRATA_430973 38 # CONFIG_ARM_ERRATA_430973
39 # CONFIG_ARM_ERRATA_454179 39 # CONFIG_ARM_ERRATA_454179
40 # CONFIG_ARM_ERRATA_621766 40 # CONFIG_ARM_ERRATA_621766
41 # CONFIG_ARM_ERRATA_798870 41 # CONFIG_ARM_ERRATA_798870
42 # CONFIG_ARM_ERRATA_801819 42 # CONFIG_ARM_ERRATA_801819
43 config ARM_ERRATA_430973 43 config ARM_ERRATA_430973
44 bool 44 bool
45 45
46 config ARM_ERRATA_454179 46 config ARM_ERRATA_454179
47 bool 47 bool
48 48
49 config ARM_ERRATA_621766 49 config ARM_ERRATA_621766
50 bool 50 bool
51 51
52 config ARM_ERRATA_716044 52 config ARM_ERRATA_716044
53 bool 53 bool
54 54
55 config ARM_ERRATA_725233 55 config ARM_ERRATA_725233
56 bool 56 bool
57 57
58 config ARM_ERRATA_742230 58 config ARM_ERRATA_742230
59 bool 59 bool
60 60
61 config ARM_ERRATA_743622 61 config ARM_ERRATA_743622
62 bool 62 bool
63 63
64 config ARM_ERRATA_751472 64 config ARM_ERRATA_751472
65 bool 65 bool
66 66
67 config ARM_ERRATA_761320 67 config ARM_ERRATA_761320
68 bool 68 bool
69 69
70 config ARM_ERRATA_773022 70 config ARM_ERRATA_773022
71 bool 71 bool
72 72
73 config ARM_ERRATA_774769 73 config ARM_ERRATA_774769
74 bool 74 bool
75 75
76 config ARM_ERRATA_794072 76 config ARM_ERRATA_794072
77 bool 77 bool
78 78
79 config ARM_ERRATA_798870 79 config ARM_ERRATA_798870
80 bool 80 bool
81 81
82 config ARM_ERRATA_801819 82 config ARM_ERRATA_801819
83 bool 83 bool
84 84
85 config ARM_ERRATA_826974 85 config ARM_ERRATA_826974
86 bool 86 bool
87 87
88 config ARM_ERRATA_828024 88 config ARM_ERRATA_828024
89 bool 89 bool
90 90
91 config ARM_ERRATA_829520 91 config ARM_ERRATA_829520
92 bool 92 bool
93 93
94 config ARM_ERRATA_833069 94 config ARM_ERRATA_833069
95 bool 95 bool
96 96
97 config ARM_ERRATA_833471 97 config ARM_ERRATA_833471
98 bool 98 bool
99 99
100 config ARM_ERRATA_845369 100 config ARM_ERRATA_845369
101 bool 101 bool
102 102
103 config ARM_ERRATA_852421 103 config ARM_ERRATA_852421
104 bool 104 bool
105 105
106 config ARM_ERRATA_852423 106 config ARM_ERRATA_852423
107 bool 107 bool
108 108
109 config CPU_ARM720T 109 config CPU_ARM720T
110 bool 110 bool
111 select SYS_CACHE_SHIFT_5 111 select SYS_CACHE_SHIFT_5
112 112
113 config CPU_ARM920T 113 config CPU_ARM920T
114 bool 114 bool
115 select SYS_CACHE_SHIFT_5 115 select SYS_CACHE_SHIFT_5
116 116
117 config CPU_ARM926EJS 117 config CPU_ARM926EJS
118 bool 118 bool
119 select SYS_CACHE_SHIFT_5 119 select SYS_CACHE_SHIFT_5
120 120
121 config CPU_ARM946ES 121 config CPU_ARM946ES
122 bool 122 bool
123 select SYS_CACHE_SHIFT_5 123 select SYS_CACHE_SHIFT_5
124 124
125 config CPU_ARM1136 125 config CPU_ARM1136
126 bool 126 bool
127 select SYS_CACHE_SHIFT_5 127 select SYS_CACHE_SHIFT_5
128 128
129 config CPU_ARM1176 129 config CPU_ARM1176
130 bool 130 bool
131 select HAS_VBAR 131 select HAS_VBAR
132 select SYS_CACHE_SHIFT_5 132 select SYS_CACHE_SHIFT_5
133 133
134 config CPU_V7 134 config CPU_V7
135 bool 135 bool
136 select HAS_VBAR 136 select HAS_VBAR
137 select HAS_THUMB2 137 select HAS_THUMB2
138 select SYS_CACHE_SHIFT_6 138 select SYS_CACHE_SHIFT_6
139 139
140 config CPU_V7M 140 config CPU_V7M
141 bool 141 bool
142 select HAS_THUMB2 142 select HAS_THUMB2
143 select THUMB2_KERNEL 143 select THUMB2_KERNEL
144 select SYS_CACHE_SHIFT_5 144 select SYS_CACHE_SHIFT_5
145 145
146 config CPU_PXA 146 config CPU_PXA
147 bool 147 bool
148 select SYS_CACHE_SHIFT_5 148 select SYS_CACHE_SHIFT_5
149 149
150 config CPU_SA1100 150 config CPU_SA1100
151 bool 151 bool
152 select SYS_CACHE_SHIFT_5 152 select SYS_CACHE_SHIFT_5
153 153
154 config SYS_CPU 154 config SYS_CPU
155 default "arm720t" if CPU_ARM720T 155 default "arm720t" if CPU_ARM720T
156 default "arm920t" if CPU_ARM920T 156 default "arm920t" if CPU_ARM920T
157 default "arm926ejs" if CPU_ARM926EJS 157 default "arm926ejs" if CPU_ARM926EJS
158 default "arm946es" if CPU_ARM946ES 158 default "arm946es" if CPU_ARM946ES
159 default "arm1136" if CPU_ARM1136 159 default "arm1136" if CPU_ARM1136
160 default "arm1176" if CPU_ARM1176 160 default "arm1176" if CPU_ARM1176
161 default "armv7" if CPU_V7 161 default "armv7" if CPU_V7
162 default "armv7m" if CPU_V7M 162 default "armv7m" if CPU_V7M
163 default "pxa" if CPU_PXA 163 default "pxa" if CPU_PXA
164 default "sa1100" if CPU_SA1100 164 default "sa1100" if CPU_SA1100
165 default "armv8" if ARM64 165 default "armv8" if ARM64
166 166
167 config SYS_ARM_ARCH 167 config SYS_ARM_ARCH
168 int 168 int
169 default 4 if CPU_ARM720T 169 default 4 if CPU_ARM720T
170 default 4 if CPU_ARM920T 170 default 4 if CPU_ARM920T
171 default 5 if CPU_ARM926EJS 171 default 5 if CPU_ARM926EJS
172 default 5 if CPU_ARM946ES 172 default 5 if CPU_ARM946ES
173 default 6 if CPU_ARM1136 173 default 6 if CPU_ARM1136
174 default 6 if CPU_ARM1176 174 default 6 if CPU_ARM1176
175 default 7 if CPU_V7 175 default 7 if CPU_V7
176 default 7 if CPU_V7M 176 default 7 if CPU_V7M
177 default 5 if CPU_PXA 177 default 5 if CPU_PXA
178 default 4 if CPU_SA1100 178 default 4 if CPU_SA1100
179 default 8 if ARM64 179 default 8 if ARM64
180 180
181 config SYS_CACHE_SHIFT_5 181 config SYS_CACHE_SHIFT_5
182 bool 182 bool
183 183
184 config SYS_CACHE_SHIFT_6 184 config SYS_CACHE_SHIFT_6
185 bool 185 bool
186 186
187 config SYS_CACHE_SHIFT_7 187 config SYS_CACHE_SHIFT_7
188 bool 188 bool
189 189
190 config SYS_CACHELINE_SIZE 190 config SYS_CACHELINE_SIZE
191 int 191 int
192 default 128 if SYS_CACHE_SHIFT_7 192 default 128 if SYS_CACHE_SHIFT_7
193 default 64 if SYS_CACHE_SHIFT_6 193 default 64 if SYS_CACHE_SHIFT_6
194 default 32 if SYS_CACHE_SHIFT_5 194 default 32 if SYS_CACHE_SHIFT_5
195 195
196 config ARM_SMCCC 196 config ARM_SMCCC
197 bool "Support for ARM SMC Calling Convention (SMCCC)" 197 bool "Support for ARM SMC Calling Convention (SMCCC)"
198 depends on CPU_V7 || ARM64 198 depends on CPU_V7 || ARM64
199 select ARM_PSCI_FW 199 select ARM_PSCI_FW
200 help 200 help
201 Say Y here if you want to enable ARM SMC Calling Convention. 201 Say Y here if you want to enable ARM SMC Calling Convention.
202 This should be enabled if U-Boot needs to communicate with system 202 This should be enabled if U-Boot needs to communicate with system
203 firmware (for example, PSCI) according to SMCCC. 203 firmware (for example, PSCI) according to SMCCC.
204 204
205 config SEMIHOSTING 205 config SEMIHOSTING
206 bool "support boot from semihosting" 206 bool "support boot from semihosting"
207 help 207 help
208 In emulated environments, semihosting is a way for 208 In emulated environments, semihosting is a way for
209 the hosted environment to call out to the emulator to 209 the hosted environment to call out to the emulator to
210 retrieve files from the host machine. 210 retrieve files from the host machine.
211 211
212 config SYS_THUMB_BUILD 212 config SYS_THUMB_BUILD
213 bool "Build U-Boot using the Thumb instruction set" 213 bool "Build U-Boot using the Thumb instruction set"
214 depends on !ARM64 214 depends on !ARM64
215 help 215 help
216 Use this flag to build U-Boot using the Thumb instruction set for 216 Use this flag to build U-Boot using the Thumb instruction set for
217 ARM architectures. Thumb instruction set provides better code 217 ARM architectures. Thumb instruction set provides better code
218 density. For ARM architectures that support Thumb2 this flag will 218 density. For ARM architectures that support Thumb2 this flag will
219 result in Thumb2 code generated by GCC. 219 result in Thumb2 code generated by GCC.
220 220
221 config SPL_SYS_THUMB_BUILD 221 config SPL_SYS_THUMB_BUILD
222 bool "Build SPL using the Thumb instruction set" 222 bool "Build SPL using the Thumb instruction set"
223 default y if SYS_THUMB_BUILD 223 default y if SYS_THUMB_BUILD
224 depends on !ARM64 224 depends on !ARM64
225 help 225 help
226 Use this flag to build SPL using the Thumb instruction set for 226 Use this flag to build SPL using the Thumb instruction set for
227 ARM architectures. Thumb instruction set provides better code 227 ARM architectures. Thumb instruction set provides better code
228 density. For ARM architectures that support Thumb2 this flag will 228 density. For ARM architectures that support Thumb2 this flag will
229 result in Thumb2 code generated by GCC. 229 result in Thumb2 code generated by GCC.
230 230
231 config SYS_L2CACHE_OFF 231 config SYS_L2CACHE_OFF
232 bool "L2cache off" 232 bool "L2cache off"
233 help 233 help
234 If SoC does not support L2CACHE or one do not want to enable 234 If SoC does not support L2CACHE or one do not want to enable
235 L2CACHE, choose this option. 235 L2CACHE, choose this option.
236 236
237 config ENABLE_ARM_SOC_BOOT0_HOOK 237 config ENABLE_ARM_SOC_BOOT0_HOOK
238 bool "prepare BOOT0 header" 238 bool "prepare BOOT0 header"
239 help 239 help
240 If the SoC's BOOT0 requires a header area filled with (magic) 240 If the SoC's BOOT0 requires a header area filled with (magic)
241 values, then choose this option, and create a define called 241 values, then choose this option, and create a define called
242 ARM_SOC_BOOT0_HOOK which contains the required assembler 242 ARM_SOC_BOOT0_HOOK which contains the required assembler
243 preprocessor code. 243 preprocessor code.
244 244
245 config ARM_CORTEX_CPU_IS_UP 245 config ARM_CORTEX_CPU_IS_UP
246 bool 246 bool
247 default n 247 default n
248 248
249 config USE_ARCH_MEMCPY 249 config USE_ARCH_MEMCPY
250 bool "Use an assembly optimized implementation of memcpy" 250 bool "Use an assembly optimized implementation of memcpy"
251 default y 251 default y
252 depends on !ARM64 252 depends on !ARM64
253 help 253 help
254 Enable the generation of an optimized version of memcpy. 254 Enable the generation of an optimized version of memcpy.
255 Such implementation may be faster under some conditions 255 Such implementation may be faster under some conditions
256 but may increase the binary size. 256 but may increase the binary size.
257 257
258 config SPL_USE_ARCH_MEMCPY 258 config SPL_USE_ARCH_MEMCPY
259 bool "Use an assembly optimized implementation of memcpy for SPL" 259 bool "Use an assembly optimized implementation of memcpy for SPL"
260 default y if USE_ARCH_MEMCPY 260 default y if USE_ARCH_MEMCPY
261 depends on !ARM64 261 depends on !ARM64
262 help 262 help
263 Enable the generation of an optimized version of memcpy. 263 Enable the generation of an optimized version of memcpy.
264 Such implementation may be faster under some conditions 264 Such implementation may be faster under some conditions
265 but may increase the binary size. 265 but may increase the binary size.
266 266
267 config USE_ARCH_MEMSET 267 config USE_ARCH_MEMSET
268 bool "Use an assembly optimized implementation of memset" 268 bool "Use an assembly optimized implementation of memset"
269 default y 269 default y
270 depends on !ARM64 270 depends on !ARM64
271 help 271 help
272 Enable the generation of an optimized version of memset. 272 Enable the generation of an optimized version of memset.
273 Such implementation may be faster under some conditions 273 Such implementation may be faster under some conditions
274 but may increase the binary size. 274 but may increase the binary size.
275 275
276 config SPL_USE_ARCH_MEMSET 276 config SPL_USE_ARCH_MEMSET
277 bool "Use an assembly optimized implementation of memset for SPL" 277 bool "Use an assembly optimized implementation of memset for SPL"
278 default y if USE_ARCH_MEMSET 278 default y if USE_ARCH_MEMSET
279 depends on !ARM64 279 depends on !ARM64
280 help 280 help
281 Enable the generation of an optimized version of memset. 281 Enable the generation of an optimized version of memset.
282 Such implementation may be faster under some conditions 282 Such implementation may be faster under some conditions
283 but may increase the binary size. 283 but may increase the binary size.
284 284
285 config ARM64_SUPPORT_AARCH32 285 config ARM64_SUPPORT_AARCH32
286 bool "ARM64 system support AArch32 execution state" 286 bool "ARM64 system support AArch32 execution state"
287 default y if ARM64 && !TARGET_THUNDERX_88XX 287 default y if ARM64 && !TARGET_THUNDERX_88XX
288 help 288 help
289 This ARM64 system supports AArch32 execution state. 289 This ARM64 system supports AArch32 execution state.
290 290
291 choice 291 choice
292 prompt "Target select" 292 prompt "Target select"
293 default TARGET_HIKEY 293 default TARGET_HIKEY
294 294
295 config ARCH_AT91 295 config ARCH_AT91
296 bool "Atmel AT91" 296 bool "Atmel AT91"
297 select SPL_BOARD_INIT if SPL 297 select SPL_BOARD_INIT if SPL
298 298
299 config TARGET_EDB93XX 299 config TARGET_EDB93XX
300 bool "Support edb93xx" 300 bool "Support edb93xx"
301 select CPU_ARM920T 301 select CPU_ARM920T
302 302
303 config TARGET_ASPENITE 303 config TARGET_ASPENITE
304 bool "Support aspenite" 304 bool "Support aspenite"
305 select CPU_ARM926EJS 305 select CPU_ARM926EJS
306 306
307 config TARGET_GPLUGD 307 config TARGET_GPLUGD
308 bool "Support gplugd" 308 bool "Support gplugd"
309 select CPU_ARM926EJS 309 select CPU_ARM926EJS
310 310
311 config ARCH_DAVINCI 311 config ARCH_DAVINCI
312 bool "TI DaVinci" 312 bool "TI DaVinci"
313 select CPU_ARM926EJS 313 select CPU_ARM926EJS
314 imply CMD_SAVES 314 imply CMD_SAVES
315 help 315 help
316 Support for TI's DaVinci platform. 316 Support for TI's DaVinci platform.
317 317
318 config KIRKWOOD 318 config KIRKWOOD
319 bool "Marvell Kirkwood" 319 bool "Marvell Kirkwood"
320 select CPU_ARM926EJS 320 select CPU_ARM926EJS
321 select BOARD_EARLY_INIT_F 321 select BOARD_EARLY_INIT_F
322 select ARCH_MISC_INIT 322 select ARCH_MISC_INIT
323 323
324 config ARCH_MVEBU 324 config ARCH_MVEBU
325 bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)" 325 bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
326 select OF_CONTROL 326 select OF_CONTROL
327 select OF_SEPARATE 327 select OF_SEPARATE
328 select DM 328 select DM
329 select DM_ETH 329 select DM_ETH
330 select DM_SERIAL 330 select DM_SERIAL
331 select DM_SPI 331 select DM_SPI
332 select DM_SPI_FLASH 332 select DM_SPI_FLASH
333 333
334 config TARGET_DEVKIT3250 334 config TARGET_DEVKIT3250
335 bool "Support devkit3250" 335 bool "Support devkit3250"
336 select CPU_ARM926EJS 336 select CPU_ARM926EJS
337 select SUPPORT_SPL 337 select SUPPORT_SPL
338 338
339 config TARGET_WORK_92105 339 config TARGET_WORK_92105
340 bool "Support work_92105" 340 bool "Support work_92105"
341 select CPU_ARM926EJS 341 select CPU_ARM926EJS
342 select SUPPORT_SPL 342 select SUPPORT_SPL
343 343
344 config TARGET_MX25PDK 344 config TARGET_MX25PDK
345 bool "Support mx25pdk" 345 bool "Support mx25pdk"
346 select BOARD_LATE_INIT 346 select BOARD_LATE_INIT
347 select CPU_ARM926EJS 347 select CPU_ARM926EJS
348 select BOARD_EARLY_INIT_F 348 select BOARD_EARLY_INIT_F
349 349
350 config TARGET_ZMX25 350 config TARGET_ZMX25
351 bool "Support zmx25" 351 bool "Support zmx25"
352 select BOARD_LATE_INIT 352 select BOARD_LATE_INIT
353 select CPU_ARM926EJS 353 select CPU_ARM926EJS
354 354
355 config TARGET_APF27 355 config TARGET_APF27
356 bool "Support apf27" 356 bool "Support apf27"
357 select CPU_ARM926EJS 357 select CPU_ARM926EJS
358 select SUPPORT_SPL 358 select SUPPORT_SPL
359 359
360 config TARGET_APX4DEVKIT 360 config TARGET_APX4DEVKIT
361 bool "Support apx4devkit" 361 bool "Support apx4devkit"
362 select CPU_ARM926EJS 362 select CPU_ARM926EJS
363 select SUPPORT_SPL 363 select SUPPORT_SPL
364 364
365 config TARGET_XFI3 365 config TARGET_XFI3
366 bool "Support xfi3" 366 bool "Support xfi3"
367 select CPU_ARM926EJS 367 select CPU_ARM926EJS
368 select SUPPORT_SPL 368 select SUPPORT_SPL
369 369
370 config TARGET_M28EVK 370 config TARGET_M28EVK
371 bool "Support m28evk" 371 bool "Support m28evk"
372 select CPU_ARM926EJS 372 select CPU_ARM926EJS
373 select SUPPORT_SPL 373 select SUPPORT_SPL
374 374
375 config TARGET_MX23EVK 375 config TARGET_MX23EVK
376 bool "Support mx23evk" 376 bool "Support mx23evk"
377 select CPU_ARM926EJS 377 select CPU_ARM926EJS
378 select SUPPORT_SPL 378 select SUPPORT_SPL
379 select BOARD_EARLY_INIT_F 379 select BOARD_EARLY_INIT_F
380 380
381 config TARGET_MX28EVK 381 config TARGET_MX28EVK
382 bool "Support mx28evk" 382 bool "Support mx28evk"
383 select CPU_ARM926EJS 383 select CPU_ARM926EJS
384 select SUPPORT_SPL 384 select SUPPORT_SPL
385 select BOARD_EARLY_INIT_F 385 select BOARD_EARLY_INIT_F
386 386
387 config TARGET_MX23_OLINUXINO 387 config TARGET_MX23_OLINUXINO
388 bool "Support mx23_olinuxino" 388 bool "Support mx23_olinuxino"
389 select CPU_ARM926EJS 389 select CPU_ARM926EJS
390 select SUPPORT_SPL 390 select SUPPORT_SPL
391 select BOARD_EARLY_INIT_F 391 select BOARD_EARLY_INIT_F
392 392
393 config TARGET_BG0900 393 config TARGET_BG0900
394 bool "Support bg0900" 394 bool "Support bg0900"
395 select CPU_ARM926EJS 395 select CPU_ARM926EJS
396 select SUPPORT_SPL 396 select SUPPORT_SPL
397 397
398 config TARGET_SANSA_FUZE_PLUS 398 config TARGET_SANSA_FUZE_PLUS
399 bool "Support sansa_fuze_plus" 399 bool "Support sansa_fuze_plus"
400 select CPU_ARM926EJS 400 select CPU_ARM926EJS
401 select SUPPORT_SPL 401 select SUPPORT_SPL
402 402
403 config TARGET_SC_SPS_1 403 config TARGET_SC_SPS_1
404 bool "Support sc_sps_1" 404 bool "Support sc_sps_1"
405 select CPU_ARM926EJS 405 select CPU_ARM926EJS
406 select SUPPORT_SPL 406 select SUPPORT_SPL
407 407
408 config ORION5X 408 config ORION5X
409 bool "Marvell Orion" 409 bool "Marvell Orion"
410 select CPU_ARM926EJS 410 select CPU_ARM926EJS
411 411
412 config TARGET_SPEAR300 412 config TARGET_SPEAR300
413 bool "Support spear300" 413 bool "Support spear300"
414 select CPU_ARM926EJS 414 select CPU_ARM926EJS
415 select BOARD_EARLY_INIT_F 415 select BOARD_EARLY_INIT_F
416 imply CMD_SAVES 416 imply CMD_SAVES
417 417
418 config TARGET_SPEAR310 418 config TARGET_SPEAR310
419 bool "Support spear310" 419 bool "Support spear310"
420 select CPU_ARM926EJS 420 select CPU_ARM926EJS
421 select BOARD_EARLY_INIT_F 421 select BOARD_EARLY_INIT_F
422 imply CMD_SAVES 422 imply CMD_SAVES
423 423
424 config TARGET_SPEAR320 424 config TARGET_SPEAR320
425 bool "Support spear320" 425 bool "Support spear320"
426 select CPU_ARM926EJS 426 select CPU_ARM926EJS
427 select BOARD_EARLY_INIT_F 427 select BOARD_EARLY_INIT_F
428 imply CMD_SAVES 428 imply CMD_SAVES
429 429
430 config TARGET_SPEAR600 430 config TARGET_SPEAR600
431 bool "Support spear600" 431 bool "Support spear600"
432 select CPU_ARM926EJS 432 select CPU_ARM926EJS
433 select BOARD_EARLY_INIT_F 433 select BOARD_EARLY_INIT_F
434 imply CMD_SAVES 434 imply CMD_SAVES
435 435
436 config TARGET_STV0991 436 config TARGET_STV0991
437 bool "Support stv0991" 437 bool "Support stv0991"
438 select CPU_V7 438 select CPU_V7
439 select DM 439 select DM
440 select DM_SERIAL 440 select DM_SERIAL
441 select DM_SPI 441 select DM_SPI
442 select DM_SPI_FLASH 442 select DM_SPI_FLASH
443 select SPI_FLASH 443 select SPI_FLASH
444 444
445 config TARGET_X600 445 config TARGET_X600
446 bool "Support x600" 446 bool "Support x600"
447 select BOARD_LATE_INIT 447 select BOARD_LATE_INIT
448 select CPU_ARM926EJS 448 select CPU_ARM926EJS
449 select SUPPORT_SPL 449 select SUPPORT_SPL
450 450
451 config TARGET_IMX31_PHYCORE 451 config TARGET_IMX31_PHYCORE
452 bool "Support imx31_phycore_eet" 452 bool "Support imx31_phycore_eet"
453 select CPU_ARM1136 453 select CPU_ARM1136
454 select BOARD_EARLY_INIT_F 454 select BOARD_EARLY_INIT_F
455 455
456 config TARGET_IMX31_PHYCORE_EET 456 config TARGET_IMX31_PHYCORE_EET
457 bool "Support imx31_phycore_eet" 457 bool "Support imx31_phycore_eet"
458 select BOARD_LATE_INIT 458 select BOARD_LATE_INIT
459 select CPU_ARM1136 459 select CPU_ARM1136
460 select BOARD_EARLY_INIT_F 460 select BOARD_EARLY_INIT_F
461 461
462 config TARGET_MX31ADS 462 config TARGET_MX31ADS
463 bool "Support mx31ads" 463 bool "Support mx31ads"
464 select CPU_ARM1136 464 select CPU_ARM1136
465 select BOARD_EARLY_INIT_F 465 select BOARD_EARLY_INIT_F
466 466
467 config TARGET_MX31PDK 467 config TARGET_MX31PDK
468 bool "Support mx31pdk" 468 bool "Support mx31pdk"
469 select BOARD_LATE_INIT 469 select BOARD_LATE_INIT
470 select CPU_ARM1136 470 select CPU_ARM1136
471 select SUPPORT_SPL 471 select SUPPORT_SPL
472 select BOARD_EARLY_INIT_F 472 select BOARD_EARLY_INIT_F
473 473
474 config TARGET_WOODBURN 474 config TARGET_WOODBURN
475 bool "Support woodburn" 475 bool "Support woodburn"
476 select CPU_ARM1136 476 select CPU_ARM1136
477 477
478 config TARGET_WOODBURN_SD 478 config TARGET_WOODBURN_SD
479 bool "Support woodburn_sd" 479 bool "Support woodburn_sd"
480 select CPU_ARM1136 480 select CPU_ARM1136
481 select SUPPORT_SPL 481 select SUPPORT_SPL
482 482
483 config TARGET_FLEA3 483 config TARGET_FLEA3
484 bool "Support flea3" 484 bool "Support flea3"
485 select CPU_ARM1136 485 select CPU_ARM1136
486 486
487 config TARGET_MX35PDK 487 config TARGET_MX35PDK
488 bool "Support mx35pdk" 488 bool "Support mx35pdk"
489 select BOARD_LATE_INIT 489 select BOARD_LATE_INIT
490 select CPU_ARM1136 490 select CPU_ARM1136
491 491
492 config ARCH_BCM283X 492 config ARCH_BCM283X
493 bool "Broadcom BCM283X family" 493 bool "Broadcom BCM283X family"
494 select DM 494 select DM
495 select DM_SERIAL 495 select DM_SERIAL
496 select DM_GPIO 496 select DM_GPIO
497 select OF_CONTROL 497 select OF_CONTROL
498 imply FAT_WRITE 498 imply FAT_WRITE
499 499
500 config TARGET_VEXPRESS_CA15_TC2 500 config TARGET_VEXPRESS_CA15_TC2
501 bool "Support vexpress_ca15_tc2" 501 bool "Support vexpress_ca15_tc2"
502 select CPU_V7 502 select CPU_V7
503 select CPU_V7_HAS_NONSEC 503 select CPU_V7_HAS_NONSEC
504 select CPU_V7_HAS_VIRT 504 select CPU_V7_HAS_VIRT
505 505
506 config TARGET_VEXPRESS_CA5X2 506 config TARGET_VEXPRESS_CA5X2
507 bool "Support vexpress_ca5x2" 507 bool "Support vexpress_ca5x2"
508 select CPU_V7 508 select CPU_V7
509 509
510 config TARGET_VEXPRESS_CA9X4 510 config TARGET_VEXPRESS_CA9X4
511 bool "Support vexpress_ca9x4" 511 bool "Support vexpress_ca9x4"
512 select CPU_V7 512 select CPU_V7
513 513
514 config TARGET_BCM23550_W1D 514 config TARGET_BCM23550_W1D
515 bool "Support bcm23550_w1d" 515 bool "Support bcm23550_w1d"
516 select CPU_V7 516 select CPU_V7
517 imply CRC32_VERIFY 517 imply CRC32_VERIFY
518 imply FAT_WRITE 518 imply FAT_WRITE
519 519
520 config TARGET_BCM28155_AP 520 config TARGET_BCM28155_AP
521 bool "Support bcm28155_ap" 521 bool "Support bcm28155_ap"
522 select CPU_V7 522 select CPU_V7
523 imply CRC32_VERIFY 523 imply CRC32_VERIFY
524 imply FAT_WRITE 524 imply FAT_WRITE
525 525
526 config TARGET_BCMCYGNUS 526 config TARGET_BCMCYGNUS
527 bool "Support bcmcygnus" 527 bool "Support bcmcygnus"
528 select CPU_V7 528 select CPU_V7
529 imply CRC32_VERIFY 529 imply CRC32_VERIFY
530 imply CMD_HASH 530 imply CMD_HASH
531 imply FAT_WRITE 531 imply FAT_WRITE
532 imply HASH_VERIFY 532 imply HASH_VERIFY
533 imply NETDEVICES 533 imply NETDEVICES
534 imply BCM_SF2_ETH 534 imply BCM_SF2_ETH
535 imply BCM_SF2_ETH_GMAC 535 imply BCM_SF2_ETH_GMAC
536 536
537 config TARGET_BCMNSP 537 config TARGET_BCMNSP
538 bool "Support bcmnsp" 538 bool "Support bcmnsp"
539 select CPU_V7 539 select CPU_V7
540 540
541 config TARGET_BCMNS2 541 config TARGET_BCMNS2
542 bool "Support Broadcom Northstar2" 542 bool "Support Broadcom Northstar2"
543 select ARM64 543 select ARM64
544 help 544 help
545 Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit 545 Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit
546 ARMv8 Cortex-A57 processors targeting a broad range of networking 546 ARMv8 Cortex-A57 processors targeting a broad range of networking
547 applications 547 applications
548 548
549 config ARCH_EXYNOS 549 config ARCH_EXYNOS
550 bool "Samsung EXYNOS" 550 bool "Samsung EXYNOS"
551 select DM 551 select DM
552 select DM_I2C 552 select DM_I2C
553 select DM_SPI_FLASH 553 select DM_SPI_FLASH
554 select DM_SERIAL 554 select DM_SERIAL
555 select DM_SPI 555 select DM_SPI
556 select DM_GPIO 556 select DM_GPIO
557 select DM_KEYBOARD 557 select DM_KEYBOARD
558 imply FAT_WRITE 558 imply FAT_WRITE
559 559
560 config ARCH_S5PC1XX 560 config ARCH_S5PC1XX
561 bool "Samsung S5PC1XX" 561 bool "Samsung S5PC1XX"
562 select CPU_V7 562 select CPU_V7
563 select DM 563 select DM
564 select DM_SERIAL 564 select DM_SERIAL
565 select DM_GPIO 565 select DM_GPIO
566 select DM_I2C 566 select DM_I2C
567 567
568 config ARCH_HIGHBANK 568 config ARCH_HIGHBANK
569 bool "Calxeda Highbank" 569 bool "Calxeda Highbank"
570 select CPU_V7 570 select CPU_V7
571 571
572 config ARCH_INTEGRATOR 572 config ARCH_INTEGRATOR
573 bool "ARM Ltd. Integrator family" 573 bool "ARM Ltd. Integrator family"
574 select DM 574 select DM
575 select DM_SERIAL 575 select DM_SERIAL
576 576
577 config ARCH_KEYSTONE 577 config ARCH_KEYSTONE
578 bool "TI Keystone" 578 bool "TI Keystone"
579 select CPU_V7 579 select CPU_V7
580 select SUPPORT_SPL 580 select SUPPORT_SPL
581 select SYS_THUMB_BUILD 581 select SYS_THUMB_BUILD
582 select CMD_POWEROFF 582 select CMD_POWEROFF
583 imply CMD_MTDPARTS 583 imply CMD_MTDPARTS
584 imply FIT 584 imply FIT
585 imply CMD_SAVES 585 imply CMD_SAVES
586 586
587 config ARCH_OMAP2PLUS 587 config ARCH_OMAP2PLUS
588 bool "TI OMAP2+" 588 bool "TI OMAP2+"
589 select CPU_V7 589 select CPU_V7
590 select SPL_BOARD_INIT if SPL 590 select SPL_BOARD_INIT if SPL
591 select SUPPORT_SPL 591 select SUPPORT_SPL
592 imply FIT 592 imply FIT
593 593
594 config ARCH_MESON 594 config ARCH_MESON
595 bool "Amlogic Meson" 595 bool "Amlogic Meson"
596 help 596 help
597 Support for the Meson SoC family developed by Amlogic Inc., 597 Support for the Meson SoC family developed by Amlogic Inc.,
598 targeted at media players and tablet computers. We currently 598 targeted at media players and tablet computers. We currently
599 support the S905 (GXBaby) 64-bit SoC. 599 support the S905 (GXBaby) 64-bit SoC.
600 600
601 config ARCH_MX7ULP 601 config ARCH_MX7ULP
602 bool "NXP MX7ULP" 602 bool "NXP MX7ULP"
603 select CPU_V7 603 select CPU_V7
604 select ROM_UNIFIED_SECTIONS 604 select ROM_UNIFIED_SECTIONS
605 605
606 config ARCH_MX7 606 config ARCH_MX7
607 bool "Freescale MX7" 607 bool "Freescale MX7"
608 select CPU_V7 608 select CPU_V7
609 select SYS_FSL_HAS_SEC if SECURE_BOOT 609 select SYS_FSL_HAS_SEC if SECURE_BOOT
610 select SYS_FSL_SEC_COMPAT_4 610 select SYS_FSL_SEC_COMPAT_4
611 select SYS_FSL_SEC_LE 611 select SYS_FSL_SEC_LE
612 select BOARD_EARLY_INIT_F 612 select BOARD_EARLY_INIT_F
613 select ARCH_MISC_INIT 613 select ARCH_MISC_INIT
614 614
615 config ARCH_MX6 615 config ARCH_MX6
616 bool "Freescale MX6" 616 bool "Freescale MX6"
617 select CPU_V7 617 select CPU_V7
618 select SYS_FSL_HAS_SEC if SECURE_BOOT 618 select SYS_FSL_HAS_SEC if SECURE_BOOT
619 select SYS_FSL_SEC_COMPAT_4 619 select SYS_FSL_SEC_COMPAT_4
620 select SYS_FSL_SEC_LE 620 select SYS_FSL_SEC_LE
621 select SYS_THUMB_BUILD if SPL 621 select SYS_THUMB_BUILD if SPL
622 622
623 if ARCH_MX6 623 if ARCH_MX6
624 config SPL_LDSCRIPT 624 config SPL_LDSCRIPT
625 default "arch/arm/mach-omap2/u-boot-spl.lds" 625 default "arch/arm/mach-omap2/u-boot-spl.lds"
626 endif 626 endif
627 627
628 config ARCH_MX5 628 config ARCH_MX5
629 bool "Freescale MX5" 629 bool "Freescale MX5"
630 select CPU_V7 630 select CPU_V7
631 select BOARD_EARLY_INIT_F 631 select BOARD_EARLY_INIT_F
632 632
633 config ARCH_RMOBILE 633 config ARCH_RMOBILE
634 bool "Renesas ARM SoCs" 634 bool "Renesas ARM SoCs"
635 select DM 635 select DM
636 select DM_SERIAL 636 select DM_SERIAL
637 select BOARD_EARLY_INIT_F 637 select BOARD_EARLY_INIT_F
638 imply FAT_WRITE 638 imply FAT_WRITE
639 imply SYS_THUMB_BUILD 639 imply SYS_THUMB_BUILD
640 640
641 config TARGET_S32V234EVB 641 config TARGET_S32V234EVB
642 bool "Support s32v234evb" 642 bool "Support s32v234evb"
643 select ARM64 643 select ARM64
644 select SYS_FSL_ERRATUM_ESDHC111 644 select SYS_FSL_ERRATUM_ESDHC111
645 645
646 config ARCH_SNAPDRAGON 646 config ARCH_SNAPDRAGON
647 bool "Qualcomm Snapdragon SoCs" 647 bool "Qualcomm Snapdragon SoCs"
648 select ARM64 648 select ARM64
649 select DM 649 select DM
650 select DM_GPIO 650 select DM_GPIO
651 select DM_SERIAL 651 select DM_SERIAL
652 select SPMI 652 select SPMI
653 select OF_CONTROL 653 select OF_CONTROL
654 select OF_SEPARATE 654 select OF_SEPARATE
655 655
656 config ARCH_SOCFPGA 656 config ARCH_SOCFPGA
657 bool "Altera SOCFPGA family" 657 bool "Altera SOCFPGA family"
658 select CPU_V7 658 select CPU_V7
659 select SUPPORT_SPL 659 select SUPPORT_SPL
660 select OF_CONTROL 660 select OF_CONTROL
661 select SPL_OF_CONTROL 661 select SPL_OF_CONTROL
662 select DM 662 select DM
663 select DM_SPI_FLASH 663 select DM_SPI_FLASH
664 select DM_SPI 664 select DM_SPI
665 select ENABLE_ARM_SOC_BOOT0_HOOK 665 select ENABLE_ARM_SOC_BOOT0_HOOK
666 select ARCH_EARLY_INIT_R 666 select ARCH_EARLY_INIT_R
667 select ARCH_MISC_INIT 667 select ARCH_MISC_INIT
668 select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION 668 select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
669 select SYS_THUMB_BUILD 669 select SYS_THUMB_BUILD
670 imply CMD_MTDPARTS 670 imply CMD_MTDPARTS
671 imply CRC32_VERIFY 671 imply CRC32_VERIFY
672 imply FAT_WRITE 672 imply FAT_WRITE
673 673
674 config ARCH_SUNXI 674 config ARCH_SUNXI
675 bool "Support sunxi (Allwinner) SoCs" 675 bool "Support sunxi (Allwinner) SoCs"
676 select CMD_GPIO 676 select CMD_GPIO
677 select CMD_MMC if MMC 677 select CMD_MMC if MMC
678 select CMD_USB if DISTRO_DEFAULTS 678 select CMD_USB if DISTRO_DEFAULTS
679 select DM 679 select DM
680 select DM_ETH 680 select DM_ETH
681 select DM_GPIO 681 select DM_GPIO
682 select DM_KEYBOARD 682 select DM_KEYBOARD
683 select DM_SERIAL 683 select DM_SERIAL
684 select DM_USB if DISTRO_DEFAULTS 684 select DM_USB if DISTRO_DEFAULTS
685 select OF_BOARD_SETUP 685 select OF_BOARD_SETUP
686 select OF_CONTROL 686 select OF_CONTROL
687 select OF_SEPARATE 687 select OF_SEPARATE
688 select SPL_STACK_R if SPL 688 select SPL_STACK_R if SPL
689 select SPL_SYS_MALLOC_SIMPLE if SPL 689 select SPL_SYS_MALLOC_SIMPLE if SPL
690 select SYS_NS16550 690 select SYS_NS16550
691 select SPL_SYS_THUMB_BUILD if !ARM64 691 select SPL_SYS_THUMB_BUILD if !ARM64
692 select USB if DISTRO_DEFAULTS 692 select USB if DISTRO_DEFAULTS
693 select USB_STORAGE if DISTRO_DEFAULTS 693 select USB_STORAGE if DISTRO_DEFAULTS
694 select USB_KEYBOARD if DISTRO_DEFAULTS 694 select USB_KEYBOARD if DISTRO_DEFAULTS
695 select USE_TINY_PRINTF 695 select USE_TINY_PRINTF
696 imply CMD_FASTBOOT 696 imply CMD_FASTBOOT
697 imply FASTBOOT 697 imply FASTBOOT
698 imply FAT_WRITE 698 imply FAT_WRITE
699 imply PRE_CONSOLE_BUFFER 699 imply PRE_CONSOLE_BUFFER
700 imply SPL_GPIO_SUPPORT 700 imply SPL_GPIO_SUPPORT
701 imply SPL_LIBCOMMON_SUPPORT 701 imply SPL_LIBCOMMON_SUPPORT
702 imply SPL_LIBDISK_SUPPORT 702 imply SPL_LIBDISK_SUPPORT
703 imply SPL_LIBGENERIC_SUPPORT 703 imply SPL_LIBGENERIC_SUPPORT
704 imply SPL_MMC_SUPPORT if MMC 704 imply SPL_MMC_SUPPORT if MMC
705 imply SPL_POWER_SUPPORT 705 imply SPL_POWER_SUPPORT
706 imply SPL_SERIAL_SUPPORT 706 imply SPL_SERIAL_SUPPORT
707 imply USB_FUNCTION_FASTBOOT 707 imply USB_FUNCTION_FASTBOOT
708 708
709 config TARGET_TS4600 709 config TARGET_TS4600
710 bool "Support TS4600" 710 bool "Support TS4600"
711 select CPU_ARM926EJS 711 select CPU_ARM926EJS
712 select SUPPORT_SPL 712 select SUPPORT_SPL
713 713
714 config ARCH_VF610 714 config ARCH_VF610
715 bool "Freescale Vybrid" 715 bool "Freescale Vybrid"
716 select CPU_V7 716 select CPU_V7
717 select SYS_FSL_ERRATUM_ESDHC111 717 select SYS_FSL_ERRATUM_ESDHC111
718 imply CMD_MTDPARTS 718 imply CMD_MTDPARTS
719 imply NAND 719 imply NAND
720 720
721 config ARCH_ZYNQ 721 config ARCH_ZYNQ
722 bool "Xilinx Zynq Platform" 722 bool "Xilinx Zynq Platform"
723 select BOARD_LATE_INIT 723 select BOARD_LATE_INIT
724 select CPU_V7 724 select CPU_V7
725 select SUPPORT_SPL 725 select SUPPORT_SPL
726 select OF_CONTROL 726 select OF_CONTROL
727 select SPL_BOARD_INIT if SPL 727 select SPL_BOARD_INIT if SPL
728 select SPL_OF_CONTROL if SPL 728 select SPL_OF_CONTROL if SPL
729 select DM 729 select DM
730 select DM_ETH 730 select DM_ETH
731 select DM_GPIO 731 select DM_GPIO
732 select SPL_DM if SPL 732 select SPL_DM if SPL
733 select DM_MMC 733 select DM_MMC
734 select DM_SPI 734 select DM_SPI
735 select DM_SERIAL 735 select DM_SERIAL
736 select DM_SPI_FLASH 736 select DM_SPI_FLASH
737 select SPL_SEPARATE_BSS if SPL 737 select SPL_SEPARATE_BSS if SPL
738 select DM_USB if USB 738 select DM_USB if USB
739 select BLK 739 select BLK
740 select CLK 740 select CLK
741 select SPL_CLK 741 select SPL_CLK
742 select CLK_ZYNQ 742 select CLK_ZYNQ
743 imply CMD_CLK 743 imply CMD_CLK
744 imply FAT_WRITE 744 imply FAT_WRITE
745 imply CMD_SPL 745 imply CMD_SPL
746 746
747 config ARCH_ZYNQMP 747 config ARCH_ZYNQMP
748 bool "Support Xilinx ZynqMP Platform" 748 bool "Support Xilinx ZynqMP Platform"
749 select ARM64 749 select ARM64
750 select BOARD_LATE_INIT 750 select BOARD_LATE_INIT
751 select DM 751 select DM
752 select OF_CONTROL 752 select OF_CONTROL
753 select DM_SERIAL 753 select DM_SERIAL
754 select SUPPORT_SPL 754 select SUPPORT_SPL
755 select CLK 755 select CLK
756 select SPL_BOARD_INIT if SPL 756 select SPL_BOARD_INIT if SPL
757 select SPL_CLK 757 select SPL_CLK
758 select DM_USB if USB 758 select DM_USB if USB
759 imply FAT_WRITE 759 imply FAT_WRITE
760 760
761 config TEGRA 761 config TEGRA
762 bool "NVIDIA Tegra" 762 bool "NVIDIA Tegra"
763 imply FAT_WRITE 763 imply FAT_WRITE
764 764
765 config TARGET_VEXPRESS64_AEMV8A 765 config TARGET_VEXPRESS64_AEMV8A
766 bool "Support vexpress_aemv8a" 766 bool "Support vexpress_aemv8a"
767 select ARM64 767 select ARM64
768 768
769 config TARGET_VEXPRESS64_BASE_FVP 769 config TARGET_VEXPRESS64_BASE_FVP
770 bool "Support Versatile Express ARMv8a FVP BASE model" 770 bool "Support Versatile Express ARMv8a FVP BASE model"
771 select ARM64 771 select ARM64
772 select SEMIHOSTING 772 select SEMIHOSTING
773 773
774 config TARGET_VEXPRESS64_BASE_FVP_DRAM 774 config TARGET_VEXPRESS64_BASE_FVP_DRAM
775 bool "Support Versatile Express ARMv8a FVP BASE model booting from DRAM" 775 bool "Support Versatile Express ARMv8a FVP BASE model booting from DRAM"
776 select ARM64 776 select ARM64
777 help 777 help
778 This target is derived from TARGET_VEXPRESS64_BASE_FVP and over-rides 778 This target is derived from TARGET_VEXPRESS64_BASE_FVP and over-rides
779 the default config to allow the user to load the images directly into 779 the default config to allow the user to load the images directly into
780 DRAM using model parameters rather than by using semi-hosting to load 780 DRAM using model parameters rather than by using semi-hosting to load
781 the files from the host filesystem. 781 the files from the host filesystem.
782 782
783 config TARGET_VEXPRESS64_JUNO 783 config TARGET_VEXPRESS64_JUNO
784 bool "Support Versatile Express Juno Development Platform" 784 bool "Support Versatile Express Juno Development Platform"
785 select ARM64 785 select ARM64
786 786
787 config TARGET_LS2080A_EMU 787 config TARGET_LS2080A_EMU
788 bool "Support ls2080a_emu" 788 bool "Support ls2080a_emu"
789 select ARCH_LS2080A 789 select ARCH_LS2080A
790 select ARM64 790 select ARM64
791 select ARMV8_MULTIENTRY 791 select ARMV8_MULTIENTRY
792 select ARCH_MISC_INIT 792 select ARCH_MISC_INIT
793 help 793 help
794 Support for Freescale LS2080A_EMU platform 794 Support for Freescale LS2080A_EMU platform
795 The LS2080A Development System (EMULATOR) is a pre silicon 795 The LS2080A Development System (EMULATOR) is a pre silicon
796 development platform that supports the QorIQ LS2080A 796 development platform that supports the QorIQ LS2080A
797 Layerscape Architecture processor. 797 Layerscape Architecture processor.
798 798
799 config TARGET_LS2080A_SIMU 799 config TARGET_LS2080A_SIMU
800 bool "Support ls2080a_simu" 800 bool "Support ls2080a_simu"
801 select ARCH_LS2080A 801 select ARCH_LS2080A
802 select ARM64 802 select ARM64
803 select ARMV8_MULTIENTRY 803 select ARMV8_MULTIENTRY
804 select ARCH_MISC_INIT 804 select ARCH_MISC_INIT
805 help 805 help
806 Support for Freescale LS2080A_SIMU platform 806 Support for Freescale LS2080A_SIMU platform
807 The LS2080A Development System (QDS) is a pre silicon 807 The LS2080A Development System (QDS) is a pre silicon
808 development platform that supports the QorIQ LS2080A 808 development platform that supports the QorIQ LS2080A
809 Layerscape Architecture processor. 809 Layerscape Architecture processor.
810 810
811 config TARGET_LS1088AQDS
812 bool "Support ls1088aqds"
813 select ARCH_LS1088A
814 select ARM64
815 select ARMV8_MULTIENTRY
816 select ARCH_MISC_INIT
817 select BOARD_LATE_INIT
818 help
819 Support for NXP LS1088AQDS platform
820 The LS1088A Development System (QDS) is a high-performance
821 development platform that supports the QorIQ LS1088A
822 Layerscape Architecture processor.
823
811 config TARGET_LS2080AQDS 824 config TARGET_LS2080AQDS
812 bool "Support ls2080aqds" 825 bool "Support ls2080aqds"
813 select ARCH_LS2080A 826 select ARCH_LS2080A
814 select ARM64 827 select ARM64
815 select ARMV8_MULTIENTRY 828 select ARMV8_MULTIENTRY
816 select BOARD_LATE_INIT 829 select BOARD_LATE_INIT
817 select SUPPORT_SPL 830 select SUPPORT_SPL
818 select ARCH_MISC_INIT 831 select ARCH_MISC_INIT
819 imply SCSI 832 imply SCSI
820 help 833 help
821 Support for Freescale LS2080AQDS platform 834 Support for Freescale LS2080AQDS platform
822 The LS2080A Development System (QDS) is a high-performance 835 The LS2080A Development System (QDS) is a high-performance
823 development platform that supports the QorIQ LS2080A 836 development platform that supports the QorIQ LS2080A
824 Layerscape Architecture processor. 837 Layerscape Architecture processor.
825 838
826 config TARGET_LS2080ARDB 839 config TARGET_LS2080ARDB
827 bool "Support ls2080ardb" 840 bool "Support ls2080ardb"
828 select ARCH_LS2080A 841 select ARCH_LS2080A
829 select ARM64 842 select ARM64
830 select ARMV8_MULTIENTRY 843 select ARMV8_MULTIENTRY
831 select BOARD_LATE_INIT 844 select BOARD_LATE_INIT
832 select SUPPORT_SPL 845 select SUPPORT_SPL
833 select ARCH_MISC_INIT 846 select ARCH_MISC_INIT
834 imply SCSI 847 imply SCSI
835 help 848 help
836 Support for Freescale LS2080ARDB platform. 849 Support for Freescale LS2080ARDB platform.
837 The LS2080A Reference design board (RDB) is a high-performance 850 The LS2080A Reference design board (RDB) is a high-performance
838 development platform that supports the QorIQ LS2080A 851 development platform that supports the QorIQ LS2080A
839 Layerscape Architecture processor. 852 Layerscape Architecture processor.
840 853
841 config TARGET_LS2081ARDB 854 config TARGET_LS2081ARDB
842 bool "Support ls2081ardb" 855 bool "Support ls2081ardb"
843 select ARCH_LS2080A 856 select ARCH_LS2080A
844 select ARM64 857 select ARM64
845 select ARMV8_MULTIENTRY 858 select ARMV8_MULTIENTRY
846 select BOARD_LATE_INIT 859 select BOARD_LATE_INIT
847 select SUPPORT_SPL 860 select SUPPORT_SPL
848 select ARCH_MISC_INIT 861 select ARCH_MISC_INIT
849 help 862 help
850 Support for Freescale LS2081ARDB platform. 863 Support for Freescale LS2081ARDB platform.
851 The LS2081A Reference design board (RDB) is a high-performance 864 The LS2081A Reference design board (RDB) is a high-performance
852 development platform that supports the QorIQ LS2081A/LS2041A 865 development platform that supports the QorIQ LS2081A/LS2041A
853 Layerscape Architecture processor. 866 Layerscape Architecture processor.
854 867
855 config TARGET_HIKEY 868 config TARGET_HIKEY
856 bool "Support HiKey 96boards Consumer Edition Platform" 869 bool "Support HiKey 96boards Consumer Edition Platform"
857 select ARM64 870 select ARM64
858 select DM 871 select DM
859 select DM_GPIO 872 select DM_GPIO
860 select DM_SERIAL 873 select DM_SERIAL
861 select OF_CONTROL 874 select OF_CONTROL
862 help 875 help
863 Support for HiKey 96boards platform. It features a HI6220 876 Support for HiKey 96boards platform. It features a HI6220
864 SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM. 877 SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
865 878
866 config TARGET_POPLAR 879 config TARGET_POPLAR
867 bool "Support Poplar 96boards Enterprise Edition Platform" 880 bool "Support Poplar 96boards Enterprise Edition Platform"
868 select ARM64 881 select ARM64
869 select DM 882 select DM
870 select OF_CONTROL 883 select OF_CONTROL
871 select DM_SERIAL 884 select DM_SERIAL
872 select DM_USB 885 select DM_USB
873 help 886 help
874 Support for Poplar 96boards EE platform. It features a HI3798cv200 887 Support for Poplar 96boards EE platform. It features a HI3798cv200
875 SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU 888 SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU
876 making it capable of running any commercial set-top solution based on 889 making it capable of running any commercial set-top solution based on
877 Linux or Android. 890 Linux or Android.
878 891
879 config TARGET_LS1012AQDS 892 config TARGET_LS1012AQDS
880 bool "Support ls1012aqds" 893 bool "Support ls1012aqds"
881 select ARCH_LS1012A 894 select ARCH_LS1012A
882 select ARM64 895 select ARM64
883 select BOARD_LATE_INIT 896 select BOARD_LATE_INIT
884 help 897 help
885 Support for Freescale LS1012AQDS platform. 898 Support for Freescale LS1012AQDS platform.
886 The LS1012A Development System (QDS) is a high-performance 899 The LS1012A Development System (QDS) is a high-performance
887 development platform that supports the QorIQ LS1012A 900 development platform that supports the QorIQ LS1012A
888 Layerscape Architecture processor. 901 Layerscape Architecture processor.
889 902
890 config TARGET_LS1012ARDB 903 config TARGET_LS1012ARDB
891 bool "Support ls1012ardb" 904 bool "Support ls1012ardb"
892 select ARCH_LS1012A 905 select ARCH_LS1012A
893 select ARM64 906 select ARM64
894 select BOARD_LATE_INIT 907 select BOARD_LATE_INIT
895 imply SCSI 908 imply SCSI
896 help 909 help
897 Support for Freescale LS1012ARDB platform. 910 Support for Freescale LS1012ARDB platform.
898 The LS1012A Reference design board (RDB) is a high-performance 911 The LS1012A Reference design board (RDB) is a high-performance
899 development platform that supports the QorIQ LS1012A 912 development platform that supports the QorIQ LS1012A
900 Layerscape Architecture processor. 913 Layerscape Architecture processor.
901 914
902 config TARGET_LS1012AFRDM 915 config TARGET_LS1012AFRDM
903 bool "Support ls1012afrdm" 916 bool "Support ls1012afrdm"
904 select ARCH_LS1012A 917 select ARCH_LS1012A
905 select ARM64 918 select ARM64
906 help 919 help
907 Support for Freescale LS1012AFRDM platform. 920 Support for Freescale LS1012AFRDM platform.
908 The LS1012A Freedom board (FRDM) is a high-performance 921 The LS1012A Freedom board (FRDM) is a high-performance
909 development platform that supports the QorIQ LS1012A 922 development platform that supports the QorIQ LS1012A
910 Layerscape Architecture processor. 923 Layerscape Architecture processor.
911 924
912 config TARGET_LS1088ARDB 925 config TARGET_LS1088ARDB
913 bool "Support ls1088ardb" 926 bool "Support ls1088ardb"
914 select ARCH_LS1088A 927 select ARCH_LS1088A
915 select ARM64 928 select ARM64
916 select ARMV8_MULTIENTRY 929 select ARMV8_MULTIENTRY
917 select ARCH_MISC_INIT 930 select ARCH_MISC_INIT
918 select BOARD_LATE_INIT 931 select BOARD_LATE_INIT
919 help 932 help
920 Support for NXP LS1088ARDB platform. 933 Support for NXP LS1088ARDB platform.
921 The LS1088A Reference design board (RDB) is a high-performance 934 The LS1088A Reference design board (RDB) is a high-performance
922 development platform that supports the QorIQ LS1088A 935 development platform that supports the QorIQ LS1088A
923 Layerscape Architecture processor. 936 Layerscape Architecture processor.
924 937
925 config TARGET_LS1021AQDS 938 config TARGET_LS1021AQDS
926 bool "Support ls1021aqds" 939 bool "Support ls1021aqds"
927 select BOARD_LATE_INIT 940 select BOARD_LATE_INIT
928 select CPU_V7 941 select CPU_V7
929 select CPU_V7_HAS_NONSEC 942 select CPU_V7_HAS_NONSEC
930 select CPU_V7_HAS_VIRT 943 select CPU_V7_HAS_VIRT
931 select SUPPORT_SPL 944 select SUPPORT_SPL
932 select ARCH_LS1021A 945 select ARCH_LS1021A
933 select ARCH_SUPPORT_PSCI 946 select ARCH_SUPPORT_PSCI
934 select LS1_DEEP_SLEEP 947 select LS1_DEEP_SLEEP
935 select SYS_FSL_DDR 948 select SYS_FSL_DDR
936 select BOARD_EARLY_INIT_F 949 select BOARD_EARLY_INIT_F
937 imply SCSI 950 imply SCSI
938 951
939 config TARGET_LS1021ATWR 952 config TARGET_LS1021ATWR
940 bool "Support ls1021atwr" 953 bool "Support ls1021atwr"
941 select BOARD_LATE_INIT 954 select BOARD_LATE_INIT
942 select CPU_V7 955 select CPU_V7
943 select CPU_V7_HAS_NONSEC 956 select CPU_V7_HAS_NONSEC
944 select CPU_V7_HAS_VIRT 957 select CPU_V7_HAS_VIRT
945 select SUPPORT_SPL 958 select SUPPORT_SPL
946 select ARCH_LS1021A 959 select ARCH_LS1021A
947 select ARCH_SUPPORT_PSCI 960 select ARCH_SUPPORT_PSCI
948 select LS1_DEEP_SLEEP 961 select LS1_DEEP_SLEEP
949 select BOARD_EARLY_INIT_F 962 select BOARD_EARLY_INIT_F
950 imply SCSI 963 imply SCSI
951 964
952 config TARGET_LS1021AIOT 965 config TARGET_LS1021AIOT
953 bool "Support ls1021aiot" 966 bool "Support ls1021aiot"
954 select BOARD_LATE_INIT 967 select BOARD_LATE_INIT
955 select CPU_V7 968 select CPU_V7
956 select CPU_V7_HAS_NONSEC 969 select CPU_V7_HAS_NONSEC
957 select CPU_V7_HAS_VIRT 970 select CPU_V7_HAS_VIRT
958 select SUPPORT_SPL 971 select SUPPORT_SPL
959 select ARCH_LS1021A 972 select ARCH_LS1021A
960 select ARCH_SUPPORT_PSCI 973 select ARCH_SUPPORT_PSCI
961 imply SCSI 974 imply SCSI
962 help 975 help
963 Support for Freescale LS1021AIOT platform. 976 Support for Freescale LS1021AIOT platform.
964 The LS1021A Freescale board (IOT) is a high-performance 977 The LS1021A Freescale board (IOT) is a high-performance
965 development platform that supports the QorIQ LS1021A 978 development platform that supports the QorIQ LS1021A
966 Layerscape Architecture processor. 979 Layerscape Architecture processor.
967 980
968 config TARGET_LS1043AQDS 981 config TARGET_LS1043AQDS
969 bool "Support ls1043aqds" 982 bool "Support ls1043aqds"
970 select ARCH_LS1043A 983 select ARCH_LS1043A
971 select ARM64 984 select ARM64
972 select ARMV8_MULTIENTRY 985 select ARMV8_MULTIENTRY
973 select BOARD_LATE_INIT 986 select BOARD_LATE_INIT
974 select SUPPORT_SPL 987 select SUPPORT_SPL
975 select BOARD_EARLY_INIT_F 988 select BOARD_EARLY_INIT_F
976 imply SCSI 989 imply SCSI
977 help 990 help
978 Support for Freescale LS1043AQDS platform. 991 Support for Freescale LS1043AQDS platform.
979 992
980 config TARGET_LS1043ARDB 993 config TARGET_LS1043ARDB
981 bool "Support ls1043ardb" 994 bool "Support ls1043ardb"
982 select ARCH_LS1043A 995 select ARCH_LS1043A
983 select ARM64 996 select ARM64
984 select ARMV8_MULTIENTRY 997 select ARMV8_MULTIENTRY
985 select BOARD_LATE_INIT 998 select BOARD_LATE_INIT
986 select SUPPORT_SPL 999 select SUPPORT_SPL
987 select BOARD_EARLY_INIT_F 1000 select BOARD_EARLY_INIT_F
988 imply SCSI 1001 imply SCSI
989 help 1002 help
990 Support for Freescale LS1043ARDB platform. 1003 Support for Freescale LS1043ARDB platform.
991 1004
992 config TARGET_LS1046AQDS 1005 config TARGET_LS1046AQDS
993 bool "Support ls1046aqds" 1006 bool "Support ls1046aqds"
994 select ARCH_LS1046A 1007 select ARCH_LS1046A
995 select ARM64 1008 select ARM64
996 select ARMV8_MULTIENTRY 1009 select ARMV8_MULTIENTRY
997 select BOARD_LATE_INIT 1010 select BOARD_LATE_INIT
998 select SUPPORT_SPL 1011 select SUPPORT_SPL
999 select DM_SPI_FLASH if DM_SPI 1012 select DM_SPI_FLASH if DM_SPI
1000 select BOARD_EARLY_INIT_F 1013 select BOARD_EARLY_INIT_F
1001 imply SCSI 1014 imply SCSI
1002 help 1015 help
1003 Support for Freescale LS1046AQDS platform. 1016 Support for Freescale LS1046AQDS platform.
1004 The LS1046A Development System (QDS) is a high-performance 1017 The LS1046A Development System (QDS) is a high-performance
1005 development platform that supports the QorIQ LS1046A 1018 development platform that supports the QorIQ LS1046A
1006 Layerscape Architecture processor. 1019 Layerscape Architecture processor.
1007 1020
1008 config TARGET_LS1046ARDB 1021 config TARGET_LS1046ARDB
1009 bool "Support ls1046ardb" 1022 bool "Support ls1046ardb"
1010 select ARCH_LS1046A 1023 select ARCH_LS1046A
1011 select ARM64 1024 select ARM64
1012 select ARMV8_MULTIENTRY 1025 select ARMV8_MULTIENTRY
1013 select BOARD_LATE_INIT 1026 select BOARD_LATE_INIT
1014 select SUPPORT_SPL 1027 select SUPPORT_SPL
1015 select DM_SPI_FLASH if DM_SPI 1028 select DM_SPI_FLASH if DM_SPI
1016 select POWER_MC34VR500 1029 select POWER_MC34VR500
1017 select BOARD_EARLY_INIT_F 1030 select BOARD_EARLY_INIT_F
1018 imply SCSI 1031 imply SCSI
1019 help 1032 help
1020 Support for Freescale LS1046ARDB platform. 1033 Support for Freescale LS1046ARDB platform.
1021 The LS1046A Reference Design Board (RDB) is a high-performance 1034 The LS1046A Reference Design Board (RDB) is a high-performance
1022 development platform that supports the QorIQ LS1046A 1035 development platform that supports the QorIQ LS1046A
1023 Layerscape Architecture processor. 1036 Layerscape Architecture processor.
1024 1037
1025 config TARGET_H2200 1038 config TARGET_H2200
1026 bool "Support h2200" 1039 bool "Support h2200"
1027 select CPU_PXA 1040 select CPU_PXA
1028 1041
1029 config TARGET_ZIPITZ2 1042 config TARGET_ZIPITZ2
1030 bool "Support zipitz2" 1043 bool "Support zipitz2"
1031 select CPU_PXA 1044 select CPU_PXA
1032 1045
1033 config TARGET_COLIBRI_PXA270 1046 config TARGET_COLIBRI_PXA270
1034 bool "Support colibri_pxa270" 1047 bool "Support colibri_pxa270"
1035 select CPU_PXA 1048 select CPU_PXA
1036 1049
1037 config ARCH_UNIPHIER 1050 config ARCH_UNIPHIER
1038 bool "Socionext UniPhier SoCs" 1051 bool "Socionext UniPhier SoCs"
1039 select BOARD_LATE_INIT 1052 select BOARD_LATE_INIT
1040 select DM 1053 select DM
1041 select DM_GPIO 1054 select DM_GPIO
1042 select DM_I2C 1055 select DM_I2C
1043 select DM_MMC 1056 select DM_MMC
1044 select DM_RESET 1057 select DM_RESET
1045 select DM_SERIAL 1058 select DM_SERIAL
1046 select DM_USB 1059 select DM_USB
1047 select OF_CONTROL 1060 select OF_CONTROL
1048 select OF_LIBFDT 1061 select OF_LIBFDT
1049 select PINCTRL 1062 select PINCTRL
1050 select SPL_BOARD_INIT if SPL 1063 select SPL_BOARD_INIT if SPL
1051 select SPL_DM if SPL 1064 select SPL_DM if SPL
1052 select SPL_LIBCOMMON_SUPPORT if SPL 1065 select SPL_LIBCOMMON_SUPPORT if SPL
1053 select SPL_LIBGENERIC_SUPPORT if SPL 1066 select SPL_LIBGENERIC_SUPPORT if SPL
1054 select SPL_OF_CONTROL if SPL 1067 select SPL_OF_CONTROL if SPL
1055 select SPL_PINCTRL if SPL 1068 select SPL_PINCTRL if SPL
1056 select SUPPORT_SPL 1069 select SUPPORT_SPL
1057 imply FAT_WRITE 1070 imply FAT_WRITE
1058 help 1071 help
1059 Support for UniPhier SoC family developed by Socionext Inc. 1072 Support for UniPhier SoC family developed by Socionext Inc.
1060 (formerly, System LSI Business Division of Panasonic Corporation) 1073 (formerly, System LSI Business Division of Panasonic Corporation)
1061 1074
1062 config STM32 1075 config STM32
1063 bool "Support STM32" 1076 bool "Support STM32"
1064 select CPU_V7M 1077 select CPU_V7M
1065 select DM 1078 select DM
1066 select DM_SERIAL 1079 select DM_SERIAL
1067 select SYS_THUMB_BUILD 1080 select SYS_THUMB_BUILD
1068 1081
1069 config ARCH_STI 1082 config ARCH_STI
1070 bool "Support STMicrolectronics SoCs" 1083 bool "Support STMicrolectronics SoCs"
1071 select CPU_V7 1084 select CPU_V7
1072 select DM 1085 select DM
1073 select DM_SERIAL 1086 select DM_SERIAL
1074 select BLK 1087 select BLK
1075 select DM_MMC 1088 select DM_MMC
1076 select DM_RESET 1089 select DM_RESET
1077 help 1090 help
1078 Support for STMicroelectronics STiH407/10 SoC family. 1091 Support for STMicroelectronics STiH407/10 SoC family.
1079 This SoC is used on Linaro 96Board STiH410-B2260 1092 This SoC is used on Linaro 96Board STiH410-B2260
1080 1093
1081 config ARCH_ROCKCHIP 1094 config ARCH_ROCKCHIP
1082 bool "Support Rockchip SoCs" 1095 bool "Support Rockchip SoCs"
1083 select OF_CONTROL 1096 select OF_CONTROL
1084 select BLK 1097 select BLK
1085 select DM 1098 select DM
1086 select SPL_DM if SPL 1099 select SPL_DM if SPL
1087 select SYS_MALLOC_F 1100 select SYS_MALLOC_F
1088 select SYS_THUMB_BUILD if !ARM64 1101 select SYS_THUMB_BUILD if !ARM64
1089 select SPL_SYS_MALLOC_SIMPLE if SPL 1102 select SPL_SYS_MALLOC_SIMPLE if SPL
1090 select DM_GPIO 1103 select DM_GPIO
1091 select DM_I2C 1104 select DM_I2C
1092 select DM_MMC 1105 select DM_MMC
1093 select DM_SERIAL 1106 select DM_SERIAL
1094 select DM_SPI 1107 select DM_SPI
1095 select DM_SPI_FLASH 1108 select DM_SPI_FLASH
1096 select DM_USB if USB 1109 select DM_USB if USB
1097 select DM_PWM 1110 select DM_PWM
1098 select DM_REGULATOR 1111 select DM_REGULATOR
1099 imply CMD_FASTBOOT 1112 imply CMD_FASTBOOT
1100 imply FASTBOOT 1113 imply FASTBOOT
1101 imply FAT_WRITE 1114 imply FAT_WRITE
1102 imply USB_FUNCTION_FASTBOOT 1115 imply USB_FUNCTION_FASTBOOT
1103 imply SPL_SYSRESET 1116 imply SPL_SYSRESET
1104 1117
1105 config TARGET_THUNDERX_88XX 1118 config TARGET_THUNDERX_88XX
1106 bool "Support ThunderX 88xx" 1119 bool "Support ThunderX 88xx"
1107 select ARM64 1120 select ARM64
1108 select OF_CONTROL 1121 select OF_CONTROL
1109 select SYS_CACHE_SHIFT_7 1122 select SYS_CACHE_SHIFT_7
1110 1123
1111 config ARCH_ASPEED 1124 config ARCH_ASPEED
1112 bool "Support Aspeed SoCs" 1125 bool "Support Aspeed SoCs"
1113 select OF_CONTROL 1126 select OF_CONTROL
1114 select DM 1127 select DM
1115 1128
1116 endchoice 1129 endchoice
1117 1130
1118 source "arch/arm/mach-aspeed/Kconfig" 1131 source "arch/arm/mach-aspeed/Kconfig"
1119 1132
1120 source "arch/arm/mach-at91/Kconfig" 1133 source "arch/arm/mach-at91/Kconfig"
1121 1134
1122 source "arch/arm/mach-bcm283x/Kconfig" 1135 source "arch/arm/mach-bcm283x/Kconfig"
1123 1136
1124 source "arch/arm/mach-davinci/Kconfig" 1137 source "arch/arm/mach-davinci/Kconfig"
1125 1138
1126 source "arch/arm/mach-exynos/Kconfig" 1139 source "arch/arm/mach-exynos/Kconfig"
1127 1140
1128 source "arch/arm/mach-highbank/Kconfig" 1141 source "arch/arm/mach-highbank/Kconfig"
1129 1142
1130 source "arch/arm/mach-integrator/Kconfig" 1143 source "arch/arm/mach-integrator/Kconfig"
1131 1144
1132 source "arch/arm/mach-keystone/Kconfig" 1145 source "arch/arm/mach-keystone/Kconfig"
1133 1146
1134 source "arch/arm/mach-kirkwood/Kconfig" 1147 source "arch/arm/mach-kirkwood/Kconfig"
1135 1148
1136 source "arch/arm/mach-mvebu/Kconfig" 1149 source "arch/arm/mach-mvebu/Kconfig"
1137 1150
1138 source "arch/arm/cpu/armv7/ls102xa/Kconfig" 1151 source "arch/arm/cpu/armv7/ls102xa/Kconfig"
1139 1152
1140 source "arch/arm/mach-imx/mx7ulp/Kconfig" 1153 source "arch/arm/mach-imx/mx7ulp/Kconfig"
1141 1154
1142 source "arch/arm/mach-imx/mx7/Kconfig" 1155 source "arch/arm/mach-imx/mx7/Kconfig"
1143 1156
1144 source "arch/arm/mach-imx/mx6/Kconfig" 1157 source "arch/arm/mach-imx/mx6/Kconfig"
1145 1158
1146 source "arch/arm/mach-imx/mx5/Kconfig" 1159 source "arch/arm/mach-imx/mx5/Kconfig"
1147 1160
1148 source "arch/arm/mach-omap2/Kconfig" 1161 source "arch/arm/mach-omap2/Kconfig"
1149 1162
1150 source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig" 1163 source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
1151 1164
1152 source "arch/arm/mach-orion5x/Kconfig" 1165 source "arch/arm/mach-orion5x/Kconfig"
1153 1166
1154 source "arch/arm/mach-rmobile/Kconfig" 1167 source "arch/arm/mach-rmobile/Kconfig"
1155 1168
1156 source "arch/arm/mach-meson/Kconfig" 1169 source "arch/arm/mach-meson/Kconfig"
1157 1170
1158 source "arch/arm/mach-rockchip/Kconfig" 1171 source "arch/arm/mach-rockchip/Kconfig"
1159 1172
1160 source "arch/arm/mach-s5pc1xx/Kconfig" 1173 source "arch/arm/mach-s5pc1xx/Kconfig"
1161 1174
1162 source "arch/arm/mach-snapdragon/Kconfig" 1175 source "arch/arm/mach-snapdragon/Kconfig"
1163 1176
1164 source "arch/arm/mach-socfpga/Kconfig" 1177 source "arch/arm/mach-socfpga/Kconfig"
1165 1178
1166 source "arch/arm/mach-sti/Kconfig" 1179 source "arch/arm/mach-sti/Kconfig"
1167 1180
1168 source "arch/arm/mach-stm32/Kconfig" 1181 source "arch/arm/mach-stm32/Kconfig"
1169 1182
1170 source "arch/arm/mach-sunxi/Kconfig" 1183 source "arch/arm/mach-sunxi/Kconfig"
1171 1184
1172 source "arch/arm/mach-tegra/Kconfig" 1185 source "arch/arm/mach-tegra/Kconfig"
1173 1186
1174 source "arch/arm/mach-uniphier/Kconfig" 1187 source "arch/arm/mach-uniphier/Kconfig"
1175 1188
1176 source "arch/arm/cpu/armv7/vf610/Kconfig" 1189 source "arch/arm/cpu/armv7/vf610/Kconfig"
1177 1190
1178 source "arch/arm/mach-zynq/Kconfig" 1191 source "arch/arm/mach-zynq/Kconfig"
1179 1192
1180 source "arch/arm/cpu/armv7/Kconfig" 1193 source "arch/arm/cpu/armv7/Kconfig"
1181 1194
1182 source "arch/arm/cpu/armv8/zynqmp/Kconfig" 1195 source "arch/arm/cpu/armv8/zynqmp/Kconfig"
1183 1196
1184 source "arch/arm/cpu/armv8/Kconfig" 1197 source "arch/arm/cpu/armv8/Kconfig"
1185 1198
1186 source "arch/arm/mach-imx/Kconfig" 1199 source "arch/arm/mach-imx/Kconfig"
1187 1200
1188 source "board/aries/m28evk/Kconfig" 1201 source "board/aries/m28evk/Kconfig"
1189 source "board/bosch/shc/Kconfig" 1202 source "board/bosch/shc/Kconfig"
1190 source "board/CarMediaLab/flea3/Kconfig" 1203 source "board/CarMediaLab/flea3/Kconfig"
1191 source "board/Marvell/aspenite/Kconfig" 1204 source "board/Marvell/aspenite/Kconfig"
1192 source "board/Marvell/gplugd/Kconfig" 1205 source "board/Marvell/gplugd/Kconfig"
1193 source "board/armadeus/apf27/Kconfig" 1206 source "board/armadeus/apf27/Kconfig"
1194 source "board/armltd/vexpress/Kconfig" 1207 source "board/armltd/vexpress/Kconfig"
1195 source "board/armltd/vexpress64/Kconfig" 1208 source "board/armltd/vexpress64/Kconfig"
1196 source "board/bluegiga/apx4devkit/Kconfig" 1209 source "board/bluegiga/apx4devkit/Kconfig"
1197 source "board/broadcom/bcm23550_w1d/Kconfig" 1210 source "board/broadcom/bcm23550_w1d/Kconfig"
1198 source "board/broadcom/bcm28155_ap/Kconfig" 1211 source "board/broadcom/bcm28155_ap/Kconfig"
1199 source "board/broadcom/bcmcygnus/Kconfig" 1212 source "board/broadcom/bcmcygnus/Kconfig"
1200 source "board/broadcom/bcmnsp/Kconfig" 1213 source "board/broadcom/bcmnsp/Kconfig"
1201 source "board/broadcom/bcmns2/Kconfig" 1214 source "board/broadcom/bcmns2/Kconfig"
1202 source "board/cavium/thunderx/Kconfig" 1215 source "board/cavium/thunderx/Kconfig"
1203 source "board/cirrus/edb93xx/Kconfig" 1216 source "board/cirrus/edb93xx/Kconfig"
1204 source "board/creative/xfi3/Kconfig" 1217 source "board/creative/xfi3/Kconfig"
1205 source "board/freescale/ls2080a/Kconfig" 1218 source "board/freescale/ls2080a/Kconfig"
1206 source "board/freescale/ls2080aqds/Kconfig" 1219 source "board/freescale/ls2080aqds/Kconfig"
1207 source "board/freescale/ls2080ardb/Kconfig" 1220 source "board/freescale/ls2080ardb/Kconfig"
1208 source "board/freescale/ls1088a/Kconfig" 1221 source "board/freescale/ls1088a/Kconfig"
1209 source "board/freescale/ls1021aqds/Kconfig" 1222 source "board/freescale/ls1021aqds/Kconfig"
1210 source "board/freescale/ls1043aqds/Kconfig" 1223 source "board/freescale/ls1043aqds/Kconfig"
1211 source "board/freescale/ls1021atwr/Kconfig" 1224 source "board/freescale/ls1021atwr/Kconfig"
1212 source "board/freescale/ls1021aiot/Kconfig" 1225 source "board/freescale/ls1021aiot/Kconfig"
1213 source "board/freescale/ls1046aqds/Kconfig" 1226 source "board/freescale/ls1046aqds/Kconfig"
1214 source "board/freescale/ls1043ardb/Kconfig" 1227 source "board/freescale/ls1043ardb/Kconfig"
1215 source "board/freescale/ls1046ardb/Kconfig" 1228 source "board/freescale/ls1046ardb/Kconfig"
1216 source "board/freescale/ls1012aqds/Kconfig" 1229 source "board/freescale/ls1012aqds/Kconfig"
1217 source "board/freescale/ls1012ardb/Kconfig" 1230 source "board/freescale/ls1012ardb/Kconfig"
1218 source "board/freescale/ls1012afrdm/Kconfig" 1231 source "board/freescale/ls1012afrdm/Kconfig"
1219 source "board/freescale/mx23evk/Kconfig" 1232 source "board/freescale/mx23evk/Kconfig"
1220 source "board/freescale/mx25pdk/Kconfig" 1233 source "board/freescale/mx25pdk/Kconfig"
1221 source "board/freescale/mx28evk/Kconfig" 1234 source "board/freescale/mx28evk/Kconfig"
1222 source "board/freescale/mx31ads/Kconfig" 1235 source "board/freescale/mx31ads/Kconfig"
1223 source "board/freescale/mx31pdk/Kconfig" 1236 source "board/freescale/mx31pdk/Kconfig"
1224 source "board/freescale/mx35pdk/Kconfig" 1237 source "board/freescale/mx35pdk/Kconfig"
1225 source "board/freescale/s32v234evb/Kconfig" 1238 source "board/freescale/s32v234evb/Kconfig"
1226 source "board/gdsys/a38x/Kconfig" 1239 source "board/gdsys/a38x/Kconfig"
1227 source "board/grinn/chiliboard/Kconfig" 1240 source "board/grinn/chiliboard/Kconfig"
1228 source "board/gumstix/pepper/Kconfig" 1241 source "board/gumstix/pepper/Kconfig"
1229 source "board/h2200/Kconfig" 1242 source "board/h2200/Kconfig"
1230 source "board/hisilicon/hikey/Kconfig" 1243 source "board/hisilicon/hikey/Kconfig"
1231 source "board/hisilicon/poplar/Kconfig" 1244 source "board/hisilicon/poplar/Kconfig"
1232 source "board/imx31_phycore/Kconfig" 1245 source "board/imx31_phycore/Kconfig"
1233 source "board/isee/igep003x/Kconfig" 1246 source "board/isee/igep003x/Kconfig"
1234 source "board/olimex/mx23_olinuxino/Kconfig" 1247 source "board/olimex/mx23_olinuxino/Kconfig"
1235 source "board/phytec/pcm051/Kconfig" 1248 source "board/phytec/pcm051/Kconfig"
1236 source "board/ppcag/bg0900/Kconfig" 1249 source "board/ppcag/bg0900/Kconfig"
1237 source "board/sandisk/sansa_fuze_plus/Kconfig" 1250 source "board/sandisk/sansa_fuze_plus/Kconfig"
1238 source "board/schulercontrol/sc_sps_1/Kconfig" 1251 source "board/schulercontrol/sc_sps_1/Kconfig"
1239 source "board/silica/pengwyn/Kconfig" 1252 source "board/silica/pengwyn/Kconfig"
1240 source "board/spear/spear300/Kconfig" 1253 source "board/spear/spear300/Kconfig"
1241 source "board/spear/spear310/Kconfig" 1254 source "board/spear/spear310/Kconfig"
1242 source "board/spear/spear320/Kconfig" 1255 source "board/spear/spear320/Kconfig"
1243 source "board/spear/spear600/Kconfig" 1256 source "board/spear/spear600/Kconfig"
1244 source "board/spear/x600/Kconfig" 1257 source "board/spear/x600/Kconfig"
1245 source "board/st/stv0991/Kconfig" 1258 source "board/st/stv0991/Kconfig"
1246 source "board/syteco/zmx25/Kconfig" 1259 source "board/syteco/zmx25/Kconfig"
1247 source "board/tcl/sl50/Kconfig" 1260 source "board/tcl/sl50/Kconfig"
1248 source "board/birdland/bav335x/Kconfig" 1261 source "board/birdland/bav335x/Kconfig"
1249 source "board/timll/devkit3250/Kconfig" 1262 source "board/timll/devkit3250/Kconfig"
1250 source "board/toradex/colibri_pxa270/Kconfig" 1263 source "board/toradex/colibri_pxa270/Kconfig"
1251 source "board/technologic/ts4600/Kconfig" 1264 source "board/technologic/ts4600/Kconfig"
1252 source "board/vscom/baltos/Kconfig" 1265 source "board/vscom/baltos/Kconfig"
1253 source "board/woodburn/Kconfig" 1266 source "board/woodburn/Kconfig"
1254 source "board/work-microwave/work_92105/Kconfig" 1267 source "board/work-microwave/work_92105/Kconfig"
1255 source "board/zipitz2/Kconfig" 1268 source "board/zipitz2/Kconfig"
1256 1269
1257 source "arch/arm/Kconfig.debug" 1270 source "arch/arm/Kconfig.debug"
1258 1271
1259 endmenu 1272 endmenu
1260 1273
1261 config SPL_LDSCRIPT 1274 config SPL_LDSCRIPT
1262 default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if TARGET_APX4DEVKIT || TARGET_BG0900 || TARGET_M28EVK || TARGET_MX23_OLINUXINO || TARGET_MX23EVK || TARGET_MX28EVK || TARGET_SANSA_FUZE_PLUS || TARGET_SC_SPS_1 || TARGET_TS4600 || TARGET_XFI3 1275 default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if TARGET_APX4DEVKIT || TARGET_BG0900 || TARGET_M28EVK || TARGET_MX23_OLINUXINO || TARGET_MX23EVK || TARGET_MX28EVK || TARGET_SANSA_FUZE_PLUS || TARGET_SC_SPS_1 || TARGET_TS4600 || TARGET_XFI3
1263 default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136 1276 default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136
1264 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64 1277 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64
1265 1278
1266 1279
1267 1280
arch/arm/cpu/armv8/Kconfig
Diff comments   View file @ 7769776
1 if ARM64 1 if ARM64
2 2
3 config ARMV8_MULTIENTRY 3 config ARMV8_MULTIENTRY
4 bool "Enable multiple CPUs to enter into U-Boot" 4 bool "Enable multiple CPUs to enter into U-Boot"
5 5
6 config ARMV8_SET_SMPEN 6 config ARMV8_SET_SMPEN
7 bool "Enable data coherency with other cores in cluster" 7 bool "Enable data coherency with other cores in cluster"
8 help 8 help
9 Say Y here if there is not any trust firmware to set 9 Say Y here if there is not any trust firmware to set
10 CPUECTLR_EL1.SMPEN bit before U-Boot. 10 CPUECTLR_EL1.SMPEN bit before U-Boot.
11 11
12 For A53, it enables data coherency with other cores in the 12 For A53, it enables data coherency with other cores in the
13 cluster, and for A57/A72, it enables receiving of instruction 13 cluster, and for A57/A72, it enables receiving of instruction
14 cache and TLB maintenance operations. 14 cache and TLB maintenance operations.
15 Cortex A53/57/72 cores require CPUECTLR_EL1.SMPEN set even 15 Cortex A53/57/72 cores require CPUECTLR_EL1.SMPEN set even
16 for single core systems. Unfortunately write access to this 16 for single core systems. Unfortunately write access to this
17 register may be controlled by EL3/EL2 firmware. To be more 17 register may be controlled by EL3/EL2 firmware. To be more
18 precise, by default (if there is EL2/EL3 firmware running) 18 precise, by default (if there is EL2/EL3 firmware running)
19 this register is RO for NS EL1. 19 this register is RO for NS EL1.
20 This switch can be used to avoid writing to CPUECTLR_EL1, 20 This switch can be used to avoid writing to CPUECTLR_EL1,
21 it can be safely enabled when EL2/EL3 initialized SMPEN bit 21 it can be safely enabled when EL2/EL3 initialized SMPEN bit
22 or when CPU implementation doesn't include that register. 22 or when CPU implementation doesn't include that register.
23 23
24 config ARMV8_SPIN_TABLE 24 config ARMV8_SPIN_TABLE
25 bool "Support spin-table enable method" 25 bool "Support spin-table enable method"
26 depends on ARMV8_MULTIENTRY && OF_LIBFDT 26 depends on ARMV8_MULTIENTRY && OF_LIBFDT
27 help 27 help
28 Say Y here to support "spin-table" enable method for booting Linux. 28 Say Y here to support "spin-table" enable method for booting Linux.
29 29
30 To use this feature, you must do: 30 To use this feature, you must do:
31 - Specify enable-method = "spin-table" in each CPU node in the 31 - Specify enable-method = "spin-table" in each CPU node in the
32 Device Tree you are using to boot the kernel 32 Device Tree you are using to boot the kernel
33 - Bring secondary CPUs into U-Boot proper in a board specific 33 - Bring secondary CPUs into U-Boot proper in a board specific
34 manner. This must be done *after* relocation. Otherwise, the 34 manner. This must be done *after* relocation. Otherwise, the
35 secondary CPUs will spin in unprotected memory area because the 35 secondary CPUs will spin in unprotected memory area because the
36 master CPU protects the relocated spin code. 36 master CPU protects the relocated spin code.
37 37
38 U-Boot automatically does: 38 U-Boot automatically does:
39 - Set "cpu-release-addr" property of each CPU node 39 - Set "cpu-release-addr" property of each CPU node
40 (overwrites it if already exists). 40 (overwrites it if already exists).
41 - Reserve the code for the spin-table and the release address 41 - Reserve the code for the spin-table and the release address
42 via a /memreserve/ region in the Device Tree. 42 via a /memreserve/ region in the Device Tree.
43 43
44 menu "ARMv8 secure monitor firmware" 44 menu "ARMv8 secure monitor firmware"
45 config ARMV8_SEC_FIRMWARE_SUPPORT 45 config ARMV8_SEC_FIRMWARE_SUPPORT
46 bool "Enable ARMv8 secure monitor firmware framework support" 46 bool "Enable ARMv8 secure monitor firmware framework support"
47 select OF_LIBFDT 47 select OF_LIBFDT
48 select FIT 48 select FIT
49 help 49 help
50 This framework is aimed at making secure monitor firmware load 50 This framework is aimed at making secure monitor firmware load
51 process brief. 51 process brief.
52 Note: Only FIT format image is supported. 52 Note: Only FIT format image is supported.
53 You should prepare and provide the below information: 53 You should prepare and provide the below information:
54 - Address of secure firmware. 54 - Address of secure firmware.
55 - Address to hold the return address from secure firmware. 55 - Address to hold the return address from secure firmware.
56 - Secure firmware FIT image related information. 56 - Secure firmware FIT image related information.
57 Such as: SEC_FIRMWARE_FIT_IMAGE and SEC_FIRMEWARE_FIT_CNF_NAME 57 Such as: SEC_FIRMWARE_FIT_IMAGE and SEC_FIRMEWARE_FIT_CNF_NAME
58 - The target exception level that secure monitor firmware will 58 - The target exception level that secure monitor firmware will
59 return to. 59 return to.
60 60
61 config SPL_ARMV8_SEC_FIRMWARE_SUPPORT 61 config SPL_ARMV8_SEC_FIRMWARE_SUPPORT
62 bool "Enable ARMv8 secure monitor firmware framework support for SPL" 62 bool "Enable ARMv8 secure monitor firmware framework support for SPL"
63 select SPL_OF_LIBFDT 63 select SPL_OF_LIBFDT
64 select SPL_FIT 64 select SPL_FIT
65 help 65 help
66 Say Y here to support this framework in SPL phase. 66 Say Y here to support this framework in SPL phase.
67 67
68 config SEC_FIRMWARE_ARMV8_PSCI 68 config SEC_FIRMWARE_ARMV8_PSCI
69 bool "PSCI implementation in secure monitor firmware" 69 bool "PSCI implementation in secure monitor firmware"
70 depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT 70 depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT
71 help 71 help
72 This config enables the ARMv8 PSCI implementation in secure monitor 72 This config enables the ARMv8 PSCI implementation in secure monitor
73 firmware. This is a private PSCI implementation and different from 73 firmware. This is a private PSCI implementation and different from
74 those implemented under the common ARMv8 PSCI framework. 74 those implemented under the common ARMv8 PSCI framework.
75 75
76 config ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT 76 config ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT
77 bool "ARMv8 secure monitor firmware ERET address byteorder swap" 77 bool "ARMv8 secure monitor firmware ERET address byteorder swap"
78 depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT 78 depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT
79 help 79 help
80 Say Y here when the endianness of the register or memory holding the 80 Say Y here when the endianness of the register or memory holding the
81 Secure firmware exception return address is different with core's. 81 Secure firmware exception return address is different with core's.
82 82
83 endmenu 83 endmenu
84 84
85 config PSCI_RESET 85 config PSCI_RESET
86 bool "Use PSCI for reset and shutdown" 86 bool "Use PSCI for reset and shutdown"
87 default y 87 default y
88 depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && !TARGET_LS2080A_EMU && \ 88 depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && !TARGET_LS2080A_EMU && \
89 !TARGET_LS2080A_SIMU && !TARGET_LS2080AQDS && \ 89 !TARGET_LS2080A_SIMU && !TARGET_LS2080AQDS && \
90 !TARGET_LS2080ARDB && !TARGET_LS1012AQDS && \ 90 !TARGET_LS2080ARDB && !TARGET_LS1012AQDS && \
91 !TARGET_LS1088ARDB && \ 91 !TARGET_LS1088ARDB && !TARGET_LS1088AQDS && \
92 !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \ 92 !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
93 !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \ 93 !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
94 !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \ 94 !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
95 !TARGET_LS2081ARDB && \ 95 !TARGET_LS2081ARDB && \
96 !ARCH_UNIPHIER && !TARGET_S32V234EVB 96 !ARCH_UNIPHIER && !TARGET_S32V234EVB
97 help 97 help
98 Most armv8 systems have PSCI support enabled in EL3, either through 98 Most armv8 systems have PSCI support enabled in EL3, either through
99 ARM Trusted Firmware or other firmware. 99 ARM Trusted Firmware or other firmware.
100 100
101 On these systems, we do not need to implement system reset manually, 101 On these systems, we do not need to implement system reset manually,
102 but can instead rely on higher level firmware to deal with it. 102 but can instead rely on higher level firmware to deal with it.
103 103
104 Select Y here to make use of PSCI calls for system reset 104 Select Y here to make use of PSCI calls for system reset
105 105
106 config ARMV8_PSCI 106 config ARMV8_PSCI
107 bool "Enable PSCI support" if EXPERT 107 bool "Enable PSCI support" if EXPERT
108 default n 108 default n
109 help 109 help
110 PSCI is Power State Coordination Interface defined by ARM. 110 PSCI is Power State Coordination Interface defined by ARM.
111 The PSCI in U-boot provides a general framework and each platform 111 The PSCI in U-boot provides a general framework and each platform
112 can implement their own specific PSCI functions. 112 can implement their own specific PSCI functions.
113 Say Y here to enable PSCI support on ARMv8 platform. 113 Say Y here to enable PSCI support on ARMv8 platform.
114 114
115 config ARMV8_PSCI_NR_CPUS 115 config ARMV8_PSCI_NR_CPUS
116 int "Maximum supported CPUs for PSCI" 116 int "Maximum supported CPUs for PSCI"
117 depends on ARMV8_PSCI 117 depends on ARMV8_PSCI
118 default 4 118 default 4
119 help 119 help
120 The maximum number of CPUs supported in the PSCI firmware. 120 The maximum number of CPUs supported in the PSCI firmware.
121 It is no problem to set a larger value than the number of CPUs in 121 It is no problem to set a larger value than the number of CPUs in
122 the actual hardware implementation. 122 the actual hardware implementation.
123 123
124 config ARMV8_PSCI_CPUS_PER_CLUSTER 124 config ARMV8_PSCI_CPUS_PER_CLUSTER
125 int "Number of CPUs per cluster" 125 int "Number of CPUs per cluster"
126 depends on ARMV8_PSCI 126 depends on ARMV8_PSCI
127 default 0 127 default 0
128 help 128 help
129 The number of CPUs per cluster, suppose each cluster has same number 129 The number of CPUs per cluster, suppose each cluster has same number
130 of CPU cores, platforms with asymmetric clusters don't apply here. 130 of CPU cores, platforms with asymmetric clusters don't apply here.
131 A value 0 or no definition of it works for single cluster system. 131 A value 0 or no definition of it works for single cluster system.
132 System with multi-cluster should difine their own exact value. 132 System with multi-cluster should difine their own exact value.
133 133
134 if SYS_HAS_ARMV8_SECURE_BASE 134 if SYS_HAS_ARMV8_SECURE_BASE
135 135
136 config ARMV8_SECURE_BASE 136 config ARMV8_SECURE_BASE
137 hex "Secure address for PSCI image" 137 hex "Secure address for PSCI image"
138 depends on ARMV8_PSCI 138 depends on ARMV8_PSCI
139 help 139 help
140 Address for placing the PSCI text, data and stack sections. 140 Address for placing the PSCI text, data and stack sections.
141 If not defined, the PSCI sections are placed together with the u-boot 141 If not defined, the PSCI sections are placed together with the u-boot
142 but platform can choose to place PSCI code image separately in other 142 but platform can choose to place PSCI code image separately in other
143 places such as some secure RAM built-in SOC etc. 143 places such as some secure RAM built-in SOC etc.
144 144
145 endif 145 endif
146 146
147 endif 147 endif
148 148
arch/arm/dts/Makefile
Diff comments   View file @ 7769776
1 # 1 #
2 # SPDX-License-Identifier: GPL-2.0+ 2 # SPDX-License-Identifier: GPL-2.0+
3 # 3 #
4 4
5 dtb-$(CONFIG_AT91FAMILY) += at91sam9260-smartweb.dtb \ 5 dtb-$(CONFIG_AT91FAMILY) += at91sam9260-smartweb.dtb \
6 at91sam9g20-taurus.dtb \ 6 at91sam9g20-taurus.dtb \
7 at91sam9g45-corvus.dtb \ 7 at91sam9g45-corvus.dtb \
8 at91sam9g45-gurnard.dtb 8 at91sam9g45-gurnard.dtb
9 9
10 dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb 10 dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb
11 dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb 11 dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb
12 dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \ 12 dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
13 exynos4210-smdkv310.dtb \ 13 exynos4210-smdkv310.dtb \
14 exynos4210-universal_c210.dtb \ 14 exynos4210-universal_c210.dtb \
15 exynos4210-trats.dtb \ 15 exynos4210-trats.dtb \
16 exynos4412-trats2.dtb \ 16 exynos4412-trats2.dtb \
17 exynos4412-odroid.dtb 17 exynos4412-odroid.dtb
18 18
19 dtb-$(CONFIG_TARGET_HIKEY) += hi6220-hikey.dtb 19 dtb-$(CONFIG_TARGET_HIKEY) += hi6220-hikey.dtb
20 20
21 dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ 21 dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
22 exynos5250-snow.dtb \ 22 exynos5250-snow.dtb \
23 exynos5250-spring.dtb \ 23 exynos5250-spring.dtb \
24 exynos5250-smdk5250.dtb \ 24 exynos5250-smdk5250.dtb \
25 exynos5420-smdk5420.dtb \ 25 exynos5420-smdk5420.dtb \
26 exynos5420-peach-pit.dtb \ 26 exynos5420-peach-pit.dtb \
27 exynos5800-peach-pi.dtb \ 27 exynos5800-peach-pi.dtb \
28 exynos5422-odroidxu3.dtb 28 exynos5422-odroidxu3.dtb
29 dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb 29 dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb
30 dtb-$(CONFIG_ARCH_ROCKCHIP) += \ 30 dtb-$(CONFIG_ARCH_ROCKCHIP) += \
31 rk3036-sdk.dtb \ 31 rk3036-sdk.dtb \
32 rk3188-radxarock.dtb \ 32 rk3188-radxarock.dtb \
33 rk3288-evb.dtb \ 33 rk3288-evb.dtb \
34 rk3288-fennec.dtb \ 34 rk3288-fennec.dtb \
35 rk3288-firefly.dtb \ 35 rk3288-firefly.dtb \
36 rk3288-miqi.dtb \ 36 rk3288-miqi.dtb \
37 rk3288-phycore-rdk.dtb \ 37 rk3288-phycore-rdk.dtb \
38 rk3288-popmetal.dtb \ 38 rk3288-popmetal.dtb \
39 rk3288-rock2-square.dtb \ 39 rk3288-rock2-square.dtb \
40 rk3288-tinker.dtb \ 40 rk3288-tinker.dtb \
41 rk3288-veyron-jerry.dtb \ 41 rk3288-veyron-jerry.dtb \
42 rk3288-veyron-mickey.dtb \ 42 rk3288-veyron-mickey.dtb \
43 rk3288-veyron-minnie.dtb \ 43 rk3288-veyron-minnie.dtb \
44 rk3328-evb.dtb \ 44 rk3328-evb.dtb \
45 rk3368-lion.dtb \ 45 rk3368-lion.dtb \
46 rk3368-sheep.dtb \ 46 rk3368-sheep.dtb \
47 rk3368-geekbox.dtb \ 47 rk3368-geekbox.dtb \
48 rk3368-px5-evb.dtb \ 48 rk3368-px5-evb.dtb \
49 rk3399-evb.dtb \ 49 rk3399-evb.dtb \
50 rk3399-firefly.dtb \ 50 rk3399-firefly.dtb \
51 rk3399-puma-ddr1333.dtb \ 51 rk3399-puma-ddr1333.dtb \
52 rk3399-puma-ddr1600.dtb \ 52 rk3399-puma-ddr1600.dtb \
53 rk3399-puma-ddr1866.dtb \ 53 rk3399-puma-ddr1866.dtb \
54 rv1108-evb.dtb 54 rv1108-evb.dtb
55 dtb-$(CONFIG_ARCH_MESON) += \ 55 dtb-$(CONFIG_ARCH_MESON) += \
56 meson-gxbb-odroidc2.dtb 56 meson-gxbb-odroidc2.dtb
57 dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ 57 dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
58 tegra20-medcom-wide.dtb \ 58 tegra20-medcom-wide.dtb \
59 tegra20-paz00.dtb \ 59 tegra20-paz00.dtb \
60 tegra20-plutux.dtb \ 60 tegra20-plutux.dtb \
61 tegra20-seaboard.dtb \ 61 tegra20-seaboard.dtb \
62 tegra20-tec.dtb \ 62 tegra20-tec.dtb \
63 tegra20-trimslice.dtb \ 63 tegra20-trimslice.dtb \
64 tegra20-ventana.dtb \ 64 tegra20-ventana.dtb \
65 tegra20-colibri.dtb \ 65 tegra20-colibri.dtb \
66 tegra30-apalis.dtb \ 66 tegra30-apalis.dtb \
67 tegra30-beaver.dtb \ 67 tegra30-beaver.dtb \
68 tegra30-cardhu.dtb \ 68 tegra30-cardhu.dtb \
69 tegra30-colibri.dtb \ 69 tegra30-colibri.dtb \
70 tegra30-tec-ng.dtb \ 70 tegra30-tec-ng.dtb \
71 tegra114-dalmore.dtb \ 71 tegra114-dalmore.dtb \
72 tegra124-apalis.dtb \ 72 tegra124-apalis.dtb \
73 tegra124-jetson-tk1.dtb \ 73 tegra124-jetson-tk1.dtb \
74 tegra124-nyan-big.dtb \ 74 tegra124-nyan-big.dtb \
75 tegra124-cei-tk1-som.dtb \ 75 tegra124-cei-tk1-som.dtb \
76 tegra124-venice2.dtb \ 76 tegra124-venice2.dtb \
77 tegra186-p2771-0000-000.dtb \ 77 tegra186-p2771-0000-000.dtb \
78 tegra186-p2771-0000-500.dtb \ 78 tegra186-p2771-0000-500.dtb \
79 tegra210-e2220-1170.dtb \ 79 tegra210-e2220-1170.dtb \
80 tegra210-p2371-0000.dtb \ 80 tegra210-p2371-0000.dtb \
81 tegra210-p2371-2180.dtb \ 81 tegra210-p2371-2180.dtb \
82 tegra210-p2571.dtb 82 tegra210-p2571.dtb
83 83
84 dtb-$(CONFIG_ARCH_MVEBU) += \ 84 dtb-$(CONFIG_ARCH_MVEBU) += \
85 armada-3720-db.dtb \ 85 armada-3720-db.dtb \
86 armada-3720-espressobin.dtb \ 86 armada-3720-espressobin.dtb \
87 armada-375-db.dtb \ 87 armada-375-db.dtb \
88 armada-388-clearfog.dtb \ 88 armada-388-clearfog.dtb \
89 armada-388-gp.dtb \ 89 armada-388-gp.dtb \
90 armada-385-amc.dtb \ 90 armada-385-amc.dtb \
91 armada-7040-db.dtb \ 91 armada-7040-db.dtb \
92 armada-7040-db-nand.dtb \ 92 armada-7040-db-nand.dtb \
93 armada-8040-db.dtb \ 93 armada-8040-db.dtb \
94 armada-8040-mcbin.dtb \ 94 armada-8040-mcbin.dtb \
95 armada-xp-gp.dtb \ 95 armada-xp-gp.dtb \
96 armada-xp-maxbcm.dtb \ 96 armada-xp-maxbcm.dtb \
97 armada-xp-synology-ds414.dtb \ 97 armada-xp-synology-ds414.dtb \
98 armada-xp-theadorable.dtb \ 98 armada-xp-theadorable.dtb \
99 armada-38x-controlcenterdc.dtb 99 armada-38x-controlcenterdc.dtb
100 100
101 dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \ 101 dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
102 uniphier-ld11-global.dtb \ 102 uniphier-ld11-global.dtb \
103 uniphier-ld11-ref.dtb 103 uniphier-ld11-ref.dtb
104 dtb-$(CONFIG_ARCH_UNIPHIER_LD20) += \ 104 dtb-$(CONFIG_ARCH_UNIPHIER_LD20) += \
105 uniphier-ld20-global.dtb \ 105 uniphier-ld20-global.dtb \
106 uniphier-ld20-ref.dtb 106 uniphier-ld20-ref.dtb
107 dtb-$(CONFIG_ARCH_UNIPHIER_LD4) += \ 107 dtb-$(CONFIG_ARCH_UNIPHIER_LD4) += \
108 uniphier-ld4-ref.dtb 108 uniphier-ld4-ref.dtb
109 dtb-$(CONFIG_ARCH_UNIPHIER_LD6B) += \ 109 dtb-$(CONFIG_ARCH_UNIPHIER_LD6B) += \
110 uniphier-ld6b-ref.dtb 110 uniphier-ld6b-ref.dtb
111 dtb-$(CONFIG_ARCH_UNIPHIER_PRO4) += \ 111 dtb-$(CONFIG_ARCH_UNIPHIER_PRO4) += \
112 uniphier-pro4-ace.dtb \ 112 uniphier-pro4-ace.dtb \
113 uniphier-pro4-ref.dtb \ 113 uniphier-pro4-ref.dtb \
114 uniphier-pro4-sanji.dtb 114 uniphier-pro4-sanji.dtb
115 dtb-$(CONFIG_ARCH_UNIPHIER_PRO5) += \ 115 dtb-$(CONFIG_ARCH_UNIPHIER_PRO5) += \
116 uniphier-pro5-4kbox.dtb 116 uniphier-pro5-4kbox.dtb
117 dtb-$(CONFIG_ARCH_UNIPHIER_PXS2) += \ 117 dtb-$(CONFIG_ARCH_UNIPHIER_PXS2) += \
118 uniphier-pxs2-gentil.dtb \ 118 uniphier-pxs2-gentil.dtb \
119 uniphier-pxs2-vodka.dtb 119 uniphier-pxs2-vodka.dtb
120 dtb-$(CONFIG_ARCH_UNIPHIER_PXS3) += \ 120 dtb-$(CONFIG_ARCH_UNIPHIER_PXS3) += \
121 uniphier-pxs3-ref.dtb 121 uniphier-pxs3-ref.dtb
122 dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \ 122 dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \
123 uniphier-sld8-ref.dtb 123 uniphier-sld8-ref.dtb
124 124
125 dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \ 125 dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
126 zynq-zc706.dtb \ 126 zynq-zc706.dtb \
127 zynq-zed.dtb \ 127 zynq-zed.dtb \
128 zynq-zybo.dtb \ 128 zynq-zybo.dtb \
129 zynq-microzed.dtb \ 129 zynq-microzed.dtb \
130 zynq-picozed.dtb \ 130 zynq-picozed.dtb \
131 zynq-topic-miami.dtb \ 131 zynq-topic-miami.dtb \
132 zynq-topic-miamilite.dtb \ 132 zynq-topic-miamilite.dtb \
133 zynq-topic-miamiplus.dtb \ 133 zynq-topic-miamiplus.dtb \
134 zynq-zturn-myir.dtb \ 134 zynq-zturn-myir.dtb \
135 zynq-zc770-xm010.dtb \ 135 zynq-zc770-xm010.dtb \
136 zynq-zc770-xm011.dtb \ 136 zynq-zc770-xm011.dtb \
137 zynq-zc770-xm012.dtb \ 137 zynq-zc770-xm012.dtb \
138 zynq-zc770-xm013.dtb 138 zynq-zc770-xm013.dtb
139 dtb-$(CONFIG_ARCH_ZYNQMP) += \ 139 dtb-$(CONFIG_ARCH_ZYNQMP) += \
140 zynqmp-ep108.dtb \ 140 zynqmp-ep108.dtb \
141 zynqmp-zcu102-revA.dtb \ 141 zynqmp-zcu102-revA.dtb \
142 zynqmp-zcu102-revB.dtb \ 142 zynqmp-zcu102-revB.dtb \
143 zynqmp-zc1751-xm015-dc1.dtb \ 143 zynqmp-zc1751-xm015-dc1.dtb \
144 zynqmp-zc1751-xm016-dc2.dtb \ 144 zynqmp-zc1751-xm016-dc2.dtb \
145 zynqmp-zc1751-xm018-dc4.dtb \ 145 zynqmp-zc1751-xm018-dc4.dtb \
146 zynqmp-zc1751-xm019-dc5.dtb 146 zynqmp-zc1751-xm019-dc5.dtb
147 dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb \ 147 dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb \
148 am335x-draco.dtb \ 148 am335x-draco.dtb \
149 am335x-evm.dtb \ 149 am335x-evm.dtb \
150 am335x-evmsk.dtb \ 150 am335x-evmsk.dtb \
151 am335x-bonegreen.dtb \ 151 am335x-bonegreen.dtb \
152 am335x-icev2.dtb \ 152 am335x-icev2.dtb \
153 am335x-pxm50.dtb \ 153 am335x-pxm50.dtb \
154 am335x-rut.dtb 154 am335x-rut.dtb
155 dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \ 155 dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \
156 am43x-epos-evm.dtb \ 156 am43x-epos-evm.dtb \
157 am437x-idk-evm.dtb 157 am437x-idk-evm.dtb
158 dtb-$(CONFIG_TI816X) += dm8168-evm.dtb 158 dtb-$(CONFIG_TI816X) += dm8168-evm.dtb
159 dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb 159 dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
160 160
161 dtb-$(CONFIG_ARCH_SOCFPGA) += \ 161 dtb-$(CONFIG_ARCH_SOCFPGA) += \
162 socfpga_arria10_socdk_sdmmc.dtb \ 162 socfpga_arria10_socdk_sdmmc.dtb \
163 socfpga_arria5_socdk.dtb \ 163 socfpga_arria5_socdk.dtb \
164 socfpga_cyclone5_is1.dtb \ 164 socfpga_cyclone5_is1.dtb \
165 socfpga_cyclone5_mcvevk.dtb \ 165 socfpga_cyclone5_mcvevk.dtb \
166 socfpga_cyclone5_socdk.dtb \ 166 socfpga_cyclone5_socdk.dtb \
167 socfpga_cyclone5_de0_nano_soc.dtb \ 167 socfpga_cyclone5_de0_nano_soc.dtb \
168 socfpga_cyclone5_de1_soc.dtb \ 168 socfpga_cyclone5_de1_soc.dtb \
169 socfpga_cyclone5_de10_nano.dtb \ 169 socfpga_cyclone5_de10_nano.dtb \
170 socfpga_cyclone5_sockit.dtb \ 170 socfpga_cyclone5_sockit.dtb \
171 socfpga_cyclone5_socrates.dtb \ 171 socfpga_cyclone5_socrates.dtb \
172 socfpga_cyclone5_sr1500.dtb \ 172 socfpga_cyclone5_sr1500.dtb \
173 socfpga_cyclone5_vining_fpga.dtb 173 socfpga_cyclone5_vining_fpga.dtb
174 174
175 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \ 175 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \
176 dra72-evm-revc.dtb dra71-evm.dtb 176 dra72-evm-revc.dtb dra71-evm.dtb
177 dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \ 177 dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \
178 am57xx-beagle-x15-revb1.dtb \ 178 am57xx-beagle-x15-revb1.dtb \
179 am572x-idk.dtb \ 179 am572x-idk.dtb \
180 am571x-idk.dtb 180 am571x-idk.dtb
181 dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb 181 dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
182 182
183 dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \ 183 dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \
184 ls1021a-qds-lpuart.dtb \ 184 ls1021a-qds-lpuart.dtb \
185 ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \ 185 ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \
186 ls1021a-iot-duart.dtb 186 ls1021a-iot-duart.dtb
187 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ 187 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
188 fsl-ls2080a-rdb.dtb \ 188 fsl-ls2080a-rdb.dtb \
189 fsl-ls2081a-rdb.dtb \ 189 fsl-ls2081a-rdb.dtb \
190 fsl-ls2088a-rdb-qspi.dtb \ 190 fsl-ls2088a-rdb-qspi.dtb \
191 fsl-ls1088a-rdb.dtb 191 fsl-ls1088a-rdb.dtb \
192 fsl-ls1088a-qds.dtb
192 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ 193 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
193 fsl-ls1043a-qds-lpuart.dtb \ 194 fsl-ls1043a-qds-lpuart.dtb \
194 fsl-ls1043a-rdb.dtb \ 195 fsl-ls1043a-rdb.dtb \
195 fsl-ls1046a-qds-duart.dtb \ 196 fsl-ls1046a-qds-duart.dtb \
196 fsl-ls1046a-qds-lpuart.dtb \ 197 fsl-ls1046a-qds-lpuart.dtb \
197 fsl-ls1046a-rdb.dtb \ 198 fsl-ls1046a-rdb.dtb \
198 fsl-ls1012a-qds.dtb \ 199 fsl-ls1012a-qds.dtb \
199 fsl-ls1012a-rdb.dtb \ 200 fsl-ls1012a-rdb.dtb \
200 fsl-ls1012a-frdm.dtb 201 fsl-ls1012a-frdm.dtb
201 202
202 dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb 203 dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
203 204
204 dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \ 205 dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \
205 stm32f769-disco.dtb 206 stm32f769-disco.dtb
206 207
207 dtb-$(CONFIG_MACH_SUN4I) += \ 208 dtb-$(CONFIG_MACH_SUN4I) += \
208 sun4i-a10-a1000.dtb \ 209 sun4i-a10-a1000.dtb \
209 sun4i-a10-ba10-tvbox.dtb \ 210 sun4i-a10-ba10-tvbox.dtb \
210 sun4i-a10-chuwi-v7-cw0825.dtb \ 211 sun4i-a10-chuwi-v7-cw0825.dtb \
211 sun4i-a10-cubieboard.dtb \ 212 sun4i-a10-cubieboard.dtb \
212 sun4i-a10-dserve-dsrv9703c.dtb \ 213 sun4i-a10-dserve-dsrv9703c.dtb \
213 sun4i-a10-gemei-g9.dtb \ 214 sun4i-a10-gemei-g9.dtb \
214 sun4i-a10-hackberry.dtb \ 215 sun4i-a10-hackberry.dtb \
215 sun4i-a10-hyundai-a7hd.dtb \ 216 sun4i-a10-hyundai-a7hd.dtb \
216 sun4i-a10-inet1.dtb \ 217 sun4i-a10-inet1.dtb \
217 sun4i-a10-inet-3f.dtb \ 218 sun4i-a10-inet-3f.dtb \
218 sun4i-a10-inet-3w.dtb \ 219 sun4i-a10-inet-3w.dtb \
219 sun4i-a10-inet97fv2.dtb \ 220 sun4i-a10-inet97fv2.dtb \
220 sun4i-a10-inet9f-rev03.dtb \ 221 sun4i-a10-inet9f-rev03.dtb \
221 sun4i-a10-itead-iteaduino-plus.dtb \ 222 sun4i-a10-itead-iteaduino-plus.dtb \
222 sun4i-a10-jesurun-q5.dtb \ 223 sun4i-a10-jesurun-q5.dtb \
223 sun4i-a10-marsboard.dtb \ 224 sun4i-a10-marsboard.dtb \
224 sun4i-a10-mini-xplus.dtb \ 225 sun4i-a10-mini-xplus.dtb \
225 sun4i-a10-mk802.dtb \ 226 sun4i-a10-mk802.dtb \
226 sun4i-a10-mk802ii.dtb \ 227 sun4i-a10-mk802ii.dtb \
227 sun4i-a10-olinuxino-lime.dtb \ 228 sun4i-a10-olinuxino-lime.dtb \
228 sun4i-a10-pcduino.dtb \ 229 sun4i-a10-pcduino.dtb \
229 sun4i-a10-pcduino2.dtb \ 230 sun4i-a10-pcduino2.dtb \
230 sun4i-a10-pov-protab2-ips9.dtb 231 sun4i-a10-pov-protab2-ips9.dtb
231 dtb-$(CONFIG_MACH_SUN5I) += \ 232 dtb-$(CONFIG_MACH_SUN5I) += \
232 sun5i-a10s-auxtek-t003.dtb \ 233 sun5i-a10s-auxtek-t003.dtb \
233 sun5i-a10s-auxtek-t004.dtb \ 234 sun5i-a10s-auxtek-t004.dtb \
234 sun5i-a10s-mk802.dtb \ 235 sun5i-a10s-mk802.dtb \
235 sun5i-a10s-olinuxino-micro.dtb \ 236 sun5i-a10s-olinuxino-micro.dtb \
236 sun5i-a10s-r7-tv-dongle.dtb \ 237 sun5i-a10s-r7-tv-dongle.dtb \
237 sun5i-a10s-wobo-i5.dtb \ 238 sun5i-a10s-wobo-i5.dtb \
238 sun5i-a13-ampe-a76.dtb \ 239 sun5i-a13-ampe-a76.dtb \
239 sun5i-a13-difrnce-dit4350.dtb \ 240 sun5i-a13-difrnce-dit4350.dtb \
240 sun5i-a13-empire-electronix-d709.dtb \ 241 sun5i-a13-empire-electronix-d709.dtb \
241 sun5i-a13-empire-electronix-m712.dtb \ 242 sun5i-a13-empire-electronix-m712.dtb \
242 sun5i-a13-hsg-h702.dtb \ 243 sun5i-a13-hsg-h702.dtb \
243 sun5i-a13-inet-86vs.dtb \ 244 sun5i-a13-inet-86vs.dtb \
244 sun5i-a13-inet-98v-rev2.dtb \ 245 sun5i-a13-inet-98v-rev2.dtb \
245 sun5i-a13-olinuxino.dtb \ 246 sun5i-a13-olinuxino.dtb \
246 sun5i-a13-olinuxino-micro.dtb \ 247 sun5i-a13-olinuxino-micro.dtb \
247 sun5i-a13-q8-tablet.dtb \ 248 sun5i-a13-q8-tablet.dtb \
248 sun5i-a13-utoo-p66.dtb \ 249 sun5i-a13-utoo-p66.dtb \
249 sun5i-gr8-chip-pro.dtb \ 250 sun5i-gr8-chip-pro.dtb \
250 sun5i-r8-chip.dtb 251 sun5i-r8-chip.dtb
251 dtb-$(CONFIG_MACH_SUN6I) += \ 252 dtb-$(CONFIG_MACH_SUN6I) += \
252 sun6i-a31-app4-evb1.dtb \ 253 sun6i-a31-app4-evb1.dtb \
253 sun6i-a31-colombus.dtb \ 254 sun6i-a31-colombus.dtb \
254 sun6i-a31-hummingbird.dtb \ 255 sun6i-a31-hummingbird.dtb \
255 sun6i-a31-i7.dtb \ 256 sun6i-a31-i7.dtb \
256 sun6i-a31-m9.dtb \ 257 sun6i-a31-m9.dtb \
257 sun6i-a31-mele-a1000g-quad.dtb \ 258 sun6i-a31-mele-a1000g-quad.dtb \
258 sun6i-a31-mixtile-loftq.dtb \ 259 sun6i-a31-mixtile-loftq.dtb \
259 sun6i-a31s-colorfly-e708-q1.dtb \ 260 sun6i-a31s-colorfly-e708-q1.dtb \
260 sun6i-a31s-cs908.dtb \ 261 sun6i-a31s-cs908.dtb \
261 sun6i-a31s-inet-q972.dtb \ 262 sun6i-a31s-inet-q972.dtb \
262 sun6i-a31s-primo81.dtb \ 263 sun6i-a31s-primo81.dtb \
263 sun6i-a31s-sina31s.dtb \ 264 sun6i-a31s-sina31s.dtb \
264 sun6i-a31s-sinovoip-bpi-m2.dtb \ 265 sun6i-a31s-sinovoip-bpi-m2.dtb \
265 sun6i-a31s-yones-toptech-bs1078-v2.dtb 266 sun6i-a31s-yones-toptech-bs1078-v2.dtb
266 dtb-$(CONFIG_MACH_SUN7I) += \ 267 dtb-$(CONFIG_MACH_SUN7I) += \
267 sun7i-a20-ainol-aw1.dtb \ 268 sun7i-a20-ainol-aw1.dtb \
268 sun7i-a20-bananapi.dtb \ 269 sun7i-a20-bananapi.dtb \
269 sun7i-a20-bananapi-m1-plus.dtb \ 270 sun7i-a20-bananapi-m1-plus.dtb \
270 sun7i-a20-bananapro.dtb \ 271 sun7i-a20-bananapro.dtb \
271 sun7i-a20-cubieboard2.dtb \ 272 sun7i-a20-cubieboard2.dtb \
272 sun7i-a20-cubietruck.dtb \ 273 sun7i-a20-cubietruck.dtb \
273 sun7i-a20-hummingbird.dtb \ 274 sun7i-a20-hummingbird.dtb \
274 sun7i-a20-i12-tvbox.dtb \ 275 sun7i-a20-i12-tvbox.dtb \
275 sun7i-a20-icnova-swac.dtb \ 276 sun7i-a20-icnova-swac.dtb \
276 sun7i-a20-itead-ibox.dtb \ 277 sun7i-a20-itead-ibox.dtb \
277 sun7i-a20-lamobo-r1.dtb \ 278 sun7i-a20-lamobo-r1.dtb \
278 sun7i-a20-m3.dtb \ 279 sun7i-a20-m3.dtb \
279 sun7i-a20-m5.dtb \ 280 sun7i-a20-m5.dtb \
280 sun7i-a20-mk808c.dtb \ 281 sun7i-a20-mk808c.dtb \
281 sun7i-a20-olimex-som-evb.dtb \ 282 sun7i-a20-olimex-som-evb.dtb \
282 sun7i-a20-olinuxino-lime.dtb \ 283 sun7i-a20-olinuxino-lime.dtb \
283 sun7i-a20-olinuxino-lime2.dtb \ 284 sun7i-a20-olinuxino-lime2.dtb \
284 sun7i-a20-olinuxino-lime2-emmc.dtb \ 285 sun7i-a20-olinuxino-lime2-emmc.dtb \
285 sun7i-a20-olinuxino-micro.dtb \ 286 sun7i-a20-olinuxino-micro.dtb \
286 sun7i-a20-orangepi.dtb \ 287 sun7i-a20-orangepi.dtb \
287 sun7i-a20-orangepi-mini.dtb \ 288 sun7i-a20-orangepi-mini.dtb \
288 sun7i-a20-pcduino3.dtb \ 289 sun7i-a20-pcduino3.dtb \
289 sun7i-a20-pcduino3-nano.dtb \ 290 sun7i-a20-pcduino3-nano.dtb \
290 sun7i-a20-primo73.dtb \ 291 sun7i-a20-primo73.dtb \
291 sun7i-a20-wexler-tab7200.dtb \ 292 sun7i-a20-wexler-tab7200.dtb \
292 sun7i-a20-wits-pro-a20-dkt.dtb \ 293 sun7i-a20-wits-pro-a20-dkt.dtb \
293 sun7i-a20-yones-toptech-bd1078.dtb 294 sun7i-a20-yones-toptech-bd1078.dtb
294 dtb-$(CONFIG_MACH_SUN8I_A23) += \ 295 dtb-$(CONFIG_MACH_SUN8I_A23) += \
295 sun8i-a23-evb.dtb \ 296 sun8i-a23-evb.dtb \
296 sun8i-a23-gt90h-v4.dtb \ 297 sun8i-a23-gt90h-v4.dtb \
297 sun8i-a23-inet86dz.dtb \ 298 sun8i-a23-inet86dz.dtb \
298 sun8i-a23-polaroid-mid2407pxe03.dtb \ 299 sun8i-a23-polaroid-mid2407pxe03.dtb \
299 sun8i-a23-polaroid-mid2809pxe04.dtb \ 300 sun8i-a23-polaroid-mid2809pxe04.dtb \
300 sun8i-a23-q8-tablet.dtb 301 sun8i-a23-q8-tablet.dtb
301 dtb-$(CONFIG_MACH_SUN8I_A33) += \ 302 dtb-$(CONFIG_MACH_SUN8I_A33) += \
302 sun8i-a33-ga10h-v1.1.dtb \ 303 sun8i-a33-ga10h-v1.1.dtb \
303 sun8i-a33-inet-d978-rev2.dtb \ 304 sun8i-a33-inet-d978-rev2.dtb \
304 sun8i-a33-olinuxino.dtb \ 305 sun8i-a33-olinuxino.dtb \
305 sun8i-a33-q8-tablet.dtb \ 306 sun8i-a33-q8-tablet.dtb \
306 sun8i-a33-sinlinx-sina33.dtb \ 307 sun8i-a33-sinlinx-sina33.dtb \
307 sun8i-r16-nintendo-nes-classic-edition.dtb \ 308 sun8i-r16-nintendo-nes-classic-edition.dtb \
308 sun8i-r16-parrot.dtb 309 sun8i-r16-parrot.dtb
309 dtb-$(CONFIG_MACH_SUN8I_A83T) += \ 310 dtb-$(CONFIG_MACH_SUN8I_A83T) += \
310 sun8i-a83t-allwinner-h8homlet-v2.dtb \ 311 sun8i-a83t-allwinner-h8homlet-v2.dtb \
311 sun8i-a83t-cubietruck-plus.dtb \ 312 sun8i-a83t-cubietruck-plus.dtb \
312 sun8i-a83t-sinovoip-bpi-m3.dtb 313 sun8i-a83t-sinovoip-bpi-m3.dtb
313 dtb-$(CONFIG_MACH_SUN8I_H3) += \ 314 dtb-$(CONFIG_MACH_SUN8I_H3) += \
314 sun8i-h2-plus-orangepi-zero.dtb \ 315 sun8i-h2-plus-orangepi-zero.dtb \
315 sun8i-h3-bananapi-m2-plus.dtb \ 316 sun8i-h3-bananapi-m2-plus.dtb \
316 sun8i-h3-orangepi-2.dtb \ 317 sun8i-h3-orangepi-2.dtb \
317 sun8i-h3-orangepi-lite.dtb \ 318 sun8i-h3-orangepi-lite.dtb \
318 sun8i-h3-orangepi-one.dtb \ 319 sun8i-h3-orangepi-one.dtb \
319 sun8i-h3-orangepi-pc.dtb \ 320 sun8i-h3-orangepi-pc.dtb \
320 sun8i-h3-orangepi-pc-plus.dtb \ 321 sun8i-h3-orangepi-pc-plus.dtb \
321 sun8i-h3-orangepi-plus.dtb \ 322 sun8i-h3-orangepi-plus.dtb \
322 sun8i-h3-orangepi-plus2e.dtb \ 323 sun8i-h3-orangepi-plus2e.dtb \
323 sun8i-h3-nanopi-m1.dtb \ 324 sun8i-h3-nanopi-m1.dtb \
324 sun8i-h3-nanopi-m1-plus.dtb \ 325 sun8i-h3-nanopi-m1-plus.dtb \
325 sun8i-h3-nanopi-neo.dtb \ 326 sun8i-h3-nanopi-neo.dtb \
326 sun8i-h3-nanopi-neo-air.dtb 327 sun8i-h3-nanopi-neo-air.dtb
327 dtb-$(CONFIG_MACH_SUN8I_R40) += \ 328 dtb-$(CONFIG_MACH_SUN8I_R40) += \
328 sun8i-r40-bananapi-m2-ultra.dtb 329 sun8i-r40-bananapi-m2-ultra.dtb
329 dtb-$(CONFIG_MACH_SUN8I_V3S) += \ 330 dtb-$(CONFIG_MACH_SUN8I_V3S) += \
330 sun8i-v3s-licheepi-zero.dtb 331 sun8i-v3s-licheepi-zero.dtb
331 dtb-$(CONFIG_MACH_SUN50I_H5) += \ 332 dtb-$(CONFIG_MACH_SUN50I_H5) += \
332 sun50i-h5-nanopi-neo2.dtb \ 333 sun50i-h5-nanopi-neo2.dtb \
333 sun50i-h5-orangepi-pc2.dtb \ 334 sun50i-h5-orangepi-pc2.dtb \
334 sun50i-h5-orangepi-prime.dtb \ 335 sun50i-h5-orangepi-prime.dtb \
335 sun50i-h5-orangepi-zero-plus2.dtb 336 sun50i-h5-orangepi-zero-plus2.dtb
336 dtb-$(CONFIG_MACH_SUN50I) += \ 337 dtb-$(CONFIG_MACH_SUN50I) += \
337 sun50i-a64-bananapi-m64.dtb \ 338 sun50i-a64-bananapi-m64.dtb \
338 sun50i-a64-nanopi-a64.dtb \ 339 sun50i-a64-nanopi-a64.dtb \
339 sun50i-a64-olinuxino.dtb \ 340 sun50i-a64-olinuxino.dtb \
340 sun50i-a64-orangepi-win.dtb \ 341 sun50i-a64-orangepi-win.dtb \
341 sun50i-a64-pine64-plus.dtb \ 342 sun50i-a64-pine64-plus.dtb \
342 sun50i-a64-pine64.dtb 343 sun50i-a64-pine64.dtb
343 dtb-$(CONFIG_MACH_SUN9I) += \ 344 dtb-$(CONFIG_MACH_SUN9I) += \
344 sun9i-a80-optimus.dtb \ 345 sun9i-a80-optimus.dtb \
345 sun9i-a80-cubieboard4.dtb \ 346 sun9i-a80-cubieboard4.dtb \
346 sun9i-a80-cx-a99.dtb 347 sun9i-a80-cx-a99.dtb
347 348
348 dtb-$(CONFIG_VF610) += vf500-colibri.dtb \ 349 dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
349 vf610-colibri.dtb \ 350 vf610-colibri.dtb \
350 vf610-twr.dtb \ 351 vf610-twr.dtb \
351 pcm052.dtb \ 352 pcm052.dtb \
352 bk4r1.dtb 353 bk4r1.dtb
353 354
354 dtb-$(CONFIG_MX53) += imx53-cx9020.dtb 355 dtb-$(CONFIG_MX53) += imx53-cx9020.dtb
355 356
356 dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \ 357 dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
357 imx6sl-evk.dtb \ 358 imx6sl-evk.dtb \
358 imx6sll-evk.dtb \ 359 imx6sll-evk.dtb \
359 imx6dl-icore.dtb \ 360 imx6dl-icore.dtb \
360 imx6dl-icore-rqs.dtb \ 361 imx6dl-icore-rqs.dtb \
361 imx6q-cm-fx6.dtb \ 362 imx6q-cm-fx6.dtb \
362 imx6q-icore.dtb \ 363 imx6q-icore.dtb \
363 imx6q-icore-rqs.dtb \ 364 imx6q-icore-rqs.dtb \
364 imx6q-logicpd.dtb \ 365 imx6q-logicpd.dtb \
365 imx6sx-sabreauto.dtb \ 366 imx6sx-sabreauto.dtb \
366 imx6ul-geam-kit.dtb \ 367 imx6ul-geam-kit.dtb \
367 imx6ul-isiot-emmc.dtb \ 368 imx6ul-isiot-emmc.dtb \
368 imx6ul-isiot-mmc.dtb \ 369 imx6ul-isiot-mmc.dtb \
369 imx6ul-isiot-nand.dtb \ 370 imx6ul-isiot-nand.dtb \
370 imx6ul-opos6uldev.dtb 371 imx6ul-opos6uldev.dtb
371 372
372 dtb-$(CONFIG_MX7) += imx7-colibri.dtb \ 373 dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
373 imx7d-sdb.dtb 374 imx7d-sdb.dtb
374 375
375 dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb 376 dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
376 377
377 dtb-$(CONFIG_RCAR_GEN3) += \ 378 dtb-$(CONFIG_RCAR_GEN3) += \
378 r8a7795-h3ulcb.dtb \ 379 r8a7795-h3ulcb.dtb \
379 r8a7795-salvator-x.dtb \ 380 r8a7795-salvator-x.dtb \
380 r8a7796-m3ulcb.dtb \ 381 r8a7796-m3ulcb.dtb \
381 r8a7796-salvator-x.dtb 382 r8a7796-salvator-x.dtb
382 383
383 dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \ 384 dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
384 keystone-k2l-evm.dtb \ 385 keystone-k2l-evm.dtb \
385 keystone-k2e-evm.dtb \ 386 keystone-k2e-evm.dtb \
386 keystone-k2g-evm.dtb \ 387 keystone-k2g-evm.dtb \
387 keystone-k2g-generic.dtb \ 388 keystone-k2g-generic.dtb \
388 keystone-k2g-ice.dtb 389 keystone-k2g-ice.dtb
389 390
390 dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb 391 dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb
391 392
392 dtb-$(CONFIG_TARGET_PM9263) += at91sam9263ek.dtb 393 dtb-$(CONFIG_TARGET_PM9263) += at91sam9263ek.dtb
393 394
394 dtb-$(CONFIG_TARGET_AT91SAM9263EK) += at91sam9263ek.dtb 395 dtb-$(CONFIG_TARGET_AT91SAM9263EK) += at91sam9263ek.dtb
395 396
396 dtb-$(CONFIG_TARGET_AT91SAM9RLEK) += at91sam9rlek.dtb 397 dtb-$(CONFIG_TARGET_AT91SAM9RLEK) += at91sam9rlek.dtb
397 398
398 dtb-$(CONFIG_TARGET_AT91SAM9260EK) += \ 399 dtb-$(CONFIG_TARGET_AT91SAM9260EK) += \
399 at91sam9260ek.dtb \ 400 at91sam9260ek.dtb \
400 at91sam9g20ek.dtb \ 401 at91sam9g20ek.dtb \
401 at91sam9g20ek_2mmc.dtb 402 at91sam9g20ek_2mmc.dtb
402 403
403 dtb-$(CONFIG_TARGET_AT91SAM9M10G45EK) += at91sam9m10g45ek.dtb 404 dtb-$(CONFIG_TARGET_AT91SAM9M10G45EK) += at91sam9m10g45ek.dtb
404 405
405 dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \ 406 dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \
406 at91sam9g15ek.dtb \ 407 at91sam9g15ek.dtb \
407 at91sam9g25ek.dtb \ 408 at91sam9g25ek.dtb \
408 at91sam9g35ek.dtb \ 409 at91sam9g35ek.dtb \
409 at91sam9x25ek.dtb \ 410 at91sam9x25ek.dtb \
410 at91sam9x35ek.dtb 411 at91sam9x35ek.dtb
411 412
412 dtb-$(CONFIG_TARGET_AT91SAM9N12EK) += at91sam9n12ek.dtb 413 dtb-$(CONFIG_TARGET_AT91SAM9N12EK) += at91sam9n12ek.dtb
413 414
414 dtb-$(CONFIG_TARGET_OMAP3_LOGIC) += \ 415 dtb-$(CONFIG_TARGET_OMAP3_LOGIC) += \
415 logicpd-torpedo-37xx-devkit.dtb \ 416 logicpd-torpedo-37xx-devkit.dtb \
416 logicpd-som-lv-37xx-devkit.dtb 417 logicpd-som-lv-37xx-devkit.dtb
417 418
418 dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \ 419 dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \
419 at91-sama5d2_xplained.dtb 420 at91-sama5d2_xplained.dtb
420 421
421 dtb-$(CONFIG_TARGET_SAMA5D3XEK) += \ 422 dtb-$(CONFIG_TARGET_SAMA5D3XEK) += \
422 sama5d31ek.dtb \ 423 sama5d31ek.dtb \
423 sama5d33ek.dtb \ 424 sama5d33ek.dtb \
424 sama5d34ek.dtb \ 425 sama5d34ek.dtb \
425 sama5d35ek.dtb \ 426 sama5d35ek.dtb \
426 sama5d36ek.dtb \ 427 sama5d36ek.dtb \
427 sama5d36ek_cmp.dtb 428 sama5d36ek_cmp.dtb
428 429
429 dtb-$(CONFIG_TARGET_SAMA5D3_XPLAINED) += \ 430 dtb-$(CONFIG_TARGET_SAMA5D3_XPLAINED) += \
430 at91-sama5d3_xplained.dtb 431 at91-sama5d3_xplained.dtb
431 432
432 dtb-$(CONFIG_TARGET_SAMA5D4EK) += \ 433 dtb-$(CONFIG_TARGET_SAMA5D4EK) += \
433 at91-sama5d4ek.dtb 434 at91-sama5d4ek.dtb
434 435
435 dtb-$(CONFIG_TARGET_SAMA5D4_XPLAINED) += \ 436 dtb-$(CONFIG_TARGET_SAMA5D4_XPLAINED) += \
436 at91-sama5d4_xplained.dtb 437 at91-sama5d4_xplained.dtb
437 438
438 dtb-$(CONFIG_ARCH_BCM283X) += \ 439 dtb-$(CONFIG_ARCH_BCM283X) += \
439 bcm2835-rpi-a-plus.dtb \ 440 bcm2835-rpi-a-plus.dtb \
440 bcm2835-rpi-a.dtb \ 441 bcm2835-rpi-a.dtb \
441 bcm2835-rpi-b-plus.dtb \ 442 bcm2835-rpi-b-plus.dtb \
442 bcm2835-rpi-b-rev2.dtb \ 443 bcm2835-rpi-b-rev2.dtb \
443 bcm2835-rpi-b.dtb \ 444 bcm2835-rpi-b.dtb \
444 bcm2836-rpi-2-b.dtb \ 445 bcm2836-rpi-2-b.dtb \
445 bcm2837-rpi-3-b.dtb 446 bcm2837-rpi-3-b.dtb
446 447
447 dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb 448 dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb
448 449
449 dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb 450 dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
450 451
451 targets += $(dtb-y) 452 targets += $(dtb-y)
452 453
453 # Add any required device tree compiler flags here 454 # Add any required device tree compiler flags here
454 DTC_FLAGS += 455 DTC_FLAGS +=
455 456
456 PHONY += dtbs 457 PHONY += dtbs
457 dtbs: $(addprefix $(obj)/, $(dtb-y)) 458 dtbs: $(addprefix $(obj)/, $(dtb-y))
458 @: 459 @:
459 460
460 clean-files := *.dtb 461 clean-files := *.dtb
461 462
arch/arm/dts/fsl-ls1088a-qds.dts
Diff comments   View file @ 7769776
File was created 1 /*
2 * NXP ls1088a QDS board device tree source
3 *
4 * Copyright 2017 NXP
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9 /dts-v1/;
10
11 #include "fsl-ls1088a.dtsi"
12
13 / {
14 model = "NXP Layerscape 1088a QDS Board";
15 compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
16 aliases {
17 spi0 = &qspi;
18 spi1 = &dspi;
19 };
20 };
21
22 &dspi {
23 bus-num = <0>;
24 status = "okay";
25
26 dflash0: n25q128a {
27 #address-cells = <1>;
28 #size-cells = <1>;
29 compatible = "spi-flash";
30 reg = <0>;
31 spi-max-frequency = <1000000>; /* input clock */
32 };
33
34 dflash1: sst25wf040b {
35 #address-cells = <1>;
36 #size-cells = <1>;
37 compatible = "spi-flash";
38 spi-max-frequency = <3500000>;
39 reg = <1>;
40 };
41
42 dflash2: en25s64 {
43 #address-cells = <1>;
44 #size-cells = <1>;
45 compatible = "spi-flash";
46 spi-max-frequency = <3500000>;
47 reg = <2>;
48 };
49 };
50
51 &qspi {
52 bus-num = <0>;
53 status = "okay";
54
55 qflash0: s25fs512s@0 {
56 #address-cells = <1>;
57 #size-cells = <1>;
58 compatible = "spi-flash";
59 spi-max-frequency = <50000000>;
60 reg = <0>;
61 };
62
63 qflash1: s25fs512s@1 {
64 #address-cells = <1>;
65 #size-cells = <1>;
66 compatible = "spi-flash";
67 spi-max-frequency = <50000000>;
68 reg = <1>;
69 };
70 };
71
board/freescale/ls1088a/Kconfig
Diff comments   View file @ 7769776
1 if TARGET_LS1088AQDS
2
3 config SYS_BOARD
4 default "ls1088a"
5
6 config SYS_VENDOR
7 default "freescale"
8
9 config SYS_SOC
10 default "fsl-layerscape"
11
12 config SYS_CONFIG_NAME
13 default "ls1088aqds"
14
15 endif
16
1 if TARGET_LS1088ARDB 17 if TARGET_LS1088ARDB
2 18
3 config SYS_BOARD 19 config SYS_BOARD
4 default "ls1088a" 20 default "ls1088a"
5 21
6 config SYS_VENDOR 22 config SYS_VENDOR
7 default "freescale" 23 default "freescale"
8 24
9 config SYS_SOC 25 config SYS_SOC
10 default "fsl-layerscape" 26 default "fsl-layerscape"
11 27
12 config SYS_CONFIG_NAME 28 config SYS_CONFIG_NAME
13 default "ls1088ardb" 29 default "ls1088ardb"
14 30
15 endif 31 endif
16 32
board/freescale/ls1088a/MAINTAINERS
Diff comments   View file @ 7769776
1 LS1088ARDB BOARD 1 LS1088ARDB BOARD
2 M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> 2 M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
3 M: Ashish Kumar <Ashish.Kumar@nxp.com> 3 M: Ashish Kumar <Ashish.Kumar@nxp.com>
4 S: Maintained 4 S: Maintained
5 F: board/freescale/ls1088a/ 5 F: board/freescale/ls1088a/
6 F: include/configs/ls1088ardb.h 6 F: include/configs/ls1088ardb.h
7 F: configs/ls1088ardb_qspi_defconfig 7 F: configs/ls1088ardb_qspi_defconfig
8
9 LS1088AQDS BOARD
10 M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
11 M: Ashish Kumar <Ashish.Kumar@nxp.com>
12 S: Maintained
13 F: board/freescale/ls1088a/
14 F: include/configs/ls1088aqds.h
15 F: configs/ls1088aqds_qspi_defconfig
8 16
board/freescale/ls1088a/Makefile
Diff comments   View file @ 7769776
1 # 1 #
2 # Copyright 2017 NXP 2 # Copyright 2017 NXP
3 # 3 #
4 # SPDX-License-Identifier: GPL-2.0+ 4 # SPDX-License-Identifier: GPL-2.0+
5 # 5 #
6 6
7 obj-y += ls1088a.o 7 obj-y += ls1088a.o
8 obj-$(CONFIG_TARGET_LS1088ARDB) += eth_ls1088ardb.o 8 obj-$(CONFIG_TARGET_LS1088ARDB) += eth_ls1088ardb.o
9 obj-$(CONFIG_TARGET_LS1088AQDS) += eth_ls1088aqds.o
9 obj-y += ddr.o 10 obj-y += ddr.o
10 11
board/freescale/ls1088a/README
Diff comments   View file @ 7769776
1 Overview 1 Overview
2 -------- 2 --------
3 The LS1088A Reference Design (RDB) is a high-performance computing, 3 The LS1088A Reference Design (RDB) is a high-performance computing,
4 evaluation, and development platform that supports ARM SoC LS1088A and its 4 evaluation, and development platform that supports ARM SoC LS1088A and its
5 derivatives. 5 derivatives.
6 6
7 7
8 LS1088A SoC Overview 8 LS1088A SoC Overview
9 -------------------------------------- 9 --------------------------------------
10 Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc 10 Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
11 11
12 RDB Default Switch Settings (1: ON; 0: OFF) 12 RDB Default Switch Settings (1: ON; 0: OFF)
13 ------------------------------------------- 13 -------------------------------------------
14 14
15 For QSPI Boot 15 For QSPI Boot
16 SW1 0011 0001 16 SW1 0011 0001
17 SW2 x100 0000 17 SW2 x100 0000
18 SW3 1111 0010 18 SW3 1111 0010
19 SW4 1001 0011 19 SW4 1001 0011
20 SW5 1111 0000 20 SW5 1111 0000
21 21
22 For SD Boot 22 For SD Boot
23 SW1 0010 0000 23 SW1 0010 0000
24 SW2 0100 0000 24 SW2 0100 0000
25 SW3 1111 0010 25 SW3 1111 0010
26 SW4 1001 0011 26 SW4 1001 0011
27 SW5 1111 0000 27 SW5 1111 0000
28 28
29 For eMMC Boot 29 For eMMC Boot
30 SW1 0010 0000 30 SW1 0010 0000
31 SW2 1100 0000 31 SW2 1100 0000
32 SW3 1111 0010 32 SW3 1111 0010
33 SW4 1001 0011 33 SW4 1001 0011
34 SW5 1111 0000 34 SW5 1111 0000
35 35
36 Alternately you can use this command to switch from QSPI to SD 36 Alternately you can use this command to switch from QSPI to SD
37 37
38 => i2c mw 66 0x60 0x20; i2c mw 66 10 10;i2c mw 66 10 21 38 => i2c mw 66 0x60 0x20; i2c mw 66 10 10;i2c mw 66 10 21
39 39
40 LS1088ARDB board Overview 40 LS1088ARDB board Overview
41 ------------------------- 41 -------------------------
42 - SERDES Connections, 16 lanes supporting: 42 - SERDES Connections, 16 lanes supporting:
43 - PCI Express - 3.0 43 - PCI Express - 3.0
44 - SATA 3.0 44 - SATA 3.0
45 - XFI 45 - XFI
46 - QSGMII 46 - QSGMII
47 - DDR Controller 47 - DDR Controller
48 - One ports of 72-bits (8-bits ECC, 64-bits DATA) DDR4. Each port supports four 48 - One ports of 72-bits (8-bits ECC, 64-bits DATA) DDR4. Each port supports four
49 chip-selects on one DIMM connector. Support is up to 2133MT/s, Although MAX default 49 chip-selects on one DIMM connector. Support is up to 2133MT/s, Although MAX default
50 with FSL refernce software is 2100MT/s 50 with FSL refernce software is 2100MT/s
51 - 2 QSPI-NOR Spansion(S25FS512SDSMFI011) flash of size 64MB 51 - 2 QSPI-NOR Spansion(S25FS512SDSMFI011) flash of size 64MB
52 - IFC/Local Bus 52 - IFC/Local Bus
53 - One 2 GB NAND flash with ECC support, not as boot source 53 - One 2 GB NAND flash with ECC support, not as boot source
54 - CPLD of size 2K 54 - CPLD of size 2K
55 - USB 3.0 55 - USB 3.0
56 - Two high speed USB 3.0 ports 56 - Two high speed USB 3.0 ports
57 - First USB 3.0 port configured as Host with Type-A connector 57 - First USB 3.0 port configured as Host with Type-A connector
58 - Second USB 3.0 port configured as OTG with micro-AB connector 58 - Second USB 3.0 port configured as OTG with micro-AB connector
59 - SDHC/eMMC 59 - SDHC/eMMC
60 - SDHC slot and onboard eMMC are muxed together 60 - SDHC slot and onboard eMMC are muxed together
61 - 4 I2C controllers 61 - 4 I2C controllers
62 - Two SATA onboard connectors 62 - Two SATA onboard connectors
63 - 2 UART 63 - 2 UART
64 - JTAG support 64 - JTAG support
65 - QSPI emulator support 65 - QSPI emulator support
66 - TDM riser support 66 - TDM riser support
67
68 QDS Default Switch Settings (1: ON; 0: OFF)
69 -------------------------------------------
70
71 For 16b IFC-NOR
72 SW1 0001 0010
73 SW2 x110 1111
74
75 For QSPI Boot
76 SW1 0011 0001
77 SW2 0110 1111
78
79 For SD Boot
80 SW1 0010 0000
81 SW2 0110 1111
82
83 For eMMC Boot
84 SW1 0010 0000
85 SW2 1110 1111
86
87 For I2C (ext. addr.)
88 SW1 0010 0100
89 SW2 1110 1111
90
91 SW3 to SW12 are identical for all boot source
92
93 SW3 0010 0100
94 SW4 0010 0000
95 SW5 1110 0111
96 SW6 1110 1000
97 SW7 0001 1101
98 SW8 0000 1101
99 SW9 1100 1010
100 SW10 1110 1000
101 SW11 1111 0100
102 SW12 1111 1111
103
104 LS1088AQDS board Overview
105 -------------------------
106 - SERDES Connections, 16 lanes supporting:
107 - PCI Express - 3.0
108 - SATA 3.0
109 - 2 XFI
110 - QSGMII, SGMII with help for Riser card
111 - 2 RGMII
112 - 5 slot for Riser card or PCIe NIC
113 - DDR Controller
114 - One ports of 72-bits (8-bits ECC, 64-bits DATA) DDR4. Each port supports four
115 chip-selects on one DIMM connector. Support is up to 2133MT/s, Although MAX default
116 with FSL refernce software is 2100MT/s
117 - 2 QSPI-NOR Spansion(S25FS512SDSMFI011) flash of size 64MB
118 - IFC/Local Bus
119 - One 2 GB NAND flash with ECC support, not as boot source
120 - CPLD of size 2K
121 - USB 3.0
122 - Two high speed USB 3.0 ports
123 - First USB 3.0 port configured as Host with Type-A connector
124 - Second USB 3.0 port configured as OTG with micro-AB connector
125 - SDHC/eMMC
126 - SDHC/eMMC slot via adaptor
127 - 4 I2C controllers
128 - Two SATA onboard connectors
129 - 2 UART
130 - JTAG support
131 - DSPI
132 - PROMJET support
133 - QSPI emulator support
134 - TDM riser support
135
136 QSPI flash memory map valid for both QDS and RDB
137 Image Flash Offset
138 RCW+PBI 0x00000000
139 Boot firmware (U-Boot) 0x00100000
140 Boot firmware Environment 0x00300000
141 PPA firmware 0x00400000
142 DPAA2 MC 0x00A00000
143 DPAA2 DPL 0x00D00000
144 DPAA2 DPC 0x00E00000
145 Kernel.itb 0x01000000
67 146
board/freescale/ls1088a/ddr.h
Diff comments   View file @ 7769776
1 /* 1 /*
2 * Copyright 2017 NXP 2 * Copyright 2017 NXP
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #ifndef __LS1088A_DDR_H__ 7 #ifndef __LS1088A_DDR_H__
8 #define __LS1088A_DDR_H__ 8 #define __LS1088A_DDR_H__
9 struct board_specific_parameters { 9 struct board_specific_parameters {
10 u32 n_ranks; 10 u32 n_ranks;
11 u32 datarate_mhz_high; 11 u32 datarate_mhz_high;
12 u32 rank_gb; 12 u32 rank_gb;
13 u32 clk_adjust; 13 u32 clk_adjust;
14 u32 wrlvl_start; 14 u32 wrlvl_start;
15 u32 wrlvl_ctl_2; 15 u32 wrlvl_ctl_2;
16 u32 wrlvl_ctl_3; 16 u32 wrlvl_ctl_3;
17 }; 17 };
18 18
19 /* 19 /*
20 * These tables contain all valid speeds we want to override with board 20 * These tables contain all valid speeds we want to override with board
21 * specific parameters. datarate_mhz_high values need to be in ascending order 21 * specific parameters. datarate_mhz_high values need to be in ascending order
22 * for each n_ranks group. 22 * for each n_ranks group.
23 */ 23 */
24 24
25 static const struct board_specific_parameters udimm0[] = { 25 static const struct board_specific_parameters udimm0[] = {
26 /* 26 /*
27 * memory controller 0 27 * memory controller 0
28 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl 28 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
29 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 29 * ranks| mhz| GB |adjst| start | ctl2 | ctl3
30 */ 30 */
31 #if defined(CONFIG_TARGET_LS1088ARDB) 31 #if defined(CONFIG_TARGET_LS1088ARDB)
32 32
33 {2, 1666, 0, 8, 8, 0x090A0B0E, 0x0F10110D,}, 33 {2, 1666, 0, 8, 8, 0x090A0B0E, 0x0F10110D,},
34 {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,}, 34 {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
35 {2, 2300, 0, 8, 9, 0x0A0C0E11, 0x1214160F,}, 35 {2, 2300, 0, 8, 9, 0x0A0C0E11, 0x1214160F,},
36 {} 36 {}
37 #elif defined(CONFIG_TARGET_LS1088AQDS)
38 {2, 1666, 0, 8, 8, 0x0A0A0C0E, 0x0F10110C,},
39 {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
40 {2, 2300, 0, 4, 9, 0x0A0C0D11, 0x1214150E,},
41 {}
37 42
38 #endif 43 #endif
39 }; 44 };
40 45
41 static const struct board_specific_parameters *udimms[] = { 46 static const struct board_specific_parameters *udimms[] = {
42 udimm0, 47 udimm0,
43 }; 48 };
44 #endif 49 #endif
45 50
board/freescale/ls1088a/eth_ls1088aqds.c
Diff comments   View file @ 7769776
File was created 1 /*
2 * Copyright 2017 NXP
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <common.h>
8 #include <netdev.h>
9 #include <asm/io.h>
10 #include <asm/arch/fsl_serdes.h>
11 #include <hwconfig.h>
12 #include <fsl_mdio.h>
13 #include <malloc.h>
14 #include <fm_eth.h>
15 #include <i2c.h>
16 #include <miiphy.h>
17 #include <fsl-mc/ldpaa_wriop.h>
18
19 #include "../common/qixis.h"
20
21 #include "ls1088a_qixis.h"
22
23 #define MC_BOOT_ENV_VAR "mcinitcmd"
24
25 #ifdef CONFIG_FSL_MC_ENET
26
27 #define SFP_TX 0
28
29 /* - In LS1088A A there are only 16 SERDES lanes, spread across 2 SERDES banks.
30 * Bank 1 -> Lanes A, B, C, D,
31 * Bank 2 -> Lanes A,B, C, D,
32 */
33
34 /* Mapping of 8 SERDES lanes to LS1088A QDS board slots. A value of '0' here
35 * means that the mapping must be determined dynamically, or that the lane
36 * maps to something other than a board slot.
37 */
38
39 static u8 lane_to_slot_fsm1[] = {
40 0, 0, 0, 0, 0, 0, 0, 0
41 };
42
43 /* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
44 * housed.
45 */
46
47 static int xqsgii_riser_phy_addr[] = {
48 XQSGMII_CARD_PHY1_PORT0_ADDR,
49 XQSGMII_CARD_PHY2_PORT0_ADDR,
50 XQSGMII_CARD_PHY3_PORT0_ADDR,
51 XQSGMII_CARD_PHY4_PORT0_ADDR,
52 XQSGMII_CARD_PHY3_PORT2_ADDR,
53 XQSGMII_CARD_PHY1_PORT2_ADDR,
54 XQSGMII_CARD_PHY4_PORT2_ADDR,
55 XQSGMII_CARD_PHY2_PORT2_ADDR,
56 };
57
58 static int sgmii_riser_phy_addr[] = {
59 SGMII_CARD_PORT1_PHY_ADDR,
60 SGMII_CARD_PORT2_PHY_ADDR,
61 SGMII_CARD_PORT3_PHY_ADDR,
62 SGMII_CARD_PORT4_PHY_ADDR,
63 };
64
65 /* Slot2 does not have EMI connections */
66 #define EMI_NONE 0xFF
67 #define EMI1_RGMII1 0
68 #define EMI1_RGMII2 1
69 #define EMI1_SLOT1 2
70
71 static const char * const mdio_names[] = {
72 "LS1088A_QDS_MDIO0",
73 "LS1088A_QDS_MDIO1",
74 "LS1088A_QDS_MDIO2",
75 DEFAULT_WRIOP_MDIO2_NAME,
76 };
77
78 struct ls1088a_qds_mdio {
79 u8 muxval;
80 struct mii_dev *realbus;
81 };
82
83 static void sgmii_configure_repeater(int dpmac)
84 {
85 struct mii_dev *bus;
86 uint8_t a = 0xf;
87 int i, j, ret;
88 unsigned short value;
89 const char *dev = "LS1088A_QDS_MDIO2";
90 int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
91 int i2c_phy_addr = 0;
92 int phy_addr = 0;
93
94 uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
95 uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
96 uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
97 uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
98
99 /* Set I2c to Slot 1 */
100 i2c_write(0x77, 0, 0, &a, 1);
101
102 switch (dpmac) {
103 case 1:
104 i2c_phy_addr = i2c_addr[1];
105 phy_addr = 4;
106 break;
107 case 2:
108 i2c_phy_addr = i2c_addr[0];
109 phy_addr = 0;
110 break;
111 case 3:
112 i2c_phy_addr = i2c_addr[3];
113 phy_addr = 0xc;
114 break;
115 case 7:
116 i2c_phy_addr = i2c_addr[2];
117 phy_addr = 8;
118 break;
119 }
120
121 /* Check the PHY status */
122 ret = miiphy_set_current_dev(dev);
123 if (ret > 0)
124 goto error;
125
126 bus = mdio_get_current_dev();
127 debug("Reading from bus %s\n", bus->name);
128
129 ret = miiphy_write(dev, phy_addr, 0x1f, 3);
130 if (ret > 0)
131 goto error;
132
133 mdelay(10);
134 ret = miiphy_read(dev, phy_addr, 0x11, &value);
135 if (ret > 0)
136 goto error;
137
138 mdelay(10);
139
140 if ((value & 0xfff) == 0x401) {
141 miiphy_write(dev, phy_addr, 0x1f, 0);
142 printf("DPMAC %d:PHY is ..... Configured\n", dpmac);
143 return;
144 }
145
146 for (i = 0; i < 4; i++) {
147 for (j = 0; j < 4; j++) {
148 a = 0x18;
149 i2c_write(i2c_phy_addr, 6, 1, &a, 1);
150 a = 0x38;
151 i2c_write(i2c_phy_addr, 4, 1, &a, 1);
152 a = 0x4;
153 i2c_write(i2c_phy_addr, 8, 1, &a, 1);
154
155 i2c_write(i2c_phy_addr, 0xf, 1,
156 &ch_a_eq[i], 1);
157 i2c_write(i2c_phy_addr, 0x11, 1,
158 &ch_a_ctl2[j], 1);
159
160 i2c_write(i2c_phy_addr, 0x16, 1,
161 &ch_b_eq[i], 1);
162 i2c_write(i2c_phy_addr, 0x18, 1,
163 &ch_b_ctl2[j], 1);
164
165 a = 0x14;
166 i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
167 a = 0xb5;
168 i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
169 a = 0x20;
170 i2c_write(i2c_phy_addr, 4, 1, &a, 1);
171 mdelay(100);
172 ret = miiphy_read(dev, phy_addr, 0x11, &value);
173 if (ret > 0)
174 goto error;
175
176 mdelay(100);
177 ret = miiphy_read(dev, phy_addr, 0x11, &value);
178 if (ret > 0)
179 goto error;
180
181 if ((value & 0xfff) == 0x401) {
182 printf("DPMAC %d :PHY is configured ",
183 dpmac);
184 printf("after setting repeater 0x%x\n",
185 value);
186 i = 5;
187 j = 5;
188 } else {
189 printf("DPMAC %d :PHY is failed to ",
190 dpmac);
191 printf("configure the repeater 0x%x\n", value);
192 }
193 }
194 }
195 miiphy_write(dev, phy_addr, 0x1f, 0);
196 error:
197 if (ret)
198 printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac);
199 return;
200 }
201
202 static void qsgmii_configure_repeater(int dpmac)
203 {
204 uint8_t a = 0xf;
205 int i, j;
206 int i2c_phy_addr = 0;
207 int phy_addr = 0;
208 int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
209
210 uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
211 uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
212 uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
213 uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
214
215 const char *dev = mdio_names[EMI1_SLOT1];
216 int ret = 0;
217 unsigned short value;
218
219 /* Set I2c to Slot 1 */
220 i2c_write(0x77, 0, 0, &a, 1);
221
222 switch (dpmac) {
223 case 7:
224 case 8:
225 case 9:
226 case 10:
227 i2c_phy_addr = i2c_addr[2];
228 phy_addr = 8;
229 break;
230
231 case 3:
232 case 4:
233 case 5:
234 case 6:
235 i2c_phy_addr = i2c_addr[3];
236 phy_addr = 0xc;
237 break;
238 }
239
240 /* Check the PHY status */
241 ret = miiphy_set_current_dev(dev);
242 ret = miiphy_write(dev, phy_addr, 0x1f, 3);
243 mdelay(10);
244 ret = miiphy_read(dev, phy_addr, 0x11, &value);
245 mdelay(10);
246 ret = miiphy_read(dev, phy_addr, 0x11, &value);
247 mdelay(10);
248 if ((value & 0xf) == 0xf) {
249 miiphy_write(dev, phy_addr, 0x1f, 0);
250 printf("DPMAC %d :PHY is ..... Configured\n", dpmac);
251 return;
252 }
253
254 for (i = 0; i < 4; i++) {
255 for (j = 0; j < 4; j++) {
256 a = 0x18;
257 i2c_write(i2c_phy_addr, 6, 1, &a, 1);
258 a = 0x38;
259 i2c_write(i2c_phy_addr, 4, 1, &a, 1);
260 a = 0x4;
261 i2c_write(i2c_phy_addr, 8, 1, &a, 1);
262
263 i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1);
264 i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1);
265
266 i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1);
267 i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1);
268
269 a = 0x14;
270 i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
271 a = 0xb5;
272 i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
273 a = 0x20;
274 i2c_write(i2c_phy_addr, 4, 1, &a, 1);
275 mdelay(100);
276 ret = miiphy_read(dev, phy_addr, 0x11, &value);
277 if (ret > 0)
278 goto error;
279 mdelay(1);
280 ret = miiphy_read(dev, phy_addr, 0x11, &value);
281 if (ret > 0)
282 goto error;
283 mdelay(10);
284 if ((value & 0xf) == 0xf) {
285 miiphy_write(dev, phy_addr, 0x1f, 0);
286 printf("DPMAC %d :PHY is ..... Configured\n",
287 dpmac);
288 return;
289 }
290 }
291 }
292 error:
293 printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac);
294 return;
295 }
296
297 static const char *ls1088a_qds_mdio_name_for_muxval(u8 muxval)
298 {
299 return mdio_names[muxval];
300 }
301
302 struct mii_dev *mii_dev_for_muxval(u8 muxval)
303 {
304 struct mii_dev *bus;
305 const char *name = ls1088a_qds_mdio_name_for_muxval(muxval);
306
307 if (!name) {
308 printf("No bus for muxval %x\n", muxval);
309 return NULL;
310 }
311
312 bus = miiphy_get_dev_by_name(name);
313
314 if (!bus) {
315 printf("No bus by name %s\n", name);
316 return NULL;
317 }
318
319 return bus;
320 }
321
322 static void ls1088a_qds_enable_SFP_TX(u8 muxval)
323 {
324 u8 brdcfg9;
325
326 brdcfg9 = QIXIS_READ(brdcfg[9]);
327 brdcfg9 &= ~BRDCFG9_SFPTX_MASK;
328 brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT);
329 QIXIS_WRITE(brdcfg[9], brdcfg9);
330 }
331
332 static void ls1088a_qds_mux_mdio(u8 muxval)
333 {
334 u8 brdcfg4;
335
336 if (muxval <= 5) {
337 brdcfg4 = QIXIS_READ(brdcfg[4]);
338 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
339 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
340 QIXIS_WRITE(brdcfg[4], brdcfg4);
341 }
342 }
343
344 static int ls1088a_qds_mdio_read(struct mii_dev *bus, int addr,
345 int devad, int regnum)
346 {
347 struct ls1088a_qds_mdio *priv = bus->priv;
348
349 ls1088a_qds_mux_mdio(priv->muxval);
350
351 return priv->realbus->read(priv->realbus, addr, devad, regnum);
352 }
353
354 static int ls1088a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
355 int regnum, u16 value)
356 {
357 struct ls1088a_qds_mdio *priv = bus->priv;
358
359 ls1088a_qds_mux_mdio(priv->muxval);
360
361 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
362 }
363
364 static int ls1088a_qds_mdio_reset(struct mii_dev *bus)
365 {
366 struct ls1088a_qds_mdio *priv = bus->priv;
367
368 return priv->realbus->reset(priv->realbus);
369 }
370
371 static int ls1088a_qds_mdio_init(char *realbusname, u8 muxval)
372 {
373 struct ls1088a_qds_mdio *pmdio;
374 struct mii_dev *bus = mdio_alloc();
375
376 if (!bus) {
377 printf("Failed to allocate ls1088a_qds MDIO bus\n");
378 return -1;
379 }
380
381 pmdio = malloc(sizeof(*pmdio));
382 if (!pmdio) {
383 printf("Failed to allocate ls1088a_qds private data\n");
384 free(bus);
385 return -1;
386 }
387
388 bus->read = ls1088a_qds_mdio_read;
389 bus->write = ls1088a_qds_mdio_write;
390 bus->reset = ls1088a_qds_mdio_reset;
391 sprintf(bus->name, ls1088a_qds_mdio_name_for_muxval(muxval));
392
393 pmdio->realbus = miiphy_get_dev_by_name(realbusname);
394
395 if (!pmdio->realbus) {
396 printf("No bus with name %s\n", realbusname);
397 free(bus);
398 free(pmdio);
399 return -1;
400 }
401
402 pmdio->muxval = muxval;
403 bus->priv = pmdio;
404
405 return mdio_register(bus);
406 }
407
408 /*
409 * Initialize the dpmac_info array.
410 *
411 */
412 static void initialize_dpmac_to_slot(void)
413 {
414 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
415 u32 serdes1_prtcl, cfg;
416
417 cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
418 FSL_CHASSIS3_SRDS1_PRTCL_MASK;
419 cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
420 serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
421
422 switch (serdes1_prtcl) {
423 case 0x12:
424 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
425 serdes1_prtcl);
426 lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
427 lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
428 lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
429 lane_to_slot_fsm1[3] = EMI1_SLOT1 - 1;
430 break;
431 case 0x15:
432 case 0x1D:
433 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
434 serdes1_prtcl);
435 lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
436 lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
437 lane_to_slot_fsm1[2] = EMI_NONE;
438 lane_to_slot_fsm1[3] = EMI_NONE;
439 break;
440 case 0x1E:
441 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
442 serdes1_prtcl);
443 lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
444 lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
445 lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
446 lane_to_slot_fsm1[3] = EMI_NONE;
447 break;
448 case 0x3A:
449 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
450 serdes1_prtcl);
451 lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
452 lane_to_slot_fsm1[1] = EMI_NONE;
453 lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
454 lane_to_slot_fsm1[3] = EMI1_SLOT1 - 1;
455 break;
456
457 default:
458 printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
459 __func__, serdes1_prtcl);
460 break;
461 }
462 }
463
464 void ls1088a_handle_phy_interface_sgmii(int dpmac_id)
465 {
466 struct mii_dev *bus;
467 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
468 u32 serdes1_prtcl, cfg;
469
470 cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
471 FSL_CHASSIS3_SRDS1_PRTCL_MASK;
472 cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
473 serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
474
475 int *riser_phy_addr;
476 char *env_hwconfig = env_get("hwconfig");
477
478 if (hwconfig_f("xqsgmii", env_hwconfig))
479 riser_phy_addr = &xqsgii_riser_phy_addr[0];
480 else
481 riser_phy_addr = &sgmii_riser_phy_addr[0];
482
483 switch (serdes1_prtcl) {
484 case 0x12:
485 case 0x15:
486 case 0x1E:
487 case 0x3A:
488 switch (dpmac_id) {
489 case 1:
490 wriop_set_phy_address(dpmac_id, riser_phy_addr[1]);
491 break;
492 case 2:
493 wriop_set_phy_address(dpmac_id, riser_phy_addr[0]);
494 break;
495 case 3:
496 wriop_set_phy_address(dpmac_id, riser_phy_addr[3]);
497 break;
498 case 7:
499 wriop_set_phy_address(dpmac_id, riser_phy_addr[2]);
500 break;
501 default:
502 printf("WRIOP: Wrong DPMAC%d set to SGMII", dpmac_id);
503 break;
504 }
505 break;
506 default:
507 printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
508 __func__, serdes1_prtcl);
509 return;
510 }
511 dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
512 bus = mii_dev_for_muxval(EMI1_SLOT1);
513 wriop_set_mdio(dpmac_id, bus);
514 }
515
516 void ls1088a_handle_phy_interface_qsgmii(int dpmac_id)
517 {
518 struct mii_dev *bus;
519 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
520 u32 serdes1_prtcl, cfg;
521
522 cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
523 FSL_CHASSIS3_SRDS1_PRTCL_MASK;
524 cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
525 serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
526
527 switch (serdes1_prtcl) {
528 case 0x1D:
529 case 0x1E:
530 switch (dpmac_id) {
531 case 3:
532 case 4:
533 case 5:
534 case 6:
535 wriop_set_phy_address(dpmac_id, dpmac_id + 9);
536 break;
537 case 7:
538 case 8:
539 case 9:
540 case 10:
541 wriop_set_phy_address(dpmac_id, dpmac_id + 1);
542 break;
543 }
544
545 dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
546 bus = mii_dev_for_muxval(EMI1_SLOT1);
547 wriop_set_mdio(dpmac_id, bus);
548 break;
549 default:
550 printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
551 serdes1_prtcl);
552 break;
553 }
554 }
555
556 void ls1088a_handle_phy_interface_xsgmii(int i)
557 {
558 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
559 u32 serdes1_prtcl, cfg;
560
561 cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
562 FSL_CHASSIS3_SRDS1_PRTCL_MASK;
563 cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
564 serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
565
566 switch (serdes1_prtcl) {
567 case 0x15:
568 case 0x1D:
569 case 0x1E:
570 wriop_set_phy_address(i, i + 26);
571 ls1088a_qds_enable_SFP_TX(SFP_TX);
572 break;
573 default:
574 printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
575 serdes1_prtcl);
576 break;
577 }
578 }
579 #endif
580
581 int board_eth_init(bd_t *bis)
582 {
583 int error = 0, i;
584 char *mc_boot_env_var;
585 #ifdef CONFIG_FSL_MC_ENET
586 struct memac_mdio_info *memac_mdio0_info;
587 char *env_hwconfig = env_get("hwconfig");
588
589 initialize_dpmac_to_slot();
590
591 memac_mdio0_info = (struct memac_mdio_info *)malloc(
592 sizeof(struct memac_mdio_info));
593 memac_mdio0_info->regs =
594 (struct memac_mdio_controller *)
595 CONFIG_SYS_FSL_WRIOP1_MDIO1;
596 memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
597
598 /* Register the real MDIO1 bus */
599 fm_memac_mdio_init(bis, memac_mdio0_info);
600
601 /* Register the muxing front-ends to the MDIO buses */
602 ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII1);
603 ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII2);
604 ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
605
606 for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
607 switch (wriop_get_enet_if(i)) {
608 case PHY_INTERFACE_MODE_QSGMII:
609 ls1088a_handle_phy_interface_qsgmii(i);
610 break;
611 case PHY_INTERFACE_MODE_SGMII:
612 ls1088a_handle_phy_interface_sgmii(i);
613 break;
614 case PHY_INTERFACE_MODE_XGMII:
615 ls1088a_handle_phy_interface_xsgmii(i);
616 break;
617 default:
618 break;
619
620 if (i == 16)
621 i = NUM_WRIOP_PORTS;
622 }
623 }
624
625 mc_boot_env_var = env_get(MC_BOOT_ENV_VAR);
626 if (mc_boot_env_var)
627 run_command_list(mc_boot_env_var, -1, 0);
628 error = cpu_eth_init(bis);
629
630 if (hwconfig_f("xqsgmii", env_hwconfig)) {
631 for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
632 switch (wriop_get_enet_if(i)) {
633 case PHY_INTERFACE_MODE_QSGMII:
634 qsgmii_configure_repeater(i);
635 break;
636 case PHY_INTERFACE_MODE_SGMII:
637 sgmii_configure_repeater(i);
638 break;
639 default:
640 break;
641 }
642
643 if (i == 16)
644 i = NUM_WRIOP_PORTS;
645 }
646 }
647 #endif
648 error = pci_eth_init(bis);
649 return error;
650 }
651
board/freescale/ls1088a/ls1088a.c
Diff comments   View file @ 7769776
1 /* 1 /*
2 * Copyright 2017 NXP 2 * Copyright 2017 NXP
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 #include <common.h> 6 #include <common.h>
7 #include <i2c.h> 7 #include <i2c.h>
8 #include <malloc.h> 8 #include <malloc.h>
9 #include <errno.h> 9 #include <errno.h>
10 #include <netdev.h> 10 #include <netdev.h>
11 #include <fsl_ifc.h> 11 #include <fsl_ifc.h>
12 #include <fsl_ddr.h> 12 #include <fsl_ddr.h>
13 #include <fsl_sec.h> 13 #include <fsl_sec.h>
14 #include <asm/io.h> 14 #include <asm/io.h>
15 #include <fdt_support.h> 15 #include <fdt_support.h>
16 #include <libfdt.h> 16 #include <libfdt.h>
17 #include <fsl-mc/fsl_mc.h> 17 #include <fsl-mc/fsl_mc.h>
18 #include <environment.h> 18 #include <environment.h>
19 #include <asm/arch-fsl-layerscape/soc.h> 19 #include <asm/arch-fsl-layerscape/soc.h>
20 #include <asm/arch/ppa.h> 20 #include <asm/arch/ppa.h>
21 21
22 #include "../common/qixis.h" 22 #include "../common/qixis.h"
23 #include "ls1088a_qixis.h" 23 #include "ls1088a_qixis.h"
24 24
25 DECLARE_GLOBAL_DATA_PTR; 25 DECLARE_GLOBAL_DATA_PTR;
26 26
27 unsigned long long get_qixis_addr(void) 27 unsigned long long get_qixis_addr(void)
28 { 28 {
29 unsigned long long addr; 29 unsigned long long addr;
30 30
31 if (gd->flags & GD_FLG_RELOC) 31 if (gd->flags & GD_FLG_RELOC)
32 addr = QIXIS_BASE_PHYS; 32 addr = QIXIS_BASE_PHYS;
33 else 33 else
34 addr = QIXIS_BASE_PHYS_EARLY; 34 addr = QIXIS_BASE_PHYS_EARLY;
35 35
36 /* 36 /*
37 * IFC address under 256MB is mapped to 0x30000000, any address above 37 * IFC address under 256MB is mapped to 0x30000000, any address above
38 * is mapped to 0x5_10000000 up to 4GB. 38 * is mapped to 0x5_10000000 up to 4GB.
39 */ 39 */
40 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000; 40 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
41 41
42 return addr; 42 return addr;
43 } 43 }
44 44
45 int checkboard(void) 45 int checkboard(void)
46 { 46 {
47 char buf[64]; 47 char buf[64];
48 u8 sw; 48 u8 sw;
49 static const char *const freq[] = {"100", "125", "156.25", 49 static const char *const freq[] = {"100", "125", "156.25",
50 "100 separate SSCG"}; 50 "100 separate SSCG"};
51 int clock; 51 int clock;
52 52
53 53 #ifdef CONFIG_TARGET_LS1088AQDS
54 printf("Board: LS1088A-QDS, ");
55 #else
54 printf("Board: LS1088A-RDB, "); 56 printf("Board: LS1088A-RDB, ");
57 #endif
55 58
56 sw = QIXIS_READ(arch); 59 sw = QIXIS_READ(arch);
57 printf("Board Arch: V%d, ", sw >> 4); 60 printf("Board Arch: V%d, ", sw >> 4);
58 61
62 #ifdef CONFIG_TARGET_LS1088AQDS
63 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
64 #else
59 printf("Board version: %c, boot from ", (sw & 0xf) + 'A'); 65 printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
66 #endif
60 67
61
62 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf)); 68 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
63 69
64 sw = QIXIS_READ(brdcfg[0]); 70 sw = QIXIS_READ(brdcfg[0]);
65 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 71 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
66 72
67 #ifdef CONFIG_SD_BOOT 73 #ifdef CONFIG_SD_BOOT
68 puts("SD card\n"); 74 puts("SD card\n");
69 #endif 75 #endif
70 switch (sw) { 76 switch (sw) {
77 #ifdef CONFIG_TARGET_LS1088AQDS
71 case 0: 78 case 0:
72 79 case 1:
80 case 2:
81 case 3:
82 case 4:
83 case 5:
84 case 6:
85 case 7:
86 printf("vBank: %d\n", sw);
87 break;
88 case 8:
89 puts("PromJet\n");
90 break;
91 case 15:
92 puts("IFCCard\n");
93 break;
94 case 14:
95 #else
96 case 0:
97 #endif
73 puts("QSPI:"); 98 puts("QSPI:");
74 sw = QIXIS_READ(brdcfg[0]); 99 sw = QIXIS_READ(brdcfg[0]);
75 sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT; 100 sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
76 if (sw == 0 || sw == 4) 101 if (sw == 0 || sw == 4)
77 puts("0\n"); 102 puts("0\n");
78 else if (sw == 1) 103 else if (sw == 1)
79 puts("1\n"); 104 puts("1\n");
80 else 105 else
81 puts("EMU\n"); 106 puts("EMU\n");
82 break; 107 break;
83 108
84 default: 109 default:
85 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 110 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
86 break; 111 break;
87 } 112 }
88 113
89 114 #ifdef CONFIG_TARGET_LS1088AQDS
115 printf("FPGA: v%d (%s), build %d",
116 (int)QIXIS_READ(scver), qixis_read_tag(buf),
117 (int)qixis_read_minor());
118 /* the timestamp string contains "\n" at the end */
119 printf(" on %s", qixis_read_time(buf));
120 #else
90 printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); 121 printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
122 #endif
91 123
92
93 /* 124 /*
94 * Display the actual SERDES reference clocks as configured by the 125 * Display the actual SERDES reference clocks as configured by the
95 * dip switches on the board. Note that the SWx registers could 126 * dip switches on the board. Note that the SWx registers could
96 * technically be set to force the reference clocks to match the 127 * technically be set to force the reference clocks to match the
97 * values that the SERDES expects (or vice versa). For now, however, 128 * values that the SERDES expects (or vice versa). For now, however,
98 * we just display both values and hope the user notices when they 129 * we just display both values and hope the user notices when they
99 * don't match. 130 * don't match.
100 */ 131 */
101 puts("SERDES1 Reference : "); 132 puts("SERDES1 Reference : ");
102 sw = QIXIS_READ(brdcfg[2]); 133 sw = QIXIS_READ(brdcfg[2]);
103 clock = (sw >> 6) & 3; 134 clock = (sw >> 6) & 3;
104 printf("Clock1 = %sMHz ", freq[clock]); 135 printf("Clock1 = %sMHz ", freq[clock]);
105 clock = (sw >> 4) & 3; 136 clock = (sw >> 4) & 3;
106 printf("Clock2 = %sMHz", freq[clock]); 137 printf("Clock2 = %sMHz", freq[clock]);
107 138
108 puts("\nSERDES2 Reference : "); 139 puts("\nSERDES2 Reference : ");
109 clock = (sw >> 2) & 3; 140 clock = (sw >> 2) & 3;
110 printf("Clock1 = %sMHz ", freq[clock]); 141 printf("Clock1 = %sMHz ", freq[clock]);
111 clock = (sw >> 0) & 3; 142 clock = (sw >> 0) & 3;
112 printf("Clock2 = %sMHz\n", freq[clock]); 143 printf("Clock2 = %sMHz\n", freq[clock]);
113 144
114 return 0; 145 return 0;
115 } 146 }
116 147
117 bool if_board_diff_clk(void) 148 bool if_board_diff_clk(void)
118 { 149 {
150 #ifdef CONFIG_TARGET_LS1088AQDS
151 u8 diff_conf = QIXIS_READ(brdcfg[11]);
152 return diff_conf & 0x40;
153 #else
119 u8 diff_conf = QIXIS_READ(dutcfg[11]); 154 u8 diff_conf = QIXIS_READ(dutcfg[11]);
120 return diff_conf & 0x80; 155 return diff_conf & 0x80;
156 #endif
121 } 157 }
122 158
123 unsigned long get_board_sys_clk(void) 159 unsigned long get_board_sys_clk(void)
124 { 160 {
125 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 161 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
126 162
127 switch (sysclk_conf & 0x0f) { 163 switch (sysclk_conf & 0x0f) {
128 case QIXIS_SYSCLK_83: 164 case QIXIS_SYSCLK_83:
129 return 83333333; 165 return 83333333;
130 case QIXIS_SYSCLK_100: 166 case QIXIS_SYSCLK_100:
131 return 100000000; 167 return 100000000;
132 case QIXIS_SYSCLK_125: 168 case QIXIS_SYSCLK_125:
133 return 125000000; 169 return 125000000;
134 case QIXIS_SYSCLK_133: 170 case QIXIS_SYSCLK_133:
135 return 133333333; 171 return 133333333;
136 case QIXIS_SYSCLK_150: 172 case QIXIS_SYSCLK_150:
137 return 150000000; 173 return 150000000;
138 case QIXIS_SYSCLK_160: 174 case QIXIS_SYSCLK_160:
139 return 160000000; 175 return 160000000;
140 case QIXIS_SYSCLK_166: 176 case QIXIS_SYSCLK_166:
141 return 166666666; 177 return 166666666;
142 } 178 }
143 179
144 return 66666666; 180 return 66666666;
145 } 181 }
146 182
147 unsigned long get_board_ddr_clk(void) 183 unsigned long get_board_ddr_clk(void)
148 { 184 {
149 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 185 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
150 186
151 if (if_board_diff_clk()) 187 if (if_board_diff_clk())
152 return get_board_sys_clk(); 188 return get_board_sys_clk();
153 switch ((ddrclk_conf & 0x30) >> 4) { 189 switch ((ddrclk_conf & 0x30) >> 4) {
154 case QIXIS_DDRCLK_100: 190 case QIXIS_DDRCLK_100:
155 return 100000000; 191 return 100000000;
156 case QIXIS_DDRCLK_125: 192 case QIXIS_DDRCLK_125:
157 return 125000000; 193 return 125000000;
158 case QIXIS_DDRCLK_133: 194 case QIXIS_DDRCLK_133:
159 return 133333333; 195 return 133333333;
160 } 196 }
161 197
162 return 66666666; 198 return 66666666;
163 } 199 }
164 200
165 int select_i2c_ch_pca9547(u8 ch) 201 int select_i2c_ch_pca9547(u8 ch)
166 { 202 {
167 int ret; 203 int ret;
168 204
169 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 205 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
170 if (ret) { 206 if (ret) {
171 puts("PCA: failed to select proper channel\n"); 207 puts("PCA: failed to select proper channel\n");
172 return ret; 208 return ret;
173 } 209 }
174 210
175 return 0; 211 return 0;
176 } 212 }
177 213
178 void board_retimer_init(void) 214 void board_retimer_init(void)
179 { 215 {
180 u8 reg; 216 u8 reg;
181 217
182 /* Retimer is connected to I2C1_CH5 */ 218 /* Retimer is connected to I2C1_CH5 */
183 select_i2c_ch_pca9547(I2C_MUX_CH5); 219 select_i2c_ch_pca9547(I2C_MUX_CH5);
184 220
185 /* Access to Control/Shared register */ 221 /* Access to Control/Shared register */
186 reg = 0x0; 222 reg = 0x0;
187 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1); 223 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
188 224
189 /* Read device revision and ID */ 225 /* Read device revision and ID */
190 i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1); 226 i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
191 debug("Retimer version id = 0x%x\n", reg); 227 debug("Retimer version id = 0x%x\n", reg);
192 228
193 /* Enable Broadcast. All writes target all channel register sets */ 229 /* Enable Broadcast. All writes target all channel register sets */
194 reg = 0x0c; 230 reg = 0x0c;
195 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1); 231 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
196 232
197 /* Reset Channel Registers */ 233 /* Reset Channel Registers */
198 i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1); 234 i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
199 reg |= 0x4; 235 reg |= 0x4;
200 i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1); 236 i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
201 237
202 /* Set data rate as 10.3125 Gbps */ 238 /* Set data rate as 10.3125 Gbps */
203 reg = 0x90; 239 reg = 0x90;
204 i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1); 240 i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
205 reg = 0xb3; 241 reg = 0xb3;
206 i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1); 242 i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
207 reg = 0x90; 243 reg = 0x90;
208 i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1); 244 i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
209 reg = 0xb3; 245 reg = 0xb3;
210 i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1); 246 i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
211 reg = 0xcd; 247 reg = 0xcd;
212 i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1); 248 i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
213 249
214 /* Select VCO Divider to full rate (000) */ 250 /* Select VCO Divider to full rate (000) */
215 i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1); 251 i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
216 reg &= 0x0f; 252 reg &= 0x0f;
217 reg |= 0x70; 253 reg |= 0x70;
218 i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1); 254 i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
219 255
256 #ifdef CONFIG_TARGET_LS1088AQDS
257 /* Retimer is connected to I2C1_CH5 */
258 select_i2c_ch_pca9547(I2C_MUX_CH5);
220 259
260 /* Access to Control/Shared register */
261 reg = 0x0;
262 i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
263
264 /* Read device revision and ID */
265 i2c_read(I2C_RETIMER_ADDR2, 1, 1, &reg, 1);
266 debug("Retimer version id = 0x%x\n", reg);
267
268 /* Enable Broadcast. All writes target all channel register sets */
269 reg = 0x0c;
270 i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
271
272 /* Reset Channel Registers */
273 i2c_read(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
274 reg |= 0x4;
275 i2c_write(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
276
277 /* Set data rate as 10.3125 Gbps */
278 reg = 0x90;
279 i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, &reg, 1);
280 reg = 0xb3;
281 i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, &reg, 1);
282 reg = 0x90;
283 i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, &reg, 1);
284 reg = 0xb3;
285 i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, &reg, 1);
286 reg = 0xcd;
287 i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, &reg, 1);
288
289 /* Select VCO Divider to full rate (000) */
290 i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
291 reg &= 0x0f;
292 reg |= 0x70;
293 i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
294 #endif
221 /*return the default channel*/ 295 /*return the default channel*/
222 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 296 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
223 } 297 }
224 298
225 int board_init(void) 299 int board_init(void)
226 { 300 {
227 init_final_memctl_regs(); 301 init_final_memctl_regs();
228 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET) 302 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
229 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; 303 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
230 #endif 304 #endif
231 305
232 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 306 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
233 board_retimer_init(); 307 board_retimer_init();
234 308
235 #ifdef CONFIG_ENV_IS_NOWHERE 309 #ifdef CONFIG_ENV_IS_NOWHERE
236 gd->env_addr = (ulong)&default_environment[0]; 310 gd->env_addr = (ulong)&default_environment[0];
237 #endif 311 #endif
238 312
239 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET) 313 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
240 /* invert AQR105 IRQ pins polarity */ 314 /* invert AQR105 IRQ pins polarity */
241 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK); 315 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
242 #endif 316 #endif
243 317
244 #ifdef CONFIG_FSL_LS_PPA 318 #ifdef CONFIG_FSL_LS_PPA
245 ppa_init(); 319 ppa_init();
246 #endif 320 #endif
247 return 0; 321 return 0;
248 } 322 }
249 323
250 int board_early_init_f(void) 324 int board_early_init_f(void)
251 { 325 {
252 fsl_lsch3_early_init_f(); 326 fsl_lsch3_early_init_f();
253 return 0; 327 return 0;
254 } 328 }
255 329
256 void detail_board_ddr_info(void) 330 void detail_board_ddr_info(void)
257 { 331 {
258 puts("\nDDR "); 332 puts("\nDDR ");
259 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); 333 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
260 print_ddr_info(0); 334 print_ddr_info(0);
261 } 335 }
262 336
263 #if defined(CONFIG_ARCH_MISC_INIT) 337 #if defined(CONFIG_ARCH_MISC_INIT)
264 int arch_misc_init(void) 338 int arch_misc_init(void)
265 { 339 {
266 #ifdef CONFIG_FSL_CAAM 340 #ifdef CONFIG_FSL_CAAM
267 sec_init(); 341 sec_init();
268 #endif 342 #endif
269 return 0; 343 return 0;
270 } 344 }
271 #endif 345 #endif
272 346
273 #ifdef CONFIG_FSL_MC_ENET 347 #ifdef CONFIG_FSL_MC_ENET
274 void fdt_fixup_board_enet(void *fdt) 348 void fdt_fixup_board_enet(void *fdt)
275 { 349 {
276 int offset; 350 int offset;
277 351
278 offset = fdt_path_offset(fdt, "/fsl-mc"); 352 offset = fdt_path_offset(fdt, "/fsl-mc");
279 353
280 if (offset < 0) 354 if (offset < 0)
281 offset = fdt_path_offset(fdt, "/fsl,dprc@0"); 355 offset = fdt_path_offset(fdt, "/fsl,dprc@0");
282 356
283 if (offset < 0) { 357 if (offset < 0) {
284 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", 358 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
285 __func__, offset); 359 __func__, offset);
286 return; 360 return;
287 } 361 }
288 362
289 if (get_mc_boot_status() == 0) 363 if (get_mc_boot_status() == 0)
290 fdt_status_okay(fdt, offset); 364 fdt_status_okay(fdt, offset);
291 else 365 else
292 fdt_status_fail(fdt, offset); 366 fdt_status_fail(fdt, offset);
293 } 367 }
294 #endif 368 #endif
295 369
296 #ifdef CONFIG_OF_BOARD_SETUP 370 #ifdef CONFIG_OF_BOARD_SETUP
297 int ft_board_setup(void *blob, bd_t *bd) 371 int ft_board_setup(void *blob, bd_t *bd)
298 { 372 {
299 int err, i; 373 int err, i;
300 u64 base[CONFIG_NR_DRAM_BANKS]; 374 u64 base[CONFIG_NR_DRAM_BANKS];
301 u64 size[CONFIG_NR_DRAM_BANKS]; 375 u64 size[CONFIG_NR_DRAM_BANKS];
302 376
303 ft_cpu_setup(blob, bd); 377 ft_cpu_setup(blob, bd);
304 378
305 /* fixup DT for the two GPP DDR banks */ 379 /* fixup DT for the two GPP DDR banks */
306 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 380 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
307 base[i] = gd->bd->bi_dram[i].start; 381 base[i] = gd->bd->bi_dram[i].start;
308 size[i] = gd->bd->bi_dram[i].size; 382 size[i] = gd->bd->bi_dram[i].size;
309 } 383 }
310 384
311 #ifdef CONFIG_RESV_RAM 385 #ifdef CONFIG_RESV_RAM
312 /* reduce size if reserved memory is within this bank */ 386 /* reduce size if reserved memory is within this bank */
313 if (gd->arch.resv_ram >= base[0] && 387 if (gd->arch.resv_ram >= base[0] &&
314 gd->arch.resv_ram < base[0] + size[0]) 388 gd->arch.resv_ram < base[0] + size[0])
315 size[0] = gd->arch.resv_ram - base[0]; 389 size[0] = gd->arch.resv_ram - base[0];
316 else if (gd->arch.resv_ram >= base[1] && 390 else if (gd->arch.resv_ram >= base[1] &&
317 gd->arch.resv_ram < base[1] + size[1]) 391 gd->arch.resv_ram < base[1] + size[1])
318 size[1] = gd->arch.resv_ram - base[1]; 392 size[1] = gd->arch.resv_ram - base[1];
319 #endif 393 #endif
320 394
321 fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS); 395 fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
322 396
323 #ifdef CONFIG_FSL_MC_ENET 397 #ifdef CONFIG_FSL_MC_ENET
324 fdt_fixup_board_enet(blob); 398 fdt_fixup_board_enet(blob);
325 err = fsl_mc_ldpaa_exit(bd); 399 err = fsl_mc_ldpaa_exit(bd);
326 if (err) 400 if (err)
327 return err; 401 return err;
328 #endif 402 #endif
329 403
330 return 0; 404 return 0;
331 } 405 }
board/freescale/ls1088a/ls1088a_qixis.h
Diff comments   View file @ 7769776
1 /* 1 /*
2 * Copyright 2017 NXP 2 * Copyright 2017 NXP
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #ifndef __LS1088AQDS_QIXIS_H__ 7 #ifndef __LS1088AQDS_QIXIS_H__
8 #define __LS1088AQDS_QIXIS_H__ 8 #define __LS1088AQDS_QIXIS_H__
9 9
10 /* Definitions of QIXIS Registers for LS1088AQDS */ 10 /* Definitions of QIXIS Registers for LS1088AQDS */
11 11
12 /* SYSCLK */ 12 /* SYSCLK */
13 #define QIXIS_SYSCLK_66 0x0 13 #define QIXIS_SYSCLK_66 0x0
14 #define QIXIS_SYSCLK_83 0x1 14 #define QIXIS_SYSCLK_83 0x1
15 #define QIXIS_SYSCLK_100 0x2 15 #define QIXIS_SYSCLK_100 0x2
16 #define QIXIS_SYSCLK_125 0x3 16 #define QIXIS_SYSCLK_125 0x3
17 #define QIXIS_SYSCLK_133 0x4 17 #define QIXIS_SYSCLK_133 0x4
18 #define QIXIS_SYSCLK_150 0x5 18 #define QIXIS_SYSCLK_150 0x5
19 #define QIXIS_SYSCLK_160 0x6 19 #define QIXIS_SYSCLK_160 0x6
20 #define QIXIS_SYSCLK_166 0x7 20 #define QIXIS_SYSCLK_166 0x7
21 21
22 /* DDRCLK */ 22 /* DDRCLK */
23 #define QIXIS_DDRCLK_66 0x0 23 #define QIXIS_DDRCLK_66 0x0
24 #define QIXIS_DDRCLK_100 0x1 24 #define QIXIS_DDRCLK_100 0x1
25 #define QIXIS_DDRCLK_125 0x2 25 #define QIXIS_DDRCLK_125 0x2
26 #define QIXIS_DDRCLK_133 0x3 26 #define QIXIS_DDRCLK_133 0x3
27 27
28 /* BRDCFG2 - SD clock*/ 28 /* BRDCFG2 - SD clock*/
29 #define QIXIS_SDCLK1_100 0x0 29 #define QIXIS_SDCLK1_100 0x0
30 #define QIXIS_SDCLK1_125 0x1 30 #define QIXIS_SDCLK1_125 0x1
31 #define QIXIS_SDCLK1_165 0x2 31 #define QIXIS_SDCLK1_165 0x2
32 #define QIXIS_SDCLK1_100_SP 0x3 32 #define QIXIS_SDCLK1_100_SP 0x3
33 33
34 #define BRDCFG4_EMISEL_MASK 0xE0
35 #define BRDCFG4_EMISEL_SHIFT 5
36 #define BRDCFG9_SFPTX_MASK 0x10
37 #define BRDCFG9_SFPTX_SHIFT 4
38
34 #endif 39 #endif
35 40
configs/ls1088aqds_qspi_defconfig
Diff comments   View file @ 7769776
File was created 1 CONFIG_ARM=y
2 CONFIG_TARGET_LS1088AQDS=y
3 # CONFIG_SYS_MALLOC_F is not set
4 CONFIG_DM_SPI=y
5 CONFIG_DM_SPI_FLASH=y
6 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
7 CONFIG_FIT=y
8 CONFIG_FIT_VERBOSE=y
9 CONFIG_OF_BOARD_SETUP=y
10 CONFIG_OF_STDOUT_VIA_ALIAS=y
11 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT"
12 CONFIG_HUSH_PARSER=y
13 CONFIG_CMD_MMC=y
14 CONFIG_CMD_SF=y
15 CONFIG_CMD_I2C=y
16 # CONFIG_CMD_SETEXPR is not set
17 CONFIG_CMD_DHCP=y
18 CONFIG_CMD_PING=y
19 CONFIG_OF_CONTROL=y
20 CONFIG_NET_RANDOM_ETHADDR=y
21 CONFIG_DM=y
22 CONFIG_SPI_FLASH=y
23 CONFIG_NETDEVICES=y
24 CONFIG_E1000=y
25 CONFIG_SYS_NS16550=y
26 CONFIG_FSL_DSPI=y
27 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
28 # CONFIG_DISPLAY_BOARDINFO is not set
29 CONFIG_FSL_LS_PPA=y
30
include/configs/ls1088aqds.h
Diff comments   View file @ 7769776
File was created 1 /*
2 * Copyright 2017 NXP
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #ifndef __LS1088A_QDS_H
8 #define __LS1088A_QDS_H
9
10 #include "ls1088a_common.h"
11
12
13 #define CONFIG_DISPLAY_BOARDINFO_LATE
14
15
16 #ifndef __ASSEMBLY__
17 unsigned long get_board_sys_clk(void);
18 unsigned long get_board_ddr_clk(void);
19 #endif
20
21
22 #if defined(CONFIG_QSPI_BOOT)
23 #define CONFIG_ENV_IS_IN_SPI_FLASH
24 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
25 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
26 #define CONFIG_ENV_SECT_SIZE 0x40000
27 #else
28 #define CONFIG_ENV_IS_IN_FLASH
29 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
30 #define CONFIG_ENV_SECT_SIZE 0x20000
31 #define CONFIG_ENV_SIZE 0x20000
32 #endif
33
34 #if defined(CONFIG_QSPI_BOOT)
35 #define CONFIG_QIXIS_I2C_ACCESS
36 #define SYS_NO_FLASH
37
38 #undef CONFIG_CMD_IMLS
39 #define CONFIG_SYS_CLK_FREQ 100000000
40 #define CONFIG_DDR_CLK_FREQ 100000000
41 #else
42 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
43 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
44 #endif
45
46 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
47 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
48
49 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
50
51 #define CONFIG_DDR_SPD
52 #define CONFIG_DDR_ECC
53 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
54 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
55 #define SPD_EEPROM_ADDRESS 0x51
56 #define CONFIG_SYS_SPD_BUS_NUM 0
57
58
59 /*
60 * IFC Definitions
61 */
62 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
63 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
64 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
65 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
66
67 #define CONFIG_SYS_NOR0_CSPR \
68 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
69 CSPR_PORT_SIZE_16 | \
70 CSPR_MSEL_NOR | \
71 CSPR_V)
72 #define CONFIG_SYS_NOR0_CSPR_EARLY \
73 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
74 CSPR_PORT_SIZE_16 | \
75 CSPR_MSEL_NOR | \
76 CSPR_V)
77 #define CONFIG_SYS_NOR1_CSPR \
78 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
79 CSPR_PORT_SIZE_16 | \
80 CSPR_MSEL_NOR | \
81 CSPR_V)
82 #define CONFIG_SYS_NOR1_CSPR_EARLY \
83 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
84 CSPR_PORT_SIZE_16 | \
85 CSPR_MSEL_NOR | \
86 CSPR_V)
87 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
88 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
89 FTIM0_NOR_TEADC(0x5) | \
90 FTIM0_NOR_TEAHC(0x5))
91 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
92 FTIM1_NOR_TRAD_NOR(0x1a) |\
93 FTIM1_NOR_TSEQRAD_NOR(0x13))
94 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
95 FTIM2_NOR_TCH(0x4) | \
96 FTIM2_NOR_TWPH(0x0E) | \
97 FTIM2_NOR_TWP(0x1c))
98 #define CONFIG_SYS_NOR_FTIM3 0x04000000
99 #define CONFIG_SYS_IFC_CCR 0x01000000
100
101 #ifndef SYS_NO_FLASH
102 #define CONFIG_FLASH_CFI_DRIVER
103 #define CONFIG_SYS_FLASH_CFI
104 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
105 #define CONFIG_SYS_FLASH_QUIET_TEST
106 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
107
108 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
109 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
110 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
111 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
112
113 #define CONFIG_SYS_FLASH_EMPTY_INFO
114 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
115 CONFIG_SYS_FLASH_BASE + 0x40000000}
116 #endif
117 #endif
118
119 #define CONFIG_NAND_FSL_IFC
120 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
121 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
122
123 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
124 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
125 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
126 | CSPR_MSEL_NAND /* MSEL = NAND */ \
127 | CSPR_V)
128 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
129
130 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
131 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
132 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
133 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
134 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
135 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
136 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
137
138 #define CONFIG_SYS_NAND_ONFI_DETECTION
139
140 /* ONFI NAND Flash mode0 Timing Params */
141 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
142 FTIM0_NAND_TWP(0x18) | \
143 FTIM0_NAND_TWCHT(0x07) | \
144 FTIM0_NAND_TWH(0x0a))
145 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
146 FTIM1_NAND_TWBE(0x39) | \
147 FTIM1_NAND_TRR(0x0e) | \
148 FTIM1_NAND_TRP(0x18))
149 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
150 FTIM2_NAND_TREH(0x0a) | \
151 FTIM2_NAND_TWHRE(0x1e))
152 #define CONFIG_SYS_NAND_FTIM3 0x0
153
154 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
155 #define CONFIG_SYS_MAX_NAND_DEVICE 1
156 #define CONFIG_MTD_NAND_VERIFY_WRITE
157 #define CONFIG_CMD_NAND
158
159 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
160
161 #define CONFIG_FSL_QIXIS
162 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
163 #define QIXIS_LBMAP_SWITCH 6
164 #define QIXIS_QMAP_MASK 0xe0
165 #define QIXIS_QMAP_SHIFT 5
166 #define QIXIS_LBMAP_MASK 0x0f
167 #define QIXIS_LBMAP_SHIFT 0
168 #define QIXIS_LBMAP_DFLTBANK 0x0e
169 #define QIXIS_LBMAP_ALTBANK 0x2e
170 #define QIXIS_LBMAP_SD 0x00
171 #define QIXIS_LBMAP_SD_QSPI 0x0e
172 #define QIXIS_LBMAP_QSPI 0x0e
173 #define QIXIS_RCW_SRC_SD 0x40
174 #define QIXIS_RCW_SRC_QSPI 0x62
175 #define QIXIS_RST_CTL_RESET 0x41
176 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
177 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
178 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
179 #define QIXIS_RST_FORCE_MEM 0x01
180 #define QIXIS_STAT_PRES1 0xb
181 #define QIXIS_SDID_MASK 0x07
182 #define QIXIS_ESDHC_NO_ADAPTER 0x7
183
184 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
185 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
186 | CSPR_PORT_SIZE_8 \
187 | CSPR_MSEL_GPCM \
188 | CSPR_V)
189 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
190 | CSPR_PORT_SIZE_8 \
191 | CSPR_MSEL_GPCM \
192 | CSPR_V)
193
194 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024)
195 #if defined(CONFIG_QSPI_BOOT)
196 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
197 #else
198 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12)
199 #endif
200 /* QIXIS Timing parameters*/
201 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
202 FTIM0_GPCM_TEADC(0x0e) | \
203 FTIM0_GPCM_TEAHC(0x0e))
204 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
205 FTIM1_GPCM_TRAD(0x3f))
206 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
207 FTIM2_GPCM_TCH(0xf) | \
208 FTIM2_GPCM_TWP(0x3E))
209 #define SYS_FPGA_CS_FTIM3 0x0
210
211 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
212 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
213 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
214 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
215 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
216 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
217 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
218 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
219 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
220 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
221 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
222 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
223 #define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK
224 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
225 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
226 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
227 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
228 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
229 #else
230 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
231 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
232 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
233 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
234 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
235 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
236 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
237 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
238 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
239 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
240 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
241 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
242 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
243 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
244 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
245 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
246 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
247 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
248 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
249 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
250 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
251 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
252 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
253 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
254 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
255 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
256 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
257 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
258 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
259 #define CONFIG_SYS_CSPR3_FINAL CONFIG_SYS_FPGA_CSPR_FINAL
260 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
261 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
262 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_CS_FTIM0
263 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_CS_FTIM1
264 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_CS_FTIM2
265 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_CS_FTIM3
266 #endif
267
268 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
269
270 /*
271 * I2C bus multiplexer
272 */
273 #define I2C_MUX_PCA_ADDR_PRI 0x77
274 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
275 #define I2C_RETIMER_ADDR 0x18
276 #define I2C_RETIMER_ADDR2 0x19
277 #define I2C_MUX_CH_DEFAULT 0x8
278 #define I2C_MUX_CH5 0xD
279
280 /*
281 * RTC configuration
282 */
283 #define RTC
284 #define CONFIG_RTC_PCF8563 1
285 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
286 #define CONFIG_CMD_DATE
287
288 /* EEPROM */
289 #define CONFIG_ID_EEPROM
290 #define CONFIG_SYS_I2C_EEPROM_NXID
291 #define CONFIG_SYS_EEPROM_BUS_NUM 0
292 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
293 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
294 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
295 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
296
297 /* QSPI device */
298 #if defined(CONFIG_QSPI_BOOT)
299 #define CONFIG_FSL_QSPI
300 #define CONFIG_SPI_FLASH_SPANSION
301 #define FSL_QSPI_FLASH_SIZE (1 << 26)
302 #define FSL_QSPI_FLASH_NUM 2
303
304 #endif
305
306 #ifdef CONFIG_FSL_DSPI
307 #define CONFIG_SPI_FLASH_STMICRO
308 #define CONFIG_SPI_FLASH_SST
309 #define CONFIG_SPI_FLASH_EON
310 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
311 #define CONFIG_SF_DEFAULT_BUS 1
312 #define CONFIG_SF_DEFAULT_CS 0
313 #endif
314 #endif
315
316 #define CONFIG_CMD_MEMINFO
317 #define CONFIG_CMD_MEMTEST
318 #define CONFIG_SYS_MEMTEST_START 0x80000000
319 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
320
321 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
322
323 #define CONFIG_FSL_MEMAC
324
325 /* MMC */
326 #define CONFIG_FSL_ESDHC
327 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
328 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
329 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
330
331 /* Initial environment variables */
332 #if defined(CONFIG_QSPI_BOOT)
333 #undef CONFIG_EXTRA_ENV_SETTINGS
334 #define CONFIG_EXTRA_ENV_SETTINGS \
335 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
336 "loadaddr=0x90100000\0" \
337 "kernel_addr=0x100000\0" \
338 "ramdisk_addr=0x800000\0" \
339 "ramdisk_size=0x2000000\0" \
340 "fdt_high=0xa0000000\0" \
341 "initrd_high=0xffffffffffffffff\0" \
342 "kernel_start=0x1000000\0" \
343 "kernel_load=0xa0000000\0" \
344 "kernel_size=0x2800000\0" \
345 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
346 "sf read 0x80100000 0xE00000 0x100000;" \
347 "fsl_mc start mc 0x80000000 0x80100000\0" \
348 "mcmemsize=0x70000000 \0"
349 #else /* NOR BOOT */
350 #undef CONFIG_EXTRA_ENV_SETTINGS
351 #define CONFIG_EXTRA_ENV_SETTINGS \
352 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
353 "loadaddr=0x90100000\0" \
354 "kernel_addr=0x100000\0" \
355 "ramdisk_addr=0x800000\0" \
356 "ramdisk_size=0x2000000\0" \
357 "fdt_high=0xa0000000\0" \
358 "initrd_high=0xffffffffffffffff\0" \
359 "kernel_start=0x1000000\0" \
360 "kernel_load=0xa0000000\0" \
361 "kernel_size=0x2800000\0" \
362 "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \
363 "mcmemsize=0x70000000 \0"
364 #endif
365
366 #ifdef CONFIG_FSL_MC_ENET
367 #define CONFIG_FSL_MEMAC
368 #define CONFIG_PHYLIB
369 #define CONFIG_PHYLIB_10G
370 #define CONFIG_PHY_VITESSE
371 #define CONFIG_PHY_REALTEK
372 #define CONFIG_PHY_TERANETICS
373 #define RGMII_PHY1_ADDR 0x1
374 #define RGMII_PHY2_ADDR 0x2
375 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
376 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
377 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
378 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
379
380 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
381 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
382 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
383 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
384 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
385 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
386 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
387 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
388 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
389 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
390 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
391 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
392 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
393 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
394 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
395 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
396
397 #define CONFIG_MII /* MII PHY management */
398 #define CONFIG_ETHPRIME "DPMAC1@xgmii"
399 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
400
401 #endif
402
403 #undef CONFIG_CMDLINE_EDITING
404 #include <config_distro_defaults.h>
405 #define BOOT_TARGET_DEVICES(func) \
406 func(USB, usb, 0) \
407 func(MMC, mmc, 0) \
408 func(SCSI, scsi, 0) \
409 func(DHCP, dhcp, na)
410 #include <config_distro_bootcmd.h>
411
412 #include <asm/fsl_secure_boot.h>
413
414 #endif /* __LS1088A_QDS_H */
415