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Commit 7769776a603f76ab1b7c1478f6cf8388b3cb5464

Authored by Ashish Kumar
Committed by York Sun
1 parent e84a324ba7
Exists in smarc_8mq_lf_v2020.04 and in 20 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf-6.6.52-2.2.0, emb_lf_v2022.04, emb_lf_v2023.04, emb_lf_v2024.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

armv8: ls1088aqds: Add support of LS1088AQDS 

This patch add support of LS1088AQDS platform.

The LS1088A QorIQTM Development System (QDS) is a high-performance
computing, evaluation, and development platform that supports the
LS1088A QorIQ Architecture processor.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

Showing 14 changed files with 1372 additions and 7 deletions Side-by-side Diff

... ... @@ -808,6 +808,19 @@
808 808 development platform that supports the QorIQ LS2080A
809 809 Layerscape Architecture processor.
810 810  
  811 +config TARGET_LS1088AQDS
  812 + bool "Support ls1088aqds"
  813 + select ARCH_LS1088A
  814 + select ARM64
  815 + select ARMV8_MULTIENTRY
  816 + select ARCH_MISC_INIT
  817 + select BOARD_LATE_INIT
  818 + help
  819 + Support for NXP LS1088AQDS platform
  820 + The LS1088A Development System (QDS) is a high-performance
  821 + development platform that supports the QorIQ LS1088A
  822 + Layerscape Architecture processor.
  823 +
811 824 config TARGET_LS2080AQDS
812 825 bool "Support ls2080aqds"
813 826 select ARCH_LS2080A
arch/arm/cpu/armv8/Kconfig
Diff comments   View file @ 7769776
... ... @@ -88,7 +88,7 @@
88 88 depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && !TARGET_LS2080A_EMU && \
89 89 !TARGET_LS2080A_SIMU && !TARGET_LS2080AQDS && \
90 90 !TARGET_LS2080ARDB && !TARGET_LS1012AQDS && \
91   - !TARGET_LS1088ARDB && \
  91 + !TARGET_LS1088ARDB && !TARGET_LS1088AQDS && \
92 92 !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
93 93 !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
94 94 !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
arch/arm/dts/Makefile
Diff comments   View file @ 7769776
... ... @@ -188,7 +188,8 @@
188 188 fsl-ls2080a-rdb.dtb \
189 189 fsl-ls2081a-rdb.dtb \
190 190 fsl-ls2088a-rdb-qspi.dtb \
191   - fsl-ls1088a-rdb.dtb
  191 + fsl-ls1088a-rdb.dtb \
  192 + fsl-ls1088a-qds.dtb
192 193 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
193 194 fsl-ls1043a-qds-lpuart.dtb \
194 195 fsl-ls1043a-rdb.dtb \
arch/arm/dts/fsl-ls1088a-qds.dts
Diff comments   View file @ 7769776
  1 +/*
  2 + * NXP ls1088a QDS board device tree source
  3 + *
  4 + * Copyright 2017 NXP
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +/dts-v1/;
  10 +
  11 +#include "fsl-ls1088a.dtsi"
  12 +
  13 +/ {
  14 + model = "NXP Layerscape 1088a QDS Board";
  15 + compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
  16 + aliases {
  17 + spi0 = &qspi;
  18 + spi1 = &dspi;
  19 + };
  20 +};
  21 +
  22 +&dspi {
  23 + bus-num = <0>;
  24 + status = "okay";
  25 +
  26 + dflash0: n25q128a {
  27 + #address-cells = <1>;
  28 + #size-cells = <1>;
  29 + compatible = "spi-flash";
  30 + reg = <0>;
  31 + spi-max-frequency = <1000000>; /* input clock */
  32 + };
  33 +
  34 + dflash1: sst25wf040b {
  35 + #address-cells = <1>;
  36 + #size-cells = <1>;
  37 + compatible = "spi-flash";
  38 + spi-max-frequency = <3500000>;
  39 + reg = <1>;
  40 + };
  41 +
  42 + dflash2: en25s64 {
  43 + #address-cells = <1>;
  44 + #size-cells = <1>;
  45 + compatible = "spi-flash";
  46 + spi-max-frequency = <3500000>;
  47 + reg = <2>;
  48 + };
  49 +};
  50 +
  51 +&qspi {
  52 + bus-num = <0>;
  53 + status = "okay";
  54 +
  55 + qflash0: s25fs512s@0 {
  56 + #address-cells = <1>;
  57 + #size-cells = <1>;
  58 + compatible = "spi-flash";
  59 + spi-max-frequency = <50000000>;
  60 + reg = <0>;
  61 + };
  62 +
  63 + qflash1: s25fs512s@1 {
  64 + #address-cells = <1>;
  65 + #size-cells = <1>;
  66 + compatible = "spi-flash";
  67 + spi-max-frequency = <50000000>;
  68 + reg = <1>;
  69 + };
  70 +};
board/freescale/ls1088a/Kconfig
Diff comments   View file @ 7769776
  1 +if TARGET_LS1088AQDS
  2 +
  3 +config SYS_BOARD
  4 + default "ls1088a"
  5 +
  6 +config SYS_VENDOR
  7 + default "freescale"
  8 +
  9 +config SYS_SOC
  10 + default "fsl-layerscape"
  11 +
  12 +config SYS_CONFIG_NAME
  13 + default "ls1088aqds"
  14 +
  15 +endif
  16 +
1 17 if TARGET_LS1088ARDB
2 18  
3 19 config SYS_BOARD
board/freescale/ls1088a/MAINTAINERS
Diff comments   View file @ 7769776
... ... @@ -5,4 +5,12 @@
5 5 F: board/freescale/ls1088a/
6 6 F: include/configs/ls1088ardb.h
7 7 F: configs/ls1088ardb_qspi_defconfig
  8 +
  9 +LS1088AQDS BOARD
  10 +M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
  11 +M: Ashish Kumar <Ashish.Kumar@nxp.com>
  12 +S: Maintained
  13 +F: board/freescale/ls1088a/
  14 +F: include/configs/ls1088aqds.h
  15 +F: configs/ls1088aqds_qspi_defconfig
board/freescale/ls1088a/Makefile
Diff comments   View file @ 7769776
... ... @@ -6,5 +6,6 @@
6 6  
7 7 obj-y += ls1088a.o
8 8 obj-$(CONFIG_TARGET_LS1088ARDB) += eth_ls1088ardb.o
  9 +obj-$(CONFIG_TARGET_LS1088AQDS) += eth_ls1088aqds.o
9 10 obj-y += ddr.o
board/freescale/ls1088a/README
Diff comments   View file @ 7769776
... ... @@ -64,4 +64,83 @@
64 64 - JTAG support
65 65 - QSPI emulator support
66 66 - TDM riser support
  67 +
  68 +QDS Default Switch Settings (1: ON; 0: OFF)
  69 +-------------------------------------------
  70 +
  71 +For 16b IFC-NOR
  72 +SW1 0001 0010
  73 +SW2 x110 1111
  74 +
  75 +For QSPI Boot
  76 +SW1 0011 0001
  77 +SW2 0110 1111
  78 +
  79 +For SD Boot
  80 +SW1 0010 0000
  81 +SW2 0110 1111
  82 +
  83 +For eMMC Boot
  84 +SW1 0010 0000
  85 +SW2 1110 1111
  86 +
  87 +For I2C (ext. addr.)
  88 +SW1 0010 0100
  89 +SW2 1110 1111
  90 +
  91 +SW3 to SW12 are identical for all boot source
  92 +
  93 +SW3 0010 0100
  94 +SW4 0010 0000
  95 +SW5 1110 0111
  96 +SW6 1110 1000
  97 +SW7 0001 1101
  98 +SW8 0000 1101
  99 +SW9 1100 1010
  100 +SW10 1110 1000
  101 +SW11 1111 0100
  102 +SW12 1111 1111
  103 +
  104 + LS1088AQDS board Overview
  105 + -------------------------
  106 + - SERDES Connections, 16 lanes supporting:
  107 + - PCI Express - 3.0
  108 + - SATA 3.0
  109 + - 2 XFI
  110 + - QSGMII, SGMII with help for Riser card
  111 + - 2 RGMII
  112 + - 5 slot for Riser card or PCIe NIC
  113 + - DDR Controller
  114 + - One ports of 72-bits (8-bits ECC, 64-bits DATA) DDR4. Each port supports four
  115 + chip-selects on one DIMM connector. Support is up to 2133MT/s, Although MAX default
  116 + with FSL refernce software is 2100MT/s
  117 + - 2 QSPI-NOR Spansion(S25FS512SDSMFI011) flash of size 64MB
  118 + - IFC/Local Bus
  119 + - One 2 GB NAND flash with ECC support, not as boot source
  120 + - CPLD of size 2K
  121 + - USB 3.0
  122 + - Two high speed USB 3.0 ports
  123 + - First USB 3.0 port configured as Host with Type-A connector
  124 + - Second USB 3.0 port configured as OTG with micro-AB connector
  125 + - SDHC/eMMC
  126 + - SDHC/eMMC slot via adaptor
  127 + - 4 I2C controllers
  128 + - Two SATA onboard connectors
  129 + - 2 UART
  130 + - JTAG support
  131 + - DSPI
  132 + - PROMJET support
  133 + - QSPI emulator support
  134 + - TDM riser support
  135 +
  136 +QSPI flash memory map valid for both QDS and RDB
  137 + Image Flash Offset
  138 + RCW+PBI 0x00000000
  139 + Boot firmware (U-Boot) 0x00100000
  140 + Boot firmware Environment 0x00300000
  141 + PPA firmware 0x00400000
  142 + DPAA2 MC 0x00A00000
  143 + DPAA2 DPL 0x00D00000
  144 + DPAA2 DPC 0x00E00000
  145 + Kernel.itb 0x01000000
board/freescale/ls1088a/ddr.h
Diff comments   View file @ 7769776
... ... @@ -34,6 +34,11 @@
34 34 {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
35 35 {2, 2300, 0, 8, 9, 0x0A0C0E11, 0x1214160F,},
36 36 {}
  37 +#elif defined(CONFIG_TARGET_LS1088AQDS)
  38 + {2, 1666, 0, 8, 8, 0x0A0A0C0E, 0x0F10110C,},
  39 + {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
  40 + {2, 2300, 0, 4, 9, 0x0A0C0D11, 0x1214150E,},
  41 + {}
37 42  
38 43 #endif
39 44 };
board/freescale/ls1088a/eth_ls1088aqds.c
Diff comments   View file @ 7769776
  1 +/*
  2 + * Copyright 2017 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <netdev.h>
  9 +#include <asm/io.h>
  10 +#include <asm/arch/fsl_serdes.h>
  11 +#include <hwconfig.h>
  12 +#include <fsl_mdio.h>
  13 +#include <malloc.h>
  14 +#include <fm_eth.h>
  15 +#include <i2c.h>
  16 +#include <miiphy.h>
  17 +#include <fsl-mc/ldpaa_wriop.h>
  18 +
  19 +#include "../common/qixis.h"
  20 +
  21 +#include "ls1088a_qixis.h"
  22 +
  23 +#define MC_BOOT_ENV_VAR "mcinitcmd"
  24 +
  25 +#ifdef CONFIG_FSL_MC_ENET
  26 +
  27 +#define SFP_TX 0
  28 +
  29 + /* - In LS1088A A there are only 16 SERDES lanes, spread across 2 SERDES banks.
  30 + * Bank 1 -> Lanes A, B, C, D,
  31 + * Bank 2 -> Lanes A,B, C, D,
  32 + */
  33 +
  34 + /* Mapping of 8 SERDES lanes to LS1088A QDS board slots. A value of '0' here
  35 + * means that the mapping must be determined dynamically, or that the lane
  36 + * maps to something other than a board slot.
  37 + */
  38 +
  39 +static u8 lane_to_slot_fsm1[] = {
  40 + 0, 0, 0, 0, 0, 0, 0, 0
  41 +};
  42 +
  43 +/* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
  44 + * housed.
  45 + */
  46 +
  47 +static int xqsgii_riser_phy_addr[] = {
  48 + XQSGMII_CARD_PHY1_PORT0_ADDR,
  49 + XQSGMII_CARD_PHY2_PORT0_ADDR,
  50 + XQSGMII_CARD_PHY3_PORT0_ADDR,
  51 + XQSGMII_CARD_PHY4_PORT0_ADDR,
  52 + XQSGMII_CARD_PHY3_PORT2_ADDR,
  53 + XQSGMII_CARD_PHY1_PORT2_ADDR,
  54 + XQSGMII_CARD_PHY4_PORT2_ADDR,
  55 + XQSGMII_CARD_PHY2_PORT2_ADDR,
  56 +};
  57 +
  58 +static int sgmii_riser_phy_addr[] = {
  59 + SGMII_CARD_PORT1_PHY_ADDR,
  60 + SGMII_CARD_PORT2_PHY_ADDR,
  61 + SGMII_CARD_PORT3_PHY_ADDR,
  62 + SGMII_CARD_PORT4_PHY_ADDR,
  63 +};
  64 +
  65 +/* Slot2 does not have EMI connections */
  66 +#define EMI_NONE 0xFF
  67 +#define EMI1_RGMII1 0
  68 +#define EMI1_RGMII2 1
  69 +#define EMI1_SLOT1 2
  70 +
  71 +static const char * const mdio_names[] = {
  72 + "LS1088A_QDS_MDIO0",
  73 + "LS1088A_QDS_MDIO1",
  74 + "LS1088A_QDS_MDIO2",
  75 + DEFAULT_WRIOP_MDIO2_NAME,
  76 +};
  77 +
  78 +struct ls1088a_qds_mdio {
  79 + u8 muxval;
  80 + struct mii_dev *realbus;
  81 +};
  82 +
  83 +static void sgmii_configure_repeater(int dpmac)
  84 +{
  85 + struct mii_dev *bus;
  86 + uint8_t a = 0xf;
  87 + int i, j, ret;
  88 + unsigned short value;
  89 + const char *dev = "LS1088A_QDS_MDIO2";
  90 + int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
  91 + int i2c_phy_addr = 0;
  92 + int phy_addr = 0;
  93 +
  94 + uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
  95 + uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
  96 + uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
  97 + uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
  98 +
  99 + /* Set I2c to Slot 1 */
  100 + i2c_write(0x77, 0, 0, &a, 1);
  101 +
  102 + switch (dpmac) {
  103 + case 1:
  104 + i2c_phy_addr = i2c_addr[1];
  105 + phy_addr = 4;
  106 + break;
  107 + case 2:
  108 + i2c_phy_addr = i2c_addr[0];
  109 + phy_addr = 0;
  110 + break;
  111 + case 3:
  112 + i2c_phy_addr = i2c_addr[3];
  113 + phy_addr = 0xc;
  114 + break;
  115 + case 7:
  116 + i2c_phy_addr = i2c_addr[2];
  117 + phy_addr = 8;
  118 + break;
  119 + }
  120 +
  121 + /* Check the PHY status */
  122 + ret = miiphy_set_current_dev(dev);
  123 + if (ret > 0)
  124 + goto error;
  125 +
  126 + bus = mdio_get_current_dev();
  127 + debug("Reading from bus %s\n", bus->name);
  128 +
  129 + ret = miiphy_write(dev, phy_addr, 0x1f, 3);
  130 + if (ret > 0)
  131 + goto error;
  132 +
  133 + mdelay(10);
  134 + ret = miiphy_read(dev, phy_addr, 0x11, &value);
  135 + if (ret > 0)
  136 + goto error;
  137 +
  138 + mdelay(10);
  139 +
  140 + if ((value & 0xfff) == 0x401) {
  141 + miiphy_write(dev, phy_addr, 0x1f, 0);
  142 + printf("DPMAC %d:PHY is ..... Configured\n", dpmac);
  143 + return;
  144 + }
  145 +
  146 + for (i = 0; i < 4; i++) {
  147 + for (j = 0; j < 4; j++) {
  148 + a = 0x18;
  149 + i2c_write(i2c_phy_addr, 6, 1, &a, 1);
  150 + a = 0x38;
  151 + i2c_write(i2c_phy_addr, 4, 1, &a, 1);
  152 + a = 0x4;
  153 + i2c_write(i2c_phy_addr, 8, 1, &a, 1);
  154 +
  155 + i2c_write(i2c_phy_addr, 0xf, 1,
  156 + &ch_a_eq[i], 1);
  157 + i2c_write(i2c_phy_addr, 0x11, 1,
  158 + &ch_a_ctl2[j], 1);
  159 +
  160 + i2c_write(i2c_phy_addr, 0x16, 1,
  161 + &ch_b_eq[i], 1);
  162 + i2c_write(i2c_phy_addr, 0x18, 1,
  163 + &ch_b_ctl2[j], 1);
  164 +
  165 + a = 0x14;
  166 + i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
  167 + a = 0xb5;
  168 + i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
  169 + a = 0x20;
  170 + i2c_write(i2c_phy_addr, 4, 1, &a, 1);
  171 + mdelay(100);
  172 + ret = miiphy_read(dev, phy_addr, 0x11, &value);
  173 + if (ret > 0)
  174 + goto error;
  175 +
  176 + mdelay(100);
  177 + ret = miiphy_read(dev, phy_addr, 0x11, &value);
  178 + if (ret > 0)
  179 + goto error;
  180 +
  181 + if ((value & 0xfff) == 0x401) {
  182 + printf("DPMAC %d :PHY is configured ",
  183 + dpmac);
  184 + printf("after setting repeater 0x%x\n",
  185 + value);
  186 + i = 5;
  187 + j = 5;
  188 + } else {
  189 + printf("DPMAC %d :PHY is failed to ",
  190 + dpmac);
  191 + printf("configure the repeater 0x%x\n", value);
  192 + }
  193 + }
  194 + }
  195 + miiphy_write(dev, phy_addr, 0x1f, 0);
  196 +error:
  197 + if (ret)
  198 + printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac);
  199 + return;
  200 +}
  201 +
  202 +static void qsgmii_configure_repeater(int dpmac)
  203 +{
  204 + uint8_t a = 0xf;
  205 + int i, j;
  206 + int i2c_phy_addr = 0;
  207 + int phy_addr = 0;
  208 + int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
  209 +
  210 + uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
  211 + uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
  212 + uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
  213 + uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
  214 +
  215 + const char *dev = mdio_names[EMI1_SLOT1];
  216 + int ret = 0;
  217 + unsigned short value;
  218 +
  219 + /* Set I2c to Slot 1 */
  220 + i2c_write(0x77, 0, 0, &a, 1);
  221 +
  222 + switch (dpmac) {
  223 + case 7:
  224 + case 8:
  225 + case 9:
  226 + case 10:
  227 + i2c_phy_addr = i2c_addr[2];
  228 + phy_addr = 8;
  229 + break;
  230 +
  231 + case 3:
  232 + case 4:
  233 + case 5:
  234 + case 6:
  235 + i2c_phy_addr = i2c_addr[3];
  236 + phy_addr = 0xc;
  237 + break;
  238 + }
  239 +
  240 + /* Check the PHY status */
  241 + ret = miiphy_set_current_dev(dev);
  242 + ret = miiphy_write(dev, phy_addr, 0x1f, 3);
  243 + mdelay(10);
  244 + ret = miiphy_read(dev, phy_addr, 0x11, &value);
  245 + mdelay(10);
  246 + ret = miiphy_read(dev, phy_addr, 0x11, &value);
  247 + mdelay(10);
  248 + if ((value & 0xf) == 0xf) {
  249 + miiphy_write(dev, phy_addr, 0x1f, 0);
  250 + printf("DPMAC %d :PHY is ..... Configured\n", dpmac);
  251 + return;
  252 + }
  253 +
  254 + for (i = 0; i < 4; i++) {
  255 + for (j = 0; j < 4; j++) {
  256 + a = 0x18;
  257 + i2c_write(i2c_phy_addr, 6, 1, &a, 1);
  258 + a = 0x38;
  259 + i2c_write(i2c_phy_addr, 4, 1, &a, 1);
  260 + a = 0x4;
  261 + i2c_write(i2c_phy_addr, 8, 1, &a, 1);
  262 +
  263 + i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1);
  264 + i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1);
  265 +
  266 + i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1);
  267 + i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1);
  268 +
  269 + a = 0x14;
  270 + i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
  271 + a = 0xb5;
  272 + i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
  273 + a = 0x20;
  274 + i2c_write(i2c_phy_addr, 4, 1, &a, 1);
  275 + mdelay(100);
  276 + ret = miiphy_read(dev, phy_addr, 0x11, &value);
  277 + if (ret > 0)
  278 + goto error;
  279 + mdelay(1);
  280 + ret = miiphy_read(dev, phy_addr, 0x11, &value);
  281 + if (ret > 0)
  282 + goto error;
  283 + mdelay(10);
  284 + if ((value & 0xf) == 0xf) {
  285 + miiphy_write(dev, phy_addr, 0x1f, 0);
  286 + printf("DPMAC %d :PHY is ..... Configured\n",
  287 + dpmac);
  288 + return;
  289 + }
  290 + }
  291 + }
  292 +error:
  293 + printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac);
  294 + return;
  295 +}
  296 +
  297 +static const char *ls1088a_qds_mdio_name_for_muxval(u8 muxval)
  298 +{
  299 + return mdio_names[muxval];
  300 +}
  301 +
  302 +struct mii_dev *mii_dev_for_muxval(u8 muxval)
  303 +{
  304 + struct mii_dev *bus;
  305 + const char *name = ls1088a_qds_mdio_name_for_muxval(muxval);
  306 +
  307 + if (!name) {
  308 + printf("No bus for muxval %x\n", muxval);
  309 + return NULL;
  310 + }
  311 +
  312 + bus = miiphy_get_dev_by_name(name);
  313 +
  314 + if (!bus) {
  315 + printf("No bus by name %s\n", name);
  316 + return NULL;
  317 + }
  318 +
  319 + return bus;
  320 +}
  321 +
  322 +static void ls1088a_qds_enable_SFP_TX(u8 muxval)
  323 +{
  324 + u8 brdcfg9;
  325 +
  326 + brdcfg9 = QIXIS_READ(brdcfg[9]);
  327 + brdcfg9 &= ~BRDCFG9_SFPTX_MASK;
  328 + brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT);
  329 + QIXIS_WRITE(brdcfg[9], brdcfg9);
  330 +}
  331 +
  332 +static void ls1088a_qds_mux_mdio(u8 muxval)
  333 +{
  334 + u8 brdcfg4;
  335 +
  336 + if (muxval <= 5) {
  337 + brdcfg4 = QIXIS_READ(brdcfg[4]);
  338 + brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
  339 + brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
  340 + QIXIS_WRITE(brdcfg[4], brdcfg4);
  341 + }
  342 +}
  343 +
  344 +static int ls1088a_qds_mdio_read(struct mii_dev *bus, int addr,
  345 + int devad, int regnum)
  346 +{
  347 + struct ls1088a_qds_mdio *priv = bus->priv;
  348 +
  349 + ls1088a_qds_mux_mdio(priv->muxval);
  350 +
  351 + return priv->realbus->read(priv->realbus, addr, devad, regnum);
  352 +}
  353 +
  354 +static int ls1088a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
  355 + int regnum, u16 value)
  356 +{
  357 + struct ls1088a_qds_mdio *priv = bus->priv;
  358 +
  359 + ls1088a_qds_mux_mdio(priv->muxval);
  360 +
  361 + return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
  362 +}
  363 +
  364 +static int ls1088a_qds_mdio_reset(struct mii_dev *bus)
  365 +{
  366 + struct ls1088a_qds_mdio *priv = bus->priv;
  367 +
  368 + return priv->realbus->reset(priv->realbus);
  369 +}
  370 +
  371 +static int ls1088a_qds_mdio_init(char *realbusname, u8 muxval)
  372 +{
  373 + struct ls1088a_qds_mdio *pmdio;
  374 + struct mii_dev *bus = mdio_alloc();
  375 +
  376 + if (!bus) {
  377 + printf("Failed to allocate ls1088a_qds MDIO bus\n");
  378 + return -1;
  379 + }
  380 +
  381 + pmdio = malloc(sizeof(*pmdio));
  382 + if (!pmdio) {
  383 + printf("Failed to allocate ls1088a_qds private data\n");
  384 + free(bus);
  385 + return -1;
  386 + }
  387 +
  388 + bus->read = ls1088a_qds_mdio_read;
  389 + bus->write = ls1088a_qds_mdio_write;
  390 + bus->reset = ls1088a_qds_mdio_reset;
  391 + sprintf(bus->name, ls1088a_qds_mdio_name_for_muxval(muxval));
  392 +
  393 + pmdio->realbus = miiphy_get_dev_by_name(realbusname);
  394 +
  395 + if (!pmdio->realbus) {
  396 + printf("No bus with name %s\n", realbusname);
  397 + free(bus);
  398 + free(pmdio);
  399 + return -1;
  400 + }
  401 +
  402 + pmdio->muxval = muxval;
  403 + bus->priv = pmdio;
  404 +
  405 + return mdio_register(bus);
  406 +}
  407 +
  408 +/*
  409 + * Initialize the dpmac_info array.
  410 + *
  411 + */
  412 +static void initialize_dpmac_to_slot(void)
  413 +{
  414 + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  415 + u32 serdes1_prtcl, cfg;
  416 +
  417 + cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
  418 + FSL_CHASSIS3_SRDS1_PRTCL_MASK;
  419 + cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
  420 + serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
  421 +
  422 + switch (serdes1_prtcl) {
  423 + case 0x12:
  424 + printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
  425 + serdes1_prtcl);
  426 + lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
  427 + lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
  428 + lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
  429 + lane_to_slot_fsm1[3] = EMI1_SLOT1 - 1;
  430 + break;
  431 + case 0x15:
  432 + case 0x1D:
  433 + printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
  434 + serdes1_prtcl);
  435 + lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
  436 + lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
  437 + lane_to_slot_fsm1[2] = EMI_NONE;
  438 + lane_to_slot_fsm1[3] = EMI_NONE;
  439 + break;
  440 + case 0x1E:
  441 + printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
  442 + serdes1_prtcl);
  443 + lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
  444 + lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
  445 + lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
  446 + lane_to_slot_fsm1[3] = EMI_NONE;
  447 + break;
  448 + case 0x3A:
  449 + printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
  450 + serdes1_prtcl);
  451 + lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
  452 + lane_to_slot_fsm1[1] = EMI_NONE;
  453 + lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
  454 + lane_to_slot_fsm1[3] = EMI1_SLOT1 - 1;
  455 + break;
  456 +
  457 + default:
  458 + printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
  459 + __func__, serdes1_prtcl);
  460 + break;
  461 + }
  462 +}
  463 +
  464 +void ls1088a_handle_phy_interface_sgmii(int dpmac_id)
  465 +{
  466 + struct mii_dev *bus;
  467 + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  468 + u32 serdes1_prtcl, cfg;
  469 +
  470 + cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
  471 + FSL_CHASSIS3_SRDS1_PRTCL_MASK;
  472 + cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
  473 + serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
  474 +
  475 + int *riser_phy_addr;
  476 + char *env_hwconfig = env_get("hwconfig");
  477 +
  478 + if (hwconfig_f("xqsgmii", env_hwconfig))
  479 + riser_phy_addr = &xqsgii_riser_phy_addr[0];
  480 + else
  481 + riser_phy_addr = &sgmii_riser_phy_addr[0];
  482 +
  483 + switch (serdes1_prtcl) {
  484 + case 0x12:
  485 + case 0x15:
  486 + case 0x1E:
  487 + case 0x3A:
  488 + switch (dpmac_id) {
  489 + case 1:
  490 + wriop_set_phy_address(dpmac_id, riser_phy_addr[1]);
  491 + break;
  492 + case 2:
  493 + wriop_set_phy_address(dpmac_id, riser_phy_addr[0]);
  494 + break;
  495 + case 3:
  496 + wriop_set_phy_address(dpmac_id, riser_phy_addr[3]);
  497 + break;
  498 + case 7:
  499 + wriop_set_phy_address(dpmac_id, riser_phy_addr[2]);
  500 + break;
  501 + default:
  502 + printf("WRIOP: Wrong DPMAC%d set to SGMII", dpmac_id);
  503 + break;
  504 + }
  505 + break;
  506 + default:
  507 + printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
  508 + __func__, serdes1_prtcl);
  509 + return;
  510 + }
  511 + dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
  512 + bus = mii_dev_for_muxval(EMI1_SLOT1);
  513 + wriop_set_mdio(dpmac_id, bus);
  514 +}
  515 +
  516 +void ls1088a_handle_phy_interface_qsgmii(int dpmac_id)
  517 +{
  518 + struct mii_dev *bus;
  519 + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  520 + u32 serdes1_prtcl, cfg;
  521 +
  522 + cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
  523 + FSL_CHASSIS3_SRDS1_PRTCL_MASK;
  524 + cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
  525 + serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
  526 +
  527 + switch (serdes1_prtcl) {
  528 + case 0x1D:
  529 + case 0x1E:
  530 + switch (dpmac_id) {
  531 + case 3:
  532 + case 4:
  533 + case 5:
  534 + case 6:
  535 + wriop_set_phy_address(dpmac_id, dpmac_id + 9);
  536 + break;
  537 + case 7:
  538 + case 8:
  539 + case 9:
  540 + case 10:
  541 + wriop_set_phy_address(dpmac_id, dpmac_id + 1);
  542 + break;
  543 + }
  544 +
  545 + dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
  546 + bus = mii_dev_for_muxval(EMI1_SLOT1);
  547 + wriop_set_mdio(dpmac_id, bus);
  548 + break;
  549 + default:
  550 + printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
  551 + serdes1_prtcl);
  552 + break;
  553 + }
  554 +}
  555 +
  556 +void ls1088a_handle_phy_interface_xsgmii(int i)
  557 +{
  558 + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  559 + u32 serdes1_prtcl, cfg;
  560 +
  561 + cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
  562 + FSL_CHASSIS3_SRDS1_PRTCL_MASK;
  563 + cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
  564 + serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
  565 +
  566 + switch (serdes1_prtcl) {
  567 + case 0x15:
  568 + case 0x1D:
  569 + case 0x1E:
  570 + wriop_set_phy_address(i, i + 26);
  571 + ls1088a_qds_enable_SFP_TX(SFP_TX);
  572 + break;
  573 + default:
  574 + printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
  575 + serdes1_prtcl);
  576 + break;
  577 + }
  578 +}
  579 +#endif
  580 +
  581 +int board_eth_init(bd_t *bis)
  582 +{
  583 + int error = 0, i;
  584 + char *mc_boot_env_var;
  585 +#ifdef CONFIG_FSL_MC_ENET
  586 + struct memac_mdio_info *memac_mdio0_info;
  587 + char *env_hwconfig = env_get("hwconfig");
  588 +
  589 + initialize_dpmac_to_slot();
  590 +
  591 + memac_mdio0_info = (struct memac_mdio_info *)malloc(
  592 + sizeof(struct memac_mdio_info));
  593 + memac_mdio0_info->regs =
  594 + (struct memac_mdio_controller *)
  595 + CONFIG_SYS_FSL_WRIOP1_MDIO1;
  596 + memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
  597 +
  598 + /* Register the real MDIO1 bus */
  599 + fm_memac_mdio_init(bis, memac_mdio0_info);
  600 +
  601 + /* Register the muxing front-ends to the MDIO buses */
  602 + ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII1);
  603 + ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII2);
  604 + ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
  605 +
  606 + for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
  607 + switch (wriop_get_enet_if(i)) {
  608 + case PHY_INTERFACE_MODE_QSGMII:
  609 + ls1088a_handle_phy_interface_qsgmii(i);
  610 + break;
  611 + case PHY_INTERFACE_MODE_SGMII:
  612 + ls1088a_handle_phy_interface_sgmii(i);
  613 + break;
  614 + case PHY_INTERFACE_MODE_XGMII:
  615 + ls1088a_handle_phy_interface_xsgmii(i);
  616 + break;
  617 + default:
  618 + break;
  619 +
  620 + if (i == 16)
  621 + i = NUM_WRIOP_PORTS;
  622 + }
  623 + }
  624 +
  625 + mc_boot_env_var = env_get(MC_BOOT_ENV_VAR);
  626 + if (mc_boot_env_var)
  627 + run_command_list(mc_boot_env_var, -1, 0);
  628 + error = cpu_eth_init(bis);
  629 +
  630 + if (hwconfig_f("xqsgmii", env_hwconfig)) {
  631 + for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
  632 + switch (wriop_get_enet_if(i)) {
  633 + case PHY_INTERFACE_MODE_QSGMII:
  634 + qsgmii_configure_repeater(i);
  635 + break;
  636 + case PHY_INTERFACE_MODE_SGMII:
  637 + sgmii_configure_repeater(i);
  638 + break;
  639 + default:
  640 + break;
  641 + }
  642 +
  643 + if (i == 16)
  644 + i = NUM_WRIOP_PORTS;
  645 + }
  646 + }
  647 +#endif
  648 + error = pci_eth_init(bis);
  649 + return error;
  650 +}
board/freescale/ls1088a/ls1088a.c
Diff comments   View file @ 7769776
... ... @@ -50,15 +50,21 @@
50 50 "100 separate SSCG"};
51 51 int clock;
52 52  
53   -
  53 +#ifdef CONFIG_TARGET_LS1088AQDS
  54 + printf("Board: LS1088A-QDS, ");
  55 +#else
54 56 printf("Board: LS1088A-RDB, ");
  57 +#endif
55 58  
56 59 sw = QIXIS_READ(arch);
57 60 printf("Board Arch: V%d, ", sw >> 4);
58 61  
  62 +#ifdef CONFIG_TARGET_LS1088AQDS
  63 + printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
  64 +#else
59 65 printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
  66 +#endif
60 67  
61   -
62 68 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
63 69  
64 70 sw = QIXIS_READ(brdcfg[0]);
65 71  
... ... @@ -68,8 +74,27 @@
68 74 puts("SD card\n");
69 75 #endif
70 76 switch (sw) {
  77 +#ifdef CONFIG_TARGET_LS1088AQDS
71 78 case 0:
72   -
  79 + case 1:
  80 + case 2:
  81 + case 3:
  82 + case 4:
  83 + case 5:
  84 + case 6:
  85 + case 7:
  86 + printf("vBank: %d\n", sw);
  87 + break;
  88 + case 8:
  89 + puts("PromJet\n");
  90 + break;
  91 + case 15:
  92 + puts("IFCCard\n");
  93 + break;
  94 + case 14:
  95 +#else
  96 + case 0:
  97 +#endif
73 98 puts("QSPI:");
74 99 sw = QIXIS_READ(brdcfg[0]);
75 100 sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
76 101  
77 102  
... ... @@ -86,10 +111,16 @@
86 111 break;
87 112 }
88 113  
89   -
  114 +#ifdef CONFIG_TARGET_LS1088AQDS
  115 + printf("FPGA: v%d (%s), build %d",
  116 + (int)QIXIS_READ(scver), qixis_read_tag(buf),
  117 + (int)qixis_read_minor());
  118 + /* the timestamp string contains "\n" at the end */
  119 + printf(" on %s", qixis_read_time(buf));
  120 +#else
90 121 printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
  122 +#endif
91 123  
92   -
93 124 /*
94 125 * Display the actual SERDES reference clocks as configured by the
95 126 * dip switches on the board. Note that the SWx registers could
96 127  
... ... @@ -116,8 +147,13 @@
116 147  
117 148 bool if_board_diff_clk(void)
118 149 {
  150 +#ifdef CONFIG_TARGET_LS1088AQDS
  151 + u8 diff_conf = QIXIS_READ(brdcfg[11]);
  152 + return diff_conf & 0x40;
  153 +#else
119 154 u8 diff_conf = QIXIS_READ(dutcfg[11]);
120 155 return diff_conf & 0x80;
  156 +#endif
121 157 }
122 158  
123 159 unsigned long get_board_sys_clk(void)
124 160  
... ... @@ -217,7 +253,45 @@
217 253 reg |= 0x70;
218 254 i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
219 255  
  256 +#ifdef CONFIG_TARGET_LS1088AQDS
  257 + /* Retimer is connected to I2C1_CH5 */
  258 + select_i2c_ch_pca9547(I2C_MUX_CH5);
220 259  
  260 + /* Access to Control/Shared register */
  261 + reg = 0x0;
  262 + i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
  263 +
  264 + /* Read device revision and ID */
  265 + i2c_read(I2C_RETIMER_ADDR2, 1, 1, &reg, 1);
  266 + debug("Retimer version id = 0x%x\n", reg);
  267 +
  268 + /* Enable Broadcast. All writes target all channel register sets */
  269 + reg = 0x0c;
  270 + i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
  271 +
  272 + /* Reset Channel Registers */
  273 + i2c_read(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
  274 + reg |= 0x4;
  275 + i2c_write(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
  276 +
  277 + /* Set data rate as 10.3125 Gbps */
  278 + reg = 0x90;
  279 + i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, &reg, 1);
  280 + reg = 0xb3;
  281 + i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, &reg, 1);
  282 + reg = 0x90;
  283 + i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, &reg, 1);
  284 + reg = 0xb3;
  285 + i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, &reg, 1);
  286 + reg = 0xcd;
  287 + i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, &reg, 1);
  288 +
  289 + /* Select VCO Divider to full rate (000) */
  290 + i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
  291 + reg &= 0x0f;
  292 + reg |= 0x70;
  293 + i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
  294 +#endif
221 295 /*return the default channel*/
222 296 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
223 297 }
board/freescale/ls1088a/ls1088a_qixis.h
Diff comments   View file @ 7769776
... ... @@ -31,5 +31,10 @@
31 31 #define QIXIS_SDCLK1_165 0x2
32 32 #define QIXIS_SDCLK1_100_SP 0x3
33 33  
  34 +#define BRDCFG4_EMISEL_MASK 0xE0
  35 +#define BRDCFG4_EMISEL_SHIFT 5
  36 +#define BRDCFG9_SFPTX_MASK 0x10
  37 +#define BRDCFG9_SFPTX_SHIFT 4
  38 +
34 39 #endif
configs/ls1088aqds_qspi_defconfig
Diff comments   View file @ 7769776
  1 +CONFIG_ARM=y
  2 +CONFIG_TARGET_LS1088AQDS=y
  3 +# CONFIG_SYS_MALLOC_F is not set
  4 +CONFIG_DM_SPI=y
  5 +CONFIG_DM_SPI_FLASH=y
  6 +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
  7 +CONFIG_FIT=y
  8 +CONFIG_FIT_VERBOSE=y
  9 +CONFIG_OF_BOARD_SETUP=y
  10 +CONFIG_OF_STDOUT_VIA_ALIAS=y
  11 +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT"
  12 +CONFIG_HUSH_PARSER=y
  13 +CONFIG_CMD_MMC=y
  14 +CONFIG_CMD_SF=y
  15 +CONFIG_CMD_I2C=y
  16 +# CONFIG_CMD_SETEXPR is not set
  17 +CONFIG_CMD_DHCP=y
  18 +CONFIG_CMD_PING=y
  19 +CONFIG_OF_CONTROL=y
  20 +CONFIG_NET_RANDOM_ETHADDR=y
  21 +CONFIG_DM=y
  22 +CONFIG_SPI_FLASH=y
  23 +CONFIG_NETDEVICES=y
  24 +CONFIG_E1000=y
  25 +CONFIG_SYS_NS16550=y
  26 +CONFIG_FSL_DSPI=y
  27 +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
  28 +# CONFIG_DISPLAY_BOARDINFO is not set
  29 +CONFIG_FSL_LS_PPA=y
include/configs/ls1088aqds.h
Diff comments   View file @ 7769776
  1 +/*
  2 + * Copyright 2017 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef __LS1088A_QDS_H
  8 +#define __LS1088A_QDS_H
  9 +
  10 +#include "ls1088a_common.h"
  11 +
  12 +
  13 +#define CONFIG_DISPLAY_BOARDINFO_LATE
  14 +
  15 +
  16 +#ifndef __ASSEMBLY__
  17 +unsigned long get_board_sys_clk(void);
  18 +unsigned long get_board_ddr_clk(void);
  19 +#endif
  20 +
  21 +
  22 +#if defined(CONFIG_QSPI_BOOT)
  23 +#define CONFIG_ENV_IS_IN_SPI_FLASH
  24 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
  25 +#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
  26 +#define CONFIG_ENV_SECT_SIZE 0x40000
  27 +#else
  28 +#define CONFIG_ENV_IS_IN_FLASH
  29 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
  30 +#define CONFIG_ENV_SECT_SIZE 0x20000
  31 +#define CONFIG_ENV_SIZE 0x20000
  32 +#endif
  33 +
  34 +#if defined(CONFIG_QSPI_BOOT)
  35 +#define CONFIG_QIXIS_I2C_ACCESS
  36 +#define SYS_NO_FLASH
  37 +
  38 +#undef CONFIG_CMD_IMLS
  39 +#define CONFIG_SYS_CLK_FREQ 100000000
  40 +#define CONFIG_DDR_CLK_FREQ 100000000
  41 +#else
  42 +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
  43 +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
  44 +#endif
  45 +
  46 +#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
  47 +#define COUNTER_FREQUENCY 25000000 /* 25MHz */
  48 +
  49 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1
  50 +
  51 +#define CONFIG_DDR_SPD
  52 +#define CONFIG_DDR_ECC
  53 +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  54 +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  55 +#define SPD_EEPROM_ADDRESS 0x51
  56 +#define CONFIG_SYS_SPD_BUS_NUM 0
  57 +
  58 +
  59 +/*
  60 + * IFC Definitions
  61 + */
  62 +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  63 +#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
  64 +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  65 +#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
  66 +
  67 +#define CONFIG_SYS_NOR0_CSPR \
  68 + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  69 + CSPR_PORT_SIZE_16 | \
  70 + CSPR_MSEL_NOR | \
  71 + CSPR_V)
  72 +#define CONFIG_SYS_NOR0_CSPR_EARLY \
  73 + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
  74 + CSPR_PORT_SIZE_16 | \
  75 + CSPR_MSEL_NOR | \
  76 + CSPR_V)
  77 +#define CONFIG_SYS_NOR1_CSPR \
  78 + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
  79 + CSPR_PORT_SIZE_16 | \
  80 + CSPR_MSEL_NOR | \
  81 + CSPR_V)
  82 +#define CONFIG_SYS_NOR1_CSPR_EARLY \
  83 + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
  84 + CSPR_PORT_SIZE_16 | \
  85 + CSPR_MSEL_NOR | \
  86 + CSPR_V)
  87 +#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
  88 +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  89 + FTIM0_NOR_TEADC(0x5) | \
  90 + FTIM0_NOR_TEAHC(0x5))
  91 +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  92 + FTIM1_NOR_TRAD_NOR(0x1a) |\
  93 + FTIM1_NOR_TSEQRAD_NOR(0x13))
  94 +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  95 + FTIM2_NOR_TCH(0x4) | \
  96 + FTIM2_NOR_TWPH(0x0E) | \
  97 + FTIM2_NOR_TWP(0x1c))
  98 +#define CONFIG_SYS_NOR_FTIM3 0x04000000
  99 +#define CONFIG_SYS_IFC_CCR 0x01000000
  100 +
  101 +#ifndef SYS_NO_FLASH
  102 +#define CONFIG_FLASH_CFI_DRIVER
  103 +#define CONFIG_SYS_FLASH_CFI
  104 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  105 +#define CONFIG_SYS_FLASH_QUIET_TEST
  106 +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  107 +
  108 +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  109 +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  110 +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  111 +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  112 +
  113 +#define CONFIG_SYS_FLASH_EMPTY_INFO
  114 +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
  115 + CONFIG_SYS_FLASH_BASE + 0x40000000}
  116 +#endif
  117 +#endif
  118 +
  119 +#define CONFIG_NAND_FSL_IFC
  120 +#define CONFIG_SYS_NAND_MAX_ECCPOS 256
  121 +#define CONFIG_SYS_NAND_MAX_OOBFREE 2
  122 +
  123 +#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
  124 +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  125 + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  126 + | CSPR_MSEL_NAND /* MSEL = NAND */ \
  127 + | CSPR_V)
  128 +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
  129 +
  130 +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  131 + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  132 + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  133 + | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
  134 + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
  135 + | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
  136 + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  137 +
  138 +#define CONFIG_SYS_NAND_ONFI_DETECTION
  139 +
  140 +/* ONFI NAND Flash mode0 Timing Params */
  141 +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  142 + FTIM0_NAND_TWP(0x18) | \
  143 + FTIM0_NAND_TWCHT(0x07) | \
  144 + FTIM0_NAND_TWH(0x0a))
  145 +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  146 + FTIM1_NAND_TWBE(0x39) | \
  147 + FTIM1_NAND_TRR(0x0e) | \
  148 + FTIM1_NAND_TRP(0x18))
  149 +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  150 + FTIM2_NAND_TREH(0x0a) | \
  151 + FTIM2_NAND_TWHRE(0x1e))
  152 +#define CONFIG_SYS_NAND_FTIM3 0x0
  153 +
  154 +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  155 +#define CONFIG_SYS_MAX_NAND_DEVICE 1
  156 +#define CONFIG_MTD_NAND_VERIFY_WRITE
  157 +#define CONFIG_CMD_NAND
  158 +
  159 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  160 +
  161 +#define CONFIG_FSL_QIXIS
  162 +#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
  163 +#define QIXIS_LBMAP_SWITCH 6
  164 +#define QIXIS_QMAP_MASK 0xe0
  165 +#define QIXIS_QMAP_SHIFT 5
  166 +#define QIXIS_LBMAP_MASK 0x0f
  167 +#define QIXIS_LBMAP_SHIFT 0
  168 +#define QIXIS_LBMAP_DFLTBANK 0x0e
  169 +#define QIXIS_LBMAP_ALTBANK 0x2e
  170 +#define QIXIS_LBMAP_SD 0x00
  171 +#define QIXIS_LBMAP_SD_QSPI 0x0e
  172 +#define QIXIS_LBMAP_QSPI 0x0e
  173 +#define QIXIS_RCW_SRC_SD 0x40
  174 +#define QIXIS_RCW_SRC_QSPI 0x62
  175 +#define QIXIS_RST_CTL_RESET 0x41
  176 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  177 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  178 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  179 +#define QIXIS_RST_FORCE_MEM 0x01
  180 +#define QIXIS_STAT_PRES1 0xb
  181 +#define QIXIS_SDID_MASK 0x07
  182 +#define QIXIS_ESDHC_NO_ADAPTER 0x7
  183 +
  184 +#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
  185 +#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
  186 + | CSPR_PORT_SIZE_8 \
  187 + | CSPR_MSEL_GPCM \
  188 + | CSPR_V)
  189 +#define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
  190 + | CSPR_PORT_SIZE_8 \
  191 + | CSPR_MSEL_GPCM \
  192 + | CSPR_V)
  193 +
  194 +#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024)
  195 +#if defined(CONFIG_QSPI_BOOT)
  196 +#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
  197 +#else
  198 +#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12)
  199 +#endif
  200 +/* QIXIS Timing parameters*/
  201 +#define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  202 + FTIM0_GPCM_TEADC(0x0e) | \
  203 + FTIM0_GPCM_TEAHC(0x0e))
  204 +#define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
  205 + FTIM1_GPCM_TRAD(0x3f))
  206 +#define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
  207 + FTIM2_GPCM_TCH(0xf) | \
  208 + FTIM2_GPCM_TWP(0x3E))
  209 +#define SYS_FPGA_CS_FTIM3 0x0
  210 +
  211 +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  212 +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  213 +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  214 +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  215 +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  216 +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  217 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  218 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  219 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  220 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
  221 +#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
  222 +#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
  223 +#define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK
  224 +#define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
  225 +#define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
  226 +#define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
  227 +#define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
  228 +#define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
  229 +#else
  230 +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  231 +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
  232 +#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
  233 +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  234 +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  235 +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  236 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  237 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  238 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  239 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  240 +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
  241 +#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
  242 +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
  243 +#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
  244 +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  245 +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  246 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  247 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  248 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  249 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
  250 +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
  251 +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
  252 +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
  253 +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
  254 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
  255 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
  256 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
  257 +#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
  258 +#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
  259 +#define CONFIG_SYS_CSPR3_FINAL CONFIG_SYS_FPGA_CSPR_FINAL
  260 +#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
  261 +#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
  262 +#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_CS_FTIM0
  263 +#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_CS_FTIM1
  264 +#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_CS_FTIM2
  265 +#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_CS_FTIM3
  266 +#endif
  267 +
  268 +#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
  269 +
  270 +/*
  271 + * I2C bus multiplexer
  272 + */
  273 +#define I2C_MUX_PCA_ADDR_PRI 0x77
  274 +#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
  275 +#define I2C_RETIMER_ADDR 0x18
  276 +#define I2C_RETIMER_ADDR2 0x19
  277 +#define I2C_MUX_CH_DEFAULT 0x8
  278 +#define I2C_MUX_CH5 0xD
  279 +
  280 +/*
  281 +* RTC configuration
  282 +*/
  283 +#define RTC
  284 +#define CONFIG_RTC_PCF8563 1
  285 +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
  286 +#define CONFIG_CMD_DATE
  287 +
  288 +/* EEPROM */
  289 +#define CONFIG_ID_EEPROM
  290 +#define CONFIG_SYS_I2C_EEPROM_NXID
  291 +#define CONFIG_SYS_EEPROM_BUS_NUM 0
  292 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  293 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  294 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  295 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  296 +
  297 +/* QSPI device */
  298 +#if defined(CONFIG_QSPI_BOOT)
  299 +#define CONFIG_FSL_QSPI
  300 +#define CONFIG_SPI_FLASH_SPANSION
  301 +#define FSL_QSPI_FLASH_SIZE (1 << 26)
  302 +#define FSL_QSPI_FLASH_NUM 2
  303 +
  304 +#endif
  305 +
  306 +#ifdef CONFIG_FSL_DSPI
  307 +#define CONFIG_SPI_FLASH_STMICRO
  308 +#define CONFIG_SPI_FLASH_SST
  309 +#define CONFIG_SPI_FLASH_EON
  310 +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  311 +#define CONFIG_SF_DEFAULT_BUS 1
  312 +#define CONFIG_SF_DEFAULT_CS 0
  313 +#endif
  314 +#endif
  315 +
  316 +#define CONFIG_CMD_MEMINFO
  317 +#define CONFIG_CMD_MEMTEST
  318 +#define CONFIG_SYS_MEMTEST_START 0x80000000
  319 +#define CONFIG_SYS_MEMTEST_END 0x9fffffff
  320 +
  321 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  322 +
  323 +#define CONFIG_FSL_MEMAC
  324 +
  325 +/* MMC */
  326 +#define CONFIG_FSL_ESDHC
  327 +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  328 +#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
  329 + QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
  330 +
  331 +/* Initial environment variables */
  332 +#if defined(CONFIG_QSPI_BOOT)
  333 +#undef CONFIG_EXTRA_ENV_SETTINGS
  334 +#define CONFIG_EXTRA_ENV_SETTINGS \
  335 + "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  336 + "loadaddr=0x90100000\0" \
  337 + "kernel_addr=0x100000\0" \
  338 + "ramdisk_addr=0x800000\0" \
  339 + "ramdisk_size=0x2000000\0" \
  340 + "fdt_high=0xa0000000\0" \
  341 + "initrd_high=0xffffffffffffffff\0" \
  342 + "kernel_start=0x1000000\0" \
  343 + "kernel_load=0xa0000000\0" \
  344 + "kernel_size=0x2800000\0" \
  345 + "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
  346 + "sf read 0x80100000 0xE00000 0x100000;" \
  347 + "fsl_mc start mc 0x80000000 0x80100000\0" \
  348 + "mcmemsize=0x70000000 \0"
  349 +#else /* NOR BOOT */
  350 +#undef CONFIG_EXTRA_ENV_SETTINGS
  351 +#define CONFIG_EXTRA_ENV_SETTINGS \
  352 + "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  353 + "loadaddr=0x90100000\0" \
  354 + "kernel_addr=0x100000\0" \
  355 + "ramdisk_addr=0x800000\0" \
  356 + "ramdisk_size=0x2000000\0" \
  357 + "fdt_high=0xa0000000\0" \
  358 + "initrd_high=0xffffffffffffffff\0" \
  359 + "kernel_start=0x1000000\0" \
  360 + "kernel_load=0xa0000000\0" \
  361 + "kernel_size=0x2800000\0" \
  362 + "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \
  363 + "mcmemsize=0x70000000 \0"
  364 +#endif
  365 +
  366 +#ifdef CONFIG_FSL_MC_ENET
  367 +#define CONFIG_FSL_MEMAC
  368 +#define CONFIG_PHYLIB
  369 +#define CONFIG_PHYLIB_10G
  370 +#define CONFIG_PHY_VITESSE
  371 +#define CONFIG_PHY_REALTEK
  372 +#define CONFIG_PHY_TERANETICS
  373 +#define RGMII_PHY1_ADDR 0x1
  374 +#define RGMII_PHY2_ADDR 0x2
  375 +#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  376 +#define SGMII_CARD_PORT2_PHY_ADDR 0x1d
  377 +#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  378 +#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  379 +
  380 +#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
  381 +#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
  382 +#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
  383 +#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
  384 +#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
  385 +#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
  386 +#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
  387 +#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
  388 +#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
  389 +#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
  390 +#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
  391 +#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
  392 +#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
  393 +#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
  394 +#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
  395 +#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
  396 +
  397 +#define CONFIG_MII /* MII PHY management */
  398 +#define CONFIG_ETHPRIME "DPMAC1@xgmii"
  399 +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
  400 +
  401 +#endif
  402 +
  403 +#undef CONFIG_CMDLINE_EDITING
  404 +#include <config_distro_defaults.h>
  405 +#define BOOT_TARGET_DEVICES(func) \
  406 + func(USB, usb, 0) \
  407 + func(MMC, mmc, 0) \
  408 + func(SCSI, scsi, 0) \
  409 + func(DHCP, dhcp, na)
  410 +#include <config_distro_bootcmd.h>
  411 +
  412 +#include <asm/fsl_secure_boot.h>
  413 +
  414 +#endif /* __LS1088A_QDS_H */