mpc83xx: MPC837XEMDS: Initialize SerDes before negating PCIE reset signal

The SerDes initialization should be finished before negating the reset signal according to the reference manual. This isn't an issue on real hardware, but we'd better stick to the specifications anyway. Suggested-by: Liu Dave <DaveLiu@freescale.com> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

mpc83xx: MPC837XEMDS: Initialize SerDes before negating PCIE reset signal
The SerDes initialization should be finished before negating the reset signal according to the reference manual. This isn't an issue on real hardware, but we'd better stick to the specifications anyway. Suggested-by: Liu Dave <DaveLiu@freescale.com> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Anton Vorontsov · Kim Phillips
1 parent 7e91558032
Showing 1 changed file with 7 additions and 7 deletions Side-by-side Diff
board/freescale/mpc837xemds/pci.c
@@ -115,6 +115,13 @@
 	if (PARTID_NO_E(spridr) == SPR_8379)
 		return;
  
+	if (pex2)
+		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX_X2,
+				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+	else
+		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
+				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+
 	/* Configure the clock for PCIE controller */
 	clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
 				    SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
@@ -131,13 +138,6 @@
  
 	out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
 	out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
-	if (pex2)
-		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX_X2,
-				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
-	else
-		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
-				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
  
 	mpc83xx_pcie_init(pex2 ? 1 : 2, pcie_reg, 0);
 }
...	...	@@ -115,6 +115,13 @@
115	115	if (PARTID_NO_E(spridr) == SPR_8379)
116	116	return;
117	117
	118	+ if (pex2)
	119	+ fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX_X2,
	120	+ FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
	121	+ else
	122	+ fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
	123	+ FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
	124	+
118	125	/* Configure the clock for PCIE controller */
119	126	clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM \| SCCR_PCIEXP2CM,
120	127	SCCR_PCIEXP1CM_1 \| SCCR_PCIEXP2CM_1);
...	...	@@ -131,13 +138,6 @@
131	138
132	139	out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
133	140	out_be32(&pcie_law[1].ar, LBLAWAR_EN \| LBLAWAR_512MB);
134		-
135		- if (pex2)
136		- fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX_X2,
137		- FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
138		- else
139		- fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
140		- FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
141	141
142	142	mpc83xx_pcie_init(pex2 ? 1 : 2, pcie_reg, 0);
143	143	}