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Commit 7edb1f7b86e31a21253fc89bd2bebf7d20ed36a5

Authored by Masahiro Yamada
Committed by Tom Rini
1 parent 2868f8625f
Exists in v2017.01-smarct4x and in 40 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

powerpc: debris: remove orphan board 

This board has been orphan for a while.
(Emails to its maintainer have been bouncing.)

Because MPC82xx family is old enough, nobody would pick up
the maintainership on it.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denx <wd@denx.de>

Showing 7 changed files with 1 additions and 1632 deletions Side-by-side Diff

board/etin/debris/Makefile
View file @ 7edb1f7
1   -#
2   -# (C) Copyright 2000-2006
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# SPDX-License-Identifier: GPL-2.0+
6   -#
7   -
8   -obj-y = debris.o flash.o phantom.o
board/etin/debris/debris.c
View file @ 7edb1f7
1   -/*
2   - * (C) Copyright 2000
3   - * Sangmoon Kim, Etin Systems. dogoil@etinsys.com.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <common.h>
9   -#include <mpc824x.h>
10   -#include <net.h>
11   -#include <pci.h>
12   -#include <i2c.h>
13   -#include <netdev.h>
14   -
15   -DECLARE_GLOBAL_DATA_PTR;
16   -
17   -int checkboard (void)
18   -{
19   - /*TODO: Check processor type */
20   -
21   - puts ( "Board: Debris "
22   -#ifdef CONFIG_MPC8240
23   - "8240"
24   -#endif
25   -#ifdef CONFIG_MPC8245
26   - "8245"
27   -#endif
28   - " ##Test not implemented yet##\n");
29   - return 0;
30   -}
31   -
32   -#if 0 /* NOT USED */
33   -int checkflash (void)
34   -{
35   - /* TODO: XXX XXX XXX */
36   - printf ("## Test not implemented yet ##\n");
37   -
38   - return (0);
39   -}
40   -#endif
41   -
42   -phys_size_t initdram (int board_type)
43   -{
44   - int m, row, col, bank, i;
45   - unsigned long start, end;
46   - uint32_t mccr1;
47   - uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
48   - uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
49   - uint8_t mber = 0;
50   -
51   - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
52   -
53   - if (i2c_reg_read (0x50, 2) != 0x04) return 0; /* Memory type */
54   - m = i2c_reg_read (0x50, 5); /* # of physical banks */
55   - row = i2c_reg_read (0x50, 3); /* # of rows */
56   - col = i2c_reg_read (0x50, 4); /* # of columns */
57   - bank = i2c_reg_read (0x50, 17); /* # of logical banks */
58   -
59   - CONFIG_READ_WORD(MCCR1, mccr1);
60   - mccr1 &= 0xffff0000;
61   -
62   - start = CONFIG_SYS_SDRAM_BASE;
63   - end = start + (1 << (col + row + 3) ) * bank - 1;
64   -
65   - for (i = 0; i < m; i++) {
66   - mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
67   - if (i < 4) {
68   - msar1 |= ((start >> 20) & 0xff) << i * 8;
69   - emsar1 |= ((start >> 28) & 0xff) << i * 8;
70   - mear1 |= ((end >> 20) & 0xff) << i * 8;
71   - emear1 |= ((end >> 28) & 0xff) << i * 8;
72   - } else {
73   - msar2 |= ((start >> 20) & 0xff) << (i-4) * 8;
74   - emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
75   - mear2 |= ((end >> 20) & 0xff) << (i-4) * 8;
76   - emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
77   - }
78   - mber |= 1 << i;
79   - start += (1 << (col + row + 3) ) * bank;
80   - end += (1 << (col + row + 3) ) * bank;
81   - }
82   - for (; i < 8; i++) {
83   - if (i < 4) {
84   - msar1 |= 0xff << i * 8;
85   - emsar1 |= 0x30 << i * 8;
86   - mear1 |= 0xff << i * 8;
87   - emear1 |= 0x30 << i * 8;
88   - } else {
89   - msar2 |= 0xff << (i-4) * 8;
90   - emsar2 |= 0x30 << (i-4) * 8;
91   - mear2 |= 0xff << (i-4) * 8;
92   - emear2 |= 0x30 << (i-4) * 8;
93   - }
94   - }
95   -
96   - CONFIG_WRITE_WORD(MCCR1, mccr1);
97   - CONFIG_WRITE_WORD(MSAR1, msar1);
98   - CONFIG_WRITE_WORD(EMSAR1, emsar1);
99   - CONFIG_WRITE_WORD(MEAR1, mear1);
100   - CONFIG_WRITE_WORD(EMEAR1, emear1);
101   - CONFIG_WRITE_WORD(MSAR2, msar2);
102   - CONFIG_WRITE_WORD(EMSAR2, emsar2);
103   - CONFIG_WRITE_WORD(MEAR2, mear2);
104   - CONFIG_WRITE_WORD(EMEAR2, emear2);
105   - CONFIG_WRITE_BYTE(MBER, mber);
106   -
107   - return (1 << (col + row + 3) ) * bank * m;
108   -}
109   -
110   -/*
111   - * Initialize PCI Devices, report devices found.
112   - */
113   -#ifndef CONFIG_PCI_PNP
114   -static struct pci_config_table pci_debris_config_table[] = {
115   - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
116   - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
117   - PCI_ENET0_MEMADDR,
118   - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
119   - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
120   - pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
121   - PCI_ENET1_MEMADDR,
122   - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
123   - { }
124   -};
125   -#endif
126   -
127   -struct pci_controller hose = {
128   -#ifndef CONFIG_PCI_PNP
129   - config_table: pci_debris_config_table,
130   -#endif
131   -};
132   -
133   -void pci_init_board(void)
134   -{
135   - pci_mpc824x_init(&hose);
136   -}
137   -
138   -void *nvram_read(void *dest, const long src, size_t count)
139   -{
140   - volatile uchar *d = (volatile uchar*) dest;
141   - volatile uchar *s = (volatile uchar*) src;
142   - while(count--) {
143   - *d++ = *s++;
144   - asm volatile("sync");
145   - }
146   - return dest;
147   -}
148   -
149   -void nvram_write(long dest, const void *src, size_t count)
150   -{
151   - volatile uchar *d = (volatile uchar*)dest;
152   - volatile uchar *s = (volatile uchar*)src;
153   - while(count--) {
154   - *d++ = *s++;
155   - asm volatile("sync");
156   - }
157   -}
158   -
159   -int misc_init_r(void)
160   -{
161   - uchar ethaddr[6];
162   -
163   - if (eth_getenv_enetaddr("ethaddr", ethaddr))
164   - /* Write ethernet addr in NVRAM for VxWorks */
165   - nvram_write(CONFIG_ENV_ADDR + CONFIG_SYS_NVRAM_VXWORKS_OFFS,
166   - ethaddr, 6);
167   -
168   - return 0;
169   -}
170   -
171   -int board_eth_init(bd_t *bis)
172   -{
173   - return pci_eth_init(bis);
174   -}
board/etin/debris/flash.c
View file @ 7edb1f7
1   -/*
2   - * board/eva/flash.c
3   - *
4   - * (C) Copyright 2002
5   - * Sangmoon Kim, Etin Systems, dogoil@etinsys.com.
6   - *
7   - * SPDX-License-Identifier: GPL-2.0+
8   - */
9   -
10   -#include <common.h>
11   -#include <asm/processor.h>
12   -#include <asm/pci_io.h>
13   -#include <mpc824x.h>
14   -#include <asm/mmu.h>
15   -
16   -int (*do_flash_erase)(flash_info_t*, uint32_t, uint32_t);
17   -int (*write_dword)(flash_info_t*, ulong, uint64_t);
18   -
19   -typedef uint64_t cfi_word;
20   -
21   -#define cfi_read(flash, addr) *((volatile cfi_word*)(flash->start[0] + addr))
22   -
23   -#define cfi_write(flash, val, addr) \
24   - move64((cfi_word*)&val, \
25   - (cfi_word*)(flash->start[0] + addr))
26   -
27   -#define CMD(x) ((((cfi_word)x)<<48)|(((cfi_word)x)<<32)|(((cfi_word)x)<<16)|(((cfi_word)x)))
28   -
29   -static void write32(unsigned long addr, uint32_t value)
30   -{
31   - *(volatile uint32_t*)(addr) = value;
32   - asm volatile("sync");
33   -}
34   -
35   -static uint32_t read32(unsigned long addr)
36   -{
37   - uint32_t value;
38   - value = *(volatile uint32_t*)addr;
39   - asm volatile("sync");
40   - return value;
41   -}
42   -
43   -static cfi_word cfi_cmd(flash_info_t *flash, uint8_t cmd, uint32_t addr)
44   -{
45   - uint32_t base = flash->start[0];
46   - uint32_t val=(cmd << 16) | cmd;
47   - addr <<= 3;
48   - write32(base + addr, val);
49   - return addr;
50   -}
51   -
52   -static uint16_t cfi_read_query(flash_info_t *flash, uint32_t addr)
53   -{
54   - uint32_t base = flash->start[0];
55   - addr <<= 3;
56   - return (uint16_t)read32(base + addr);
57   -}
58   -
59   -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
60   -
61   -static void move64(uint64_t *src, uint64_t *dest)
62   -{
63   - asm volatile("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
64   - "stfd 0, 0(4)" /* *dest = fpr0 */
65   - : : : "fr0" ); /* Clobbers fr0 */
66   - return;
67   -}
68   -
69   -static int cfi_write_dword(flash_info_t *flash, ulong dest, cfi_word data)
70   -{
71   - unsigned long start;
72   - cfi_word status = 0;
73   -
74   - status = cfi_read(flash, dest);
75   - data &= status;
76   -
77   - cfi_cmd(flash, 0x40, 0);
78   - cfi_write(flash, data, dest);
79   -
80   - udelay(10);
81   - start = get_timer (0);
82   - for(;;) {
83   - status = cfi_read(flash, dest);
84   - status &= CMD(0x80);
85   - if(status == CMD(0x80))
86   - break;
87   - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
88   - cfi_cmd(flash, 0xff, 0);
89   - return 1;
90   - }
91   - udelay(1);
92   - }
93   - cfi_cmd(flash, 0xff, 0);
94   -
95   - return 0;
96   -}
97   -
98   -static int jedec_write_dword (flash_info_t *flash, ulong dest, cfi_word data)
99   -{
100   - ulong start;
101   - cfi_word status = 0;
102   -
103   - status = cfi_read(flash, dest);
104   - if(status != CMD(0xffff)) return 2;
105   -
106   - cfi_cmd(flash, 0xaa, 0x555);
107   - cfi_cmd(flash, 0x55, 0x2aa);
108   - cfi_cmd(flash, 0xa0, 0x555);
109   -
110   - cfi_write(flash, data, dest);
111   -
112   - udelay(10);
113   - start = get_timer (0);
114   - status = ~data;
115   - while(status != data) {
116   - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
117   - return 1;
118   - status = cfi_read(flash, dest);
119   - udelay(1);
120   - }
121   - return 0;
122   -}
123   -
124   -static __inline__ unsigned long get_msr(void)
125   -{
126   - unsigned long msr;
127   - __asm__ __volatile__ ("mfmsr %0" : "=r" (msr) :);
128   - return msr;
129   -}
130   -
131   -static __inline__ void set_msr(unsigned long msr)
132   -{
133   - __asm__ __volatile__ ("mtmsr %0" : : "r" (msr));
134   -}
135   -
136   -int write_buff (flash_info_t *flash, uchar *src, ulong addr, ulong cnt)
137   -{
138   - ulong wp;
139   - int i, s, l, rc;
140   - cfi_word data;
141   - uint8_t *t = (uint8_t*)&data;
142   - unsigned long base = flash->start[0];
143   - uint32_t msr;
144   -
145   - if (flash->flash_id == FLASH_UNKNOWN)
146   - return 4;
147   -
148   - if (cnt == 0)
149   - return 0;
150   -
151   - addr -= base;
152   -
153   - msr = get_msr();
154   - set_msr(msr|MSR_FP);
155   -
156   - wp = (addr & ~7); /* get lower word aligned address */
157   -
158   - if((addr-wp) != 0) {
159   - data = cfi_read(flash, wp);
160   - s = addr & 7;
161   - l = ( cnt < (8-s) ) ? cnt : (8-s);
162   - for(i = 0; i < l; i++)
163   - t[s+i] = *src++;
164   - if ((rc = write_dword(flash, wp, data)) != 0)
165   - goto DONE;
166   - wp += 8;
167   - cnt -= l;
168   - }
169   -
170   - while (cnt >= 8) {
171   - for (i = 0; i < 8; i++)
172   - t[i] = *src++;
173   - if ((rc = write_dword(flash, wp, data)) != 0)
174   - goto DONE;
175   - wp += 8;
176   - cnt -= 8;
177   - }
178   -
179   - if (cnt == 0) {
180   - rc = 0;
181   - goto DONE;
182   - }
183   -
184   - data = cfi_read(flash, wp);
185   - for(i = 0; i < cnt; i++)
186   - t[i] = *src++;
187   - rc = write_dword(flash, wp, data);
188   -DONE:
189   - set_msr(msr);
190   - return rc;
191   -}
192   -
193   -static int cfi_erase_oneblock(flash_info_t *flash, uint32_t sect)
194   -{
195   - int sa;
196   - int flag;
197   - ulong start, last, now;
198   - cfi_word status;
199   -
200   - flag = disable_interrupts();
201   -
202   - sa = (flash->start[sect] - flash->start[0]);
203   - write32(flash->start[sect], 0x00200020);
204   - write32(flash->start[sect], 0x00d000d0);
205   -
206   - if (flag)
207   - enable_interrupts();
208   -
209   - udelay(1000);
210   - start = get_timer (0);
211   - last = start;
212   -
213   - for (;;) {
214   - status = cfi_read(flash, sa);
215   - status &= CMD(0x80);
216   - if (status == CMD(0x80))
217   - break;
218   - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
219   - cfi_cmd(flash, 0xff, 0);
220   - printf ("Timeout\n");
221   - return ERR_TIMOUT;
222   - }
223   -
224   - if ((now - last) > 1000) {
225   - serial_putc ('.');
226   - last = now;
227   - }
228   - udelay(10);
229   - }
230   - cfi_cmd(flash, 0xff, 0);
231   - return ERR_OK;
232   -}
233   -
234   -static int cfi_erase(flash_info_t *flash, uint32_t s_first, uint32_t s_last)
235   -{
236   - int sect;
237   - int rc = ERR_OK;
238   -
239   - for (sect = s_first; sect <= s_last; sect++) {
240   - if (flash->protect[sect] == 0) {
241   - rc = cfi_erase_oneblock(flash, sect);
242   - if (rc != ERR_OK) break;
243   - }
244   - }
245   - printf (" done\n");
246   - return rc;
247   -}
248   -
249   -static int jedec_erase(flash_info_t *flash, uint32_t s_first, uint32_t s_last)
250   -{
251   - int sect;
252   - cfi_word status;
253   - int sa = -1;
254   - int flag;
255   - ulong start, last, now;
256   -
257   - flag = disable_interrupts();
258   -
259   - cfi_cmd(flash, 0xaa, 0x555);
260   - cfi_cmd(flash, 0x55, 0x2aa);
261   - cfi_cmd(flash, 0x80, 0x555);
262   - cfi_cmd(flash, 0xaa, 0x555);
263   - cfi_cmd(flash, 0x55, 0x2aa);
264   - for ( sect = s_first; sect <= s_last; sect++) {
265   - if (flash->protect[sect] == 0) {
266   - sa = flash->start[sect] - flash->start[0];
267   - write32(flash->start[sect], 0x00300030);
268   - }
269   - }
270   - if (flag)
271   - enable_interrupts();
272   -
273   - if (sa < 0)
274   - goto DONE;
275   -
276   - udelay (1000);
277   - start = get_timer (0);
278   - last = start;
279   - for(;;) {
280   - status = cfi_read(flash, sa);
281   - if (status == CMD(0xffff))
282   - break;
283   -
284   - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
285   - printf ("Timeout\n");
286   - return ERR_TIMOUT;
287   - }
288   -
289   - if ((now - last) > 1000) {
290   - serial_putc ('.');
291   - last = now;
292   - }
293   - udelay(10);
294   - }
295   -DONE:
296   - cfi_cmd(flash, 0xf0, 0);
297   -
298   - printf (" done\n");
299   -
300   - return ERR_OK;
301   -}
302   -
303   -int flash_erase (flash_info_t *flash, int s_first, int s_last)
304   -{
305   - int sect;
306   - int prot;
307   -
308   - if ((s_first < 0) || (s_first > s_last)) {
309   - if (flash->flash_id == FLASH_UNKNOWN)
310   - printf ("- missing\n");
311   - else
312   - printf ("- no sectors to erase\n");
313   - return ERR_NOT_ERASED;
314   - }
315   - if (flash->flash_id == FLASH_UNKNOWN) {
316   - printf ("Can't erase unknown flash type - aborted\n");
317   - return ERR_NOT_ERASED;
318   - }
319   -
320   - prot = 0;
321   - for (sect = s_first; sect <= s_last; sect++)
322   - if (flash->protect[sect]) prot++;
323   -
324   - if (prot)
325   - printf ("- Warning: %d protected sectors will not be erased!\n",
326   - prot);
327   - else
328   - printf ("\n");
329   -
330   - return do_flash_erase(flash, s_first, s_last);
331   -}
332   -
333   -struct jedec_flash_info {
334   - const uint16_t mfr_id;
335   - const uint16_t dev_id;
336   - const char *name;
337   - const int DevSize;
338   - const int InterfaceDesc;
339   - const int NumEraseRegions;
340   - const ulong regions[4];
341   -};
342   -
343   -#define ERASEINFO(size,blocks) (size<<8)|(blocks-1)
344   -
345   -#define SIZE_1MiB 20
346   -#define SIZE_2MiB 21
347   -#define SIZE_4MiB 22
348   -
349   -static const struct jedec_flash_info jedec_table[] = {
350   - {
351   - mfr_id: (uint16_t)AMD_MANUFACT,
352   - dev_id: (uint16_t)AMD_ID_LV800T,
353   - name: "AMD AM29LV800T",
354   - DevSize: SIZE_1MiB,
355   - NumEraseRegions: 4,
356   - regions: {ERASEINFO(0x10000,15),
357   - ERASEINFO(0x08000,1),
358   - ERASEINFO(0x02000,2),
359   - ERASEINFO(0x04000,1)
360   - }
361   - }, {
362   - mfr_id: (uint16_t)AMD_MANUFACT,
363   - dev_id: (uint16_t)AMD_ID_LV800B,
364   - name: "AMD AM29LV800B",
365   - DevSize: SIZE_1MiB,
366   - NumEraseRegions: 4,
367   - regions: {ERASEINFO(0x10000,15),
368   - ERASEINFO(0x08000,1),
369   - ERASEINFO(0x02000,2),
370   - ERASEINFO(0x04000,1)
371   - }
372   - }, {
373   - mfr_id: (uint16_t)AMD_MANUFACT,
374   - dev_id: (uint16_t)AMD_ID_LV160T,
375   - name: "AMD AM29LV160T",
376   - DevSize: SIZE_2MiB,
377   - NumEraseRegions: 4,
378   - regions: {ERASEINFO(0x10000,31),
379   - ERASEINFO(0x08000,1),
380   - ERASEINFO(0x02000,2),
381   - ERASEINFO(0x04000,1)
382   - }
383   - }, {
384   - mfr_id: (uint16_t)AMD_MANUFACT,
385   - dev_id: (uint16_t)AMD_ID_LV160B,
386   - name: "AMD AM29LV160B",
387   - DevSize: SIZE_2MiB,
388   - NumEraseRegions: 4,
389   - regions: {ERASEINFO(0x04000,1),
390   - ERASEINFO(0x02000,2),
391   - ERASEINFO(0x08000,1),
392   - ERASEINFO(0x10000,31)
393   - }
394   - }, {
395   - mfr_id: (uint16_t)AMD_MANUFACT,
396   - dev_id: (uint16_t)AMD_ID_LV320T,
397   - name: "AMD AM29LV320T",
398   - DevSize: SIZE_4MiB,
399   - NumEraseRegions: 2,
400   - regions: {ERASEINFO(0x10000,63),
401   - ERASEINFO(0x02000,8)
402   - }
403   -
404   - }, {
405   - mfr_id: (uint16_t)AMD_MANUFACT,
406   - dev_id: (uint16_t)AMD_ID_LV320B,
407   - name: "AMD AM29LV320B",
408   - DevSize: SIZE_4MiB,
409   - NumEraseRegions: 2,
410   - regions: {ERASEINFO(0x02000,8),
411   - ERASEINFO(0x10000,63)
412   - }
413   - }
414   -};
415   -
416   -static ulong cfi_init(uint32_t base, flash_info_t *flash)
417   -{
418   - int sector;
419   - int block;
420   - int block_count;
421   - int offset = 0;
422   - int reverse = 0;
423   - int primary;
424   - int mfr_id;
425   - int dev_id;
426   -
427   - flash->start[0] = base;
428   - cfi_cmd(flash, 0xF0, 0);
429   - cfi_cmd(flash, 0x98, 0);
430   - if ( !( cfi_read_query(flash, 0x10) == 'Q' &&
431   - cfi_read_query(flash, 0x11) == 'R' &&
432   - cfi_read_query(flash, 0x12) == 'Y' )) {
433   - cfi_cmd(flash, 0xff, 0);
434   - return 0;
435   - }
436   -
437   - flash->size = 1 << cfi_read_query(flash, 0x27);
438   - flash->size *= 4;
439   - block_count = cfi_read_query(flash, 0x2c);
440   - primary = cfi_read_query(flash, 0x15);
441   - if ( cfi_read_query(flash, primary + 4) == 0x30)
442   - reverse = (cfi_read_query(flash, 0x1) & 0x01);
443   - else
444   - reverse = (cfi_read_query(flash, primary+15) == 3);
445   -
446   - flash->sector_count = 0;
447   -
448   - for ( block = reverse ? block_count - 1 : 0;
449   - reverse ? block >= 0 : block < block_count;
450   - reverse ? block-- : block ++) {
451   - int sector_size =
452   - (cfi_read_query(flash, 0x2d + block*4+2) |
453   - (cfi_read_query(flash, 0x2d + block*4+3) << 8)) << 8;
454   - int sector_count =
455   - (cfi_read_query(flash, 0x2d + block*4+0) |
456   - (cfi_read_query(flash, 0x2d + block*4+1) << 8)) + 1;
457   - for(sector = 0; sector < sector_count; sector++) {
458   - flash->start[flash->sector_count++] = base + offset;
459   - offset += sector_size * 4;
460   - }
461   - }
462   - mfr_id = cfi_read_query(flash, 0x00);
463   - dev_id = cfi_read_query(flash, 0x01);
464   -
465   - cfi_cmd(flash, 0xff, 0);
466   -
467   - flash->flash_id = (mfr_id << 16) | dev_id;
468   -
469   - for (sector = 0; sector < flash->sector_count; sector++) {
470   - write32(flash->start[sector], 0x00600060);
471   - write32(flash->start[sector], 0x00d000d0);
472   - }
473   - cfi_cmd(flash, 0xff, 0);
474   -
475   - for (sector = 0; sector < flash->sector_count; sector++)
476   - flash->protect[sector] = 0;
477   -
478   - do_flash_erase = cfi_erase;
479   - write_dword = cfi_write_dword;
480   -
481   - return flash->size;
482   -}
483   -
484   -static ulong jedec_init(unsigned long base, flash_info_t *flash)
485   -{
486   - int i;
487   - int block, block_count;
488   - int sector, offset;
489   - int mfr_id, dev_id;
490   - flash->start[0] = base;
491   - cfi_cmd(flash, 0xF0, 0x000);
492   - cfi_cmd(flash, 0xAA, 0x555);
493   - cfi_cmd(flash, 0x55, 0x2AA);
494   - cfi_cmd(flash, 0x90, 0x555);
495   - mfr_id = cfi_read_query(flash, 0x000);
496   - dev_id = cfi_read_query(flash, 0x0001);
497   - cfi_cmd(flash, 0xf0, 0x000);
498   -
499   - for(i=0; i<sizeof(jedec_table)/sizeof(struct jedec_flash_info); i++) {
500   - if((jedec_table[i].mfr_id == mfr_id) &&
501   - (jedec_table[i].dev_id == dev_id)) {
502   -
503   - flash->flash_id = (mfr_id << 16) | dev_id;
504   - flash->size = 1 << jedec_table[0].DevSize;
505   - flash->size *= 4;
506   - block_count = jedec_table[i].NumEraseRegions;
507   - offset = 0;
508   - flash->sector_count = 0;
509   - for (block = 0; block < block_count; block++) {
510   - int sector_size = jedec_table[i].regions[block];
511   - int sector_count = (sector_size & 0xff) + 1;
512   - sector_size >>= 8;
513   - for (sector=0; sector<sector_count; sector++) {
514   - flash->start[flash->sector_count++] =
515   - base + offset;
516   - offset += sector_size * 4;
517   - }
518   - }
519   - break;
520   - }
521   - }
522   -
523   - for (sector = 0; sector < flash->sector_count; sector++)
524   - flash->protect[sector] = 0;
525   -
526   - do_flash_erase = jedec_erase;
527   - write_dword = jedec_write_dword;
528   -
529   - return flash->size;
530   -}
531   -
532   -inline void mtibat1u(unsigned int x)
533   -{
534   - __asm__ __volatile__ ("mtspr 530, %0" :: "r" (x));
535   -}
536   -
537   -inline void mtibat1l(unsigned int x)
538   -{
539   - __asm__ __volatile__ ("mtspr 531, %0" :: "r" (x));
540   -}
541   -
542   -inline void mtdbat1u(unsigned int x)
543   -{
544   - __asm__ __volatile__ ("mtspr 538, %0" :: "r" (x));
545   -}
546   -
547   -inline void mtdbat1l(unsigned int x)
548   -{
549   - __asm__ __volatile__ ("mtspr 539, %0" :: "r" (x));
550   -}
551   -
552   -unsigned long flash_init (void)
553   -{
554   - unsigned long size = 0;
555   - int i;
556   - unsigned int msr;
557   -
558   - /* BAT1 */
559   - CONFIG_WRITE_WORD(ERCR3, 0x0C00000C);
560   - CONFIG_WRITE_WORD(ERCR4, 0x0800000C);
561   - msr = get_msr();
562   - set_msr(msr & ~(MSR_IR | MSR_DR));
563   - mtibat1l(0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
564   - mtibat1u(0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
565   - mtdbat1l(0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
566   - mtdbat1u(0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
567   - set_msr(msr);
568   -
569   - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
570   - flash_info[i].flash_id = FLASH_UNKNOWN;
571   - size = cfi_init(FLASH_BASE0_PRELIM, &flash_info[0]);
572   - if (!size)
573   - size = jedec_init(FLASH_BASE0_PRELIM, &flash_info[0]);
574   -
575   - if (flash_info[0].flash_id == FLASH_UNKNOWN)
576   - printf ("# Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n",
577   - size, size<<20);
578   -
579   - return size;
580   -}
581   -
582   -void flash_print_info (flash_info_t *flash)
583   -{
584   - int i;
585   - int k;
586   - int size;
587   - int erased;
588   - volatile unsigned long *p;
589   -
590   - if (flash->flash_id == FLASH_UNKNOWN) {
591   - printf ("missing or unknown FLASH type\n");
592   - flash_init();
593   - }
594   -
595   - if (flash->flash_id == FLASH_UNKNOWN) {
596   - printf ("missing or unknown FLASH type\n");
597   - return;
598   - }
599   -
600   - switch (((flash->flash_id) >> 16) & 0xff) {
601   - case 0x01:
602   - printf ("AMD ");
603   - break;
604   - case 0x04:
605   - printf("FUJITSU ");
606   - break;
607   - case 0x20:
608   - printf("STM ");
609   - break;
610   - case 0xBF:
611   - printf("SST ");
612   - break;
613   - case 0x89:
614   - case 0xB0:
615   - printf("INTEL ");
616   - break;
617   - default:
618   - printf ("Unknown Vendor ");
619   - break;
620   - }
621   -
622   - switch ((flash->flash_id) & 0xffff) {
623   - case (uint16_t)AMD_ID_LV800T:
624   - printf ("AM29LV800T\n");
625   - break;
626   - case (uint16_t)AMD_ID_LV800B:
627   - printf ("AM29LV800B\n");
628   - break;
629   - case (uint16_t)AMD_ID_LV160T:
630   - printf ("AM29LV160T\n");
631   - break;
632   - case (uint16_t)AMD_ID_LV160B:
633   - printf ("AM29LV160B\n");
634   - break;
635   - case (uint16_t)AMD_ID_LV320T:
636   - printf ("AM29LV320T\n");
637   - break;
638   - case (uint16_t)AMD_ID_LV320B:
639   - printf ("AM29LV320B\n");
640   - break;
641   - case (uint16_t)INTEL_ID_28F800C3T:
642   - printf ("28F800C3T\n");
643   - break;
644   - case (uint16_t)INTEL_ID_28F800C3B:
645   - printf ("28F800C3B\n");
646   - break;
647   - case (uint16_t)INTEL_ID_28F160C3T:
648   - printf ("28F160C3T\n");
649   - break;
650   - case (uint16_t)INTEL_ID_28F160C3B:
651   - printf ("28F160C3B\n");
652   - break;
653   - case (uint16_t)INTEL_ID_28F320C3T:
654   - printf ("28F320C3T\n");
655   - break;
656   - case (uint16_t)INTEL_ID_28F320C3B:
657   - printf ("28F320C3B\n");
658   - break;
659   - case (uint16_t)INTEL_ID_28F640C3T:
660   - printf ("28F640C3T\n");
661   - break;
662   - case (uint16_t)INTEL_ID_28F640C3B:
663   - printf ("28F640C3B\n");
664   - break;
665   - default:
666   - printf ("Unknown Chip Type\n");
667   - break;
668   - }
669   -
670   - if (flash->size >= (1 << 20)) {
671   - printf (" Size: %ld MB in %d Sectors\n",
672   - flash->size >> 20, flash->sector_count);
673   - } else {
674   - printf (" Size: %ld kB in %d Sectors\n",
675   - flash->size >> 10, flash->sector_count);
676   - }
677   -
678   - printf (" Sector Start Addresses:");
679   - for (i = 0; i < flash->sector_count; ++i) {
680   - /* Check if whole sector is erased*/
681   - if (i != (flash->sector_count-1))
682   - size = flash->start[i+1] - flash->start[i];
683   - else
684   - size = flash->start[0] + flash->size - flash->start[i];
685   -
686   - erased = 1;
687   - p = (volatile unsigned long *)flash->start[i];
688   - size = size >> 2; /* divide by 4 for longword access */
689   - for (k=0; k<size; k++) {
690   - if (*p++ != 0xffffffff) {
691   - erased = 0;
692   - break;
693   - }
694   - }
695   -
696   - if ((i % 5) == 0)
697   - printf ("\n ");
698   -
699   - printf (" %08lX%s%s",
700   - flash->start[i],
701   - erased ? " E" : " ",
702   - flash->protect[i] ? "RO " : " ");
703   - }
704   - printf ("\n");
705   -}
board/etin/debris/phantom.c
View file @ 7edb1f7
1   -/*
2   - * board/eva/phantom.c
3   - *
4   - * Phantom RTC device driver for EVA
5   - *
6   - * Author: Sangmoon Kim
7   - * dogoil@etinsys.com
8   - *
9   - * Copyright 2002 Etinsys Inc.
10   - *
11   - * SPDX-License-Identifier: GPL-2.0+
12   - */
13   -
14   -#include <common.h>
15   -#include <command.h>
16   -#include <rtc.h>
17   -
18   -#if defined(CONFIG_CMD_DATE)
19   -
20   -#define RTC_BASE (CONFIG_SYS_NVRAM_BASE_ADDR + 0x7fff8)
21   -
22   -#define RTC_YEAR ( RTC_BASE + 7 )
23   -#define RTC_MONTH ( RTC_BASE + 6 )
24   -#define RTC_DAY_OF_MONTH ( RTC_BASE + 5 )
25   -#define RTC_DAY_OF_WEEK ( RTC_BASE + 4 )
26   -#define RTC_HOURS ( RTC_BASE + 3 )
27   -#define RTC_MINUTES ( RTC_BASE + 2 )
28   -#define RTC_SECONDS ( RTC_BASE + 1 )
29   -#define RTC_CENTURY ( RTC_BASE + 0 )
30   -
31   -#define RTC_CONTROLA RTC_CENTURY
32   -#define RTC_CONTROLB RTC_SECONDS
33   -#define RTC_CONTROLC RTC_DAY_OF_WEEK
34   -
35   -#define RTC_CA_WRITE 0x80
36   -#define RTC_CA_READ 0x40
37   -
38   -#define RTC_CB_OSC_DISABLE 0x80
39   -
40   -#define RTC_CC_BATTERY_FLAG 0x80
41   -#define RTC_CC_FREQ_TEST 0x40
42   -
43   -
44   -static int phantom_flag = -1;
45   -static int century_flag = -1;
46   -
47   -static uchar rtc_read(unsigned int addr)
48   -{
49   - return *(volatile unsigned char *)(addr);
50   -}
51   -
52   -static void rtc_write(unsigned int addr, uchar val)
53   -{
54   - *(volatile unsigned char *)(addr) = val;
55   -}
56   -
57   -static unsigned char phantom_rtc_sequence[] = {
58   - 0xc5, 0x3a, 0xa3, 0x5c, 0xc5, 0x3a, 0xa3, 0x5c
59   -};
60   -
61   -static unsigned char* phantom_rtc_read(int addr, unsigned char rtc[8])
62   -{
63   - int i, j;
64   - unsigned char v;
65   - unsigned char save = rtc_read(addr);
66   -
67   - for (j = 0; j < 8; j++) {
68   - v = phantom_rtc_sequence[j];
69   - for (i = 0; i < 8; i++) {
70   - rtc_write(addr, v & 1);
71   - v >>= 1;
72   - }
73   - }
74   - for (j = 0; j < 8; j++) {
75   - v = 0;
76   - for (i = 0; i < 8; i++) {
77   - if(rtc_read(addr) & 1)
78   - v |= 1 << i;
79   - }
80   - rtc[j] = v;
81   - }
82   - rtc_write(addr, save);
83   - return rtc;
84   -}
85   -
86   -static void phantom_rtc_write(int addr, unsigned char rtc[8])
87   -{
88   - int i, j;
89   - unsigned char v;
90   - unsigned char save = rtc_read(addr);
91   - for (j = 0; j < 8; j++) {
92   - v = phantom_rtc_sequence[j];
93   - for (i = 0; i < 8; i++) {
94   - rtc_write(addr, v & 1);
95   - v >>= 1;
96   - }
97   - }
98   - for (j = 0; j < 8; j++) {
99   - v = rtc[j];
100   - for (i = 0; i < 8; i++) {
101   - rtc_write(addr, v & 1);
102   - v >>= 1;
103   - }
104   - }
105   - rtc_write(addr, save);
106   -}
107   -
108   -static int get_phantom_flag(void)
109   -{
110   - int i;
111   - unsigned char rtc[8];
112   -
113   - phantom_rtc_read(RTC_BASE, rtc);
114   -
115   - for(i = 1; i < 8; i++) {
116   - if (rtc[i] != rtc[0])
117   - return 1;
118   - }
119   - return 0;
120   -}
121   -
122   -void rtc_reset(void)
123   -{
124   - if (phantom_flag < 0)
125   - phantom_flag = get_phantom_flag();
126   -
127   - if (phantom_flag) {
128   - unsigned char rtc[8];
129   - phantom_rtc_read(RTC_BASE, rtc);
130   - if(rtc[4] & 0x30) {
131   - printf( "real-time-clock was stopped. Now starting...\n" );
132   - rtc[4] &= 0x07;
133   - phantom_rtc_write(RTC_BASE, rtc);
134   - }
135   - } else {
136   - uchar reg_a, reg_b, reg_c;
137   - reg_a = rtc_read( RTC_CONTROLA );
138   - reg_b = rtc_read( RTC_CONTROLB );
139   -
140   - if ( reg_b & RTC_CB_OSC_DISABLE )
141   - {
142   - printf( "real-time-clock was stopped. Now starting...\n" );
143   - reg_a |= RTC_CA_WRITE;
144   - reg_b &= ~RTC_CB_OSC_DISABLE;
145   - rtc_write( RTC_CONTROLA, reg_a );
146   - rtc_write( RTC_CONTROLB, reg_b );
147   - }
148   -
149   - /* make sure read/write clock register bits are cleared */
150   - reg_a &= ~( RTC_CA_WRITE | RTC_CA_READ );
151   - rtc_write( RTC_CONTROLA, reg_a );
152   -
153   - reg_c = rtc_read( RTC_CONTROLC );
154   - if (( reg_c & RTC_CC_BATTERY_FLAG ) == 0 )
155   - printf( "RTC battery low. Clock setting may not be reliable.\n");
156   - }
157   -}
158   -
159   -static int get_century_flag(void)
160   -{
161   - int flag = 0;
162   - int bcd, century;
163   - bcd = rtc_read( RTC_CENTURY );
164   - century = bcd2bin( bcd & 0x3F );
165   - rtc_write( RTC_CENTURY, bin2bcd(century+1));
166   - if (bcd == rtc_read( RTC_CENTURY ))
167   - flag = 1;
168   - rtc_write( RTC_CENTURY, bcd);
169   - return flag;
170   -}
171   -
172   -int rtc_get( struct rtc_time *tmp)
173   -{
174   - if (phantom_flag < 0)
175   - phantom_flag = get_phantom_flag();
176   -
177   - if (phantom_flag)
178   - {
179   - unsigned char rtc[8];
180   -
181   - phantom_rtc_read(RTC_BASE, rtc);
182   -
183   - tmp->tm_sec = bcd2bin(rtc[1] & 0x7f);
184   - tmp->tm_min = bcd2bin(rtc[2] & 0x7f);
185   - tmp->tm_hour = bcd2bin(rtc[3] & 0x1f);
186   - tmp->tm_wday = bcd2bin(rtc[4] & 0x7);
187   - tmp->tm_mday = bcd2bin(rtc[5] & 0x3f);
188   - tmp->tm_mon = bcd2bin(rtc[6] & 0x1f);
189   - tmp->tm_year = bcd2bin(rtc[7]) + 1900;
190   - tmp->tm_yday = 0;
191   - tmp->tm_isdst = 0;
192   -
193   - if( (rtc[3] & 0x80) && (rtc[3] & 0x40) ) tmp->tm_hour += 12;
194   - if (tmp->tm_year < 1970) tmp->tm_year += 100;
195   - } else {
196   - uchar sec, min, hour;
197   - uchar mday, wday, mon, year;
198   -
199   - int century;
200   -
201   - uchar reg_a;
202   -
203   - if (century_flag < 0)
204   - century_flag = get_century_flag();
205   -
206   - reg_a = rtc_read( RTC_CONTROLA );
207   - /* lock clock registers for read */
208   - rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_READ ));
209   -
210   - sec = rtc_read( RTC_SECONDS );
211   - min = rtc_read( RTC_MINUTES );
212   - hour = rtc_read( RTC_HOURS );
213   - mday = rtc_read( RTC_DAY_OF_MONTH );
214   - wday = rtc_read( RTC_DAY_OF_WEEK );
215   - mon = rtc_read( RTC_MONTH );
216   - year = rtc_read( RTC_YEAR );
217   - century = rtc_read( RTC_CENTURY );
218   -
219   - /* unlock clock registers after read */
220   - rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_READ ));
221   -
222   - tmp->tm_sec = bcd2bin( sec & 0x7F );
223   - tmp->tm_min = bcd2bin( min & 0x7F );
224   - tmp->tm_hour = bcd2bin( hour & 0x3F );
225   - tmp->tm_mday = bcd2bin( mday & 0x3F );
226   - tmp->tm_mon = bcd2bin( mon & 0x1F );
227   - tmp->tm_wday = bcd2bin( wday & 0x07 );
228   -
229   - if (century_flag) {
230   - tmp->tm_year = bcd2bin( year ) +
231   - ( bcd2bin( century & 0x3F ) * 100 );
232   - } else {
233   - tmp->tm_year = bcd2bin( year ) + 1900;
234   - if (tmp->tm_year < 1970) tmp->tm_year += 100;
235   - }
236   -
237   - tmp->tm_yday = 0;
238   - tmp->tm_isdst= 0;
239   - }
240   -
241   - return 0;
242   -}
243   -
244   -int rtc_set( struct rtc_time *tmp )
245   -{
246   - if (phantom_flag < 0)
247   - phantom_flag = get_phantom_flag();
248   -
249   - if (phantom_flag) {
250   - uint year;
251   - unsigned char rtc[8];
252   -
253   - year = tmp->tm_year;
254   - year -= (year < 2000) ? 1900 : 2000;
255   -
256   - rtc[0] = bin2bcd(0);
257   - rtc[1] = bin2bcd(tmp->tm_sec);
258   - rtc[2] = bin2bcd(tmp->tm_min);
259   - rtc[3] = bin2bcd(tmp->tm_hour);
260   - rtc[4] = bin2bcd(tmp->tm_wday);
261   - rtc[5] = bin2bcd(tmp->tm_mday);
262   - rtc[6] = bin2bcd(tmp->tm_mon);
263   - rtc[7] = bin2bcd(year);
264   -
265   - phantom_rtc_write(RTC_BASE, rtc);
266   - } else {
267   - uchar reg_a;
268   - if (century_flag < 0)
269   - century_flag = get_century_flag();
270   -
271   - /* lock clock registers for write */
272   - reg_a = rtc_read( RTC_CONTROLA );
273   - rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_WRITE ));
274   -
275   - rtc_write( RTC_MONTH, bin2bcd( tmp->tm_mon ));
276   -
277   - rtc_write( RTC_DAY_OF_WEEK, bin2bcd( tmp->tm_wday ));
278   - rtc_write( RTC_DAY_OF_MONTH, bin2bcd( tmp->tm_mday ));
279   - rtc_write( RTC_HOURS, bin2bcd( tmp->tm_hour ));
280   - rtc_write( RTC_MINUTES, bin2bcd( tmp->tm_min ));
281   - rtc_write( RTC_SECONDS, bin2bcd( tmp->tm_sec ));
282   -
283   - /* break year up into century and year in century */
284   - if (century_flag) {
285   - rtc_write( RTC_YEAR, bin2bcd( tmp->tm_year % 100 ));
286   - rtc_write( RTC_CENTURY, bin2bcd( tmp->tm_year / 100 ));
287   - reg_a &= 0xc0;
288   - reg_a |= bin2bcd( tmp->tm_year / 100 );
289   - } else {
290   - rtc_write(RTC_YEAR, bin2bcd(tmp->tm_year -
291   - ((tmp->tm_year < 2000) ? 1900 : 2000)));
292   - }
293   -
294   - /* unlock clock registers after read */
295   - rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_WRITE ));
296   - }
297   -
298   - return 0;
299   -}
300   -
301   -#endif
... ... @@ -1240,7 +1240,6 @@
1240 1240 Orphan powerpc mpc5xxx - matrix_vision mvbc_p MVBC_P MVBC_P:MVBC_P Andre Schwarz <andre.schwarz@matrix-vision.de>
1241 1241 Orphan powerpc mpc5xxx - matrix_vision mvsmr MVSMR - Andre Schwarz <andre.schwarz@matrix-vision.de>
1242 1242 Orphan powerpc mpc824x - - hidden_dragon HIDDEN_DRAGON - Yusdi Santoso <yusdi_santoso@adaptec.com>
1243   -Orphan powerpc mpc824x - etin - debris - Sangmoon Kim <dogoil@etinsys.com>
1244 1243 Orphan powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK - Anton Vorontsov <avorontsov@ru.mvista.com>
1245 1244 Orphan powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK_33 MPC8360ERDK:CLKIN_33MHZ Anton Vorontsov <avorontsov@ru.mvista.com>
1246 1245 Orphan powerpc mpc83xx - matrix_vision mergerbox MERGERBOX - Andre Schwarz <andre.schwarz@matrix-vision.de>
doc/README.scrapyard
Diff comments   View file @ 7edb1f7
... ... @@ -11,6 +11,7 @@
11 11  
12 12 Board Arch CPU Commit Removed Last known maintainer/contact
13 13 =================================================================================================
  14 +debris powerpc mpc824x - - Sangmoon Kim <dogoil@etinsys.com>
14 15 kvme080 powerpc mpc824x - - Sangmoon Kim <dogoil@etinsys.com>
15 16 ep8248 powerpc mpc8260 - - Yuli Barcohen <yuli@arabellasw.com>
16 17 ispan powerpc mpc8260 - - Yuli Barcohen <yuli@arabellasw.com>
include/configs/debris.h
View file @ 7edb1f7
1   -/*
2   - * (C) Copyright 2001, 2002
3   - * Sangmoon Kim, Etin Systems, dogoil@etinsys.com.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -/* ------------------------------------------------------------------------- */
9   -
10   -/*
11   - * board/config.h - configuration options, board specific
12   - */
13   -
14   -#ifndef __CONFIG_H
15   -#define __CONFIG_H
16   -
17   -#define CONFIG_SYS_TEXT_BASE 0xFFF00000
18   -
19   -/* Environments */
20   -
21   -/* bootargs */
22   -#define CONFIG_BOOTARGS \
23   - "console=ttyS0,9600 init=/linuxrc " \
24   - "root=/dev/nfs rw nfsroot=192.168.0.1:" \
25   - "/tftpboot/target " \
26   - "ip=192.168.0.2:192.168.0.1:192.168.0.1:" \
27   - "255.255.255.0:debris:eth0:none " \
28   - "mtdparts=phys:12m(root),-(kernel)"
29   -
30   -/* bootcmd */
31   -#define CONFIG_BOOTCOMMAND \
32   - "tftp 800000 pImage; " \
33   - "setenv bootargs console=ttyS0,9600 init=/linuxrc " \
34   - "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
35   - "ip=${ipaddr}:${serverip}:${gatewayip}:" \
36   - "${netmask}:${hostname}:eth0:none " \
37   - "mtdparts=phys:12m(root),-(kernel); " \
38   - "bootm 800000"
39   -
40   -/* bootdelay */
41   -#define CONFIG_BOOTDELAY 5 /* autoboot 5s */
42   -
43   -/* baudrate */
44   -#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
45   -
46   -/* loads_echo */
47   -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
48   -
49   -/* ethaddr */
50   -#undef CONFIG_ETHADDR
51   -
52   -/* eth2addr */
53   -#undef CONFIG_ETH2ADDR
54   -
55   -/* eth3addr */
56   -#undef CONFIG_ETH3ADDR
57   -
58   -/* ipaddr */
59   -#define CONFIG_IPADDR 192.168.0.2
60   -
61   -/* serverip */
62   -#define CONFIG_SERVERIP 192.168.0.1
63   -
64   -/* autoload */
65   -#undef CONFIG_SYS_AUTOLOAD
66   -
67   -/* rootpath */
68   -#define CONFIG_ROOTPATH "/tftpboot/target"
69   -
70   -/* gatewayip */
71   -#define CONFIG_GATEWAYIP 192.168.0.1
72   -
73   -/* netmask */
74   -#define CONFIG_NETMASK 255.255.255.0
75   -
76   -/* hostname */
77   -#define CONFIG_HOSTNAME debris
78   -
79   -/* bootfile */
80   -#define CONFIG_BOOTFILE "pImage"
81   -
82   -/* loadaddr */
83   -#define CONFIG_LOADADDR 800000
84   -
85   -/* preboot */
86   -#undef CONFIG_PREBOOT
87   -
88   -/* clocks_in_mhz */
89   -#undef CONFIG_CLOCKS_IN_MHZ
90   -
91   -
92   -/*
93   - * High Level Configuration Options
94   - * (easy to change)
95   - */
96   -
97   -#define CONFIG_MPC8245 1
98   -#define CONFIG_DEBRIS 1
99   -
100   -#if 0
101   -#define USE_DINK32 1
102   -#else
103   -#undef USE_DINK32
104   -#endif
105   -
106   -#define CONFIG_CONS_INDEX 1
107   -#define CONFIG_BAUDRATE 9600
108   -#define CONFIG_DRAM_SPEED 100 /* MHz */
109   -
110   -
111   -/*
112   - * BOOTP options
113   - */
114   -#define CONFIG_BOOTP_BOOTFILESIZE
115   -#define CONFIG_BOOTP_BOOTPATH
116   -#define CONFIG_BOOTP_GATEWAY
117   -#define CONFIG_BOOTP_HOSTNAME
118   -
119   -
120   -/*
121   - * Command line configuration.
122   - */
123   -#include <config_cmd_default.h>
124   -
125   -#define CONFIG_CMD_ASKENV
126   -#define CONFIG_CMD_CACHE
127   -#define CONFIG_CMD_DATE
128   -#define CONFIG_CMD_DHCP
129   -#define CONFIG_CMD_DIAG
130   -#define CONFIG_CMD_EEPROM
131   -#define CONFIG_CMD_ELF
132   -#define CONFIG_CMD_I2C
133   -#define CONFIG_CMD_JFFS2
134   -#define CONFIG_CMD_KGDB
135   -#define CONFIG_CMD_PCI
136   -#define CONFIG_CMD_PING
137   -#define CONFIG_CMD_SAVES
138   -#define CONFIG_CMD_SDRAM
139   -
140   -
141   -/*
142   - * Miscellaneous configurable options
143   - */
144   -#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
145   -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
146   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
147   -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
148   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
149   -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
150   -
151   -/*-----------------------------------------------------------------------
152   - * PCI stuff
153   - *-----------------------------------------------------------------------
154   - */
155   -#define CONFIG_PCI /* include pci support */
156   -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
157   -#define CONFIG_PCI_PNP
158   -
159   -#define CONFIG_EEPRO100
160   -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
161   -#define CONFIG_EEPRO100_SROM_WRITE
162   -
163   -#define PCI_ENET0_IOADDR 0x80000000
164   -#define PCI_ENET0_MEMADDR 0x80000000
165   -#define PCI_ENET1_IOADDR 0x81000000
166   -#define PCI_ENET1_MEMADDR 0x81000000
167   -/*-----------------------------------------------------------------------
168   - * Start addresses for the final memory configuration
169   - * (Set up by the startup code)
170   - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
171   - */
172   -#define CONFIG_SYS_SDRAM_BASE 0x00000000
173   -#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
174   -#define CONFIG_VERY_BIG_RAM
175   -
176   -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
177   -
178   -#if defined (USE_DINK32)
179   -#define CONFIG_SYS_MONITOR_LEN 0x00040000
180   -#define CONFIG_SYS_MONITOR_BASE 0x00090000
181   -#define CONFIG_SYS_RAMBOOT 1
182   -#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
183   -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
184   -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
185   -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
186   -#else
187   -#undef CONFIG_SYS_RAMBOOT
188   -#define CONFIG_SYS_MONITOR_LEN 0x00040000
189   -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
190   -
191   -
192   -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
193   -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
194   -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
195   -
196   -#endif
197   -
198   -#define CONFIG_SYS_FLASH_BASE 0x7C000000
199   -#define CONFIG_SYS_FLASH_SIZE (16*1024*1024) /* debris has tiny eeprom */
200   -
201   -#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
202   -
203   -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
204   -#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
205   -
206   -#define CONFIG_SYS_EUMB_ADDR 0xFC000000
207   -
208   -#define CONFIG_SYS_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */
209   -#define CONFIG_SYS_FLASH_RANGE_SIZE 0x01000000
210   -#define FLASH_BASE0_PRELIM 0x7C000000 /* debris flash */
211   -
212   -/*
213   - * JFFS2 partitions
214   - *
215   - */
216   -/* No command line, one static partition, whole device */
217   -#undef CONFIG_CMD_MTDPARTS
218   -#define CONFIG_JFFS2_DEV "nor0"
219   -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
220   -#define CONFIG_JFFS2_PART_OFFSET 0x00000000
221   -
222   -/* mtdparts command line support */
223   -
224   -/* Use first bank for JFFS2, second bank contains U-Boot.
225   - *
226   - * Note: fake mtd_id's used, no linux mtd map file.
227   - */
228   -/*
229   -#define CONFIG_CMD_MTDPARTS
230   -#define MTDIDS_DEFAULT "nor0=debris-0"
231   -#define MTDPARTS_DEFAULT "mtdparts=debris-0:-(jffs2)"
232   -*/
233   -
234   -#define CONFIG_ENV_IS_IN_NVRAM 1
235   -#define CONFIG_ENV_OVERWRITE 1
236   -#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE 1
237   -#define CONFIG_ENV_ADDR 0xFF000000 /* right at the start of NVRAM */
238   -#define CONFIG_ENV_SIZE 0x400 /* Size of the Environment - 8K */
239   -#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
240   -
241   -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xff000000
242   -
243   -/*
244   - * CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_VXWORKS_OFFS =
245   - * NV_RAM_ADDRS + NV_BOOT_OFFSET + NV_ENET_OFFSET
246   - */
247   -#define CONFIG_SYS_NVRAM_VXWORKS_OFFS 0x6900
248   -
249   -/*
250   - * select i2c support configuration
251   - *
252   - * Supported configurations are {none, software, hardware} drivers.
253   - * If the software driver is chosen, there are some additional
254   - * configuration items that the driver uses to drive the port pins.
255   - */
256   -#define CONFIG_HARD_I2C 1 /* To enable I2C support */
257   -#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
258   -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
259   -#define CONFIG_SYS_I2C_SLAVE 0x7F
260   -
261   -#ifdef CONFIG_SYS_I2C_SOFT
262   -#error "Soft I2C is not configured properly. Please review!"
263   -#define CONFIG_SYS_I2C
264   -#define CONFIG_SYS_I2C_SOFT_SPEED 50000
265   -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
266   -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
267   -#define I2C_ACTIVE (iop->pdir |= 0x00010000)
268   -#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
269   -#define I2C_READ ((iop->pdat & 0x00010000) != 0)
270   -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
271   - else iop->pdat &= ~0x00010000
272   -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
273   - else iop->pdat &= ~0x00020000
274   -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
275   -#endif /* CONFIG_SYS_I2C_SOFT */
276   -
277   -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
278   -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
279   -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
280   -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
281   -
282   -#define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM }
283   -
284   -/*-----------------------------------------------------------------------
285   - * Definitions for initial stack pointer and data area (in DPRAM)
286   - */
287   -
288   -/*
289   - * NS16550 Configuration
290   - */
291   -#define CONFIG_SYS_NS16550
292   -#define CONFIG_SYS_NS16550_SERIAL
293   -
294   -#define CONFIG_SYS_NS16550_REG_SIZE 1
295   -
296   -#define CONFIG_SYS_NS16550_CLK 7372800
297   -
298   -#define CONFIG_SYS_NS16550_COM1 0xFF080000
299   -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_NS16550_COM1 + 8)
300   -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_NS16550_COM1 + 16)
301   -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_NS16550_COM1 + 24)
302   -
303   -/*
304   - * Low Level Configuration Settings
305   - * (address mappings, register initial values, etc.)
306   - * You should know what you are doing if you make changes here.
307   - */
308   -
309   -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
310   -#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3
311   -
312   -#define CONFIG_SYS_DLL_EXTEND 0x00
313   -#define CONFIG_SYS_PCI_HOLD_DEL 0x20
314   -
315   -#define CONFIG_SYS_ROMNAL 15 /* rom/flash next access time */
316   -#define CONFIG_SYS_ROMFAL 31 /* rom/flash access time */
317   -
318   -#define CONFIG_SYS_REFINT 430 /* # of clocks between CBR refresh cycles */
319   -
320   -#define CONFIG_SYS_DBUS_SIZE2 1 /* set for 8-bit RCS1, clear for 32,64 */
321   -
322   -/* the following are for SDRAM only*/
323   -#define CONFIG_SYS_BSTOPRE 121 /* Burst To Precharge, sets open page interval */
324   -#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */
325   -#define CONFIG_SYS_RDLAT 4 /* data latency from read command */
326   -#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */
327   -#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
328   -#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */
329   -#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
330   -#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
331   -#if 0
332   -#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */
333   -#endif
334   -
335   -#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
336   -#define CONFIG_SYS_EXTROM 1
337   -#define CONFIG_SYS_REGDIMM 0
338   -
339   -
340   -/* memory bank settings*/
341   -/*
342   - * only bits 20-29 are actually used from these vales to set the
343   - * start/end address the upper two bits will be 0, and the lower 20
344   - * bits will be set to 0x00000 for a start address, or 0xfffff for an
345   - * end address
346   - */
347   -#define CONFIG_SYS_BANK0_START 0x00000000
348   -#define CONFIG_SYS_BANK0_END (0x4000000 - 1)
349   -#define CONFIG_SYS_BANK0_ENABLE 1
350   -#define CONFIG_SYS_BANK1_START 0x04000000
351   -#define CONFIG_SYS_BANK1_END (0x8000000 - 1)
352   -#define CONFIG_SYS_BANK1_ENABLE 1
353   -#define CONFIG_SYS_BANK2_START 0x3ff00000
354   -#define CONFIG_SYS_BANK2_END 0x3fffffff
355   -#define CONFIG_SYS_BANK2_ENABLE 0
356   -#define CONFIG_SYS_BANK3_START 0x3ff00000
357   -#define CONFIG_SYS_BANK3_END 0x3fffffff
358   -#define CONFIG_SYS_BANK3_ENABLE 0
359   -#define CONFIG_SYS_BANK4_START 0x00000000
360   -#define CONFIG_SYS_BANK4_END 0x00000000
361   -#define CONFIG_SYS_BANK4_ENABLE 0
362   -#define CONFIG_SYS_BANK5_START 0x00000000
363   -#define CONFIG_SYS_BANK5_END 0x00000000
364   -#define CONFIG_SYS_BANK5_ENABLE 0
365   -#define CONFIG_SYS_BANK6_START 0x00000000
366   -#define CONFIG_SYS_BANK6_END 0x00000000
367   -#define CONFIG_SYS_BANK6_ENABLE 0
368   -#define CONFIG_SYS_BANK7_START 0x00000000
369   -#define CONFIG_SYS_BANK7_END 0x00000000
370   -#define CONFIG_SYS_BANK7_ENABLE 0
371   -/*
372   - * Memory bank enable bitmask, specifying which of the banks defined above
373   - are actually present. MSB is for bank #7, LSB is for bank #0.
374   - */
375   -#define CONFIG_SYS_BANK_ENABLE 0x01
376   -
377   -#define CONFIG_SYS_ODCR 0x75 /* configures line driver impedances, */
378   - /* see 8240 book for bit definitions */
379   -#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
380   - /* currently accessed page in memory */
381   - /* see 8240 book for details */
382   -
383   -/* SDRAM 0 - 256MB */
384   -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
385   -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
386   -
387   -/* stack in DCACHE @ 1GB (no backing mem) */
388   -#if defined(USE_DINK32)
389   -#define CONFIG_SYS_IBAT1L (0x40000000 | BATL_PP_00 )
390   -#define CONFIG_SYS_IBAT1U (0x40000000 | BATU_BL_128K )
391   -#else
392   -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
393   -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
394   -#endif
395   -
396   -/* PCI memory */
397   -#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
398   -#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
399   -
400   -/* Flash, config addrs, etc */
401   -#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
402   -#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
403   -
404   -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
405   -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
406   -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
407   -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
408   -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
409   -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
410   -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
411   -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
412   -
413   -/*
414   - * For booting Linux, the board info and command line data
415   - * have to be in the first 8 MB of memory, since this is
416   - * the maximum mapped by the Linux kernel during initialization.
417   - */
418   -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
419   -/*-----------------------------------------------------------------------
420   - * FLASH organization
421   - */
422   -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
423   -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
424   -
425   -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
426   -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
427   -
428   -/*-----------------------------------------------------------------------
429   - * Cache Configuration
430   - */
431   -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */
432   -#if defined(CONFIG_CMD_KGDB)
433   -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
434   -#endif
435   -
436   -/* values according to the manual */
437   -
438   -#define CONFIG_DRAM_50MHZ 1
439   -#define CONFIG_SDRAM_50MHZ
440   -
441   -#define CONFIG_DISK_SPINUP_TIME 1000000
442   -
443   -#endif /* __CONFIG_H */