MLK-12791 mx6qpsabresd: Change ENET TXCLK clock from PLL

In u-boot, i.MX6QP sabresd board uses 125Mhz ref clock from PHY, While kernel uses the clock from internal PLL by setting GPR5 bit 9. When doing warm reset in kernel, the GPR regigster is not reset, so the clock source still is the PLL. This causes ENET in u-boot can't work. In this patch, we change the u-boot to use internal PLL to align with kernel for i.MX6QP. This also fixes the ENET issue after kernel warm reset. Signed-off-by: Ye Li <ye.li@nxp.com>

MLK-12791 mx6qpsabresd: Change ENET TXCLK clock from PLL
In u-boot, i.MX6QP sabresd board uses 125Mhz ref clock from PHY, While kernel uses the clock from internal PLL by setting GPR5 bit 9. When doing warm reset in kernel, the GPR regigster is not reset, so the clock source still is the PLL. This causes ENET in u-boot can't work. In this patch, we change the u-boot to use internal PLL to align with kernel for i.MX6QP. This also fixes the ENET issue after kernel warm reset. Signed-off-by: Ye Li <ye.li@nxp.com>
Ye Li · Eric Lee · Eric Lee · Eric Lee · Eric Lee · Eric Lee
1 parent 7004df470b
Showing 1 changed file with 10 additions and 0 deletions Side-by-side Diff
board/freescale/mx6sabresd/mx6sabresd.c
@@ -805,6 +805,16 @@
  
 int board_eth_init(bd_t *bis)
 {
+	if (is_mx6dqp()) {
+		int ret;
+
+		/* select ENET MAC0 TX clock from PLL */
+		imx_iomux_set_gpr_register(5, 9, 1, 1);
+		ret = enable_fec_anatop_clock(0, ENET_125MHZ);
+		if (ret)
+		    printf("Error fec anatop clock settings!\n");
+	}
+
 	setup_iomux_enet();
 	setup_pcie();
...	...	@@ -805,6 +805,16 @@
805	805
806	806	int board_eth_init(bd_t *bis)
807	807	{
	808	+ if (is_mx6dqp()) {
	809	+ int ret;
	810	+
	811	+ /* select ENET MAC0 TX clock from PLL */
	812	+ imx_iomux_set_gpr_register(5, 9, 1, 1);
	813	+ ret = enable_fec_anatop_clock(0, ENET_125MHZ);
	814	+ if (ret)
	815	+ printf("Error fec anatop clock settings!\n");
	816	+ }
	817	+
808	818	setup_iomux_enet();
809	819	setup_pcie();
810	820