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Commit 807abb18f1376bcd674540e374f2ab7503caea51

Authored by Marek Vasut
1 parent abb25f4e95
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

arm: socfpga: sysmgr: Add FPGA bits into system manager 

Add missing system manager bits from Altera U-Boot to make the code
comparable. These are the bits which depend on the FPGA manager.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

Showing 1 changed file with 39 additions and 0 deletions Side-by-side Diff

arch/arm/cpu/armv7/socfpga/system_manager.c
Diff comments   View file @ 807abb1
... ... @@ -15,6 +15,43 @@
15 15 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
16 16  
17 17 /*
  18 + * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
  19 + * The value is not wrote to SYSMGR.FPGAINTF.MODULE but
  20 + * CONFIG_SYSMGR_ISWGRP_HANDOFF.
  21 + */
  22 +static void populate_sysmgr_fpgaintf_module(void)
  23 +{
  24 + uint32_t handoff_val = 0;
  25 +
  26 + /* ISWGRP_HANDOFF_FPGAINTF */
  27 + writel(0, &sysmgr_regs->iswgrp_handoff[2]);
  28 +
  29 + /* Enable the signal for those HPS peripherals that use FPGA. */
  30 + if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA)
  31 + handoff_val |= SYSMGR_FPGAINTF_NAND;
  32 + if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
  33 + handoff_val |= SYSMGR_FPGAINTF_EMAC1;
  34 + if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA)
  35 + handoff_val |= SYSMGR_FPGAINTF_SDMMC;
  36 + if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
  37 + handoff_val |= SYSMGR_FPGAINTF_EMAC0;
  38 + if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
  39 + handoff_val |= SYSMGR_FPGAINTF_SPIM0;
  40 + if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
  41 + handoff_val |= SYSMGR_FPGAINTF_SPIM1;
  42 +
  43 + /* populate (not writing) the value for SYSMGR.FPGAINTF.MODULE
  44 + based on pinmux setting */
  45 + setbits_le32(&sysmgr_regs->iswgrp_handoff[2], handoff_val);
  46 +
  47 + handoff_val = readl(&sysmgr_regs->iswgrp_handoff[2]);
  48 + if (fpgamgr_test_fpga_ready()) {
  49 + /* Enable the required signals only */
  50 + writel(handoff_val, &sysmgr_regs->fpgaintfgrp_module);
  51 + }
  52 +}
  53 +
  54 +/*
18 55 * Configure all the pin muxes
19 56 */
20 57 void sysmgr_pinmux_init(void)
... ... @@ -26,5 +63,7 @@
26 63 writel(sys_mgr_init_table[i], regs);
27 64 regs += sizeof(regs);
28 65 }
  66 +
  67 + populate_sysmgr_fpgaintf_module();
29 68 }