Eric Lee / smarc-uboot

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Commit 827e6a7e0dc0c457a51cdd8b1b81d4e895289046

Authored by Ley Foon Tan
Committed by Marek Vasut
1 parent d83b8193ad
Exists in smarc_8mq_lf_v2020.04 and in 18 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

arm: socfpga: Add reset driver support for Arria 10 

Add reset driver support for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>

Showing 5 changed files with 644 additions and 0 deletions Side-by-side Diff

arch/arm/mach-socfpga/Makefile
Diff comments   View file @ 827e6a7
... ... @@ -10,6 +10,8 @@
10 10 obj-y += misc.o timer.o reset_manager.o clock_manager.o \
11 11 fpga_manager.o board.o
12 12  
  13 +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
  14 +
13 15 obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
14 16  
15 17 # QTS-generated config file wrappers
arch/arm/mach-socfpga/include/mach/reset_manager.h
Diff comments   View file @ 827e6a7
... ... @@ -43,6 +43,8 @@
43 43  
44 44 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
45 45 #include <asm/arch/reset_manager_gen5.h>
  46 +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
  47 +#include <asm/arch/reset_manager_arria10.h>
46 48 #endif
47 49  
48 50 #endif /* _RESET_MANAGER_H_ */
arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
Diff comments   View file @ 827e6a7
  1 +/*
  2 + * Copyright (C) 2016-2017 Intel Corporation
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0
  5 + */
  6 +
  7 +#ifndef _RESET_MANAGER_ARRIA10_H_
  8 +#define _RESET_MANAGER_ARRIA10_H_
  9 +
  10 +#include <dt-bindings/reset/altr,rst-mgr-a10.h>
  11 +
  12 +void socfpga_watchdog_disable(void);
  13 +void socfpga_reset_deassert_noc_ddr_scheduler(void);
  14 +int socfpga_is_wdt_in_reset(void);
  15 +void socfpga_emac_manage_reset(ulong emacbase, u32 state);
  16 +int socfpga_reset_deassert_bridges_handoff(void);
  17 +void socfpga_reset_assert_fpga_connected_peripherals(void);
  18 +void socfpga_reset_deassert_osc1wd0(void);
  19 +void socfpga_reset_uart(int assert);
  20 +int socfpga_bridges_reset(int enable);
  21 +
  22 +struct socfpga_reset_manager {
  23 + u32 stat;
  24 + u32 ramstat;
  25 + u32 miscstat;
  26 + u32 ctrl;
  27 + u32 hdsken;
  28 + u32 hdskreq;
  29 + u32 hdskack;
  30 + u32 counts;
  31 + u32 mpumodrst;
  32 + u32 per0modrst;
  33 + u32 per1modrst;
  34 + u32 brgmodrst;
  35 + u32 sysmodrst;
  36 + u32 coldmodrst;
  37 + u32 nrstmodrst;
  38 + u32 dbgmodrst;
  39 + u32 mpuwarmmask;
  40 + u32 per0warmmask;
  41 + u32 per1warmmask;
  42 + u32 brgwarmmask;
  43 + u32 syswarmmask;
  44 + u32 nrstwarmmask;
  45 + u32 l3warmmask;
  46 + u32 tststa;
  47 + u32 tstscratch;
  48 + u32 hdsktimeout;
  49 + u32 hmcintr;
  50 + u32 hmcintren;
  51 + u32 hmcintrens;
  52 + u32 hmcintrenr;
  53 + u32 hmcgpout;
  54 + u32 hmcgpin;
  55 +};
  56 +
  57 +/*
  58 + * SocFPGA Arria10 reset IDs, bank mapping is as follows:
  59 + * 0 ... mpumodrst
  60 + * 1 ... per0modrst
  61 + * 2 ... per1modrst
  62 + * 3 ... brgmodrst
  63 + * 4 ... sysmodrst
  64 + */
  65 +#define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0)
  66 +#define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1)
  67 +#define RSTMGR_EMAC2 RSTMGR_DEFINE(1, 2)
  68 +#define RSTMGR_NAND RSTMGR_DEFINE(1, 5)
  69 +#define RSTMGR_QSPI RSTMGR_DEFINE(1, 6)
  70 +#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 7)
  71 +#define RSTMGR_DMA RSTMGR_DEFINE(1, 16)
  72 +#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 17)
  73 +#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 18)
  74 +#define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0)
  75 +#define RSTMGR_L4WD1 RSTMGR_DEFINE(2, 1)
  76 +#define RSTMGR_L4SYSTIMER0 RSTMGR_DEFINE(2, 2)
  77 +#define RSTMGR_L4SYSTIMER1 RSTMGR_DEFINE(2, 3)
  78 +#define RSTMGR_SPTIMER0 RSTMGR_DEFINE(2, 4)
  79 +#define RSTMGR_SPTIMER1 RSTMGR_DEFINE(2, 5)
  80 +#define RSTMGR_UART0 RSTMGR_DEFINE(2, 16)
  81 +#define RSTMGR_UART1 RSTMGR_DEFINE(2, 17)
  82 +#define RSTMGR_DDRSCH RSTMGR_DEFINE(3, 6)
  83 +
  84 +#define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK BIT(1)
  85 +#define ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK BIT(0)
  86 +#define ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK BIT(1)
  87 +#define ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK BIT(2)
  88 +#define ALT_RSTMGR_PER0MODRST_USB0_SET_MSK BIT(3)
  89 +#define ALT_RSTMGR_PER0MODRST_USB1_SET_MSK BIT(4)
  90 +#define ALT_RSTMGR_PER0MODRST_NAND_SET_MSK BIT(5)
  91 +#define ALT_RSTMGR_PER0MODRST_QSPI_SET_MSK BIT(6)
  92 +#define ALT_RSTMGR_PER0MODRST_SDMMC_SET_MSK BIT(7)
  93 +#define ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK BIT(8)
  94 +#define ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK BIT(9)
  95 +#define ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK BIT(10)
  96 +#define ALT_RSTMGR_PER0MODRST_USBECC0_SET_MSK BIT(11)
  97 +#define ALT_RSTMGR_PER0MODRST_USBECC1_SET_MSK BIT(12)
  98 +#define ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK BIT(13)
  99 +#define ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK BIT(14)
  100 +#define ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK BIT(15)
  101 +#define ALT_RSTMGR_PER0MODRST_DMA_SET_MSK BIT(16)
  102 +#define ALT_RSTMGR_PER0MODRST_SPIM0_SET_MSK BIT(17)
  103 +#define ALT_RSTMGR_PER0MODRST_SPIM1_SET_MSK BIT(18)
  104 +#define ALT_RSTMGR_PER0MODRST_SPIS0_SET_MSK BIT(19)
  105 +#define ALT_RSTMGR_PER0MODRST_SPIS1_SET_MSK BIT(20)
  106 +#define ALT_RSTMGR_PER0MODRST_DMAECC_SET_MSK BIT(21)
  107 +#define ALT_RSTMGR_PER0MODRST_EMACPTP_SET_MSK BIT(22)
  108 +#define ALT_RSTMGR_PER0MODRST_DMAIF0_SET_MSK BIT(24)
  109 +#define ALT_RSTMGR_PER0MODRST_DMAIF1_SET_MSK BIT(25)
  110 +#define ALT_RSTMGR_PER0MODRST_DMAIF2_SET_MSK BIT(26)
  111 +#define ALT_RSTMGR_PER0MODRST_DMAIF3_SET_MSK BIT(27)
  112 +#define ALT_RSTMGR_PER0MODRST_DMAIF4_SET_MSK BIT(28)
  113 +#define ALT_RSTMGR_PER0MODRST_DMAIF5_SET_MSK BIT(29)
  114 +#define ALT_RSTMGR_PER0MODRST_DMAIF6_SET_MSK BIT(30)
  115 +#define ALT_RSTMGR_PER0MODRST_DMAIF7_SET_MSK BIT(31)
  116 +
  117 +#define ALT_RSTMGR_PER1MODRST_WD0_SET_MSK BIT(0)
  118 +#define ALT_RSTMGR_PER1MODRST_WD1_SET_MSK BIT(1)
  119 +#define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_SET_MSK BIT(2)
  120 +#define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_SET_MSK BIT(3)
  121 +#define ALT_RSTMGR_PER1MODRST_SPTMR0_SET_MSK BIT(4)
  122 +#define ALT_RSTMGR_PER1MODRST_SPTMR1_SET_MSK BIT(5)
  123 +#define ALT_RSTMGR_PER1MODRST_I2C0_SET_MSK BIT(8)
  124 +#define ALT_RSTMGR_PER1MODRST_I2C1_SET_MSK BIT(9)
  125 +#define ALT_RSTMGR_PER1MODRST_I2C2_SET_MSK BIT(10)
  126 +#define ALT_RSTMGR_PER1MODRST_I2C3_SET_MSK BIT(11)
  127 +#define ALT_RSTMGR_PER1MODRST_I2C4_SET_MSK BIT(12)
  128 +#define ALT_RSTMGR_PER1MODRST_UART0_SET_MSK BIT(16)
  129 +#define ALT_RSTMGR_PER1MODRST_UART1_SET_MSK BIT(17)
  130 +#define ALT_RSTMGR_PER1MODRST_GPIO0_SET_MSK BIT(24)
  131 +#define ALT_RSTMGR_PER1MODRST_GPIO1_SET_MSK BIT(25)
  132 +#define ALT_RSTMGR_PER1MODRST_GPIO2_SET_MSK BIT(26)
  133 +
  134 +#define ALT_RSTMGR_BRGMODRST_H2F_SET_MSK BIT(0)
  135 +#define ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK BIT(1)
  136 +#define ALT_RSTMGR_BRGMODRST_F2H_SET_MSK BIT(2)
  137 +#define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK BIT(3)
  138 +#define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK BIT(4)
  139 +#define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK BIT(5)
  140 +#define ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK BIT(6)
  141 +
  142 +#define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_SET_MSK BIT(0)
  143 +#define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_SET_MSK BIT(1)
  144 +#define ALT_RSTMGR_HDSKEN_FPGAHSEN_SET_MSK BIT(2)
  145 +#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_SET_MSK BIT(3)
  146 +
  147 +#endif /* _RESET_MANAGER_ARRIA10_H_ */
arch/arm/mach-socfpga/reset_manager_arria10.c
Diff comments   View file @ 827e6a7
  1 +/*
  2 + * Copyright (C) 2016-2017 Intel Corporation
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0
  5 + */
  6 +
  7 +#include <asm/io.h>
  8 +#include <asm/arch/fpga_manager.h>
  9 +#include <asm/arch/misc.h>
  10 +#include <asm/arch/reset_manager.h>
  11 +#include <asm/arch/system_manager.h>
  12 +#include <common.h>
  13 +#include <errno.h>
  14 +#include <fdtdec.h>
  15 +#include <wait_bit.h>
  16 +
  17 +DECLARE_GLOBAL_DATA_PTR;
  18 +
  19 +static const struct socfpga_reset_manager *reset_manager_base =
  20 + (void *)SOCFPGA_RSTMGR_ADDRESS;
  21 +static const struct socfpga_system_manager *sysmgr_regs =
  22 + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  23 +
  24 +#define ECC_MASK (ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK | \
  25 + ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK | \
  26 + ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK | \
  27 + ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK | \
  28 + ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK | \
  29 + ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK)
  30 +
  31 +void socfpga_reset_uart(int assert)
  32 +{
  33 + unsigned int com_port;
  34 +
  35 + com_port = uart_com_port(gd->fdt_blob);
  36 +
  37 + if (com_port == SOCFPGA_UART1_ADDRESS)
  38 + socfpga_per_reset(SOCFPGA_RESET(UART1), assert);
  39 + else if (com_port == SOCFPGA_UART0_ADDRESS)
  40 + socfpga_per_reset(SOCFPGA_RESET(UART0), assert);
  41 +}
  42 +
  43 +static const u32 per0fpgamasks[] = {
  44 + ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK |
  45 + ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK,
  46 + ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK |
  47 + ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK,
  48 + ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK |
  49 + ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK,
  50 + 0, /* i2c0 per1mod */
  51 + 0, /* i2c1 per1mod */
  52 + 0, /* i2c0_emac */
  53 + 0, /* i2c1_emac */
  54 + 0, /* i2c2_emac */
  55 + ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK |
  56 + ALT_RSTMGR_PER0MODRST_NAND_SET_MSK,
  57 + ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK |
  58 + ALT_RSTMGR_PER0MODRST_QSPI_SET_MSK,
  59 + ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK |
  60 + ALT_RSTMGR_PER0MODRST_SDMMC_SET_MSK,
  61 + ALT_RSTMGR_PER0MODRST_SPIM0_SET_MSK,
  62 + ALT_RSTMGR_PER0MODRST_SPIM1_SET_MSK,
  63 + ALT_RSTMGR_PER0MODRST_SPIS0_SET_MSK,
  64 + ALT_RSTMGR_PER0MODRST_SPIS1_SET_MSK,
  65 + 0, /* uart0 per1mod */
  66 + 0, /* uart1 per1mod */
  67 +};
  68 +
  69 +static const u32 per1fpgamasks[] = {
  70 + 0, /* emac0 per0mod */
  71 + 0, /* emac1 per0mod */
  72 + 0, /* emac2 per0mod */
  73 + ALT_RSTMGR_PER1MODRST_I2C0_SET_MSK,
  74 + ALT_RSTMGR_PER1MODRST_I2C1_SET_MSK,
  75 + ALT_RSTMGR_PER1MODRST_I2C2_SET_MSK, /* i2c0_emac */
  76 + ALT_RSTMGR_PER1MODRST_I2C3_SET_MSK, /* i2c1_emac */
  77 + ALT_RSTMGR_PER1MODRST_I2C4_SET_MSK, /* i2c2_emac */
  78 + 0, /* nand per0mod */
  79 + 0, /* qspi per0mod */
  80 + 0, /* sdmmc per0mod */
  81 + 0, /* spim0 per0mod */
  82 + 0, /* spim1 per0mod */
  83 + 0, /* spis0 per0mod */
  84 + 0, /* spis1 per0mod */
  85 + ALT_RSTMGR_PER1MODRST_UART0_SET_MSK,
  86 + ALT_RSTMGR_PER1MODRST_UART1_SET_MSK,
  87 +};
  88 +
  89 +struct bridge_cfg {
  90 + int compat_id;
  91 + u32 mask_noc;
  92 + u32 mask_rstmgr;
  93 +};
  94 +
  95 +static const struct bridge_cfg bridge_cfg_tbl[] = {
  96 + {
  97 + COMPAT_ALTERA_SOCFPGA_H2F_BRG,
  98 + ALT_SYSMGR_NOC_H2F_SET_MSK,
  99 + ALT_RSTMGR_BRGMODRST_H2F_SET_MSK,
  100 + },
  101 + {
  102 + COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,
  103 + ALT_SYSMGR_NOC_LWH2F_SET_MSK,
  104 + ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK,
  105 + },
  106 + {
  107 + COMPAT_ALTERA_SOCFPGA_F2H_BRG,
  108 + ALT_SYSMGR_NOC_F2H_SET_MSK,
  109 + ALT_RSTMGR_BRGMODRST_F2H_SET_MSK,
  110 + },
  111 + {
  112 + COMPAT_ALTERA_SOCFPGA_F2SDR0,
  113 + ALT_SYSMGR_NOC_F2SDR0_SET_MSK,
  114 + ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK,
  115 + },
  116 + {
  117 + COMPAT_ALTERA_SOCFPGA_F2SDR1,
  118 + ALT_SYSMGR_NOC_F2SDR1_SET_MSK,
  119 + ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK,
  120 + },
  121 + {
  122 + COMPAT_ALTERA_SOCFPGA_F2SDR2,
  123 + ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
  124 + ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK,
  125 + },
  126 +};
  127 +
  128 +/* Disable the watchdog (toggle reset to watchdog) */
  129 +void socfpga_watchdog_disable(void)
  130 +{
  131 + /* assert reset for watchdog */
  132 + setbits_le32(&reset_manager_base->per1modrst,
  133 + ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
  134 +}
  135 +
  136 +/* Release NOC ddr scheduler from reset */
  137 +void socfpga_reset_deassert_noc_ddr_scheduler(void)
  138 +{
  139 + clrbits_le32(&reset_manager_base->brgmodrst,
  140 + ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK);
  141 +}
  142 +
  143 +/* Check whether Watchdog in reset state? */
  144 +int socfpga_is_wdt_in_reset(void)
  145 +{
  146 + u32 val;
  147 +
  148 + val = readl(&reset_manager_base->per1modrst);
  149 + val &= ALT_RSTMGR_PER1MODRST_WD0_SET_MSK;
  150 +
  151 + /* return 0x1 if watchdog in reset */
  152 + return val;
  153 +}
  154 +
  155 +/* emacbase: base address of emac to enable/disable reset
  156 + * state: 0 - disable reset, !0 - enable reset
  157 + */
  158 +void socfpga_emac_manage_reset(ulong emacbase, u32 state)
  159 +{
  160 + ulong eccmask;
  161 + ulong emacmask;
  162 +
  163 + switch (emacbase) {
  164 + case SOCFPGA_EMAC0_ADDRESS:
  165 + eccmask = ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK;
  166 + emacmask = ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK;
  167 + break;
  168 + case SOCFPGA_EMAC1_ADDRESS:
  169 + eccmask = ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK;
  170 + emacmask = ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK;
  171 + break;
  172 + case SOCFPGA_EMAC2_ADDRESS:
  173 + eccmask = ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK;
  174 + emacmask = ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK;
  175 + break;
  176 + default:
  177 + error("emac base address unexpected! %lx", emacbase);
  178 + hang();
  179 + break;
  180 + }
  181 +
  182 + if (state) {
  183 + /* Enable ECC OCP first */
  184 + setbits_le32(&reset_manager_base->per0modrst, eccmask);
  185 + setbits_le32(&reset_manager_base->per0modrst, emacmask);
  186 + } else {
  187 + /* Disable ECC OCP first */
  188 + clrbits_le32(&reset_manager_base->per0modrst, emacmask);
  189 + clrbits_le32(&reset_manager_base->per0modrst, eccmask);
  190 + }
  191 +}
  192 +
  193 +static int get_bridge_init_val(const void *blob, int compat_id)
  194 +{
  195 + int node;
  196 +
  197 + node = fdtdec_next_compatible(blob, 0, compat_id);
  198 + if (node < 0)
  199 + return 0;
  200 +
  201 + return fdtdec_get_uint(blob, node, "init-val", 0);
  202 +}
  203 +
  204 +/* Enable bridges (hps2fpga, lwhps2fpga, fpga2hps, fpga2sdram) per handoff */
  205 +int socfpga_reset_deassert_bridges_handoff(void)
  206 +{
  207 + u32 mask_noc = 0, mask_rstmgr = 0;
  208 + int i;
  209 +
  210 + for (i = 0; i < ARRAY_SIZE(bridge_cfg_tbl); i++) {
  211 + if (get_bridge_init_val(gd->fdt_blob,
  212 + bridge_cfg_tbl[i].compat_id)) {
  213 + mask_noc |= bridge_cfg_tbl[i].mask_noc;
  214 + mask_rstmgr |= bridge_cfg_tbl[i].mask_rstmgr;
  215 + }
  216 + }
  217 +
  218 + /* clear idle request to all bridges */
  219 + setbits_le32(&sysmgr_regs->noc_idlereq_clr, mask_noc);
  220 +
  221 + /* Release bridges from reset state per handoff value */
  222 + clrbits_le32(&reset_manager_base->brgmodrst, mask_rstmgr);
  223 +
  224 + /* Poll until all idleack to 0, timeout at 1000ms */
  225 + return wait_for_bit(__func__, &sysmgr_regs->noc_idleack, mask_noc,
  226 + false, 1000, false);
  227 +}
  228 +
  229 +void socfpga_reset_assert_fpga_connected_peripherals(void)
  230 +{
  231 + u32 mask0 = 0;
  232 + u32 mask1 = 0;
  233 + u32 fpga_pinux_addr = SOCFPGA_PINMUX_FPGA_INTERFACE_ADDRESS;
  234 + int i;
  235 +
  236 + for (i = 0; i < ARRAY_SIZE(per1fpgamasks); i++) {
  237 + if (readl(fpga_pinux_addr)) {
  238 + mask0 |= per0fpgamasks[i];
  239 + mask1 |= per1fpgamasks[i];
  240 + }
  241 + fpga_pinux_addr += sizeof(u32);
  242 + }
  243 +
  244 + setbits_le32(&reset_manager_base->per0modrst, mask0 & ECC_MASK);
  245 + setbits_le32(&reset_manager_base->per1modrst, mask1);
  246 + setbits_le32(&reset_manager_base->per0modrst, mask0);
  247 +}
  248 +
  249 +/* Release L4 OSC1 Watchdog Timer 0 from reset through reset manager */
  250 +void socfpga_reset_deassert_osc1wd0(void)
  251 +{
  252 + clrbits_le32(&reset_manager_base->per1modrst,
  253 + ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
  254 +}
  255 +
  256 +/*
  257 + * Assert or de-assert SoCFPGA reset manager reset.
  258 + */
  259 +void socfpga_per_reset(u32 reset, int set)
  260 +{
  261 + const u32 *reg;
  262 + u32 rstmgr_bank = RSTMGR_BANK(reset);
  263 +
  264 + switch (rstmgr_bank) {
  265 + case 0:
  266 + reg = &reset_manager_base->mpumodrst;
  267 + break;
  268 + case 1:
  269 + reg = &reset_manager_base->per0modrst;
  270 + break;
  271 + case 2:
  272 + reg = &reset_manager_base->per1modrst;
  273 + break;
  274 + case 3:
  275 + reg = &reset_manager_base->brgmodrst;
  276 + break;
  277 + case 4:
  278 + reg = &reset_manager_base->sysmodrst;
  279 + break;
  280 +
  281 + default:
  282 + return;
  283 + }
  284 +
  285 + if (set)
  286 + setbits_le32(reg, 1 << RSTMGR_RESET(reset));
  287 + else
  288 + clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
  289 +}
  290 +
  291 +/*
  292 + * Assert reset on every peripheral but L4WD0.
  293 + * Watchdog must be kept intact to prevent glitches
  294 + * and/or hangs.
  295 + * For the Arria10, we disable all the peripherals except L4 watchdog0,
  296 + * L4 Timer 0, and ECC.
  297 + */
  298 +void socfpga_per_reset_all(void)
  299 +{
  300 + const u32 l4wd0 = (1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)) |
  301 + (1 << RSTMGR_RESET(SOCFPGA_RESET(L4SYSTIMER0))));
  302 + unsigned mask_ecc_ocp =
  303 + ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK |
  304 + ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK |
  305 + ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK |
  306 + ALT_RSTMGR_PER0MODRST_USBECC0_SET_MSK |
  307 + ALT_RSTMGR_PER0MODRST_USBECC1_SET_MSK |
  308 + ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK |
  309 + ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK |
  310 + ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK;
  311 +
  312 + /* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
  313 + writel(~l4wd0, &reset_manager_base->per1modrst);
  314 + setbits_le32(&reset_manager_base->per0modrst, ~mask_ecc_ocp);
  315 +
  316 + /* Finally disable the ECC_OCP */
  317 + setbits_le32(&reset_manager_base->per0modrst, mask_ecc_ocp);
  318 +}
  319 +
  320 +#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
  321 +int socfpga_bridges_reset(int enable)
  322 +{
  323 + /* For SoCFPGA-VT, this is NOP. */
  324 + return 0;
  325 +}
  326 +#else
  327 +int socfpga_bridges_reset(int enable)
  328 +{
  329 + int ret;
  330 +
  331 + /* Disable all the bridges (hps2fpga, lwhps2fpga, fpga2hps,
  332 + fpga2sdram) */
  333 + /* set idle request to all bridges */
  334 + writel(ALT_SYSMGR_NOC_H2F_SET_MSK |
  335 + ALT_SYSMGR_NOC_LWH2F_SET_MSK |
  336 + ALT_SYSMGR_NOC_F2H_SET_MSK |
  337 + ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
  338 + ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
  339 + ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
  340 + &sysmgr_regs->noc_idlereq_set);
  341 +
  342 + /* Enable the NOC timeout */
  343 + writel(ALT_SYSMGR_NOC_TMO_EN_SET_MSK, &sysmgr_regs->noc_timeout);
  344 +
  345 + /* Poll until all idleack to 1 */
  346 + ret = wait_for_bit(__func__, &sysmgr_regs->noc_idleack,
  347 + ALT_SYSMGR_NOC_H2F_SET_MSK |
  348 + ALT_SYSMGR_NOC_LWH2F_SET_MSK |
  349 + ALT_SYSMGR_NOC_F2H_SET_MSK |
  350 + ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
  351 + ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
  352 + ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
  353 + true, 10000, false);
  354 + if (ret)
  355 + return ret;
  356 +
  357 + /* Poll until all idlestatus to 1 */
  358 + ret = wait_for_bit(__func__, &sysmgr_regs->noc_idlestatus,
  359 + ALT_SYSMGR_NOC_H2F_SET_MSK |
  360 + ALT_SYSMGR_NOC_LWH2F_SET_MSK |
  361 + ALT_SYSMGR_NOC_F2H_SET_MSK |
  362 + ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
  363 + ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
  364 + ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
  365 + true, 10000, false);
  366 + if (ret)
  367 + return ret;
  368 +
  369 + /* Put all bridges (except NOR DDR scheduler) into reset state */
  370 + setbits_le32(&reset_manager_base->brgmodrst,
  371 + (ALT_RSTMGR_BRGMODRST_H2F_SET_MSK |
  372 + ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK |
  373 + ALT_RSTMGR_BRGMODRST_F2H_SET_MSK |
  374 + ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK |
  375 + ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK |
  376 + ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK));
  377 +
  378 + /* Disable NOC timeout */
  379 + writel(0, &sysmgr_regs->noc_timeout);
  380 +
  381 + return 0;
  382 +}
  383 +#endif
include/dt-bindings/reset/altr,rst-mgr-a10.h
Diff comments   View file @ 827e6a7
  1 +/*
  2 + * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de>
  3 + *
  4 + * This software is licensed under the terms of the GNU General Public
  5 + * License version 2, as published by the Free Software Foundation, and
  6 + * may be copied, distributed, and modified under those terms.
  7 + *
  8 + * This program is distributed in the hope that it will be useful,
  9 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11 + * GNU General Public License for more details.
  12 + */
  13 +
  14 +#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
  15 +#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
  16 +
  17 +/* MPUMODRST */
  18 +#define CPU0_RESET 0
  19 +#define CPU1_RESET 1
  20 +#define WDS_RESET 2
  21 +#define SCUPER_RESET 3
  22 +
  23 +/* PER0MODRST */
  24 +#define EMAC0_RESET 32
  25 +#define EMAC1_RESET 33
  26 +#define EMAC2_RESET 34
  27 +#define USB0_RESET 35
  28 +#define USB1_RESET 36
  29 +#define NAND_RESET 37
  30 +#define QSPI_RESET 38
  31 +#define SDMMC_RESET 39
  32 +#define EMAC0_OCP_RESET 40
  33 +#define EMAC1_OCP_RESET 41
  34 +#define EMAC2_OCP_RESET 42
  35 +#define USB0_OCP_RESET 43
  36 +#define USB1_OCP_RESET 44
  37 +#define NAND_OCP_RESET 45
  38 +#define QSPI_OCP_RESET 46
  39 +#define SDMMC_OCP_RESET 47
  40 +#define DMA_RESET 48
  41 +#define SPIM0_RESET 49
  42 +#define SPIM1_RESET 50
  43 +#define SPIS0_RESET 51
  44 +#define SPIS1_RESET 52
  45 +#define DMA_OCP_RESET 53
  46 +#define EMAC_PTP_RESET 54
  47 +/* 55 is empty*/
  48 +#define DMAIF0_RESET 56
  49 +#define DMAIF1_RESET 57
  50 +#define DMAIF2_RESET 58
  51 +#define DMAIF3_RESET 59
  52 +#define DMAIF4_RESET 60
  53 +#define DMAIF5_RESET 61
  54 +#define DMAIF6_RESET 62
  55 +#define DMAIF7_RESET 63
  56 +
  57 +/* PER1MODRST */
  58 +#define L4WD0_RESET 64
  59 +#define L4WD1_RESET 65
  60 +#define L4SYSTIMER0_RESET 66
  61 +#define L4SYSTIMER1_RESET 67
  62 +#define SPTIMER0_RESET 68
  63 +#define SPTIMER1_RESET 69
  64 +/* 70-71 is reserved */
  65 +#define I2C0_RESET 72
  66 +#define I2C1_RESET 73
  67 +#define I2C2_RESET 74
  68 +#define I2C3_RESET 75
  69 +#define I2C4_RESET 76
  70 +/* 77-79 is reserved */
  71 +#define UART0_RESET 80
  72 +#define UART1_RESET 81
  73 +/* 82-87 is reserved */
  74 +#define GPIO0_RESET 88
  75 +#define GPIO1_RESET 89
  76 +#define GPIO2_RESET 90
  77 +
  78 +/* BRGMODRST */
  79 +#define HPS2FPGA_RESET 96
  80 +#define LWHPS2FPGA_RESET 97
  81 +#define FPGA2HPS_RESET 98
  82 +#define F2SSDRAM0_RESET 99
  83 +#define F2SSDRAM1_RESET 100
  84 +#define F2SSDRAM2_RESET 101
  85 +#define DDRSCH_RESET 102
  86 +
  87 +/* SYSMODRST*/
  88 +#define ROM_RESET 128
  89 +#define OCRAM_RESET 129
  90 +/* 130 is reserved */
  91 +#define FPGAMGR_RESET 131
  92 +#define S2F_RESET 132
  93 +#define SYSDBG_RESET 133
  94 +#define OCRAM_OCP_RESET 134
  95 +
  96 +/* COLDMODRST */
  97 +#define CLKMGRCOLD_RESET 160
  98 +/* 161-162 is reserved */
  99 +#define S2FCOLD_RESET 163
  100 +#define TIMESTAMPCOLD_RESET 164
  101 +#define TAPCOLD_RESET 165
  102 +#define HMCCOLD_RESET 166
  103 +#define IOMGRCOLD_RESET 167
  104 +
  105 +/* NRSTMODRST */
  106 +#define NRSTPINOE_RESET 192
  107 +
  108 +/* DBGMODRST */
  109 +#define DBG_RESET 224
  110 +#endif