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Commit 8cb78722306351c5d61ce4da18c284ef59c0caef

Authored by Stefan Roese
Committed by Luka Perkov
1 parent 350b50eea3
Exists in v2017.01-smarct4x and in 34 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

arm: armada-xp: Move SoC headers to mach-mvebu/include/mach 

Move arch/arm/include/asm/arch-armada-xp/*
     -> arch/arm/mach-mvebu/include/mach/*

Additionally the SYS_SOC is renamed from "armada-xp" to "mvebu". With this
change all these files can better be shared with other, newer Mavell
MVEBU SoC's. Like the upcoming Armada 38x support.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Tested-by: Dirk Eibach <dirk.eibach@gdsys.cc>

Showing 9 changed files with 269 additions and 269 deletions Side-by-side Diff

... ... @@ -86,7 +86,7 @@
86 86 endif
87 87 endif
88 88  
89   -ifneq (,$(filter $(SOC), armada-xp kirkwood))
  89 +ifneq (,$(filter $(SOC), mvebu kirkwood))
90 90 libs-y += arch/arm/mvebu-common/
91 91 endif
92 92  
arch/arm/include/asm/arch-armada-xp/config.h
View file @ 8cb7872
1   -/*
2   - * (C) Copyright 2011
3   - * Marvell Semiconductor <www.marvell.com>
4   - * Written-by: Lei Wen <leiwen@marvell.com>
5   - *
6   - * SPDX-License-Identifier: GPL-2.0+
7   - */
8   -
9   -/*
10   - * This file should be included in board config header file.
11   - *
12   - * It supports common definitions for Armada XP platforms
13   - */
14   -
15   -#ifndef _ARMADA_XP_CONFIG_H
16   -#define _ARMADA_XP_CONFIG_H
17   -
18   -#include <asm/arch/soc.h>
19   -
20   -#define MV88F78X60 /* for the DDR training bin_hdr code */
21   -
22   -#define CONFIG_SYS_CACHELINE_SIZE 32
23   -
24   -/*
25   - * By default kwbimage.cfg from board specific folder is used
26   - * If for some board, different configuration file need to be used,
27   - * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
28   - */
29   -#ifndef CONFIG_SYS_KWD_CONFIG
30   -#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
31   -#endif /* CONFIG_SYS_KWD_CONFIG */
32   -
33   -/* Add target to build it automatically upon "make" */
34   -#ifdef CONFIG_SPL
35   -#define CONFIG_BUILD_TARGET "u-boot-spl.kwb"
36   -#else
37   -#define CONFIG_BUILD_TARGET "u-boot.kwb"
38   -#endif
39   -
40   -/* end of 16M scrubbed by training in bootrom */
41   -#define CONFIG_SYS_INIT_SP_ADDR 0x00FF0000
42   -#define CONFIG_NR_DRAM_BANKS_MAX 2
43   -
44   -#define MV_UART_CONSOLE_BASE MVEBU_UART0_BASE
45   -
46   -/*
47   - * SPI Flash configuration
48   - */
49   -#ifdef CONFIG_CMD_SF
50   -#define CONFIG_HARD_SPI 1
51   -#define CONFIG_KIRKWOOD_SPI 1
52   -#ifndef CONFIG_ENV_SPI_BUS
53   -# define CONFIG_ENV_SPI_BUS 0
54   -#endif
55   -#ifndef CONFIG_ENV_SPI_CS
56   -# define CONFIG_ENV_SPI_CS 0
57   -#endif
58   -#ifndef CONFIG_ENV_SPI_MAX_HZ
59   -# define CONFIG_ENV_SPI_MAX_HZ 50000000
60   -#endif
61   -#endif
62   -
63   -/*
64   - * Ethernet Driver configuration
65   - */
66   -#ifdef CONFIG_CMD_NET
67   -#define CONFIG_CMD_MII
68   -#define CONFIG_MII /* expose smi ove miiphy interface */
69   -#define CONFIG_MVNETA /* Enable Marvell Gbe Controller Driver */
70   -#define CONFIG_PHYLIB
71   -#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
72   -#define CONFIG_PHY_GIGE /* GbE speed/duplex detect */
73   -#endif /* CONFIG_CMD_NET */
74   -
75   -/*
76   - * I2C related stuff
77   - */
78   -#ifdef CONFIG_CMD_I2C
79   -#ifndef CONFIG_SYS_I2C_SOFT
80   -#define CONFIG_I2C_MVTWSI
81   -#endif
82   -#define CONFIG_SYS_I2C_SLAVE 0x0
83   -#define CONFIG_SYS_I2C_SPEED 100000
84   -#endif
85   -
86   -#endif /* _ARMADA_XP_CONFIG_H */
arch/arm/include/asm/arch-armada-xp/cpu.h
View file @ 8cb7872
1   -/*
2   - * (C) Copyright 2009
3   - * Marvell Semiconductor <www.marvell.com>
4   - * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5   - *
6   - * SPDX-License-Identifier: GPL-2.0+
7   - */
8   -
9   -#ifndef _ARMADA_XP_CPU_H
10   -#define _ARMADA_XP_CPU_H
11   -
12   -#include <asm/system.h>
13   -
14   -#ifndef __ASSEMBLY__
15   -
16   -#define MVEBU_REG_PCIE_DEVID (MVEBU_REG_PCIE_BASE + 0x00)
17   -#define MVEBU_REG_PCIE_REVID (MVEBU_REG_PCIE_BASE + 0x08)
18   -
19   -enum memory_bank {
20   - BANK0,
21   - BANK1,
22   - BANK2,
23   - BANK3
24   -};
25   -
26   -enum cpu_winen {
27   - CPU_WIN_DISABLE,
28   - CPU_WIN_ENABLE
29   -};
30   -
31   -enum cpu_target {
32   - CPU_TARGET_DRAM = 0x0,
33   - CPU_TARGET_DEVICEBUS_BOOTROM_SPI = 0x1,
34   - CPU_TARGET_ETH23 = 0x3,
35   - CPU_TARGET_PCIE02 = 0x4,
36   - CPU_TARGET_ETH01 = 0x7,
37   - CPU_TARGET_PCIE13 = 0x8,
38   - CPU_TARGET_SASRAM = 0x9,
39   - CPU_TARGET_NAND = 0xd,
40   -};
41   -
42   -enum cpu_attrib {
43   - CPU_ATTR_SASRAM = 0x01,
44   - CPU_ATTR_DRAM_CS0 = 0x0e,
45   - CPU_ATTR_DRAM_CS1 = 0x0d,
46   - CPU_ATTR_DRAM_CS2 = 0x0b,
47   - CPU_ATTR_DRAM_CS3 = 0x07,
48   - CPU_ATTR_NANDFLASH = 0x2f,
49   - CPU_ATTR_SPIFLASH = 0x1e,
50   - CPU_ATTR_BOOTROM = 0x1d,
51   - CPU_ATTR_PCIE_IO = 0xe0,
52   - CPU_ATTR_PCIE_MEM = 0xe8,
53   - CPU_ATTR_DEV_CS0 = 0x3e,
54   - CPU_ATTR_DEV_CS1 = 0x3d,
55   - CPU_ATTR_DEV_CS2 = 0x3b,
56   - CPU_ATTR_DEV_CS3 = 0x37,
57   -};
58   -
59   -/*
60   - * Default Device Address MAP BAR values
61   - */
62   -#define DEFADR_PCI_MEM 0x90000000
63   -#define DEFADR_PCI_IO 0xC0000000
64   -#define DEFADR_SPIF 0xF4000000
65   -#define DEFADR_BOOTROM 0xF8000000
66   -
67   -struct mbus_win {
68   - u32 base;
69   - u32 size;
70   - u8 target;
71   - u8 attr;
72   -};
73   -
74   -/*
75   - * System registers
76   - * Ref: Datasheet sec:A.28
77   - */
78   -struct mvebu_system_registers {
79   - u8 pad1[0x60];
80   - u32 rstoutn_mask; /* 0x60 */
81   - u32 sys_soft_rst; /* 0x64 */
82   -};
83   -
84   -/*
85   - * GPIO Registers
86   - * Ref: Datasheet sec:A.19
87   - */
88   -struct kwgpio_registers {
89   - u32 dout;
90   - u32 oe;
91   - u32 blink_en;
92   - u32 din_pol;
93   - u32 din;
94   - u32 irq_cause;
95   - u32 irq_mask;
96   - u32 irq_level;
97   -};
98   -
99   -/* Needed for dynamic (board-specific) mbus configuration */
100   -extern struct mvebu_mbus_state mbus_state;
101   -
102   -/*
103   - * functions
104   - */
105   -unsigned int mvebu_sdram_bar(enum memory_bank bank);
106   -unsigned int mvebu_sdram_bs(enum memory_bank bank);
107   -void mvebu_sdram_size_adjust(enum memory_bank bank);
108   -int mvebu_mbus_probe(struct mbus_win windows[], int count);
109   -
110   -/*
111   - * Highspeed SERDES PHY config init, ported from bin_hdr
112   - * to mainline U-Boot
113   - */
114   -int serdes_phy_config(void);
115   -
116   -/*
117   - * DDR3 init / training code ported from Marvell bin_hdr. Now
118   - * available in mainline U-Boot in:
119   - * drivers/ddr/mvebu/
120   - */
121   -int ddr3_init(void);
122   -#endif /* __ASSEMBLY__ */
123   -#endif /* _ARMADA_XP_CPU_H */
arch/arm/include/asm/arch-armada-xp/soc.h
View file @ 8cb7872
1   -/*
2   - * (C) Copyright 2009
3   - * Marvell Semiconductor <www.marvell.com>
4   - * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5   - *
6   - * Header file for the Marvell's Feroceon CPU core.
7   - *
8   - * SPDX-License-Identifier: GPL-2.0+
9   - */
10   -
11   -#ifndef _ASM_ARCH_ARMADA_XP_H
12   -#define _ASM_ARCH_ARMADA_XP_H
13   -
14   -#define SOC_MV78460_ID 0x7846
15   -
16   -/* TCLK Core Clock definition */
17   -#ifndef CONFIG_SYS_TCLK
18   -#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
19   -#endif
20   -
21   -/* SOC specific definations */
22   -#define INTREG_BASE 0xd0000000
23   -#define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080)
24   -#define SOC_REGS_PHY_BASE 0xf1000000
25   -#define MVEBU_REGISTER(x) (SOC_REGS_PHY_BASE + x)
26   -
27   -#define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504))
28   -#define MVEBU_SPI_BASE (MVEBU_REGISTER(0x10600))
29   -#define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000))
30   -#define MVEBU_UART0_BASE (MVEBU_REGISTER(0x12000))
31   -#define MVEBU_UART1_BASE (MVEBU_REGISTER(0x12100))
32   -#define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000))
33   -#define MVEBU_GPIO0_BASE (MVEBU_REGISTER(0x18100))
34   -#define MVEBU_GPIO1_BASE (MVEBU_REGISTER(0x18140))
35   -#define MVEBU_GPIO2_BASE (MVEBU_REGISTER(0x18180))
36   -#define MVEBU_SYSTEM_REG_BASE (MVEBU_REGISTER(0x18200))
37   -#define MVEBU_CPU_WIN_BASE (MVEBU_REGISTER(0x20000))
38   -#define MVEBU_SDRAM_BASE (MVEBU_REGISTER(0x20180))
39   -#define MVEBU_TIMER_BASE (MVEBU_REGISTER(0x20300))
40   -#define MVEBU_EGIGA2_BASE (MVEBU_REGISTER(0x30000))
41   -#define MVEBU_EGIGA3_BASE (MVEBU_REGISTER(0x34000))
42   -#define MVEBU_REG_PCIE_BASE (MVEBU_REGISTER(0x40000))
43   -#define MVEBU_EGIGA0_BASE (MVEBU_REGISTER(0x70000))
44   -#define MVEBU_EGIGA1_BASE (MVEBU_REGISTER(0x74000))
45   -
46   -#define SDRAM_MAX_CS 4
47   -#define SDRAM_ADDR_MASK 0xFF000000
48   -
49   -/* Armada XP GbE controller has 4 ports */
50   -#define MAX_MVNETA_DEVS 4
51   -
52   -/* Kirkwood CPU memory windows */
53   -#define MVCPU_WIN_CTRL_DATA CPU_WIN_CTRL_DATA
54   -#define MVCPU_WIN_ENABLE CPU_WIN_ENABLE
55   -#define MVCPU_WIN_DISABLE CPU_WIN_DISABLE
56   -
57   -#endif /* _ASM_ARCH_ARMADA_XP_H */
arch/arm/mach-mvebu/include/mach/config.h
Diff comments   View file @ 8cb7872
  1 +/*
  2 + * (C) Copyright 2011
  3 + * Marvell Semiconductor <www.marvell.com>
  4 + * Written-by: Lei Wen <leiwen@marvell.com>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +/*
  10 + * This file should be included in board config header file.
  11 + *
  12 + * It supports common definitions for Armada XP platforms
  13 + */
  14 +
  15 +#ifndef _ARMADA_XP_CONFIG_H
  16 +#define _ARMADA_XP_CONFIG_H
  17 +
  18 +#include <asm/arch/soc.h>
  19 +
  20 +#define MV88F78X60 /* for the DDR training bin_hdr code */
  21 +
  22 +#define CONFIG_SYS_CACHELINE_SIZE 32
  23 +
  24 +/*
  25 + * By default kwbimage.cfg from board specific folder is used
  26 + * If for some board, different configuration file need to be used,
  27 + * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
  28 + */
  29 +#ifndef CONFIG_SYS_KWD_CONFIG
  30 +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
  31 +#endif /* CONFIG_SYS_KWD_CONFIG */
  32 +
  33 +/* Add target to build it automatically upon "make" */
  34 +#ifdef CONFIG_SPL
  35 +#define CONFIG_BUILD_TARGET "u-boot-spl.kwb"
  36 +#else
  37 +#define CONFIG_BUILD_TARGET "u-boot.kwb"
  38 +#endif
  39 +
  40 +/* end of 16M scrubbed by training in bootrom */
  41 +#define CONFIG_SYS_INIT_SP_ADDR 0x00FF0000
  42 +#define CONFIG_NR_DRAM_BANKS_MAX 2
  43 +
  44 +#define MV_UART_CONSOLE_BASE MVEBU_UART0_BASE
  45 +
  46 +/*
  47 + * SPI Flash configuration
  48 + */
  49 +#ifdef CONFIG_CMD_SF
  50 +#define CONFIG_HARD_SPI 1
  51 +#define CONFIG_KIRKWOOD_SPI 1
  52 +#ifndef CONFIG_ENV_SPI_BUS
  53 +# define CONFIG_ENV_SPI_BUS 0
  54 +#endif
  55 +#ifndef CONFIG_ENV_SPI_CS
  56 +# define CONFIG_ENV_SPI_CS 0
  57 +#endif
  58 +#ifndef CONFIG_ENV_SPI_MAX_HZ
  59 +# define CONFIG_ENV_SPI_MAX_HZ 50000000
  60 +#endif
  61 +#endif
  62 +
  63 +/*
  64 + * Ethernet Driver configuration
  65 + */
  66 +#ifdef CONFIG_CMD_NET
  67 +#define CONFIG_CMD_MII
  68 +#define CONFIG_MII /* expose smi ove miiphy interface */
  69 +#define CONFIG_MVNETA /* Enable Marvell Gbe Controller Driver */
  70 +#define CONFIG_PHYLIB
  71 +#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
  72 +#define CONFIG_PHY_GIGE /* GbE speed/duplex detect */
  73 +#endif /* CONFIG_CMD_NET */
  74 +
  75 +/*
  76 + * I2C related stuff
  77 + */
  78 +#ifdef CONFIG_CMD_I2C
  79 +#ifndef CONFIG_SYS_I2C_SOFT
  80 +#define CONFIG_I2C_MVTWSI
  81 +#endif
  82 +#define CONFIG_SYS_I2C_SLAVE 0x0
  83 +#define CONFIG_SYS_I2C_SPEED 100000
  84 +#endif
  85 +
  86 +#endif /* _ARMADA_XP_CONFIG_H */
arch/arm/mach-mvebu/include/mach/cpu.h
Diff comments   View file @ 8cb7872
  1 +/*
  2 + * (C) Copyright 2009
  3 + * Marvell Semiconductor <www.marvell.com>
  4 + * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#ifndef _ARMADA_XP_CPU_H
  10 +#define _ARMADA_XP_CPU_H
  11 +
  12 +#include <asm/system.h>
  13 +
  14 +#ifndef __ASSEMBLY__
  15 +
  16 +#define MVEBU_REG_PCIE_DEVID (MVEBU_REG_PCIE_BASE + 0x00)
  17 +#define MVEBU_REG_PCIE_REVID (MVEBU_REG_PCIE_BASE + 0x08)
  18 +
  19 +enum memory_bank {
  20 + BANK0,
  21 + BANK1,
  22 + BANK2,
  23 + BANK3
  24 +};
  25 +
  26 +enum cpu_winen {
  27 + CPU_WIN_DISABLE,
  28 + CPU_WIN_ENABLE
  29 +};
  30 +
  31 +enum cpu_target {
  32 + CPU_TARGET_DRAM = 0x0,
  33 + CPU_TARGET_DEVICEBUS_BOOTROM_SPI = 0x1,
  34 + CPU_TARGET_ETH23 = 0x3,
  35 + CPU_TARGET_PCIE02 = 0x4,
  36 + CPU_TARGET_ETH01 = 0x7,
  37 + CPU_TARGET_PCIE13 = 0x8,
  38 + CPU_TARGET_SASRAM = 0x9,
  39 + CPU_TARGET_NAND = 0xd,
  40 +};
  41 +
  42 +enum cpu_attrib {
  43 + CPU_ATTR_SASRAM = 0x01,
  44 + CPU_ATTR_DRAM_CS0 = 0x0e,
  45 + CPU_ATTR_DRAM_CS1 = 0x0d,
  46 + CPU_ATTR_DRAM_CS2 = 0x0b,
  47 + CPU_ATTR_DRAM_CS3 = 0x07,
  48 + CPU_ATTR_NANDFLASH = 0x2f,
  49 + CPU_ATTR_SPIFLASH = 0x1e,
  50 + CPU_ATTR_BOOTROM = 0x1d,
  51 + CPU_ATTR_PCIE_IO = 0xe0,
  52 + CPU_ATTR_PCIE_MEM = 0xe8,
  53 + CPU_ATTR_DEV_CS0 = 0x3e,
  54 + CPU_ATTR_DEV_CS1 = 0x3d,
  55 + CPU_ATTR_DEV_CS2 = 0x3b,
  56 + CPU_ATTR_DEV_CS3 = 0x37,
  57 +};
  58 +
  59 +/*
  60 + * Default Device Address MAP BAR values
  61 + */
  62 +#define DEFADR_PCI_MEM 0x90000000
  63 +#define DEFADR_PCI_IO 0xC0000000
  64 +#define DEFADR_SPIF 0xF4000000
  65 +#define DEFADR_BOOTROM 0xF8000000
  66 +
  67 +struct mbus_win {
  68 + u32 base;
  69 + u32 size;
  70 + u8 target;
  71 + u8 attr;
  72 +};
  73 +
  74 +/*
  75 + * System registers
  76 + * Ref: Datasheet sec:A.28
  77 + */
  78 +struct mvebu_system_registers {
  79 + u8 pad1[0x60];
  80 + u32 rstoutn_mask; /* 0x60 */
  81 + u32 sys_soft_rst; /* 0x64 */
  82 +};
  83 +
  84 +/*
  85 + * GPIO Registers
  86 + * Ref: Datasheet sec:A.19
  87 + */
  88 +struct kwgpio_registers {
  89 + u32 dout;
  90 + u32 oe;
  91 + u32 blink_en;
  92 + u32 din_pol;
  93 + u32 din;
  94 + u32 irq_cause;
  95 + u32 irq_mask;
  96 + u32 irq_level;
  97 +};
  98 +
  99 +/* Needed for dynamic (board-specific) mbus configuration */
  100 +extern struct mvebu_mbus_state mbus_state;
  101 +
  102 +/*
  103 + * functions
  104 + */
  105 +unsigned int mvebu_sdram_bar(enum memory_bank bank);
  106 +unsigned int mvebu_sdram_bs(enum memory_bank bank);
  107 +void mvebu_sdram_size_adjust(enum memory_bank bank);
  108 +int mvebu_mbus_probe(struct mbus_win windows[], int count);
  109 +
  110 +/*
  111 + * Highspeed SERDES PHY config init, ported from bin_hdr
  112 + * to mainline U-Boot
  113 + */
  114 +int serdes_phy_config(void);
  115 +
  116 +/*
  117 + * DDR3 init / training code ported from Marvell bin_hdr. Now
  118 + * available in mainline U-Boot in:
  119 + * drivers/ddr/mvebu/
  120 + */
  121 +int ddr3_init(void);
  122 +#endif /* __ASSEMBLY__ */
  123 +#endif /* _ARMADA_XP_CPU_H */
arch/arm/mach-mvebu/include/mach/soc.h
Diff comments   View file @ 8cb7872
  1 +/*
  2 + * (C) Copyright 2009
  3 + * Marvell Semiconductor <www.marvell.com>
  4 + * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  5 + *
  6 + * Header file for the Marvell's Feroceon CPU core.
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +
  11 +#ifndef _ASM_ARCH_ARMADA_XP_H
  12 +#define _ASM_ARCH_ARMADA_XP_H
  13 +
  14 +#define SOC_MV78460_ID 0x7846
  15 +
  16 +/* TCLK Core Clock definition */
  17 +#ifndef CONFIG_SYS_TCLK
  18 +#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
  19 +#endif
  20 +
  21 +/* SOC specific definations */
  22 +#define INTREG_BASE 0xd0000000
  23 +#define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080)
  24 +#define SOC_REGS_PHY_BASE 0xf1000000
  25 +#define MVEBU_REGISTER(x) (SOC_REGS_PHY_BASE + x)
  26 +
  27 +#define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504))
  28 +#define MVEBU_SPI_BASE (MVEBU_REGISTER(0x10600))
  29 +#define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000))
  30 +#define MVEBU_UART0_BASE (MVEBU_REGISTER(0x12000))
  31 +#define MVEBU_UART1_BASE (MVEBU_REGISTER(0x12100))
  32 +#define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000))
  33 +#define MVEBU_GPIO0_BASE (MVEBU_REGISTER(0x18100))
  34 +#define MVEBU_GPIO1_BASE (MVEBU_REGISTER(0x18140))
  35 +#define MVEBU_GPIO2_BASE (MVEBU_REGISTER(0x18180))
  36 +#define MVEBU_SYSTEM_REG_BASE (MVEBU_REGISTER(0x18200))
  37 +#define MVEBU_CPU_WIN_BASE (MVEBU_REGISTER(0x20000))
  38 +#define MVEBU_SDRAM_BASE (MVEBU_REGISTER(0x20180))
  39 +#define MVEBU_TIMER_BASE (MVEBU_REGISTER(0x20300))
  40 +#define MVEBU_EGIGA2_BASE (MVEBU_REGISTER(0x30000))
  41 +#define MVEBU_EGIGA3_BASE (MVEBU_REGISTER(0x34000))
  42 +#define MVEBU_REG_PCIE_BASE (MVEBU_REGISTER(0x40000))
  43 +#define MVEBU_EGIGA0_BASE (MVEBU_REGISTER(0x70000))
  44 +#define MVEBU_EGIGA1_BASE (MVEBU_REGISTER(0x74000))
  45 +
  46 +#define SDRAM_MAX_CS 4
  47 +#define SDRAM_ADDR_MASK 0xFF000000
  48 +
  49 +/* Armada XP GbE controller has 4 ports */
  50 +#define MAX_MVNETA_DEVS 4
  51 +
  52 +/* Kirkwood CPU memory windows */
  53 +#define MVCPU_WIN_CTRL_DATA CPU_WIN_CTRL_DATA
  54 +#define MVCPU_WIN_ENABLE CPU_WIN_ENABLE
  55 +#define MVCPU_WIN_DISABLE CPU_WIN_DISABLE
  56 +
  57 +#endif /* _ASM_ARCH_ARMADA_XP_H */
board/Marvell/db-mv784mp-gp/Kconfig
Diff comments   View file @ 8cb7872
... ... @@ -7,7 +7,7 @@
7 7 default "Marvell"
8 8  
9 9 config SYS_SOC
10   - default "armada-xp"
  10 + default "mvebu"
11 11  
12 12 config SYS_CONFIG_NAME
13 13 default "db-mv784mp-gp"
board/maxbcm/Kconfig
Diff comments   View file @ 8cb7872
... ... @@ -4,7 +4,7 @@
4 4 default "maxbcm"
5 5  
6 6 config SYS_SOC
7   - default "armada-xp"
  7 + default "mvebu"
8 8  
9 9 config SYS_CONFIG_NAME
10 10 default "maxbcm"