Commit 8d352247ecf3638cdd1ef7df31a6ad700bb80574
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- CHANGELOG
- CREDITS
- MAINTAINERS
- MAKEALL
- Makefile
- board/gth2/Makefile
- board/gth2/config.mk
- board/gth2/ee_access.c
- board/gth2/ee_access.h
- board/gth2/ee_dev.h
- board/gth2/flash.c
- board/gth2/gth2.c
- board/gth2/lowlevel_init.S
- board/gth2/u-boot.lds
- board/tqm5200/Makefile
- board/tqm5200/flash.c
- board/tqm5200/tqm5200.c
- board/tqm834x/tqm834x.c
- board/tqm85xx/tqm85xx.c
- board/trab/cmd_trab.c
- board/trab/trab.c
- board/trab/tsc2000.c
- board/trab/vfd.c
- common/cmd_ide.c
- common/serial.c
- cpu/arm920t/s3c24x0/i2c.c
- cpu/mpc5xxx/serial.c
- doc/README.serial_multi
- drivers/keyboard.c
- drivers/ps2ser.c
- include/asm-mips/au1x00.h
- include/configs/TQM5200.h
- include/configs/TQM85xx.h
- include/configs/cmc_pu2.h
- include/configs/gth2.h
- include/configs/spieval.h
- include/configs/trab.h
- include/serial.h
CHANGELOG
... | ... | @@ -2,6 +2,76 @@ |
2 | 2 | Changes since U-Boot 1.1.4: |
3 | 3 | ====================================================================== |
4 | 4 | |
5 | +* Add support for gth2 board | |
6 | + Patch by Thomas Lange, Aug 11 2005 | |
7 | + | |
8 | +* Add support for CONFIG_SERIAL_MULTI on MPC5xxx | |
9 | + Patch by Martin Krause, 8 Jun 2006 | |
10 | + | |
11 | + This patch supports two serial consoles on boards with | |
12 | + a MPC5xxx CPU. The console can be switched at runtime | |
13 | + by setting stdin, stdout and stderr to the desired serial | |
14 | + interface (serial0 or serial1). The PSCs to be used as | |
15 | + console port are definded by CONFIG_PSC_CONSOLE | |
16 | + and CONFIG_PSC_CONSOLE2. | |
17 | + See README.serial_multi for details. | |
18 | + | |
19 | +* Bugfix in I2C initialisation on S3C2400. | |
20 | + If the bus is blocked because of a previously interrupted | |
21 | + transfer, up to eleven clocks are generated on the I2CSCL | |
22 | + line to complete the transfer and to free the bus. | |
23 | + With this fix pin I2CSCL (PG6) is really configured as GPIO | |
24 | + so the clock pulses are really generated. | |
25 | + Patch by Martin Krause, 04 Apr 2006 | |
26 | + | |
27 | +* Fix DDR6 errata on TQM834x boards | |
28 | + Patch by Thomas Waehner, 07 Mar 2006 | |
29 | + | |
30 | +* Remove obsolete flash driver board/tqm5200/flash.c | |
31 | + Patch by Martin Krause, 11 Jan 2006 | |
32 | + | |
33 | +* Update configuration for CMC-PU2 board | |
34 | + Patch by Martin Krause, 17 Nov 2005 | |
35 | + | |
36 | +* Add support for PS/2 keyboard on TQM85xx board | |
37 | + Patch by Martin Krause, 07 Nov 2005 | |
38 | + | |
39 | + Tested on a STK85XX baseboard. Make sure the PS/2 controller | |
40 | + has been programmed. Jumper Settings: X66 1-2, 9-10; X61 2-3 | |
41 | + | |
42 | +* Fix TRAB channel switching delay for trab_fkt.bin standalone applikation | |
43 | + In tsc2000_read_channel() the delay after setting the multiplexer | |
44 | + to a temperature channel is increased from 1,5 ms to 10 ms. This | |
45 | + is to allow the multiplexer inputs to stabilize after huge steps | |
46 | + of the input signal level. | |
47 | + Patch by Martin Krause, 08 Nov 2005 | |
48 | + | |
49 | +* Adjust TQM5200 make targets | |
50 | + Make the automatic CS configuration the default. | |
51 | + The dedicated configurations CONFIG_TQM5200_AA, CONFIG_TQM5200_AB | |
52 | + and CONFIG_TQM5200_AC are removed. | |
53 | + "TQM5200_config" is now the default for STK52XX.200 base boards. | |
54 | + On a STK52XX.100 base board "TQM5200_STK100_config" must be used. | |
55 | + Patch by Martin Krause, 07 Nov 2005 | |
56 | + | |
57 | +* Fix setting of environment variable "ver" on trab board | |
58 | + The environment variable "ver" is now set before | |
59 | + do_auto_update() is called, so that "ver" can be used | |
60 | + in USB update scripts. | |
61 | + Patch by Martin Krause, 27 Oct 2005 | |
62 | + | |
63 | +* Fix wrong usage of udelay() in led_blink() on trab board | |
64 | + Patch by Martin Krause, 27 Oct 2005 | |
65 | + | |
66 | +* Fix udelay bug in vfd.c for trab board | |
67 | + Patch by Martin Krause, 27 Oct 2005 | |
68 | + | |
69 | +* Disable JFFS2 support for trab board | |
70 | + Patch by Martin Krause, 27 Oct 2005 | |
71 | + | |
72 | +* Change mtdparts definition on trab board to match current flash map | |
73 | + Patch by Martin Krause, 27 Oct 2005 | |
74 | + | |
5 | 75 | * Fix memory init problems on MCC200 board |
6 | 76 | |
7 | 77 | * Fix IxEthDB.h to compile again |
CREDITS
MAINTAINERS
MAKEALL
... | ... | @@ -28,7 +28,7 @@ |
28 | 28 | BC3450 cpci5200 EVAL5200 icecube_5100 \ |
29 | 29 | icecube_5200 lite5200b mcc200 o2dnt \ |
30 | 30 | pf5200 PM520 Total5100 Total5200 \ |
31 | - Total5200_Rev2 TQM5200_auto \ | |
31 | + Total5200_Rev2 TQM5200 \ | |
32 | 32 | " |
33 | 33 | |
34 | 34 | ######################################################################### |
... | ... | @@ -226,7 +226,7 @@ |
226 | 226 | |
227 | 227 | LIST_mips5kc="purple" |
228 | 228 | |
229 | -LIST_au1xx0="dbau1000 dbau1100 dbau1500 dbau1550 dbau1550_el" | |
229 | +LIST_au1xx0="dbau1000 dbau1100 dbau1500 dbau1550 dbau1550_el gth2" | |
230 | 230 | |
231 | 231 | LIST_mips="${LIST_mips4kc} ${LIST_mips5kc} ${LIST_au1xx0}" |
232 | 232 |
Makefile
... | ... | @@ -356,8 +356,8 @@ |
356 | 356 | @./mkconfig -a smmaco4 ppc mpc5xxx tqm5200 |
357 | 357 | |
358 | 358 | spieval_config: unconfig |
359 | - echo "#define CONFIG_CS_AUTOCONF">>include/config.h | |
360 | - echo "... with automatic CS configuration" | |
359 | + @echo "#define CONFIG_CS_AUTOCONF">>include/config.h | |
360 | + @echo "... with automatic CS configuration" | |
361 | 361 | @./mkconfig -a spieval ppc mpc5xxx tqm5200 |
362 | 362 | |
363 | 363 | MINI5200_config \ |
364 | 364 | |
365 | 365 | |
366 | 366 | |
... | ... | @@ -394,35 +394,20 @@ |
394 | 394 | } |
395 | 395 | @./mkconfig -a Total5200 ppc mpc5xxx total5200 |
396 | 396 | |
397 | -TQM5200_auto_config \ | |
398 | -TQM5200_AA_config \ | |
399 | -TQM5200_AB_config \ | |
400 | -TQM5200_AC_config \ | |
397 | +TQM5200_config \ | |
398 | +TQM5200_STK100_config \ | |
401 | 399 | MiniFAP_config: unconfig |
402 | 400 | @ >include/config.h |
403 | 401 | @[ -z "$(findstring MiniFAP,$@)" ] || \ |
404 | 402 | { echo "#define CONFIG_MINIFAP" >>include/config.h ; \ |
405 | - echo "#define CONFIG_TQM5200_AC" >>include/config.h ; \ | |
406 | 403 | echo "... TQM5200_AC on MiniFAP" ; \ |
407 | 404 | } |
408 | - @[ -z "$(findstring AA,$@)" ] || \ | |
409 | - { echo "#define CONFIG_TQM5200_AA" >>include/config.h ; \ | |
410 | - echo "... with 4 MB Flash, 16 MB SDRAM, 32 kB EEPROM" ; \ | |
405 | + @[ -z "$(findstring STK100,$@)" ] || \ | |
406 | + { echo "#define CONFIG_STK52XX_REV100" >>include/config.h ; \ | |
407 | + echo "... on a STK52XX.100 base board" ; \ | |
411 | 408 | } |
412 | - @[ -z "$(findstring AB,$@)" ] || \ | |
413 | - { echo "#define CONFIG_TQM5200_AB" >>include/config.h ; \ | |
414 | - echo "... with 64 MB Flash, 64 MB SDRAM, 32 kB EEPROM, 512 kB SRAM" ; \ | |
415 | - echo "... with Graphics Controller"; \ | |
416 | - } | |
417 | - @[ -z "$(findstring AC,$@)" ] || \ | |
418 | - { echo "#define CONFIG_TQM5200_AC" >>include/config.h ; \ | |
419 | - echo "... with 4 MB Flash, 128 MB SDRAM" ; \ | |
420 | - echo "... with Graphics Controller"; \ | |
421 | - } | |
422 | - @[ -z "$(findstring auto,$@)" ] || \ | |
423 | - { echo "#define CONFIG_CS_AUTOCONF" >>include/config.h ; \ | |
424 | - echo "... with automatic CS configuration" ; \ | |
425 | - } | |
409 | + @echo "#define CONFIG_CS_AUTOCONF">>include/config.h ; | |
410 | + @echo "... with automatic CS configuration" ; | |
426 | 411 | @./mkconfig -a TQM5200 ppc mpc5xxx tqm5200 |
427 | 412 | |
428 | 413 | ######################################################################### |
... | ... | @@ -1666,6 +1651,11 @@ |
1666 | 1651 | |
1667 | 1652 | cm41xx_config : unconfig |
1668 | 1653 | @./mkconfig $(@:_config=) arm arm920t cm41xx NULL ks8695 |
1654 | + | |
1655 | +gth2_config : unconfig | |
1656 | + @ >include/config.h | |
1657 | + @echo "#define CONFIG_GTH2 1" >>include/config.h | |
1658 | + @./mkconfig -a gth2 mips mips gth2 | |
1669 | 1659 | |
1670 | 1660 | ######################################################################### |
1671 | 1661 | ## S3C44B0 Systems |
board/gth2/Makefile
1 | +# | |
2 | +# (C) Copyright 2005 | |
3 | +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | +# | |
5 | +# See file CREDITS for list of people who contributed to this | |
6 | +# project. | |
7 | +# | |
8 | +# This program is free software; you can redistribute it and/or | |
9 | +# modify it under the terms of the GNU General Public License as | |
10 | +# published by the Free Software Foundation; either version 2 of | |
11 | +# the License, or (at your option) any later version. | |
12 | +# | |
13 | +# This program is distributed in the hope that it will be useful, | |
14 | +# but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | +# GNU General Public License for more details. | |
17 | +# | |
18 | +# You should have received a copy of the GNU General Public License | |
19 | +# along with this program; if not, write to the Free Software | |
20 | +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | +# MA 02111-1307 USA | |
22 | +# | |
23 | + | |
24 | +include $(TOPDIR)/config.mk | |
25 | + | |
26 | +LIB = lib$(BOARD).a | |
27 | + | |
28 | +OBJS = $(BOARD).o flash.o ee_access.o | |
29 | +SOBJS = lowlevel_init.o | |
30 | + | |
31 | +$(LIB): .depend $(OBJS) $(SOBJS) | |
32 | + $(AR) crv $@ $(OBJS) $(SOBJS) | |
33 | + | |
34 | +######################################################################### | |
35 | + | |
36 | +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) | |
37 | + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ | |
38 | + | |
39 | +sinclude .depend | |
40 | + | |
41 | +######################################################################### |
board/gth2/config.mk
1 | +# | |
2 | +# (C) Copyright 2004-2005 | |
3 | +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | +# | |
5 | +# See file CREDITS for list of people who contributed to this | |
6 | +# project. | |
7 | +# | |
8 | +# This program is free software; you can redistribute it and/or | |
9 | +# modify it under the terms of the GNU General Public License as | |
10 | +# published by the Free Software Foundation; either version 2 of | |
11 | +# the License, or (at your option) any later version. | |
12 | +# | |
13 | +# This program is distributed in the hope that it will be useful, | |
14 | +# but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | +# GNU General Public License for more details. | |
17 | +# | |
18 | +# You should have received a copy of the GNU General Public License | |
19 | +# along with this program; if not, write to the Free Software | |
20 | +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | +# MA 02111-1307 USA | |
22 | +# | |
23 | + | |
24 | +# | |
25 | +# AMD Alchemy AU1000, MIPS32 core | |
26 | +# | |
27 | + | |
28 | +ifeq ($(TBASE),0) | |
29 | +TEXT_BASE = 0 | |
30 | +else | |
31 | +ifeq ($(TBASE),1) | |
32 | +TEXT_BASE = 0xbfc10070 | |
33 | +else | |
34 | +ifeq ($(TBASE),2) | |
35 | +TEXT_BASE = 0xbfc30070 | |
36 | +else | |
37 | +## Only to make ordinary make work | |
38 | +TEXT_BASE = 0x90000000 | |
39 | +endif | |
40 | +endif | |
41 | +endif |
board/gth2/ee_access.c
1 | +/* Module for handling DALLAS DS2438, smart battery monitor | |
2 | + Chip can store up to 40 bytes of user data in EEPROM, | |
3 | + perform temp, voltage and current measurements. | |
4 | + Chip also contains a unique serial number. | |
5 | + | |
6 | + Always read/write LSb first | |
7 | + | |
8 | + For documentaion, see data sheet for DS2438, 2438.pdf | |
9 | + | |
10 | + By Thomas.Lange@corelatus.com 001025 | |
11 | + | |
12 | + Copyright (C) 2000-2005 Corelatus AB */ | |
13 | + | |
14 | +/* This program is free software; you can redistribute it and/or | |
15 | + * modify it under the terms of the GNU General Public License as | |
16 | + * published by the Free Software Foundation; either version 2 of | |
17 | + * the License, or (at your option) any later version. | |
18 | + * | |
19 | + * This program is distributed in the hope that it will be useful, | |
20 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | + * GNU General Public License for more details. | |
23 | + * | |
24 | + * You should have received a copy of the GNU General Public License | |
25 | + * along with this program; if not, write to the Free Software | |
26 | + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
27 | + * MA 02111-1307 USA | |
28 | + */ | |
29 | + | |
30 | +#include <common.h> | |
31 | +#include <command.h> | |
32 | +#include <asm/au1x00.h> | |
33 | +#include <asm/io.h> | |
34 | +#include "ee_dev.h" | |
35 | +#include "ee_access.h" | |
36 | + | |
37 | +/* static int Debug = 1; */ | |
38 | +#undef E_DEBUG | |
39 | +#define E_DEBUG(fmt,args...) /* */ | |
40 | +/* #define E_DEBUG(fmt,args...) printk("EEA:"fmt,##args); */ | |
41 | + | |
42 | +/* We dont have kernel functions */ | |
43 | +#define printk printf | |
44 | +#define KERN_DEBUG | |
45 | +#define KERN_ERR | |
46 | +#define EIO 1 | |
47 | + | |
48 | +#ifndef TRUE | |
49 | +#define TRUE 1 | |
50 | +#endif | |
51 | +#ifndef FALSE | |
52 | +#define FALSE 0 | |
53 | +#endif | |
54 | + | |
55 | +/* lookup table ripped from DS app note 17, understanding and using cyclic redundancy checks... */ | |
56 | + | |
57 | +static u8 crc_lookup[256] = { | |
58 | + 0, 94, 188, 226, 97, 63, 221, 131, | |
59 | + 194, 156, 126, 32, 163, 253, 31, 65, | |
60 | + 157, 195, 33, 127, 252, 162, 64, 30, | |
61 | + 95, 1, 227, 189, 62, 96, 130, 220, | |
62 | + 35, 125, 159, 193, 66, 28, 254, 160, | |
63 | + 225, 191, 93, 3, 128, 222, 60, 98, | |
64 | + 190, 224, 2, 92, 223, 129, 99, 61, | |
65 | + 124, 34, 192, 158, 29, 67, 161, 255, | |
66 | + 70, 24, 250, 164, 39, 121, 155, 197, | |
67 | + 132, 218, 56, 102, 229, 187, 89, 7, | |
68 | + 219, 133, 103, 57, 186, 228, 6, 88, | |
69 | + 25, 71, 165, 251, 120, 38, 196, 154, | |
70 | + 101, 59, 217, 135, 4, 90, 184, 230, | |
71 | + 167, 249, 27, 69, 198, 152, 122, 36, | |
72 | + 248, 166, 68, 26, 153, 199, 37, 123, | |
73 | + 58, 100, 134, 216, 91, 5, 231, 185, | |
74 | + 140, 210, 48, 110, 237, 179, 81, 15, | |
75 | + 78, 16, 242, 172, 47, 113, 147, 205, | |
76 | + 17, 79, 173, 243, 112, 46, 204, 146, | |
77 | + 211, 141, 111, 49, 178, 236, 14, 80, | |
78 | + 175, 241, 19, 77, 206, 144, 114, 44, | |
79 | + 109, 51, 209, 143, 12, 82, 176, 238, | |
80 | + 50, 108, 142, 208, 83, 13, 239, 177, | |
81 | + 240, 174, 76, 18, 145, 207, 45, 115, | |
82 | + 202, 148, 118, 40, 171, 245, 23, 73, | |
83 | + 8, 86, 180, 234, 105, 55, 213, 139, | |
84 | + 87, 9, 235, 181, 54, 104, 138, 212, | |
85 | + 149, 203, 41, 119, 244, 170, 72, 22, | |
86 | + 233, 183, 85, 11, 136, 214, 52, 106, | |
87 | + 43, 117, 151, 201, 74, 20, 246, 168, | |
88 | + 116, 42, 200, 150, 21, 75, 169, 247, | |
89 | + 182, 232, 10, 84, 215, 137, 107, 53 | |
90 | +}; | |
91 | + | |
92 | +static void | |
93 | +write_gpio_data(int value ){ | |
94 | + if(value){ | |
95 | + /* Tristate */ | |
96 | + gpio_tristate(GPIO_EEDQ); | |
97 | + } | |
98 | + else{ | |
99 | + /* Drive 0 */ | |
100 | + gpio_clear(GPIO_EEDQ); | |
101 | + } | |
102 | +} | |
103 | + | |
104 | +static u8 make_new_crc( u8 Old_crc, u8 New_value ){ | |
105 | + /* Compute a new checksum with new byte, using previous checksum as input | |
106 | + See DS app note 17, understanding and using cyclic redundancy checks... | |
107 | + Also see DS2438, page 11 */ | |
108 | + return( crc_lookup[Old_crc ^ New_value ]); | |
109 | +} | |
110 | + | |
111 | +int ee_crc_ok( u8 *Buffer, int Len, u8 Crc ){ | |
112 | + /* Check if the checksum for this buffer is correct */ | |
113 | + u8 Curr_crc=0; | |
114 | + int i; | |
115 | + u8 *Curr_byte = Buffer; | |
116 | + | |
117 | + for(i=0;i<Len;i++){ | |
118 | + Curr_crc = make_new_crc( Curr_crc, *Curr_byte); | |
119 | + Curr_byte++; | |
120 | + } | |
121 | + E_DEBUG("Calculated CRC = 0x%x, read = 0x%x\n", Curr_crc, Crc); | |
122 | + | |
123 | + if(Curr_crc == Crc){ | |
124 | + /* Good */ | |
125 | + return(TRUE); | |
126 | + } | |
127 | + printk(KERN_ERR"EE checksum error, Calculated CRC = 0x%x, read = 0x%x\n", Curr_crc, Crc); | |
128 | + return(FALSE); | |
129 | +} | |
130 | + | |
131 | +static void | |
132 | +set_idle(void){ | |
133 | + /* Send idle and keep start time | |
134 | + Continous 1 is idle */ | |
135 | + WRITE_PORT(1); | |
136 | +} | |
137 | + | |
138 | + | |
139 | +static int | |
140 | +do_cpu_reset(void){ | |
141 | + /* Release reset and verify that chip responds with presence pulse */ | |
142 | + int Retries=0; | |
143 | + while(Retries<15){ | |
144 | + udelay(RESET_LOW_TIME); | |
145 | + | |
146 | + /* Send reset */ | |
147 | + WRITE_PORT(0); | |
148 | + udelay(RESET_LOW_TIME); | |
149 | + | |
150 | + /* Release reset */ | |
151 | + WRITE_PORT(1); | |
152 | + | |
153 | + /* Wait for EEPROM to drive output */ | |
154 | + udelay(PRESENCE_TIMEOUT); | |
155 | + if(!READ_PORT){ | |
156 | + /* Ok, EEPROM is driving a 0 */ | |
157 | + E_DEBUG("Presence detected\n"); | |
158 | + if(Retries){ | |
159 | + E_DEBUG("Retries %d\n",Retries); | |
160 | + } | |
161 | + /* Make sure chip releases pin */ | |
162 | + udelay(PRESENCE_LOW_TIME); | |
163 | + return 0; | |
164 | + } | |
165 | + Retries++; | |
166 | + } | |
167 | + | |
168 | + printk(KERN_ERR"eeprom did not respond when releasing reset\n"); | |
169 | + | |
170 | + /* Make sure chip releases pin */ | |
171 | + udelay(PRESENCE_LOW_TIME); | |
172 | + | |
173 | + /* Set to idle again */ | |
174 | + set_idle(); | |
175 | + | |
176 | + return(-EIO); | |
177 | +} | |
178 | + | |
179 | +static u8 | |
180 | +read_cpu_byte(void){ | |
181 | + /* Read a single byte from EEPROM | |
182 | + Read LSb first */ | |
183 | + int i; | |
184 | + int Value; | |
185 | + u8 Result=0; | |
186 | + u32 Flags; | |
187 | + | |
188 | + E_DEBUG("Reading byte\n"); | |
189 | + | |
190 | + for(i=0;i<8;i++){ | |
191 | + /* Small delay between pulses */ | |
192 | + udelay(1); | |
193 | + | |
194 | +#ifdef __KERNEL__ | |
195 | + /* Disable irq */ | |
196 | + save_flags(Flags); | |
197 | + cli(); | |
198 | +#endif | |
199 | + | |
200 | + /* Pull down pin short time to start read | |
201 | + See page 26 in data sheet */ | |
202 | + | |
203 | + WRITE_PORT(0); | |
204 | + udelay(READ_LOW); | |
205 | + WRITE_PORT(1); | |
206 | + | |
207 | + /* Wait for chip to drive pin */ | |
208 | + udelay(READ_TIMEOUT); | |
209 | + | |
210 | + Value = READ_PORT; | |
211 | + if(Value) | |
212 | + Value=1; | |
213 | + | |
214 | +#ifdef __KERNEL__ | |
215 | + /* Enable irq */ | |
216 | + restore_flags(Flags); | |
217 | +#endif | |
218 | + | |
219 | + /* Wait for chip to release pin */ | |
220 | + udelay(TOTAL_READ_LOW-READ_TIMEOUT); | |
221 | + | |
222 | + /* LSb first */ | |
223 | + Result|=Value<<i; | |
224 | + /* E_DEBUG("Read %d\n",Value); */ | |
225 | + | |
226 | + } | |
227 | + | |
228 | + E_DEBUG("Read byte 0x%x\n",Result); | |
229 | + | |
230 | + return(Result); | |
231 | +} | |
232 | + | |
233 | +static void | |
234 | +write_cpu_byte(u8 Byte){ | |
235 | + /* Write a single byte to EEPROM | |
236 | + Write LSb first */ | |
237 | + int i; | |
238 | + int Value; | |
239 | + u32 Flags; | |
240 | + | |
241 | + E_DEBUG("Writing byte 0x%x\n",Byte); | |
242 | + | |
243 | + for(i=0;i<8;i++){ | |
244 | + /* Small delay between pulses */ | |
245 | + udelay(1); | |
246 | + Value = Byte&1; | |
247 | + | |
248 | +#ifdef __KERNEL__ | |
249 | + /* Disable irq */ | |
250 | + save_flags(Flags); | |
251 | + cli(); | |
252 | +#endif | |
253 | + | |
254 | + /* Pull down pin short time for a 1, long time for a 0 | |
255 | + See page 26 in data sheet */ | |
256 | + | |
257 | + WRITE_PORT(0); | |
258 | + if(Value){ | |
259 | + /* Write a 1 */ | |
260 | + udelay(WRITE_1_LOW); | |
261 | + } | |
262 | + else{ | |
263 | + /* Write a 0 */ | |
264 | + udelay(WRITE_0_LOW); | |
265 | + } | |
266 | + | |
267 | + WRITE_PORT(1); | |
268 | + | |
269 | +#ifdef __KERNEL__ | |
270 | + /* Enable irq */ | |
271 | + restore_flags(Flags); | |
272 | +#endif | |
273 | + | |
274 | + if(Value) | |
275 | + /* Wait for chip to read the 1 */ | |
276 | + udelay(TOTAL_WRITE_LOW-WRITE_1_LOW); | |
277 | + | |
278 | + /* E_DEBUG("Wrote %d\n",Value); */ | |
279 | + Byte>>=1; | |
280 | + } | |
281 | +} | |
282 | + | |
283 | +int ee_do_cpu_command( u8 *Tx, int Tx_len, u8 *Rx, int Rx_len, int Send_skip ){ | |
284 | + /* Execute this command string, including | |
285 | + giving reset and setting to idle after command | |
286 | + if Rx_len is set, we read out data from EEPROM */ | |
287 | + int i; | |
288 | + | |
289 | + E_DEBUG("Command, Tx_len %d, Rx_len %d\n", Tx_len, Rx_len ); | |
290 | + | |
291 | + if(do_cpu_reset()){ | |
292 | + /* Failed! */ | |
293 | + return(-EIO); | |
294 | + } | |
295 | + | |
296 | + if(Send_skip) | |
297 | + /* Always send SKIP_ROM first to tell chip we are sending a command, | |
298 | + except when we read out rom data for chip */ | |
299 | + write_cpu_byte(SKIP_ROM); | |
300 | + | |
301 | + /* Always have Tx data */ | |
302 | + for(i=0;i<Tx_len;i++){ | |
303 | + write_cpu_byte(Tx[i]); | |
304 | + } | |
305 | + | |
306 | + if(Rx_len){ | |
307 | + for(i=0;i<Rx_len;i++){ | |
308 | + Rx[i]=read_cpu_byte(); | |
309 | + } | |
310 | + } | |
311 | + | |
312 | + set_idle(); | |
313 | + | |
314 | + E_DEBUG("Command done\n"); | |
315 | + | |
316 | + return(0); | |
317 | +} | |
318 | + | |
319 | +int ee_init_cpu_data(void){ | |
320 | + int i; | |
321 | + u8 Tx[10]; | |
322 | + | |
323 | + /* Leave it floting since altera is driving the same pin */ | |
324 | + set_idle(); | |
325 | + | |
326 | + /* Copy all User EEPROM data to scratchpad */ | |
327 | + for(i=0;i<USER_PAGES;i++){ | |
328 | + Tx[0]=RECALL_MEMORY; | |
329 | + Tx[1]=EE_USER_PAGE_0+i; | |
330 | + if(ee_do_cpu_command(Tx,2,NULL,0,TRUE)) return(-EIO); | |
331 | + } | |
332 | + | |
333 | + /* Make sure chip doesnt store measurements in NVRAM */ | |
334 | + Tx[0]=WRITE_SCRATCHPAD; | |
335 | + Tx[1]=0; /* Page */ | |
336 | + Tx[2]=9; | |
337 | + if(ee_do_cpu_command(Tx,3,NULL,0,TRUE)) return(-EIO); | |
338 | + | |
339 | + Tx[0]=COPY_SCRATCHPAD; | |
340 | + if(ee_do_cpu_command(Tx,2,NULL,0,TRUE)) return(-EIO); | |
341 | + | |
342 | + for(i=0;i<10;i++){ | |
343 | + udelay(1000); | |
344 | + } | |
345 | + | |
346 | + return(0); | |
347 | +} |
board/gth2/ee_access.h
1 | +/* By Thomas.Lange@Corelatus.com 001025 */ | |
2 | + | |
3 | +/* Definitions for EEPROM/VOLT METER DS2438 */ | |
4 | +/* Copyright (C) 2000-2005 Corelatus AB */ | |
5 | + | |
6 | +#ifndef INCeeaccessh | |
7 | +#define INCeeaccessh | |
8 | + | |
9 | +#include <asm/types.h> | |
10 | +#include "ee_dev.h" | |
11 | + | |
12 | +int ee_do_cpu_command( u8 *Tx, int Tx_len, u8 *Rx, int Rx_len, int Send_skip ); | |
13 | +int ee_init_cpu_data(void); | |
14 | + | |
15 | +int ee_crc_ok( u8 *Buffer, int Len, u8 Crc ); | |
16 | + | |
17 | +/* Defs for altera reg */ | |
18 | +#define EE_WRITE_SHIFT 8 /* bits to shift left */ | |
19 | +#define EE_READ_SHIFT 16 /* bits to shift left */ | |
20 | +#define EE_DONE 0x80000000 | |
21 | +#define EE_BUSY 0x40000000 | |
22 | +#define EE_ERROR 0x20000000 | |
23 | + | |
24 | +/* Commands */ | |
25 | +#define EE_CMD_NOP 0 | |
26 | +#define EE_CMD_INIT_RES 1 | |
27 | +#define EE_CMD_WR_BYTE 2 | |
28 | +#define EE_CMD_RD_BYTE 3 | |
29 | + | |
30 | +#endif /* INCeeaccessh */ |
board/gth2/ee_dev.h
1 | +/* By Thomas.Lange@Corelatus.com 001025 */ | |
2 | +/* Definitions for EEPROM/VOLT METER DS2438 */ | |
3 | +/* Copyright (C) 2000-2005 Corelatus AB */ | |
4 | + | |
5 | +/* This program is free software; you can redistribute it and/or | |
6 | + * modify it under the terms of the GNU General Public License as | |
7 | + * published by the Free Software Foundation; either version 2 of | |
8 | + * the License, or (at your option) any later version. | |
9 | + * | |
10 | + * This program is distributed in the hope that it will be useful, | |
11 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | + * GNU General Public License for more details. | |
14 | + * | |
15 | + * You should have received a copy of the GNU General Public License | |
16 | + * along with this program; if not, write to the Free Software | |
17 | + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
18 | + * MA 02111-1307 USA | |
19 | + */ | |
20 | + | |
21 | +#ifndef INCeedevh | |
22 | +#define INCeedevh | |
23 | + | |
24 | +#define E_DEBUG(fmt,args...) if( Debug ) printk(KERN_DEBUG"EE: " fmt, ##args) | |
25 | + | |
26 | +/* MIPS */ | |
27 | +#define WRITE_PORT(Value) write_gpio_data(Value) | |
28 | + | |
29 | +#define READ_PORT (gpio_read()&GPIO_EEDQ) | |
30 | + | |
31 | +/* 64 bytes chip */ | |
32 | +#define EE_CHIP_SIZE 64 | |
33 | + | |
34 | +/* Board with new current resistor */ | |
35 | +#define EE_GTH_0304 1 | |
36 | + | |
37 | +/* new dsp and 64 MB SDRAM */ | |
38 | +#define EE_DSP_64 0x10 | |
39 | + | |
40 | +/* microsecs */ | |
41 | +/* Pull line down at least this long for reset pulse */ | |
42 | +#define RESET_LOW_TIME 490 | |
43 | + | |
44 | +/* Read presence pulse after we release reset pulse */ | |
45 | +#define PRESENCE_TIMEOUT 100 | |
46 | +#define PRESENCE_LOW_TIME 200 | |
47 | + | |
48 | +#define WRITE_0_LOW 60 | |
49 | +#define WRITE_1_LOW 1 | |
50 | +#define TOTAL_WRITE_LOW 60 | |
51 | + | |
52 | +#define READ_LOW 1 | |
53 | +#define READ_TIMEOUT 10 | |
54 | +#define TOTAL_READ_LOW 70 | |
55 | + | |
56 | +/* Rom function commands */ | |
57 | +#define READ_ROM 0x33 | |
58 | +#define MATCH_ROM 0x55 | |
59 | +#define SKIP_ROM 0xCC | |
60 | +#define SEARCH_ROM 0xF0 | |
61 | + | |
62 | + | |
63 | +/* Memory_command_function */ | |
64 | +#define WRITE_SCRATCHPAD 0x4E | |
65 | +#define READ_SCRATCHPAD 0xBE | |
66 | +#define COPY_SCRATCHPAD 0x48 | |
67 | +#define RECALL_MEMORY 0xB8 | |
68 | +#define CONVERT_TEMP 0x44 | |
69 | +#define CONVERT_VOLTAGE 0xB4 | |
70 | + | |
71 | +/* Chip is divided in 8 pages, 8 bytes each */ | |
72 | + | |
73 | +#define EE_PAGE_SIZE 8 | |
74 | + | |
75 | +/* All chip data we want are in page 0 */ | |
76 | + | |
77 | +/* Bytes in page 0 */ | |
78 | +#define EE_P0_STATUS 0 | |
79 | +#define EE_P0_TEMP_LSB 1 | |
80 | +#define EE_P0_TEMP_MSB 2 | |
81 | +#define EE_P0_VOLT_LSB 3 | |
82 | +#define EE_P0_VOLT_MSB 4 | |
83 | +#define EE_P0_CURRENT_LSB 5 | |
84 | +#define EE_P0_CURRENT_MSB 6 | |
85 | + | |
86 | + | |
87 | +/* 40 byte user data is located at page 3-7 */ | |
88 | +#define EE_USER_PAGE_0 3 | |
89 | +#define USER_PAGES 5 | |
90 | + | |
91 | +/* Layout of gth user pages usage */ | |
92 | +/* Bytes 0-16 ethernet addr in ascii ( len 17 ) */ | |
93 | + | |
94 | +#define EE_ETHERNET_OFFSET 0 | |
95 | + | |
96 | +#endif /* INCeedevh */ |
board/gth2/flash.c
1 | +/* | |
2 | + * (C) Copyright 2005 | |
3 | + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | + * | |
5 | + * See file CREDITS for list of people who contributed to this | |
6 | + * project. | |
7 | + * | |
8 | + * This program is free software; you can redistribute it and/or | |
9 | + * modify it under the terms of the GNU General Public License as | |
10 | + * published by the Free Software Foundation; either version 2 of | |
11 | + * the License, or (at your option) any later version. | |
12 | + * | |
13 | + * This program is distributed in the hope that it will be useful, | |
14 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | + * GNU General Public License for more details. | |
17 | + * | |
18 | + * You should have received a copy of the GNU General Public License | |
19 | + * along with this program; if not, write to the Free Software | |
20 | + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | + * MA 02111-1307 USA | |
22 | + */ | |
23 | + | |
24 | +#include <common.h> | |
25 | + | |
26 | +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ | |
27 | + | |
28 | +/*----------------------------------------------------------------------- | |
29 | + * flash_init() | |
30 | + * | |
31 | + * sets up flash_info and returns size of FLASH (bytes) | |
32 | + */ | |
33 | +unsigned long flash_init (void) | |
34 | +{ | |
35 | + printf ("Skipping flash_init\n"); | |
36 | + return (0); | |
37 | +} | |
38 | + | |
39 | +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) | |
40 | +{ | |
41 | + printf ("write_buff not implemented\n"); | |
42 | + return (-1); | |
43 | +} |
board/gth2/gth2.c
1 | +/* | |
2 | + * (C) Copyright 2005 | |
3 | + * Thomas.Lange@corelatus.se | |
4 | + * | |
5 | + * See file CREDITS for list of people who contributed to this | |
6 | + * project. | |
7 | + * | |
8 | + * This program is free software; you can redistribute it and/or | |
9 | + * modify it under the terms of the GNU General Public License as | |
10 | + * published by the Free Software Foundation; either version 2 of | |
11 | + * the License, or (at your option) any later version. | |
12 | + * | |
13 | + * This program is distributed in the hope that it will be useful, | |
14 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | + * GNU General Public License for more details. | |
17 | + * | |
18 | + * You should have received a copy of the GNU General Public License | |
19 | + * along with this program; if not, write to the Free Software | |
20 | + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | + * MA 02111-1307 USA | |
22 | + */ | |
23 | + | |
24 | +#include <common.h> | |
25 | +#include <command.h> | |
26 | +#include <asm/au1x00.h> | |
27 | +#include <asm/addrspace.h> | |
28 | +#include <asm/mipsregs.h> | |
29 | +#include <watchdog.h> | |
30 | + | |
31 | +#include "ee_access.h" | |
32 | + | |
33 | +static int wdi_status = 0; | |
34 | + | |
35 | +unsigned long mips_io_port_base = 0; | |
36 | + | |
37 | +#define SDRAM_SIZE ((64*1024*1024)-(12*4096)) | |
38 | + | |
39 | + | |
40 | +#define SERIAL_LOG_BUFFER KSEG1ADDR(SDRAM_SIZE + (8*4096)) | |
41 | + | |
42 | +void inline log_serial_char(char c){ | |
43 | + char *serial_log_buffer = (char*)SERIAL_LOG_BUFFER; | |
44 | + int serial_log_offset; | |
45 | + u32 *serial_log_offsetp = (u32*)SERIAL_LOG_BUFFER; | |
46 | + | |
47 | + serial_log_offset = *serial_log_offsetp; | |
48 | + | |
49 | + *(serial_log_buffer + serial_log_offset) = c; | |
50 | + | |
51 | + serial_log_offset++; | |
52 | + | |
53 | + if(serial_log_offset >= 4096){ | |
54 | + serial_log_offset = 4; | |
55 | + } | |
56 | + *serial_log_offsetp = serial_log_offset; | |
57 | +} | |
58 | + | |
59 | +void init_log_serial(void){ | |
60 | + char *serial_log_buffer = (char*)SERIAL_LOG_BUFFER; | |
61 | + u32 *serial_log_offsetp = (u32*)SERIAL_LOG_BUFFER; | |
62 | + | |
63 | + /* Copy buffer from last run */ | |
64 | + memcpy(serial_log_buffer + 4096, | |
65 | + serial_log_buffer, | |
66 | + 4096); | |
67 | + | |
68 | + memset(serial_log_buffer, 0, 4096); | |
69 | + | |
70 | + *serial_log_offsetp = 4; | |
71 | +} | |
72 | + | |
73 | + | |
74 | +void hw_watchdog_reset(void){ | |
75 | + volatile u32 *sys_outputset = (volatile u32*)SYS_OUTPUTSET; | |
76 | + volatile u32 *sys_outputclear = (volatile u32*)SYS_OUTPUTCLR; | |
77 | + if(wdi_status){ | |
78 | + *sys_outputset = GPIO_CPU_LED|GPIO_WDI; | |
79 | + wdi_status = 0; | |
80 | + } | |
81 | + else{ | |
82 | + *sys_outputclear = GPIO_CPU_LED|GPIO_WDI; | |
83 | + wdi_status = 1; | |
84 | + } | |
85 | +} | |
86 | + | |
87 | +long int initdram(int board_type) | |
88 | +{ | |
89 | + /* Sdram is setup by assembler code */ | |
90 | + /* If memory could be changed, we should return the true value here */ | |
91 | + | |
92 | + WATCHDOG_RESET(); | |
93 | + | |
94 | + return (SDRAM_SIZE); | |
95 | +} | |
96 | + | |
97 | +/* In cpu/mips/cpu.c */ | |
98 | +void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 ); | |
99 | + | |
100 | +void set_ledcard(u32 value){ | |
101 | + /* Clock 24 bits to led card */ | |
102 | + int i; | |
103 | + volatile u32 *sys_outputset = (volatile u32*)SYS_OUTPUTSET; | |
104 | + volatile u32 *sys_outputclr = (volatile u32*)SYS_OUTPUTCLR; | |
105 | + | |
106 | + /* Start with known values */ | |
107 | + *sys_outputclr = GPIO_LEDCLK|GPIO_LEDD; | |
108 | + | |
109 | + for(i=0;i<24;i++){ | |
110 | + if(value&0x00800000){ | |
111 | + *sys_outputset = GPIO_LEDD; | |
112 | + } | |
113 | + else{ | |
114 | + *sys_outputclr = GPIO_LEDD; | |
115 | + } | |
116 | + udelay(1); | |
117 | + *sys_outputset = GPIO_LEDCLK; | |
118 | + udelay(1); | |
119 | + *sys_outputclr = GPIO_LEDCLK; | |
120 | + udelay(1); | |
121 | + | |
122 | + value<<=1; | |
123 | + } | |
124 | + /* Data is enable output */ | |
125 | + *sys_outputset = GPIO_LEDD; | |
126 | +} | |
127 | + | |
128 | +int checkboard (void) | |
129 | +{ | |
130 | + volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL; | |
131 | + volatile u32 *sys_outputset = (volatile u32*)SYS_OUTPUTSET; | |
132 | + volatile u32 *sys_outputclr = (volatile u32*)SYS_OUTPUTCLR; | |
133 | + u32 proc_id; | |
134 | + | |
135 | + WATCHDOG_RESET(); | |
136 | + | |
137 | + *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */ | |
138 | + | |
139 | + proc_id = read_32bit_cp0_register(CP0_PRID); | |
140 | + | |
141 | + switch (proc_id >> 24) { | |
142 | + case 0: | |
143 | + puts ("Board: GTH2\n"); | |
144 | + printf ("CPU: Au1000 500 MHz, id: 0x%02x, rev: 0x%02x\n", | |
145 | + (proc_id >> 8) & 0xFF, proc_id & 0xFF); | |
146 | + break; | |
147 | + default: | |
148 | + printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id); | |
149 | + } | |
150 | +#ifdef CONFIG_IDE_PCMCIA | |
151 | + /* PCMCIA is on a 36 bit physical address. | |
152 | + We need to map it into a 32 bit addresses */ | |
153 | + write_one_tlb(20, /* index */ | |
154 | + 0x01ffe000, /* Pagemask, 16 MB pages */ | |
155 | + CFG_PCMCIA_IO_BASE, /* Hi */ | |
156 | + 0x3C000017, /* Lo0 */ | |
157 | + 0x3C200017); /* Lo1 */ | |
158 | + | |
159 | + write_one_tlb(21, /* index */ | |
160 | + 0x01ffe000, /* Pagemask, 16 MB pages */ | |
161 | + CFG_PCMCIA_ATTR_BASE, /* Hi */ | |
162 | + 0x3D000017, /* Lo0 */ | |
163 | + 0x3D200017); /* Lo1 */ | |
164 | + | |
165 | + write_one_tlb(22, /* index */ | |
166 | + 0x01ffe000, /* Pagemask, 16 MB pages */ | |
167 | + CFG_PCMCIA_MEM_ADDR, /* Hi */ | |
168 | + 0x3E000017, /* Lo0 */ | |
169 | + 0x3E200017); /* Lo1 */ | |
170 | + | |
171 | +#endif /* CONFIG_IDE_PCMCIA */ | |
172 | + | |
173 | + /* Wait for GPIO ports to become stable */ | |
174 | + udelay(5000); /* FIXME */ | |
175 | + | |
176 | + /* Release reset of ethernet PHY chips */ | |
177 | + /* Always do this, because linux does not know about it */ | |
178 | + *sys_outputset = GPIO_ERESET; | |
179 | + | |
180 | + /* Kill FPGA:s */ | |
181 | + *sys_outputclr = GPIO_CACONFIG|GPIO_DPACONFIG; | |
182 | + udelay(2); | |
183 | + *sys_outputset = GPIO_CACONFIG|GPIO_DPACONFIG; | |
184 | + | |
185 | + /* Turn front led yellow */ | |
186 | + set_ledcard(0x00100000); | |
187 | + | |
188 | + return 0; | |
189 | +} | |
190 | + | |
191 | +#define POWER_OFFSET 0xF0000 | |
192 | +#define SW_WATCHDOG_REASON 13 | |
193 | + | |
194 | +#define BOOTDATA_OFFSET 0xF8000 | |
195 | +#define MAX_ATTEMPTS 5 | |
196 | + | |
197 | +#define FAILSAFE_BOOT 1 | |
198 | +#define SYSTEM_BOOT 2 | |
199 | +#define SYSTEM2_BOOT 3 | |
200 | + | |
201 | +#define WRITE_FLASH16(a, d) \ | |
202 | +do \ | |
203 | +{ \ | |
204 | + *((volatile u16 *) (a)) = (d);\ | |
205 | + } while(0) | |
206 | + | |
207 | +static void write_bootdata (volatile u16 * addr, u8 System, u8 Count) | |
208 | +{ | |
209 | + u16 data; | |
210 | + volatile u16 *flash = (u16 *) (CFG_FLASH_BASE); | |
211 | + | |
212 | + switch(System){ | |
213 | + case FAILSAFE_BOOT: | |
214 | + printf ("Setting failsafe boot in flash\n"); | |
215 | + break; | |
216 | + case SYSTEM_BOOT: | |
217 | + printf ("Setting system boot in flash\n"); | |
218 | + break; | |
219 | + case SYSTEM2_BOOT: | |
220 | + printf ("Setting system2 boot in flash\n"); | |
221 | + break; | |
222 | + default: | |
223 | + printf ("Invalid system data %u, setting failsafe\n", System); | |
224 | + System = FAILSAFE_BOOT; | |
225 | + } | |
226 | + | |
227 | + if ((Count < 1) | (Count > MAX_ATTEMPTS)) { | |
228 | + printf ("Invalid boot count %u, setting 1\n", Count); | |
229 | + Count = 1; | |
230 | + } | |
231 | + | |
232 | + printf ("Boot attempt %d\n", Count); | |
233 | + | |
234 | + data = (System << 8) | Count; | |
235 | + /* AMD 16 bit */ | |
236 | + WRITE_FLASH16 (&flash[0x555], 0xAAAA); | |
237 | + WRITE_FLASH16 (&flash[0x2AA], 0x5555); | |
238 | + WRITE_FLASH16 (&flash[0x555], 0xA0A0); | |
239 | + | |
240 | + WRITE_FLASH16 (addr, data); | |
241 | +} | |
242 | + | |
243 | +static int random_system(void){ | |
244 | + /* EEPROM read failed. Just try to choose one | |
245 | + system release and hope it works */ | |
246 | + | |
247 | + /* FIXME */ | |
248 | + return(SYSTEM_BOOT); | |
249 | +} | |
250 | + | |
251 | +static int switch_system(int old_system){ | |
252 | + u8 Rx[10]; | |
253 | + u8 Tx[5]; | |
254 | + int valid_release; | |
255 | + | |
256 | + if(old_system==FAILSAFE_BOOT){ | |
257 | + /* Find out which system release to use */ | |
258 | + | |
259 | + /* Copy from nvram to scratchpad */ | |
260 | + Tx[0] = RECALL_MEMORY; | |
261 | + Tx[1] = 7; /* Page */ | |
262 | + if (ee_do_cpu_command (Tx, 2, NULL, 0, 1)) { | |
263 | + printf ("EE user page 7 recall failed\n"); | |
264 | + return (random_system()); | |
265 | + } | |
266 | + | |
267 | + Tx[0] = READ_SCRATCHPAD; | |
268 | + if (ee_do_cpu_command (Tx, 2, Rx, 9, 1)) { | |
269 | + printf ("EE user page 7 read failed\n"); | |
270 | + return (random_system()); | |
271 | + } | |
272 | + /* Crc in 9:th byte */ | |
273 | + if (!ee_crc_ok (Rx, 8, *(Rx + 8))) { | |
274 | + printf ("EE read failed, page 7. CRC error\n"); | |
275 | + return (random_system()); | |
276 | + } | |
277 | + | |
278 | + valid_release = Rx[7]; | |
279 | + if((valid_release==0xFF)| | |
280 | + ((valid_release&1) == 0)){ | |
281 | + return(SYSTEM_BOOT); | |
282 | + } | |
283 | + else{ | |
284 | + return(SYSTEM2_BOOT); | |
285 | + } | |
286 | + } | |
287 | + else{ | |
288 | + return(FAILSAFE_BOOT); | |
289 | + } | |
290 | +} | |
291 | + | |
292 | +static void check_boot_tries (void) | |
293 | +{ | |
294 | + /* Count the number of boot attemps | |
295 | + switch system if too many */ | |
296 | + | |
297 | + int i; | |
298 | + volatile u16 *addr; | |
299 | + volatile u16 data; | |
300 | + u8 system = FAILSAFE_BOOT; | |
301 | + u8 count; | |
302 | + | |
303 | + addr = (u16 *) (CFG_FLASH_BASE + BOOTDATA_OFFSET); | |
304 | + | |
305 | + if (*addr == 0xFFFF) { | |
306 | + printf ("*** No bootdata exists. ***\n"); | |
307 | + write_bootdata (addr, FAILSAFE_BOOT, 1); | |
308 | + } else { | |
309 | + /* Search for latest written bootdata */ | |
310 | + i = 0; | |
311 | + while ((*(addr + 1) != 0xFFFF) & (i < 8000)) { | |
312 | + addr++; | |
313 | + i++; | |
314 | + } | |
315 | + if (i >= 8000) { | |
316 | + /* Whoa, dont write any more */ | |
317 | + printf ("*** No bootdata found. Not updating flash***\n"); | |
318 | + } else { | |
319 | + /* See how many times we have tried to boot real system */ | |
320 | + data = *addr; | |
321 | + system = data >> 8; | |
322 | + count = data & 0xFF; | |
323 | + if ((system != SYSTEM_BOOT) & | |
324 | + (system != SYSTEM2_BOOT) & | |
325 | + (system != FAILSAFE_BOOT)) { | |
326 | + printf ("*** Wrong system %d\n", system); | |
327 | + system = FAILSAFE_BOOT; | |
328 | + count = 1; | |
329 | + } else { | |
330 | + switch (count) { | |
331 | + case 0: | |
332 | + case 1: | |
333 | + case 2: | |
334 | + case 3: | |
335 | + case 4: | |
336 | + /* Try same system again if needed */ | |
337 | + count++; | |
338 | + break; | |
339 | + | |
340 | + case 5: | |
341 | + /* Switch system and reset tries */ | |
342 | + count = 1; | |
343 | + system = switch_system(system); | |
344 | + printf ("***Too many boot attempts, switching system***\n"); | |
345 | + break; | |
346 | + default: | |
347 | + /* Switch system, start over and hope it works */ | |
348 | + printf ("***Unexpected data on addr 0x%x, %u***\n", | |
349 | + (u32) addr, data); | |
350 | + count = 1; | |
351 | + system = switch_system(system); | |
352 | + } | |
353 | + } | |
354 | + write_bootdata (addr + 1, system, count); | |
355 | + } | |
356 | + } | |
357 | + switch(system){ | |
358 | + case FAILSAFE_BOOT: | |
359 | + printf ("Booting failsafe system\n"); | |
360 | + setenv ("bootargs", "panic=1 root=/dev/hda7"); | |
361 | + setenv ("bootcmd", "ide reset;disk 0x81000000 0:5;run addmisc;bootm"); | |
362 | + break; | |
363 | + | |
364 | + case SYSTEM_BOOT: | |
365 | + printf ("Using normal system\n"); | |
366 | + setenv ("bootargs", "panic=1 root=/dev/hda4"); | |
367 | + setenv ("bootcmd", "ide reset;disk 0x81000000 0:2;run addmisc;bootm"); | |
368 | + break; | |
369 | + | |
370 | + case SYSTEM2_BOOT: | |
371 | + printf ("Using normal system2\n"); | |
372 | + setenv ("bootargs", "panic=1 root=/dev/hda9"); | |
373 | + setenv ("bootcmd", "ide reset;disk 0x81000000 0:8;run addmisc;bootm"); | |
374 | + break; | |
375 | + default: | |
376 | + printf ("Invalid system %d\n", system); | |
377 | + printf ("Hanging\n"); | |
378 | + while(1); | |
379 | + } | |
380 | +} | |
381 | + | |
382 | +int misc_init_r(void){ | |
383 | + u8 Rx[80]; | |
384 | + u8 Tx[5]; | |
385 | + int page; | |
386 | + int read = 0; | |
387 | + | |
388 | + WATCHDOG_RESET(); | |
389 | + | |
390 | + if (ee_init_cpu_data ()) { | |
391 | + printf ("EEPROM init failed\n"); | |
392 | + return (0); | |
393 | + } | |
394 | + | |
395 | + /* Check which release to boot */ | |
396 | + check_boot_tries (); | |
397 | + | |
398 | + /* Read the pages where ethernet address is stored */ | |
399 | + | |
400 | + for (page = EE_USER_PAGE_0; page <= EE_USER_PAGE_0 + 2; page++) { | |
401 | + /* Copy from nvram to scratchpad */ | |
402 | + Tx[0] = RECALL_MEMORY; | |
403 | + Tx[1] = page; | |
404 | + if (ee_do_cpu_command (Tx, 2, NULL, 0, 1)) { | |
405 | + printf ("EE user page %d recall failed\n", page); | |
406 | + return (0); | |
407 | + } | |
408 | + | |
409 | + Tx[0] = READ_SCRATCHPAD; | |
410 | + if (ee_do_cpu_command (Tx, 2, Rx + read, 9, 1)) { | |
411 | + printf ("EE user page %d read failed\n", page); | |
412 | + return (0); | |
413 | + } | |
414 | + /* Crc in 9:th byte */ | |
415 | + if (!ee_crc_ok (Rx + read, 8, *(Rx + read + 8))) { | |
416 | + printf ("EE read failed, page %d. CRC error\n", page); | |
417 | + return (0); | |
418 | + } | |
419 | + read += 8; | |
420 | + } | |
421 | + | |
422 | + /* Add eos after eth addr */ | |
423 | + Rx[17] = 0; | |
424 | + | |
425 | + printf ("Ethernet addr read from eeprom: %s\n\n", Rx); | |
426 | + | |
427 | + if ((Rx[2] != ':') | | |
428 | + (Rx[5] != ':') | | |
429 | + (Rx[8] != ':') | (Rx[11] != ':') | (Rx[14] != ':')) { | |
430 | + printf ("*** ethernet addr invalid, using default ***\n"); | |
431 | + } else { | |
432 | + setenv ("ethaddr", Rx); | |
433 | + } | |
434 | + return (0); | |
435 | +} |
board/gth2/lowlevel_init.S
1 | +/* Memory sub-system initialization code */ | |
2 | + | |
3 | +#include <config.h> | |
4 | +#include <version.h> | |
5 | +#include <asm/regdef.h> | |
6 | +#include <asm/au1x00.h> | |
7 | +#include <asm/mipsregs.h> | |
8 | + | |
9 | +#define CP0_Config0 $16 | |
10 | +#define MEM_1MS ((CFG_MHZ) * 1000) | |
11 | +#define GPIO_RJ1LY (1<<22) | |
12 | +#define GPIO_CFRESET (1<<10) | |
13 | + | |
14 | + .text | |
15 | + .set noreorder | |
16 | + .set mips32 | |
17 | + | |
18 | + .globl lowlevel_init | |
19 | +lowlevel_init: | |
20 | + /* | |
21 | + * Step 2) Establish Status Register | |
22 | + * (set BEV, clear ERL, clear EXL, clear IE) | |
23 | + */ | |
24 | + li t1, 0x00400000 | |
25 | + mtc0 t1, CP0_STATUS | |
26 | + | |
27 | + /* | |
28 | + * Step 3) Establish CP0 Config0 | |
29 | + * (set OD, set K0=3) | |
30 | + */ | |
31 | + li t1, 0x00080003 | |
32 | + mtc0 t1, CP0_CONFIG | |
33 | + | |
34 | + /* | |
35 | + * Step 4) Disable Watchpoint facilities | |
36 | + */ | |
37 | + li t1, 0x00000000 | |
38 | + mtc0 t1, CP0_WATCHLO | |
39 | + mtc0 t1, CP0_IWATCHLO | |
40 | + /* | |
41 | + * Step 5) Disable the performance counters | |
42 | + */ | |
43 | + mtc0 zero, CP0_PERFORMANCE | |
44 | + nop | |
45 | + | |
46 | + /* | |
47 | + * Step 6) Establish EJTAG Debug register | |
48 | + */ | |
49 | + mtc0 zero, CP0_DEBUG | |
50 | + nop | |
51 | + | |
52 | + /* | |
53 | + * Step 7) Establish Cause | |
54 | + * (set IV bit) | |
55 | + */ | |
56 | + li t1, 0x00800000 | |
57 | + mtc0 t1, CP0_CAUSE | |
58 | + | |
59 | + /* Establish Wired (and Random) */ | |
60 | + mtc0 zero, CP0_WIRED | |
61 | + nop | |
62 | + | |
63 | + /* No workaround if running from ram */ | |
64 | + lui t0, 0xffc0 | |
65 | + lui t3, 0xbfc0 | |
66 | + and t1, ra, t0 | |
67 | + bne t1, t3, noCacheJump | |
68 | + nop | |
69 | + | |
70 | + /*** From AMD YAMON ***/ | |
71 | + /* | |
72 | + * Step 8) Initialize the caches | |
73 | + */ | |
74 | + li t0, (16*1024) | |
75 | + li t1, 32 | |
76 | + li t2, 0x80000000 | |
77 | + addu t3, t0, t2 | |
78 | +cacheloop: | |
79 | + cache 0, 0(t2) | |
80 | + cache 1, 0(t2) | |
81 | + addu t2, t1 | |
82 | + bne t2, t3, cacheloop | |
83 | + nop | |
84 | + | |
85 | + /* Save return address */ | |
86 | + move t3, ra | |
87 | + | |
88 | + /* Run from cacheable space now */ | |
89 | + bal cachehere | |
90 | + nop | |
91 | +cachehere: | |
92 | + li t1, ~0x20000000 /* convert to KSEG0 */ | |
93 | + and t0, ra, t1 | |
94 | + addi t0, 5*4 /* 5 insns beyond cachehere */ | |
95 | + jr t0 | |
96 | + nop | |
97 | + | |
98 | + /* Restore return address */ | |
99 | + move ra, t3 | |
100 | + | |
101 | + /* | |
102 | + * Step 9) Initialize the TLB | |
103 | + */ | |
104 | + li t0, 0 # index value | |
105 | + li t1, 0x00000000 # entryhi value | |
106 | + li t2, 32 # 32 entries | |
107 | + | |
108 | +tlbloop: | |
109 | + /* Probe TLB for matching EntryHi */ | |
110 | + mtc0 t1, CP0_ENTRYHI | |
111 | + tlbp | |
112 | + nop | |
113 | + | |
114 | + /* Examine Index[P], 1=no matching entry */ | |
115 | + mfc0 t3, CP0_INDEX | |
116 | + li t4, 0x80000000 | |
117 | + and t3, t4, t3 | |
118 | + addiu t1, t1, 1 # increment t1 (asid) | |
119 | + beq zero, t3, tlbloop | |
120 | + nop | |
121 | + | |
122 | + /* Initialize the TLB entry */ | |
123 | + mtc0 t0, CP0_INDEX | |
124 | + mtc0 zero, CP0_ENTRYLO0 | |
125 | + mtc0 zero, CP0_ENTRYLO1 | |
126 | + mtc0 zero, CP0_PAGEMASK | |
127 | + tlbwi | |
128 | + | |
129 | + /* Do it again */ | |
130 | + addiu t0, t0, 1 | |
131 | + bne t0, t2, tlbloop | |
132 | + nop | |
133 | + | |
134 | + /* First setup pll:s to make serial work ok */ | |
135 | + /* We have a 12.5 MHz crystal */ | |
136 | + li t0, SYS_CPUPLL | |
137 | + li t1, 0x28 /* CPU clock, 500 MHz */ | |
138 | + sw t1, 0(t0) | |
139 | + sync | |
140 | + nop | |
141 | + nop | |
142 | + | |
143 | + /* wait 1mS for clocks to settle */ | |
144 | + li t1, MEM_1MS | |
145 | +1: add t1, -1 | |
146 | + bne t1, zero, 1b | |
147 | + nop | |
148 | + /* Setup AUX PLL */ | |
149 | + li t0, SYS_AUXPLL | |
150 | + li t1, 0 | |
151 | + sw t1, 0(t0) /* aux pll */ | |
152 | + sync | |
153 | + | |
154 | + /* Static memory controller */ | |
155 | + /* RCE0 - can not change while fetching, do so from icache */ | |
156 | + move t2, ra /* Store return address */ | |
157 | + bal getAddr | |
158 | + nop | |
159 | + | |
160 | +getAddr: | |
161 | + move t1, ra | |
162 | + move ra, t2 /* Move return addess back */ | |
163 | + | |
164 | + cache 0x14,0(t1) | |
165 | + cache 0x14,32(t1) | |
166 | + /*** /From YAMON ***/ | |
167 | + | |
168 | +noCacheJump: | |
169 | + | |
170 | + /* Static memory controller */ | |
171 | + | |
172 | + /* RCE0 AMD 29LV800 Flash */ | |
173 | + li t0, MEM_STCFG0 | |
174 | + li t1, 0x00000243 | |
175 | + sw t1, 0(t0) | |
176 | + | |
177 | + li t0, MEM_STTIME0 | |
178 | + li t1, 0x040181D7 /* FIXME */ | |
179 | + sw t1, 0(t0) | |
180 | + | |
181 | + li t0, MEM_STADDR0 | |
182 | + li t1, 0x11E03F80 | |
183 | + sw t1, 0(t0) | |
184 | + | |
185 | + /* RCE1 PCMCIA 250ns */ | |
186 | + li t0, MEM_STCFG1 | |
187 | + li t1, 0x00000002 | |
188 | + sw t1, 0(t0) | |
189 | + | |
190 | + li t0, MEM_STTIME1 | |
191 | + li t1, 0x280E3E07 | |
192 | + sw t1, 0(t0) | |
193 | + | |
194 | + li t0, MEM_STADDR1 | |
195 | + li t1, 0x10000000 | |
196 | + sw t1, 0(t0) | |
197 | + | |
198 | + /* RCE2 CP Altera */ | |
199 | + li t0, MEM_STCFG2 | |
200 | + li t1, 0x00000280 /* BE, EW */ | |
201 | + sw t1, 0(t0) | |
202 | + | |
203 | + li t0, MEM_STTIME2 | |
204 | + li t1, 0x0303000c | |
205 | + sw t1, 0(t0) | |
206 | + | |
207 | + li t0, MEM_STADDR2 | |
208 | + li t1, 0x10c03f80 /* 1 MB */ | |
209 | + sw t1, 0(t0) | |
210 | + | |
211 | + /* RCE3 DP Altera */ | |
212 | + li t0, MEM_STCFG3 | |
213 | + li t1, 0x00000280 /* BE, EW */ | |
214 | + sw t1, 0(t0) | |
215 | + | |
216 | + li t0, MEM_STTIME3 | |
217 | + li t1, 0x0303000c | |
218 | + sw t1, 0(t0) | |
219 | + | |
220 | + li t0, MEM_STADDR3 | |
221 | + li t1, 0x10e03f80 /* 1 MB */ | |
222 | + sw t1, 0(t0) | |
223 | + | |
224 | + sync | |
225 | + | |
226 | + /* Set peripherals to a known state */ | |
227 | + li t0, IC0_CFG0CLR | |
228 | + li t1, 0xFFFFFFFF | |
229 | + sw t1, 0(t0) | |
230 | + | |
231 | + li t0, IC0_CFG0CLR | |
232 | + sw t1, 0(t0) | |
233 | + | |
234 | + li t0, IC0_CFG1CLR | |
235 | + sw t1, 0(t0) | |
236 | + | |
237 | + li t0, IC0_CFG2CLR | |
238 | + sw t1, 0(t0) | |
239 | + | |
240 | + li t0, IC0_SRCSET | |
241 | + sw t1, 0(t0) | |
242 | + | |
243 | + li t0, IC0_ASSIGNSET | |
244 | + sw t1, 0(t0) | |
245 | + | |
246 | + li t0, IC0_WAKECLR | |
247 | + sw t1, 0(t0) | |
248 | + | |
249 | + li t0, IC0_RISINGCLR | |
250 | + sw t1, 0(t0) | |
251 | + | |
252 | + li t0, IC0_FALLINGCLR | |
253 | + sw t1, 0(t0) | |
254 | + | |
255 | + li t0, IC0_TESTBIT | |
256 | + li t1, 0x00000000 | |
257 | + sw t1, 0(t0) | |
258 | + sync | |
259 | + | |
260 | + li t0, IC1_CFG0CLR | |
261 | + li t1, 0xFFFFFFFF | |
262 | + sw t1, 0(t0) | |
263 | + | |
264 | + li t0, IC1_CFG0CLR | |
265 | + sw t1, 0(t0) | |
266 | + | |
267 | + li t0, IC1_CFG1CLR | |
268 | + sw t1, 0(t0) | |
269 | + | |
270 | + li t0, IC1_CFG2CLR | |
271 | + sw t1, 0(t0) | |
272 | + | |
273 | + li t0, IC1_SRCSET | |
274 | + sw t1, 0(t0) | |
275 | + | |
276 | + li t0, IC1_ASSIGNSET | |
277 | + sw t1, 0(t0) | |
278 | + | |
279 | + li t0, IC1_WAKECLR | |
280 | + sw t1, 0(t0) | |
281 | + | |
282 | + li t0, IC1_RISINGCLR | |
283 | + sw t1, 0(t0) | |
284 | + | |
285 | + li t0, IC1_FALLINGCLR | |
286 | + sw t1, 0(t0) | |
287 | + | |
288 | + li t0, IC1_TESTBIT | |
289 | + li t1, 0x00000000 | |
290 | + sw t1, 0(t0) | |
291 | + sync | |
292 | + | |
293 | + li t0, SYS_FREQCTRL0 | |
294 | + li t1, 0x00000000 | |
295 | + sw t1, 0(t0) | |
296 | + | |
297 | + li t0, SYS_FREQCTRL1 | |
298 | + li t1, 0x00000000 | |
299 | + sw t1, 0(t0) | |
300 | + | |
301 | + li t0, SYS_CLKSRC | |
302 | + li t1, 0x00000000 | |
303 | + sw t1, 0(t0) | |
304 | + | |
305 | + li t0, SYS_PININPUTEN | |
306 | + li t1, 0x00000000 | |
307 | + sw t1, 0(t0) | |
308 | + sync | |
309 | + | |
310 | + li t0, 0xB1100100 | |
311 | + li t1, 0x00000000 | |
312 | + sw t1, 0(t0) | |
313 | + | |
314 | + li t0, 0xB1400100 | |
315 | + li t1, 0x00000000 | |
316 | + sw t1, 0(t0) | |
317 | + | |
318 | + | |
319 | + li t0, SYS_WAKEMSK | |
320 | + li t1, 0x00000000 | |
321 | + sw t1, 0(t0) | |
322 | + | |
323 | + li t0, SYS_WAKESRC | |
324 | + li t1, 0x00000000 | |
325 | + sw t1, 0(t0) | |
326 | + | |
327 | + /* wait 1mS before setup */ | |
328 | + li t1, MEM_1MS | |
329 | +1: add t1, -1 | |
330 | + bne t1, zero, 1b | |
331 | + nop | |
332 | + | |
333 | + | |
334 | +/* SDCS 0 SDRAM */ | |
335 | + li t0, MEM_SDMODE0 | |
336 | + li t1, 0x592CD1 | |
337 | + sw t1, 0(t0) | |
338 | + | |
339 | + li t0, MEM_SDMODE1 | |
340 | + li t1, 0x00000000 | |
341 | + sw t1, 0(t0) | |
342 | + | |
343 | + li t0, MEM_SDMODE2 | |
344 | + li t1, 0x00000000 | |
345 | + sw t1, 0(t0) | |
346 | + | |
347 | +/* 64 MB SDRAM at addr 0 */ | |
348 | + li t0, MEM_SDADDR0 | |
349 | + li t1, 0x001003F0 | |
350 | + sw t1, 0(t0) | |
351 | + | |
352 | + | |
353 | + li t0, MEM_SDADDR1 | |
354 | + li t1, 0x00000000 | |
355 | + sw t1, 0(t0) | |
356 | + | |
357 | + li t0, MEM_SDADDR2 | |
358 | + li t1, 0x00000000 | |
359 | + sw t1, 0(t0) | |
360 | + | |
361 | + sync | |
362 | + | |
363 | + li t0, MEM_SDREFCFG | |
364 | + li t1, 0x880007A1 /* Disable */ | |
365 | + sw t1, 0(t0) | |
366 | + sync | |
367 | + | |
368 | + li t0, MEM_SDPRECMD | |
369 | + sw zero, 0(t0) | |
370 | + sync | |
371 | + | |
372 | + li t0, MEM_SDAUTOREF | |
373 | + sw zero, 0(t0) | |
374 | + sync | |
375 | + sw zero, 0(t0) | |
376 | + sync | |
377 | + | |
378 | + li t0, MEM_SDREFCFG | |
379 | + li t1, 0x8A0007A1 /* Enable */ | |
380 | + sw t1, 0(t0) | |
381 | + sync | |
382 | + | |
383 | + li t0, MEM_SDWRMD0 | |
384 | + li t1, 0x00000023 | |
385 | + sw t1, 0(t0) | |
386 | + sync | |
387 | + | |
388 | + /* wait 1mS after setup */ | |
389 | + li t1, MEM_1MS | |
390 | +1: add t1, -1 | |
391 | + bne t1, zero, 1b | |
392 | + nop | |
393 | + | |
394 | + /* Setup GPIO pins */ | |
395 | + | |
396 | + li t0, SYS_PINFUNC | |
397 | + li t1, 0x00007025 /* 0x8080 */ | |
398 | + sw t1, 0(t0) | |
399 | + | |
400 | + li t0, SYS_TRIOUTCLR | |
401 | + li t1, 0xFFFFFFFF /* 0x1FFF */ | |
402 | + sw t1, 0(t0) | |
403 | + | |
404 | + /* Turn yellow front led on */ | |
405 | + /* Release reset on CF */ | |
406 | + li t0, SYS_OUTPUTCLR | |
407 | + li t1, GPIO_RJ1LG | |
408 | + sw t1, 0(t0) | |
409 | + li t0, SYS_OUTPUTSET | |
410 | + li t1, GPIO_RJ1LY|GPIO_CFRESET | |
411 | + sw t1, 0(t0) | |
412 | + sync | |
413 | + j clearmem | |
414 | + nop | |
415 | + | |
416 | + .globl memtest | |
417 | +memtest: | |
418 | + /* Fill memory with address */ | |
419 | + li t0, 0x80000000 | |
420 | + li t1, 0xFFF000 /* 64 MB */ | |
421 | +mt0: sw t0, 0(t0) | |
422 | + add t1, -1 | |
423 | + add t0, 4 | |
424 | + bne t1, zero, mt0 | |
425 | + nop | |
426 | + nop | |
427 | + /* Verify addr */ | |
428 | + li t0, 0x80000000 | |
429 | + li t1, 0xFFF000 /* 64 MB */ | |
430 | +mt1: lw t2, 0(t0) | |
431 | + bne t0, t2, memhang | |
432 | + add t1, -1 | |
433 | + add t0, 4 | |
434 | + bne t1, zero, mt1 | |
435 | + nop | |
436 | + nop | |
437 | + .globl clearmem | |
438 | +clearmem: | |
439 | + /* Clear memory */ | |
440 | + li t0, 0x80000000 | |
441 | + li t1, 0xFFF000 /* 64 MB */ | |
442 | +mtc: sw zero, 0(t0) | |
443 | + add t1, -1 | |
444 | + add t0, 4 | |
445 | + bne t1, zero, mtc | |
446 | + nop | |
447 | + nop | |
448 | +memtestend: | |
449 | + j ra | |
450 | + nop | |
451 | + | |
452 | +memhang: | |
453 | + b memhang | |
454 | + nop |
board/gth2/u-boot.lds
1 | +/* | |
2 | + * (C) Copyright 2003-2005 | |
3 | + * Wolfgang Denk Engineering, <wd@denx.de> | |
4 | + * | |
5 | + * See file CREDITS for list of people who contributed to this | |
6 | + * project. | |
7 | + * | |
8 | + * This program is free software; you can redistribute it and/or | |
9 | + * modify it under the terms of the GNU General Public License as | |
10 | + * published by the Free Software Foundation; either version 2 of | |
11 | + * the License, or (at your option) any later version. | |
12 | + * | |
13 | + * This program is distributed in the hope that it will be useful, | |
14 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | + * GNU General Public License for more details. | |
17 | + * | |
18 | + * You should have received a copy of the GNU General Public License | |
19 | + * along with this program; if not, write to the Free Software | |
20 | + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | + * MA 02111-1307 USA | |
22 | + */ | |
23 | + | |
24 | +/* | |
25 | +OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") | |
26 | +*/ | |
27 | +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") | |
28 | +OUTPUT_ARCH(mips) | |
29 | +ENTRY(_start) | |
30 | +SECTIONS | |
31 | +{ | |
32 | + . = 0x00000000; | |
33 | + | |
34 | + . = ALIGN(4); | |
35 | + .text : | |
36 | + { | |
37 | + *(.text) | |
38 | + } | |
39 | + | |
40 | + . = ALIGN(4); | |
41 | + .rodata : { *(.rodata) } | |
42 | + | |
43 | + . = ALIGN(4); | |
44 | + .data : { *(.data) } | |
45 | + | |
46 | + . = ALIGN(4); | |
47 | + .sdata : { *(.sdata) } | |
48 | + | |
49 | + _gp = ALIGN(16); | |
50 | + | |
51 | + __got_start = .; | |
52 | + .got : { *(.got) } | |
53 | + __got_end = .; | |
54 | + | |
55 | + .sdata : { *(.sdata) } | |
56 | + | |
57 | + __u_boot_cmd_start = .; | |
58 | + .u_boot_cmd : { *(.u_boot_cmd) } | |
59 | + __u_boot_cmd_end = .; | |
60 | + | |
61 | + uboot_end_data = .; | |
62 | + num_got_entries = (__got_end - __got_start) >> 2; | |
63 | + | |
64 | + . = ALIGN(4); | |
65 | + .sbss : { *(.sbss) } | |
66 | + .bss : { *(.bss) } | |
67 | + uboot_end = .; | |
68 | +} |
board/tqm5200/Makefile
board/tqm5200/flash.c
1 | -/* | |
2 | - * (C) Copyright 2003-2004 | |
3 | - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | - * | |
5 | - * (C) Copyright 2004 | |
6 | - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de | |
7 | - * | |
8 | - * See file CREDITS for list of people who contributed to this | |
9 | - * project. | |
10 | - * | |
11 | - * This program is free software; you can redistribute it and/or | |
12 | - * modify it under the terms of the GNU General Public License as | |
13 | - * published by the Free Software Foundation; either version 2 of | |
14 | - * the License, or (at your option) any later version. | |
15 | - * | |
16 | - * This program is distributed in the hope that it will be useful, | |
17 | - * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | - * GNU General Public License for more details. | |
20 | - * | |
21 | - * You should have received a copy of the GNU General Public License | |
22 | - * along with this program; if not, write to the Free Software | |
23 | - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | - * MA 02111-1307 USA | |
25 | - */ | |
26 | - | |
27 | -#include <common.h> | |
28 | - | |
29 | -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ | |
30 | - | |
31 | -/* | |
32 | - * CPU to flash interface is 32-bit, so make declaration accordingly | |
33 | - */ | |
34 | -typedef unsigned long FLASH_PORT_WIDTH; | |
35 | -typedef volatile unsigned long FLASH_PORT_WIDTHV; | |
36 | - | |
37 | -#define FPW FLASH_PORT_WIDTH | |
38 | -#define FPWV FLASH_PORT_WIDTHV | |
39 | - | |
40 | -#define FLASH_CYCLE1 0x0555 | |
41 | -#define FLASH_CYCLE2 0x02aa | |
42 | - | |
43 | -/*----------------------------------------------------------------------- | |
44 | - * Functions | |
45 | - */ | |
46 | -static ulong flash_get_size(FPWV *addr, flash_info_t *info); | |
47 | -static void flash_reset(flash_info_t *info); | |
48 | -static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); | |
49 | -static flash_info_t *flash_get_info(ulong base); | |
50 | - | |
51 | -/*----------------------------------------------------------------------- | |
52 | - * flash_init() | |
53 | - * | |
54 | - * sets up flash_info and returns size of FLASH (bytes) | |
55 | - */ | |
56 | -unsigned long flash_init (void) | |
57 | -{ | |
58 | - unsigned long size = 0; | |
59 | - extern void flash_preinit(void); | |
60 | - ulong flashbase = CFG_FLASH_BASE; | |
61 | - | |
62 | - flash_preinit(); | |
63 | - | |
64 | - /* Init: no FLASHes known */ | |
65 | - memset(&flash_info[0], 0, sizeof(flash_info_t)); | |
66 | - | |
67 | - flash_info[0].size = | |
68 | - flash_get_size((FPW *)flashbase, &flash_info[0]); | |
69 | - | |
70 | - size = flash_info[0].size; | |
71 | - | |
72 | -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE | |
73 | - /* monitor protection ON by default */ | |
74 | - flash_protect(FLAG_PROTECT_SET, | |
75 | - CFG_MONITOR_BASE, | |
76 | - CFG_MONITOR_BASE+monitor_flash_len-1, | |
77 | - flash_get_info(CFG_MONITOR_BASE)); | |
78 | -#endif | |
79 | - | |
80 | -#ifdef CFG_ENV_IS_IN_FLASH | |
81 | - /* ENV protection ON by default */ | |
82 | - flash_protect(FLAG_PROTECT_SET, | |
83 | - CFG_ENV_ADDR, | |
84 | - CFG_ENV_ADDR+CFG_ENV_SIZE-1, | |
85 | - flash_get_info(CFG_ENV_ADDR)); | |
86 | -#endif | |
87 | - | |
88 | - return size ? size : 1; | |
89 | -} | |
90 | - | |
91 | -/*----------------------------------------------------------------------- | |
92 | - */ | |
93 | -static void flash_reset(flash_info_t *info) | |
94 | -{ | |
95 | - FPWV *base = (FPWV *)(info->start[0]); | |
96 | - | |
97 | - /* Put FLASH back in read mode */ | |
98 | - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) | |
99 | - *base = (FPW)0x00FF00FF; /* Intel Read Mode */ | |
100 | - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) | |
101 | - *base = (FPW)0x00F000F0; /* AMD Read Mode */ | |
102 | -} | |
103 | - | |
104 | -/*----------------------------------------------------------------------- | |
105 | - */ | |
106 | - | |
107 | -static flash_info_t *flash_get_info(ulong base) | |
108 | -{ | |
109 | - int i; | |
110 | - flash_info_t * info; | |
111 | - | |
112 | - for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { | |
113 | - info = & flash_info[i]; | |
114 | - if (info->size && info->start[0] <= base && | |
115 | - base <= info->start[0] + info->size - 1) | |
116 | - break; | |
117 | - } | |
118 | - | |
119 | - return i == CFG_MAX_FLASH_BANKS ? 0 : info; | |
120 | -} | |
121 | - | |
122 | -/*----------------------------------------------------------------------- | |
123 | - */ | |
124 | - | |
125 | -void flash_print_info (flash_info_t *info) | |
126 | -{ | |
127 | - int i; | |
128 | - | |
129 | - if (info->flash_id == FLASH_UNKNOWN) { | |
130 | - printf ("missing or unknown FLASH type\n"); | |
131 | - return; | |
132 | - } | |
133 | - | |
134 | - switch (info->flash_id & FLASH_VENDMASK) { | |
135 | - case FLASH_MAN_AMD: printf ("AMD "); break; | |
136 | - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; | |
137 | - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; | |
138 | - case FLASH_MAN_SST: printf ("SST "); break; | |
139 | - case FLASH_MAN_STM: printf ("STM "); break; | |
140 | - case FLASH_MAN_INTEL: printf ("INTEL "); break; | |
141 | - default: printf ("Unknown Vendor "); break; | |
142 | - } | |
143 | - | |
144 | - switch (info->flash_id & FLASH_TYPEMASK) { | |
145 | - case FLASH_AMLV128U: | |
146 | - printf ("AM29LV128ML (128Mbit, uniform sector size)\n"); | |
147 | - break; | |
148 | - case FLASH_AM160B: | |
149 | - printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); | |
150 | - break; | |
151 | - default: | |
152 | - printf ("Unknown Chip Type\n"); | |
153 | - break; | |
154 | - } | |
155 | - | |
156 | - printf (" Size: %ld MB in %d Sectors\n", | |
157 | - info->size >> 20, | |
158 | - info->sector_count); | |
159 | - | |
160 | - printf (" Sector Start Addresses:"); | |
161 | - | |
162 | - for (i=0; i<info->sector_count; ++i) { | |
163 | - if ((i % 5) == 0) { | |
164 | - printf ("\n "); | |
165 | - } | |
166 | - printf (" %08lX%s", | |
167 | - info->start[i], | |
168 | - info->protect[i] ? " (RO)" : " "); | |
169 | - } | |
170 | - printf ("\n"); | |
171 | - return; | |
172 | -} | |
173 | - | |
174 | -/*----------------------------------------------------------------------- | |
175 | - */ | |
176 | - | |
177 | -/* | |
178 | - * The following code cannot be run from FLASH! | |
179 | - */ | |
180 | - | |
181 | -ulong flash_get_size (FPWV *addr, flash_info_t *info) | |
182 | -{ | |
183 | - int i; | |
184 | - ulong base = (ulong)addr; | |
185 | - | |
186 | - /* Write auto select command: read Manufacturer ID */ | |
187 | - /* Write auto select command sequence and test FLASH answer */ | |
188 | - addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ | |
189 | - addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */ | |
190 | - addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */ | |
191 | - | |
192 | - /* The manufacturer codes are only 1 byte, so just use 1 byte. | |
193 | - * This works for any bus width and any FLASH device width. | |
194 | - */ | |
195 | - udelay(100); | |
196 | - switch (addr[0] & 0xff) { | |
197 | - | |
198 | - case (uchar)AMD_MANUFACT: | |
199 | - debug ("Manufacturer: AMD (Spansion)\n"); | |
200 | - info->flash_id = FLASH_MAN_AMD; | |
201 | - break; | |
202 | - | |
203 | - case (uchar)INTEL_MANUFACT: | |
204 | - debug ("Manufacturer: Intel (not supported yet)\n"); | |
205 | - info->flash_id = FLASH_MAN_INTEL; | |
206 | - break; | |
207 | - | |
208 | - default: | |
209 | - info->flash_id = FLASH_UNKNOWN; | |
210 | - info->sector_count = 0; | |
211 | - info->size = 0; | |
212 | - break; | |
213 | - } | |
214 | - | |
215 | - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ | |
216 | - if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) { | |
217 | - | |
218 | - case (FPW)AMD_ID_LV160B: | |
219 | - debug ("Chip: AM29LV160MB\n"); | |
220 | - info->flash_id += FLASH_AM160B; | |
221 | - info->sector_count = 35; | |
222 | - info->size = 0x00400000; | |
223 | - /* | |
224 | - * The first 4 sectors are 16 kB, 8 kB, 8 kB and 32 kB, all | |
225 | - * the other ones are 64 kB | |
226 | - */ | |
227 | - info->start[0] = base + 0x00000000; | |
228 | - info->start[1] = base + 0x00008000; | |
229 | - info->start[2] = base + 0x0000C000; | |
230 | - info->start[3] = base + 0x00010000; | |
231 | - for( i = 4; i < info->sector_count; i++ ) | |
232 | - info->start[i] = | |
233 | - base + (i * 2 * (64 << 10)) - 0x00060000; | |
234 | - break; /* => 4 MB */ | |
235 | - | |
236 | - case AMD_ID_MIRROR: | |
237 | - debug ("Mirror Bit flash: addr[14] = %08lX addr[15] = %08lX\n", | |
238 | - addr[14], addr[15]); | |
239 | - | |
240 | - switch(addr[14]) { | |
241 | - case AMD_ID_LV128U_2: | |
242 | - if (addr[15] != AMD_ID_LV128U_3) { | |
243 | - debug ("Chip: AM29LVxxxM -> unknown\n"); | |
244 | - info->flash_id = FLASH_UNKNOWN; | |
245 | - info->sector_count = 0; | |
246 | - info->size = 0; | |
247 | - } else { | |
248 | - debug ("Chip: AM29LV128M\n"); | |
249 | - info->flash_id += FLASH_AMLV128U; | |
250 | - info->sector_count = 256; | |
251 | - info->size = 0x02000000; | |
252 | - for (i = 0; i < info->sector_count; i++) { | |
253 | - info->start[i] = base; | |
254 | - base += 0x20000; | |
255 | - } | |
256 | - } | |
257 | - break; /* => 32 MB */ | |
258 | - default: | |
259 | - debug ("Chip: *** unknown ***\n"); | |
260 | - info->flash_id = FLASH_UNKNOWN; | |
261 | - info->sector_count = 0; | |
262 | - info->size = 0; | |
263 | - break; | |
264 | - } | |
265 | - break; | |
266 | - | |
267 | - default: | |
268 | - info->flash_id = FLASH_UNKNOWN; | |
269 | - info->sector_count = 0; | |
270 | - info->size = 0; | |
271 | - } | |
272 | - | |
273 | - /* Put FLASH back in read mode */ | |
274 | - flash_reset(info); | |
275 | - | |
276 | - return (info->size); | |
277 | -} | |
278 | - | |
279 | -/*----------------------------------------------------------------------- | |
280 | - */ | |
281 | - | |
282 | -int flash_erase (flash_info_t *info, int s_first, int s_last) | |
283 | -{ | |
284 | - vu_long *addr = (vu_long*)(info->start[0]); | |
285 | - int flag, prot, sect, l_sect; | |
286 | - ulong start, now, last; | |
287 | - | |
288 | - debug ("flash_erase: first: %d last: %d\n", s_first, s_last); | |
289 | - | |
290 | - if ((s_first < 0) || (s_first > s_last)) { | |
291 | - if (info->flash_id == FLASH_UNKNOWN) { | |
292 | - printf ("- missing\n"); | |
293 | - } else { | |
294 | - printf ("- no sectors to erase\n"); | |
295 | - } | |
296 | - return 1; | |
297 | - } | |
298 | - | |
299 | - if ((info->flash_id == FLASH_UNKNOWN) || | |
300 | - (info->flash_id > FLASH_AMD_COMP)) { | |
301 | - printf ("Can't erase unknown flash type %08lx - aborted\n", | |
302 | - info->flash_id); | |
303 | - return 1; | |
304 | - } | |
305 | - | |
306 | - prot = 0; | |
307 | - for (sect=s_first; sect<=s_last; ++sect) { | |
308 | - if (info->protect[sect]) { | |
309 | - prot++; | |
310 | - } | |
311 | - } | |
312 | - | |
313 | - if (prot) { | |
314 | - printf ("- Warning: %d protected sectors will not be erased!\n", | |
315 | - prot); | |
316 | - } else { | |
317 | - printf ("\n"); | |
318 | - } | |
319 | - | |
320 | - l_sect = -1; | |
321 | - | |
322 | - /* Disable interrupts which might cause a timeout here */ | |
323 | - flag = disable_interrupts(); | |
324 | - | |
325 | - addr[0x0555] = 0x00AA00AA; | |
326 | - addr[0x02AA] = 0x00550055; | |
327 | - addr[0x0555] = 0x00800080; | |
328 | - addr[0x0555] = 0x00AA00AA; | |
329 | - addr[0x02AA] = 0x00550055; | |
330 | - | |
331 | - /* Start erase on unprotected sectors */ | |
332 | - for (sect = s_first; sect<=s_last; sect++) { | |
333 | - if (info->protect[sect] == 0) { /* not protected */ | |
334 | - addr = (vu_long*)(info->start[sect]); | |
335 | - addr[0] = 0x00300030; | |
336 | - l_sect = sect; | |
337 | - } | |
338 | - } | |
339 | - | |
340 | - /* re-enable interrupts if necessary */ | |
341 | - if (flag) | |
342 | - enable_interrupts(); | |
343 | - | |
344 | - /* wait at least 80us - let's wait 1 ms */ | |
345 | - udelay (1000); | |
346 | - | |
347 | - /* | |
348 | - * We wait for the last triggered sector | |
349 | - */ | |
350 | - if (l_sect < 0) | |
351 | - goto DONE; | |
352 | - | |
353 | - start = get_timer (0); | |
354 | - last = start; | |
355 | - addr = (vu_long*)(info->start[l_sect]); | |
356 | - while ((addr[0] & 0x00800080) != 0x00800080) { | |
357 | - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { | |
358 | - printf ("Timeout\n"); | |
359 | - return 1; | |
360 | - } | |
361 | - /* show that we're waiting */ | |
362 | - if ((now - last) > 1000) { /* every second */ | |
363 | - putc ('.'); | |
364 | - last = now; | |
365 | - } | |
366 | - } | |
367 | - | |
368 | -DONE: | |
369 | - /* reset to read mode */ | |
370 | - addr = (volatile unsigned long *)info->start[0]; | |
371 | - addr[0] = 0x00F000F0; /* reset bank */ | |
372 | - | |
373 | - printf (" done\n"); | |
374 | - return 0; | |
375 | -} | |
376 | - | |
377 | -/*----------------------------------------------------------------------- | |
378 | - * Copy memory to flash, returns: | |
379 | - * 0 - OK | |
380 | - * 1 - write timeout | |
381 | - * 2 - Flash not erased | |
382 | - */ | |
383 | - | |
384 | -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) | |
385 | -{ | |
386 | - ulong cp, wp, data; | |
387 | - int i, l, rc; | |
388 | - | |
389 | - /* | |
390 | - * Get lower word aligned address. Assumes 32 bit flash bus width. | |
391 | - */ | |
392 | - wp = (addr & ~3); | |
393 | - | |
394 | - /* | |
395 | - * handle unaligned start bytes | |
396 | - */ | |
397 | - if ((l = addr - wp) != 0) { | |
398 | - data = 0; | |
399 | - for (i=0, cp=wp; i<l; ++i, ++cp) { | |
400 | - data = (data << 8) | (*(uchar *)cp); | |
401 | - } | |
402 | - for (; i<4 && cnt>0; ++i) { | |
403 | - data = (data << 8) | *src++; | |
404 | - --cnt; | |
405 | - ++cp; | |
406 | - } | |
407 | - for (; cnt==0 && i<4; ++i, ++cp) { | |
408 | - data = (data << 8) | (*(uchar *)cp); | |
409 | - } | |
410 | - | |
411 | - if ((rc = write_word_amd(info, (FPW *)wp, data)) != 0) { | |
412 | - return (rc); | |
413 | - } | |
414 | - wp += 4; | |
415 | - } | |
416 | - | |
417 | - /* | |
418 | - * handle word aligned part | |
419 | - */ | |
420 | - while (cnt >= 4) { | |
421 | - data = 0; | |
422 | - for (i=0; i<4; ++i) { | |
423 | - data = (data << 8) | *src++; | |
424 | - } | |
425 | - if ((rc = write_word_amd(info, (FPW *)wp, data)) != 0) { | |
426 | - return (rc); | |
427 | - } | |
428 | - wp += 4; | |
429 | - cnt -= 4; | |
430 | - } | |
431 | - | |
432 | - if (cnt == 0) { | |
433 | - return (0); | |
434 | - } | |
435 | - | |
436 | - /* | |
437 | - * handle unaligned tail bytes | |
438 | - */ | |
439 | - data = 0; | |
440 | - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { | |
441 | - data = (data << 8) | *src++; | |
442 | - --cnt; | |
443 | - } | |
444 | - for (; i<4; ++i, ++cp) { | |
445 | - data = (data << 8) | (*(uchar *)cp); | |
446 | - } | |
447 | - | |
448 | - return (write_word_amd(info, (FPW *)wp, data)); | |
449 | -} | |
450 | - | |
451 | -/*----------------------------------------------------------------------- | |
452 | - * Write a word to Flash for AMD FLASH | |
453 | - * A word is 16 or 32 bits, whichever the bus width of the flash bank | |
454 | - * (not an individual chip) is. | |
455 | - * | |
456 | - * returns: | |
457 | - * 0 - OK | |
458 | - * 1 - write timeout | |
459 | - * 2 - Flash not erased | |
460 | - */ | |
461 | -static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) | |
462 | -{ | |
463 | - ulong start; | |
464 | - int flag; | |
465 | - FPWV *base; /* first address in flash bank */ | |
466 | - | |
467 | - /* Check if Flash is (sufficiently) erased */ | |
468 | - if ((*dest & data) != data) { | |
469 | - return (2); | |
470 | - } | |
471 | - | |
472 | - base = (FPWV *)(info->start[0]); | |
473 | - | |
474 | - /* Disable interrupts which might cause a timeout here */ | |
475 | - flag = disable_interrupts(); | |
476 | - | |
477 | - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ | |
478 | - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ | |
479 | - base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */ | |
480 | - | |
481 | - *dest = data; /* start programming the data */ | |
482 | - | |
483 | - /* re-enable interrupts if necessary */ | |
484 | - if (flag) | |
485 | - enable_interrupts(); | |
486 | - | |
487 | - start = get_timer (0); | |
488 | - | |
489 | - /* data polling for D7 */ | |
490 | - while ((*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { | |
491 | - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { | |
492 | - *dest = (FPW)0x00F000F0; /* reset bank */ | |
493 | - return (1); | |
494 | - } | |
495 | - } | |
496 | - return (0); | |
497 | -} |
board/tqm5200/tqm5200.c
... | ... | @@ -254,13 +254,7 @@ |
254 | 254 | puts ("Board: AEVFIFO\n"); |
255 | 255 | return 0; |
256 | 256 | #endif |
257 | -#if defined (CONFIG_TQM5200_AA) | |
258 | - puts ("Board: TQM5200-AA (TQ-Components GmbH)\n"); | |
259 | -#elif defined (CONFIG_TQM5200_AB) | |
260 | - puts ("Board: TQM5200-AB (TQ-Components GmbH)\n"); | |
261 | -#elif defined (CONFIG_TQM5200_AC) | |
262 | - puts ("Board: TQM5200-AC (TQ-Components GmbH)\n"); | |
263 | -#elif defined (CONFIG_TQM5200) | |
257 | +#if defined (CONFIG_TQM5200) | |
264 | 258 | puts ("Board: TQM5200 (TQ-Components GmbH)\n"); |
265 | 259 | #endif |
266 | 260 | #if defined (CONFIG_STK52XX) |
... | ... | @@ -572,17 +566,7 @@ |
572 | 566 | void video_get_info_str (int line_number, char *info) |
573 | 567 | { |
574 | 568 | if (line_number == 1) { |
575 | -#if defined (CONFIG_TQM5200_AA) | |
576 | - strcpy (info, " Board: TQM5200-AA (TQ-Components GmbH)"); | |
577 | -#elif defined (CONFIG_TQM5200_AB) | |
578 | - strcpy (info, " Board: TQM5200-AB (TQ-Components GmbH)"); | |
579 | -#elif defined (CONFIG_TQM5200_AC) | |
580 | - strcpy (info, " Board: TQM5200-AC (TQ-Components GmbH)"); | |
581 | -#elif defined (CONFIG_TQM5200) | |
582 | - strcpy (info, " Board: TQM5200 (TQ-Components GmbH)"); | |
583 | -#else | |
584 | -#error No supported board selected | |
585 | -#endif | |
569 | + strcpy (info, " Board: TQM5200 (TQ-Components GmbH)"); | |
586 | 570 | #if defined (CONFIG_STK52XX) |
587 | 571 | } else if (line_number == 2) { |
588 | 572 | strcpy (info, " on a STK52XX baseboard"); |
board/tqm834x/tqm834x.c
... | ... | @@ -406,5 +406,29 @@ |
406 | 406 | (DDR_REFINT_166MHZ_7US << SDRAM_INTERVAL_REFINT_SHIFT) | |
407 | 407 | (DDR_BSTOPRE << SDRAM_INTERVAL_BSTOPRE_SHIFT); |
408 | 408 | SYNC; |
409 | + | |
410 | + /* Workaround for DDR6 Erratum | |
411 | + * see MPC8349E Device Errata Rev.8, 2/2006 | |
412 | + * This workaround influences the MPC internal "input enables" | |
413 | + * dependent on CAS latency and MPC revision. According to errata | |
414 | + * sheet the internal reserved registers for this workaround are | |
415 | + * not available from revision 2.0 and up. | |
416 | + */ | |
417 | + | |
418 | + /* Get REVID from register SPRIDR. Skip workaround if rev >= 2.0 | |
419 | + * (0x200) | |
420 | + */ | |
421 | + if ((im->sysconf.spridr & SPRIDR_REVID) < 0x200) { | |
422 | + | |
423 | + /* There is a internal reserved register at IMMRBAR+0x2F00 | |
424 | + * which has to be written with a certain value defined by | |
425 | + * errata sheet. | |
426 | + */ | |
427 | +#if defined(DDR_CASLAT_20) | |
428 | + *((u8 *)im + 0x2f00) = 0x201c0000; | |
429 | +#else | |
430 | + *((u8 *)im + 0x2f00) = 0x202c0000; | |
431 | +#endif | |
432 | + } | |
409 | 433 | } |
board/tqm85xx/tqm85xx.c
... | ... | @@ -27,6 +27,9 @@ |
27 | 27 | * MA 02111-1307 USA |
28 | 28 | */ |
29 | 29 | |
30 | +#ifdef CONFIG_PS2MULT | |
31 | +void ps2mult_early_init(void); | |
32 | +#endif | |
30 | 33 | |
31 | 34 | #include <common.h> |
32 | 35 | #include <pci.h> |
... | ... | @@ -410,4 +413,14 @@ |
410 | 413 | pci_mpc85xx_init (&hose); |
411 | 414 | #endif /* CONFIG_PCI */ |
412 | 415 | } |
416 | + | |
417 | +#ifdef CONFIG_BOARD_EARLY_INIT_R | |
418 | +int board_early_init_r (void) | |
419 | +{ | |
420 | +#ifdef CONFIG_PS2MULT | |
421 | + ps2mult_early_init(); | |
422 | +#endif /* CONFIG_PS2MULT */ | |
423 | + return (0); | |
424 | +} | |
425 | +#endif /* CONFIG_BOARD_EARLY_INIT_R */ |
board/trab/cmd_trab.c
board/trab/trab.c
... | ... | @@ -161,6 +161,19 @@ |
161 | 161 | uchar *str; |
162 | 162 | int i; |
163 | 163 | |
164 | +#ifdef CONFIG_VERSION_VARIABLE | |
165 | + { | |
166 | + /* Set version variable. Please note, that this variable is | |
167 | + * also set in main_loop() later in the boot process. The | |
168 | + * version variable has to be set this early, because so it | |
169 | + * could be used in script files on an usb stick, which | |
170 | + * might be called during do_auto_update() */ | |
171 | + extern char version_string[]; | |
172 | + | |
173 | + setenv ("ver", version_string); | |
174 | + } | |
175 | +#endif /* CONFIG_VERSION_VARIABLE */ | |
176 | + | |
164 | 177 | #ifdef CONFIG_AUTO_UPDATE |
165 | 178 | extern int do_auto_update(void); |
166 | 179 | /* this has priority over all else */ |
board/trab/tsc2000.c
board/trab/vfd.c
... | ... | @@ -358,6 +358,8 @@ |
358 | 358 | */ |
359 | 359 | int vfd_init_clocks (void) |
360 | 360 | { |
361 | + int i; | |
362 | + | |
361 | 363 | S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); |
362 | 364 | S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS(); |
363 | 365 | S3C24X0_LCD * const lcd = S3C24X0_GetBase_LCD(); |
... | ... | @@ -367,7 +369,9 @@ |
367 | 369 | */ |
368 | 370 | gpio->PCUP = (gpio->PCUP & 0xFFF0); /* activate GPC0...GPC3 pullups */ |
369 | 371 | gpio->PCCON = (gpio->PCCON & 0xFFFFFF00); /* configure GPC0...GPC3 as inputs */ |
370 | - udelay (10); /* allow signals to settle */ | |
372 | + /* allow signals to settle */ | |
373 | + for (i=0; i<10000; i++) /* udelay isn't working yet at this point! */ | |
374 | + __asm("NOP"); | |
371 | 375 | vfd_board_id = (~gpio->PCDAT) & 0x000F; /* read GPC0...GPC3 port pins */ |
372 | 376 | |
373 | 377 | VFD_DISABLE; /* activate blank for the vfd */ |
common/cmd_ide.c
... | ... | @@ -855,7 +855,7 @@ |
855 | 855 | |
856 | 856 | /* We only need to swap data if we are running on a big endian cpu. */ |
857 | 857 | /* But Au1x00 cpu:s already swaps data in big endian mode! */ |
858 | -#if defined(__LITTLE_ENDIAN) || defined(CONFIG_AU1X00) | |
858 | +#if defined(__LITTLE_ENDIAN) || ( defined(CONFIG_AU1X00) && !defined(CONFIG_GTH2) ) | |
859 | 859 | #define input_swap_data(x,y,z) input_data(x,y,z) |
860 | 860 | #else |
861 | 861 | static void |
862 | 862 | |
... | ... | @@ -881,8 +881,13 @@ |
881 | 881 | debug("in input swap data base for read is %lx\n", (unsigned long) pbuf); |
882 | 882 | |
883 | 883 | while (words--) { |
884 | +#ifdef __MIPS__ | |
885 | + *dbuf++ = swab16p((u16*)pbuf); | |
886 | + *dbuf++ = swab16p((u16*)pbuf); | |
887 | +#else | |
884 | 888 | *dbuf++ = ld_le16(pbuf); |
885 | 889 | *dbuf++ = ld_le16(pbuf); |
890 | +#endif /* !MIPS */ | |
886 | 891 | } |
887 | 892 | #endif |
888 | 893 | } |
common/serial.c
... | ... | @@ -41,7 +41,7 @@ |
41 | 41 | || defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4) |
42 | 42 | return &serial_scc_device; |
43 | 43 | #elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \ |
44 | - || defined(CONFIG_405EP) | |
44 | + || defined(CONFIG_405EP) || defined(CONFIG_MPC5xxx) | |
45 | 45 | return &serial0_device; |
46 | 46 | #else |
47 | 47 | #error No default console |
... | ... | @@ -75,7 +75,7 @@ |
75 | 75 | #endif |
76 | 76 | |
77 | 77 | #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \ |
78 | - || defined(CONFIG_405EP) | |
78 | + || defined(CONFIG_405EP) || defined(CONFIG_MPC5xxx) | |
79 | 79 | serial_register(&serial0_device); |
80 | 80 | serial_register(&serial1_device); |
81 | 81 | #endif |
cpu/arm920t/s3c24x0/i2c.c
... | ... | @@ -153,7 +153,7 @@ |
153 | 153 | #endif |
154 | 154 | #ifdef CONFIG_S3C2400 |
155 | 155 | /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */ |
156 | - gpio->PGCON = (gpio->PGCON & ~0x00003c00) | 0x00000c00; | |
156 | + gpio->PGCON = (gpio->PGCON & ~0x00003c00) | 0x00001000; | |
157 | 157 | #endif |
158 | 158 | |
159 | 159 | /* toggle I2CSCL until bus idle */ |
cpu/mpc5xxx/serial.c
... | ... | @@ -23,6 +23,9 @@ |
23 | 23 | * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00, with |
24 | 24 | * changes based on the file arch/ppc/mbxboot/m8260_tty.c from the |
25 | 25 | * Linux/PPC sources (m8260_tty.c had no copyright info in it). |
26 | + * | |
27 | + * Martin Krause, 8 Jun 2006 | |
28 | + * Added CONFIG_SERIAL_MULTI support | |
26 | 29 | */ |
27 | 30 | |
28 | 31 | /* |
... | ... | @@ -33,6 +36,10 @@ |
33 | 36 | #include <common.h> |
34 | 37 | #include <mpc5xxx.h> |
35 | 38 | |
39 | +#if defined (CONFIG_SERIAL_MULTI) | |
40 | +#include <serial.h> | |
41 | +#endif | |
42 | + | |
36 | 43 | DECLARE_GLOBAL_DATA_PTR; |
37 | 44 | |
38 | 45 | #if defined(CONFIG_PSC_CONSOLE) |
39 | 46 | |
40 | 47 | |
41 | 48 | |
... | ... | @@ -55,9 +62,41 @@ |
55 | 62 | #error CONFIG_PSC_CONSOLE must be in 1 ... 6 |
56 | 63 | #endif |
57 | 64 | |
65 | +#if defined(CONFIG_SERIAL_MULTI) && !defined(CONFIG_PSC_CONSOLE2) | |
66 | +#error you must define CONFIG_PSC_CONSOLE2 if CONFIG_SERIAL_MULTI is set | |
67 | +#endif | |
68 | + | |
69 | +#if defined(CONFIG_SERIAL_MULTI) | |
70 | +#if CONFIG_PSC_CONSOLE2 == 1 | |
71 | +#define PSC_BASE2 MPC5XXX_PSC1 | |
72 | +#elif CONFIG_PSC_CONSOLE2 == 2 | |
73 | +#define PSC_BASE2 MPC5XXX_PSC2 | |
74 | +#elif CONFIG_PSC_CONSOLE2 == 3 | |
75 | +#define PSC_BASE2 MPC5XXX_PSC3 | |
76 | +#elif defined(CONFIG_MGT5100) | |
77 | +#error CONFIG_PSC_CONSOLE2 must be in 1, 2 or 3 | |
78 | +#elif CONFIG_PSC_CONSOLE2 == 4 | |
79 | +#define PSC_BASE2 MPC5XXX_PSC4 | |
80 | +#elif CONFIG_PSC_CONSOLE2 == 5 | |
81 | +#define PSC_BASE2 MPC5XXX_PSC5 | |
82 | +#elif CONFIG_PSC_CONSOLE2 == 6 | |
83 | +#define PSC_BASE2 MPC5XXX_PSC6 | |
84 | +#else | |
85 | +#error CONFIG_PSC_CONSOLE2 must be in 1 ... 6 | |
86 | +#endif | |
87 | +#endif /* CONFIG_SERIAL_MULTI */ | |
88 | + | |
89 | +#if defined(CONFIG_SERIAL_MULTI) | |
90 | +int serial_init_dev (unsigned long dev_base) | |
91 | +#else | |
58 | 92 | int serial_init (void) |
93 | +#endif | |
59 | 94 | { |
95 | +#if defined(CONFIG_SERIAL_MULTI) | |
96 | + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; | |
97 | +#else | |
60 | 98 | volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; |
99 | +#endif | |
61 | 100 | unsigned long baseclk; |
62 | 101 | int div; |
63 | 102 | |
64 | 103 | |
65 | 104 | |
66 | 105 | |
67 | 106 | |
... | ... | @@ -100,13 +139,24 @@ |
100 | 139 | return (0); |
101 | 140 | } |
102 | 141 | |
103 | -void | |
104 | -serial_putc(const char c) | |
142 | +#if defined(CONFIG_SERIAL_MULTI) | |
143 | +void serial_putc_dev (unsigned long dev_base, const char c) | |
144 | +#else | |
145 | +void serial_putc(const char c) | |
146 | +#endif | |
105 | 147 | { |
148 | +#if defined(CONFIG_SERIAL_MULTI) | |
149 | + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; | |
150 | +#else | |
106 | 151 | volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; |
152 | +#endif | |
107 | 153 | |
108 | 154 | if (c == '\n') |
155 | +#if defined(CONFIG_SERIAL_MULTI) | |
156 | + serial_putc_dev (dev_base, '\r'); | |
157 | +#else | |
109 | 158 | serial_putc('\r'); |
159 | +#endif | |
110 | 160 | |
111 | 161 | /* Wait for last character to go. */ |
112 | 162 | while (!(psc->psc_status & PSC_SR_TXEMP)) |
113 | 163 | |
114 | 164 | |
115 | 165 | |
116 | 166 | |
117 | 167 | |
... | ... | @@ -115,18 +165,32 @@ |
115 | 165 | psc->psc_buffer_8 = c; |
116 | 166 | } |
117 | 167 | |
118 | -void | |
119 | -serial_puts (const char *s) | |
168 | +#if defined(CONFIG_SERIAL_MULTI) | |
169 | +void serial_puts_dev (unsigned long dev_base, const char *s) | |
170 | +#else | |
171 | +void serial_puts (const char *s) | |
172 | +#endif | |
120 | 173 | { |
121 | 174 | while (*s) { |
175 | +#if defined(CONFIG_SERIAL_MULTI) | |
176 | + serial_putc_dev (dev_base, *s++); | |
177 | +#else | |
122 | 178 | serial_putc (*s++); |
179 | +#endif | |
123 | 180 | } |
124 | 181 | } |
125 | 182 | |
126 | -int | |
127 | -serial_getc(void) | |
183 | +#if defined(CONFIG_SERIAL_MULTI) | |
184 | +int serial_getc_dev (unsigned long dev_base) | |
185 | +#else | |
186 | +int serial_getc(void) | |
187 | +#endif | |
128 | 188 | { |
189 | +#if defined(CONFIG_SERIAL_MULTI) | |
190 | + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; | |
191 | +#else | |
129 | 192 | volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; |
193 | +#endif | |
130 | 194 | |
131 | 195 | /* Wait for a character to arrive. */ |
132 | 196 | while (!(psc->psc_status & PSC_SR_RXRDY)) |
133 | 197 | |
134 | 198 | |
135 | 199 | |
136 | 200 | |
137 | 201 | |
... | ... | @@ -135,18 +199,32 @@ |
135 | 199 | return psc->psc_buffer_8; |
136 | 200 | } |
137 | 201 | |
138 | -int | |
139 | -serial_tstc(void) | |
202 | +#if defined(CONFIG_SERIAL_MULTI) | |
203 | +int serial_tstc_dev (unsigned long dev_base) | |
204 | +#else | |
205 | +int serial_tstc(void) | |
206 | +#endif | |
140 | 207 | { |
208 | +#if defined(CONFIG_SERIAL_MULTI) | |
209 | + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; | |
210 | +#else | |
141 | 211 | volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; |
212 | +#endif | |
142 | 213 | |
143 | 214 | return (psc->psc_status & PSC_SR_RXRDY); |
144 | 215 | } |
145 | 216 | |
146 | -void | |
147 | -serial_setbrg(void) | |
217 | +#if defined(CONFIG_SERIAL_MULTI) | |
218 | +void serial_setbrg_dev (unsigned long dev_base) | |
219 | +#else | |
220 | +void serial_setbrg(void) | |
221 | +#endif | |
148 | 222 | { |
223 | +#if defined(CONFIG_SERIAL_MULTI) | |
224 | + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; | |
225 | +#else | |
149 | 226 | volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; |
227 | +#endif | |
150 | 228 | unsigned long baseclk, div; |
151 | 229 | |
152 | 230 | #if defined(CONFIG_MGT5100) |
... | ... | @@ -160,5 +238,88 @@ |
160 | 238 | psc->ctur = (div >> 8) & 0xFF; |
161 | 239 | psc->ctlr = div & 0xff; |
162 | 240 | } |
241 | + | |
242 | +#if defined(CONFIG_SERIAL_MULTI) | |
243 | +int serial0_init(void) | |
244 | +{ | |
245 | + return (serial_init_dev(PSC_BASE)); | |
246 | +} | |
247 | + | |
248 | +int serial1_init(void) | |
249 | +{ | |
250 | + return (serial_init_dev(PSC_BASE2)); | |
251 | +} | |
252 | +void serial0_setbrg (void) | |
253 | +{ | |
254 | + serial_setbrg_dev(PSC_BASE); | |
255 | +} | |
256 | +void serial1_setbrg (void) | |
257 | +{ | |
258 | + serial_setbrg_dev(PSC_BASE2); | |
259 | +} | |
260 | + | |
261 | +void serial0_putc(const char c) | |
262 | +{ | |
263 | + serial_putc_dev(PSC_BASE,c); | |
264 | +} | |
265 | + | |
266 | +void serial1_putc(const char c) | |
267 | +{ | |
268 | + serial_putc_dev(PSC_BASE2, c); | |
269 | +} | |
270 | +void serial0_puts(const char *s) | |
271 | +{ | |
272 | + serial_puts_dev(PSC_BASE, s); | |
273 | +} | |
274 | + | |
275 | +void serial1_puts(const char *s) | |
276 | +{ | |
277 | + serial_puts_dev(PSC_BASE2, s); | |
278 | +} | |
279 | + | |
280 | +int serial0_getc(void) | |
281 | +{ | |
282 | + return(serial_getc_dev(PSC_BASE)); | |
283 | +} | |
284 | + | |
285 | +int serial1_getc(void) | |
286 | +{ | |
287 | + return(serial_getc_dev(PSC_BASE2)); | |
288 | +} | |
289 | +int serial0_tstc(void) | |
290 | +{ | |
291 | + return (serial_tstc_dev(PSC_BASE)); | |
292 | +} | |
293 | + | |
294 | +int serial1_tstc(void) | |
295 | +{ | |
296 | + return (serial_tstc_dev(PSC_BASE2)); | |
297 | +} | |
298 | + | |
299 | +struct serial_device serial0_device = | |
300 | +{ | |
301 | + "serial0", | |
302 | + "UART0", | |
303 | + serial0_init, | |
304 | + serial0_setbrg, | |
305 | + serial0_getc, | |
306 | + serial0_tstc, | |
307 | + serial0_putc, | |
308 | + serial0_puts, | |
309 | +}; | |
310 | + | |
311 | +struct serial_device serial1_device = | |
312 | +{ | |
313 | + "serial1", | |
314 | + "UART1", | |
315 | + serial1_init, | |
316 | + serial1_setbrg, | |
317 | + serial1_getc, | |
318 | + serial1_tstc, | |
319 | + serial1_putc, | |
320 | + serial1_puts, | |
321 | +}; | |
322 | +#endif /* CONFIG_SERIAL_MULTI */ | |
323 | + | |
163 | 324 | #endif /* CONFIG_PSC_CONSOLE */ |
doc/README.serial_multi
... | ... | @@ -52,4 +52,30 @@ |
52 | 52 | setenv stdout serial0 |
53 | 53 | setenv stderr serial0 |
54 | 54 | setenv stdin serial0 |
55 | + | |
56 | +MPC5xxx Specific | |
57 | +================ | |
58 | + | |
59 | +Up to two PSCs can be used as console. | |
60 | + | |
61 | +Support for hardware handshake has not been implemented yet. | |
62 | + | |
63 | +*) The first (default) console port is defined by: | |
64 | + #define CONFIG_PSC_CONSOLE <PSC number> | |
65 | + | |
66 | +*) The second (alternative) console port is defined by: | |
67 | + #define CONFIG_PSC_CONSOLE2 <PSC number> | |
68 | + | |
69 | +*) Commands to switch to the second console: | |
70 | + setenv stdout serial1 | |
71 | + setenv stderr serial1 | |
72 | + setenv stdin serial1 | |
73 | + | |
74 | +*) Commands to switch to the first console: | |
75 | + setenv stdout serial0 | |
76 | + setenv stderr serial0 | |
77 | + setenv stdin serial0 | |
78 | + | |
79 | +*) If a file descriptor is set to "serial" then the | |
80 | + current serial device will be used. |
drivers/keyboard.c
... | ... | @@ -33,7 +33,7 @@ |
33 | 33 | |
34 | 34 | #define KBD_BUFFER_LEN 0x20 /* size of the keyboardbuffer */ |
35 | 35 | |
36 | -#ifdef CONFIG_MPC5xxx | |
36 | +#if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC85xx) | |
37 | 37 | int ps2ser_check(void); |
38 | 38 | #endif |
39 | 39 | |
... | ... | @@ -75,7 +75,7 @@ |
75 | 75 | /* test if a character is in the queue */ |
76 | 76 | static int kbd_testc(void) |
77 | 77 | { |
78 | -#ifdef CONFIG_MPC5xxx | |
78 | +#if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC85xx) | |
79 | 79 | /* no ISR is used, so received chars must be polled */ |
80 | 80 | ps2ser_check(); |
81 | 81 | #endif |
... | ... | @@ -90,7 +90,7 @@ |
90 | 90 | { |
91 | 91 | char c; |
92 | 92 | while(in_pointer==out_pointer) { |
93 | -#ifdef CONFIG_MPC5xxx | |
93 | +#if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC85xx) | |
94 | 94 | /* no ISR is used, so received chars must be polled */ |
95 | 95 | ps2ser_check(); |
96 | 96 | #endif |
drivers/ps2ser.c
... | ... | @@ -20,6 +20,9 @@ |
20 | 20 | #include <asm/io.h> |
21 | 21 | #include <asm/atomic.h> |
22 | 22 | #include <ps2mult.h> |
23 | +#ifdef CFG_NS16550 | |
24 | +#include <ns16550.h> | |
25 | +#endif | |
23 | 26 | |
24 | 27 | DECLARE_GLOBAL_DATA_PTR; |
25 | 28 | |
26 | 29 | |
27 | 30 | |
... | ... | @@ -45,13 +48,24 @@ |
45 | 48 | #else |
46 | 49 | #error CONFIG_PS2SERIAL must be in 1 ... 6 |
47 | 50 | #endif |
48 | -#endif /* CONFIG_MPC5xxx */ | |
49 | 51 | |
52 | +#elif defined(CONFIG_MPC85xx) | |
53 | + | |
54 | +#if CONFIG_PS2SERIAL == 1 | |
55 | +#define COM_BASE (CFG_CCSRBAR+0x4500) | |
56 | +#elif CONFIG_PS2SERIAL == 2 | |
57 | +#define COM_BASE (CFG_CCSRBAR+0x4600) | |
58 | +#else | |
59 | +#error CONFIG_PS2SERIAL must be in 1 ... 2 | |
60 | +#endif | |
61 | + | |
62 | +#endif /* CONFIG_MPC5xxx / CONFIG_MPC85xx */ | |
63 | + | |
50 | 64 | static int ps2ser_getc_hw(void); |
51 | 65 | static void ps2ser_interrupt(void *dev_id); |
52 | 66 | |
53 | 67 | extern struct serial_state rs_table[]; /* in serial.c */ |
54 | -#ifndef CONFIG_MPC5xxx | |
68 | +#if !defined(CONFIG_MPC5xxx) && !defined(CONFIG_MPC85xx) | |
55 | 69 | static struct serial_state *state; |
56 | 70 | #endif |
57 | 71 | |
58 | 72 | |
... | ... | @@ -106,8 +120,24 @@ |
106 | 120 | return (0); |
107 | 121 | } |
108 | 122 | |
109 | -#else /* !CONFIG_MPC5xxx */ | |
123 | +#elif defined(CONFIG_MPC85xx) | |
124 | +int ps2ser_init(void) | |
125 | +{ | |
126 | + NS16550_t com_port = (NS16550_t)COM_BASE; | |
110 | 127 | |
128 | + com_port->ier = 0x00; | |
129 | + com_port->lcr = LCR_BKSE | LCR_8N1; | |
130 | + com_port->dll = (CFG_NS16550_CLK / 16 / PS2SER_BAUD) & 0xff; | |
131 | + com_port->dlm = ((CFG_NS16550_CLK / 16 / PS2SER_BAUD) >> 8) & 0xff; | |
132 | + com_port->lcr = LCR_8N1; | |
133 | + com_port->mcr = (MCR_DTR | MCR_RTS); | |
134 | + com_port->fcr = (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR); | |
135 | + | |
136 | + return (0); | |
137 | +} | |
138 | + | |
139 | +#else /* !CONFIG_MPC5xxx && !CONFIG_MPC85xx */ | |
140 | + | |
111 | 141 | static inline unsigned int ps2ser_in(int offset) |
112 | 142 | { |
113 | 143 | return readb((unsigned long) state->iomem_base + offset); |
114 | 144 | |
... | ... | @@ -150,12 +180,14 @@ |
150 | 180 | |
151 | 181 | return 0; |
152 | 182 | } |
153 | -#endif /* CONFIG_MPC5xxx */ | |
183 | +#endif /* CONFIG_MPC5xxx / CONFIG_MPC85xx / other */ | |
154 | 184 | |
155 | 185 | void ps2ser_putc(int chr) |
156 | 186 | { |
157 | 187 | #ifdef CONFIG_MPC5xxx |
158 | 188 | volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; |
189 | +#elif defined(CONFIG_MPC85xx) | |
190 | + NS16550_t com_port = (NS16550_t)COM_BASE; | |
159 | 191 | #endif |
160 | 192 | #ifdef DEBUG |
161 | 193 | printf(">>>> 0x%02x\n", chr); |
... | ... | @@ -165,6 +197,9 @@ |
165 | 197 | while (!(psc->psc_status & PSC_SR_TXRDY)); |
166 | 198 | |
167 | 199 | psc->psc_buffer_8 = chr; |
200 | +#elif defined(CONFIG_MPC85xx) | |
201 | + while ((com_port->lsr & LSR_THRE) == 0); | |
202 | + com_port->thr = chr; | |
168 | 203 | #else |
169 | 204 | while (!(ps2ser_in(UART_LSR) & UART_LSR_THRE)); |
170 | 205 | |
... | ... | @@ -176,6 +211,8 @@ |
176 | 211 | { |
177 | 212 | #ifdef CONFIG_MPC5xxx |
178 | 213 | volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; |
214 | +#elif defined(CONFIG_MPC85xx) | |
215 | + NS16550_t com_port = (NS16550_t)COM_BASE; | |
179 | 216 | #endif |
180 | 217 | int res = -1; |
181 | 218 | |
... | ... | @@ -183,6 +220,10 @@ |
183 | 220 | if (psc->psc_status & PSC_SR_RXRDY) { |
184 | 221 | res = (psc->psc_buffer_8); |
185 | 222 | } |
223 | +#elif defined(CONFIG_MPC85xx) | |
224 | + if (com_port->lsr & LSR_DR) { | |
225 | + res = com_port->rbr; | |
226 | + } | |
186 | 227 | #else |
187 | 228 | if (ps2ser_in(UART_LSR) & UART_LSR_DR) { |
188 | 229 | res = (ps2ser_in(UART_RX)); |
... | ... | @@ -238,6 +279,8 @@ |
238 | 279 | { |
239 | 280 | #ifdef CONFIG_MPC5xxx |
240 | 281 | volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; |
282 | +#elif defined(CONFIG_MPC85xx) | |
283 | + NS16550_t com_port = (NS16550_t)COM_BASE; | |
241 | 284 | #endif |
242 | 285 | int chr; |
243 | 286 | int status; |
... | ... | @@ -246,6 +289,8 @@ |
246 | 289 | chr = ps2ser_getc_hw(); |
247 | 290 | #ifdef CONFIG_MPC5xxx |
248 | 291 | status = psc->psc_status; |
292 | +#elif defined(CONFIG_MPC85xx) | |
293 | + status = com_port->lsr; | |
249 | 294 | #else |
250 | 295 | status = ps2ser_in(UART_IIR); |
251 | 296 | #endif |
... | ... | @@ -260,6 +305,8 @@ |
260 | 305 | } |
261 | 306 | #ifdef CONFIG_MPC5xxx |
262 | 307 | } while (status & PSC_SR_RXRDY); |
308 | +#elif defined(CONFIG_MPC85xx) | |
309 | + } while (status & LSR_DR); | |
263 | 310 | #else |
264 | 311 | } while (status & UART_IIR_RDI); |
265 | 312 | #endif |
include/asm-mips/au1x00.h
... | ... | @@ -119,6 +119,11 @@ |
119 | 119 | return __ilog2(x & -x) + 1; |
120 | 120 | } |
121 | 121 | |
122 | +#define gpio_set(Value) outl(Value, SYS_OUTPUTSET) | |
123 | +#define gpio_clear(Value) outl(Value, SYS_OUTPUTCLR) | |
124 | +#define gpio_read() inl(SYS_PINSTATERD) | |
125 | +#define gpio_tristate(Value) outl(Value, SYS_TRIOUTCLR) | |
126 | + | |
122 | 127 | #endif /* !ASSEMBLY */ |
123 | 128 | |
124 | 129 | #ifdef CONFIG_PM |
include/configs/TQM5200.h
... | ... | @@ -37,7 +37,6 @@ |
37 | 37 | #define CONFIG_TQM5200 1 /* ... on TQM5200 module */ |
38 | 38 | #undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ |
39 | 39 | #define CONFIG_STK52XX 1 /* ... on a STK52XX base board */ |
40 | -#define CONFIG_STK52XX_REV100 1 /* define for revision 100 baseboards */ | |
41 | 40 | |
42 | 41 | #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ |
43 | 42 | |
... | ... | @@ -83,7 +82,7 @@ |
83 | 82 | #define CONFIG_PCI_IO_SIZE 0x01000000 |
84 | 83 | |
85 | 84 | #define CONFIG_NET_MULTI 1 |
86 | -#define CONFIG_EEPRO100 | |
85 | +#define CONFIG_EEPRO100 1 | |
87 | 86 | #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
88 | 87 | #define CONFIG_NS8382X 1 |
89 | 88 | #endif /* CONFIG_STK52XX */ |
... | ... | @@ -192,16 +191,6 @@ |
192 | 191 | |
193 | 192 | #undef CONFIG_BOOTARGS |
194 | 193 | |
195 | -#if defined (CONFIG_TQM5200_AA) | |
196 | -# define CONFIG_U_BOOT_SUFFIX "-AA\0" | |
197 | -#elif defined (CONFIG_TQM5200_AB) | |
198 | -# define CONFIG_U_BOOT_SUFFIX "-AB\0" | |
199 | -#elif defined (CONFIG_TQM5200_AC) | |
200 | -# define CONFIG_U_BOOT_SUFFIX "-AC\0" | |
201 | -#else | |
202 | -# define CONFIG_U_BOOT_SUFFIX "\0" | |
203 | -#endif | |
204 | - | |
205 | 194 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
206 | 195 | "netdev=eth0\0" \ |
207 | 196 | "rootpath=/opt/eldk/ppc_6xx\0" \ |
... | ... | @@ -218,7 +207,7 @@ |
218 | 207 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ |
219 | 208 | "bootfile=/tftpboot/tqm5200/uImage\0" \ |
220 | 209 | "load=tftp 200000 ${u-boot}\0" \ |
221 | - "u-boot=/tftpboot/tqm5200/u-boot.bin" CONFIG_U_BOOT_SUFFIX \ | |
210 | + "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \ | |
222 | 211 | "update=protect off FC000000 FC05FFFF;" \ |
223 | 212 | "erase FC000000 FC05FFFF;" \ |
224 | 213 | "cp.b 200000 FC000000 ${filesize};" \ |
... | ... | @@ -284,13 +273,6 @@ |
284 | 273 | #endif |
285 | 274 | |
286 | 275 | /* List of I2C addresses to be verified by POST */ |
287 | -#if defined (CONFIG_TQM5200_AA) || defined (CONFIG_TQM5200_AB) | |
288 | -#define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \ | |
289 | - CFG_I2C_SLAVE } | |
290 | -#elif defined (CONFIG_TQM5200_AC) | |
291 | -#define I2C_ADDR_LIST { CFG_I2C_SLAVE } | |
292 | -#endif | |
293 | - | |
294 | 276 | #if defined (CONFIG_MINIFAP) |
295 | 277 | #undef I2C_ADDR_LIST |
296 | 278 | #define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \ |
297 | 279 | |
298 | 280 | |
... | ... | @@ -493,13 +475,9 @@ |
493 | 475 | * SRAM - Do not map below 2 GB in address space, because this area is used |
494 | 476 | * for SDRAM autosizing. |
495 | 477 | */ |
496 | -#if defined CONFIG_TQM5200_AB || defined (CONFIG_CS_AUTOCONF) | |
478 | +#if defined (CONFIG_CS_AUTOCONF) | |
497 | 479 | #define CFG_CS2_START 0xE5000000 |
498 | -#ifdef CONFIG_TQM5200_AB | |
499 | -#define CFG_CS2_SIZE 0x80000 /* 512 kByte */ | |
500 | -#else /* CONFIG_CS_AUTOCONF */ | |
501 | 480 | #define CFG_CS2_SIZE 0x100000 /* 1 MByte */ |
502 | -#endif | |
503 | 481 | #define CFG_CS2_CFG 0x0004D930 |
504 | 482 | #endif |
505 | 483 | |
... | ... | @@ -507,8 +485,7 @@ |
507 | 485 | * Grafic controller - Do not map below 2 GB in address space, because this |
508 | 486 | * area is used for SDRAM autosizing. |
509 | 487 | */ |
510 | -#if defined (CONFIG_TQM5200_AB) || defined (CONFIG_TQM5200_AC) || \ | |
511 | - defined (CONFIG_CS_AUTOCONF) | |
488 | +#if defined (CONFIG_CS_AUTOCONF) | |
512 | 489 | #define SM501_FB_BASE 0xE0000000 |
513 | 490 | #define CFG_CS1_START (SM501_FB_BASE) |
514 | 491 | #define CFG_CS1_SIZE 0x4000000 /* 64 MByte */ |
include/configs/TQM85xx.h
... | ... | @@ -177,6 +177,13 @@ |
177 | 177 | #define CFG_BAUDRATE_TABLE \ |
178 | 178 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
179 | 179 | |
180 | +/* PS/2 Keyboard */ | |
181 | +#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */ | |
182 | +#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */ | |
183 | +#define CONFIG_PS2SERIAL 2 /* .. on DUART2 */ | |
184 | +#define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */ | |
185 | +#define CONFIG_BOARD_EARLY_INIT_R 1 | |
186 | + | |
180 | 187 | /* Use the HUSH parser */ |
181 | 188 | #define CFG_HUSH_PARSER |
182 | 189 | #ifdef CFG_HUSH_PARSER |
include/configs/cmc_pu2.h
... | ... | @@ -108,7 +108,7 @@ |
108 | 108 | /* still about 20 kB free with this defined */ |
109 | 109 | #define CFG_LONGHELP |
110 | 110 | |
111 | -#define CONFIG_BOOTDELAY 3 | |
111 | +#define CONFIG_BOOTDELAY 1 | |
112 | 112 | |
113 | 113 | #ifdef CONFIG_HARD_I2C |
114 | 114 | #define CONFIG_COMMANDS \ |
... | ... | @@ -205,15 +205,6 @@ |
205 | 205 | #ifdef CONFIG_USE_IRQ |
206 | 206 | #error CONFIG_USE_IRQ not supported |
207 | 207 | #endif |
208 | - | |
209 | -#define CFG_DEVICE_NULLDEV 1 /* enble null device */ | |
210 | -#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */ | |
211 | - | |
212 | -#define CONFIG_AUTOBOOT_KEYED | |
213 | -#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n" | |
214 | -#define CONFIG_AUTOBOOT_STOP_STR "R" /* default password */ | |
215 | - | |
216 | -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ | |
217 | 208 | |
218 | 209 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
219 | 210 | "net_nfs=tftp ${loadaddr} ${bootfile};run nfsargs addip addcons " \ |
include/configs/gth2.h
1 | +/* | |
2 | + * (C) Copyright 2005 | |
3 | + * Thomas.Lange@corelatus.se | |
4 | + * | |
5 | + * See file CREDITS for list of people who contributed to this | |
6 | + * project. | |
7 | + * | |
8 | + * This program is free software; you can redistribute it and/or | |
9 | + * modify it under the terms of the GNU General Public License as | |
10 | + * published by the Free Software Foundation; either version 2 of | |
11 | + * the License, or (at your option) any later version. | |
12 | + * | |
13 | + * This program is distributed in the hope that it will be useful, | |
14 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | + * GNU General Public License for more details. | |
17 | + * | |
18 | + * You should have received a copy of the GNU General Public License | |
19 | + * along with this program; if not, write to the Free Software | |
20 | + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | + * MA 02111-1307 USA | |
22 | + */ | |
23 | + | |
24 | +/* | |
25 | + * This file contains the configuration parameters for the gth2 board. | |
26 | + */ | |
27 | + | |
28 | +#ifndef __CONFIG_H | |
29 | +#define __CONFIG_H | |
30 | + | |
31 | +#define CONFIG_MIPS32 1 /* MIPS32 CPU core */ | |
32 | +#define CONFIG_GTH2 1 | |
33 | +#define CONFIG_AU1X00 1 /* alchemy series cpu */ | |
34 | + | |
35 | +#define CONFIG_AU1000 1 | |
36 | + | |
37 | +#define CONFIG_MISC_INIT_R 1 | |
38 | + | |
39 | +#define CONFIG_ETHADDR DE:AD:BE:EF:01:02 /* Ethernet address */ | |
40 | + | |
41 | +#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */ | |
42 | + | |
43 | +#define CONFIG_ENV_OVERWRITE 1 /* Allow change of ethernet address */ | |
44 | + | |
45 | +#define CONFIG_BOOT_RETRY_TIME 5 /* Retry boot in 5 secs */ | |
46 | + | |
47 | +#define CONFIG_RESET_TO_RETRY 1 /* If timeout waiting for command, perform a reset */ | |
48 | + | |
49 | +#define CONFIG_BAUDRATE 115200 | |
50 | + | |
51 | +/* valid baudrates */ | |
52 | +#define CFG_BAUDRATE_TABLE { 115200 } | |
53 | + | |
54 | +/* Only interrupt boot if space is pressed */ | |
55 | +/* If a long serial cable is connected but */ | |
56 | +/* other end is dead, garbage will be read */ | |
57 | +#define CONFIG_AUTOBOOT_KEYED 1 | |
58 | +#define CONFIG_AUTOBOOT_PROMPT "Press space to abort autoboot in %d second\n" | |
59 | +#define CONFIG_AUTOBOOT_DELAY_STR "d" | |
60 | +#define CONFIG_AUTOBOOT_STOP_STR " " | |
61 | + | |
62 | +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ | |
63 | +#define CONFIG_BOOTARGS "panic=1" | |
64 | + | |
65 | +#define CONFIG_EXTRA_ENV_SETTINGS \ | |
66 | + "addmisc=setenv bootargs $(bootargs) " \ | |
67 | + "ethaddr=$(ethaddr) \0" \ | |
68 | + "netboot=bootp;run addmisc;bootm\0" \ | |
69 | + "" | |
70 | + | |
71 | +/* Boot from Compact flash partition 2 as default */ | |
72 | +#define CONFIG_BOOTCOMMAND "ide reset;disk 0x81000000 0:2;run addmisc;bootm" | |
73 | + | |
74 | +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_IDE | CFG_CMD_DHCP ) & \ | |
75 | + ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | \ | |
76 | + CFG_CMD_MII | CFG_CMD_LOADS | CFG_CMD_LOADB | CFG_CMD_ELF | \ | |
77 | + CFG_CMD_BDI | CFG_CMD_BEDBUG | CFG_CMD_NFS | CFG_CMD_AUTOSCRIPT )) | |
78 | + | |
79 | +#include <cmd_confdefs.h> | |
80 | + | |
81 | +/* | |
82 | + * Miscellaneous configurable options | |
83 | + */ | |
84 | +#define CFG_LONGHELP /* undef to save memory */ | |
85 | +#define CFG_PROMPT "GTH2 # " /* Monitor Command Prompt */ | |
86 | +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
87 | +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
88 | +#define CFG_MAXARGS 16 /* max number of command args*/ | |
89 | + | |
90 | +#define CFG_MALLOC_LEN 128*1024 | |
91 | + | |
92 | +#define CFG_BOOTPARAMS_LEN 128*1024 | |
93 | + | |
94 | +#define CFG_MHZ 500 | |
95 | + | |
96 | +#define CFG_HZ (CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */ | |
97 | + | |
98 | +#define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ | |
99 | + | |
100 | +#define CFG_LOAD_ADDR 0x81000000 /* default load address */ | |
101 | + | |
102 | +#define CFG_MEMTEST_START 0x80100000 | |
103 | +#define CFG_MEMTEST_END 0x83000000 | |
104 | + | |
105 | +#define CONFIG_HW_WATCHDOG 1 | |
106 | + | |
107 | +/*----------------------------------------------------------------------- | |
108 | + * FLASH and environment organization | |
109 | + */ | |
110 | +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ | |
111 | +#define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ | |
112 | + | |
113 | +#define PHYS_FLASH 0xbfc00000 /* Flash Bank #1 */ | |
114 | + | |
115 | +/* The following #defines are needed to get flash environment right */ | |
116 | +#define CFG_MONITOR_BASE TEXT_BASE | |
117 | +#define CFG_MONITOR_LEN (192 << 10) | |
118 | + | |
119 | +#define CFG_INIT_SP_OFFSET 0x400000 | |
120 | + | |
121 | +/* We boot from this flash, selected with dip switch */ | |
122 | +#define CFG_FLASH_BASE PHYS_FLASH | |
123 | + | |
124 | +/* timeout values are in ticks */ | |
125 | +#define CFG_FLASH_ERASE_TOUT (2 * CFG_HZ) /* Timeout for Flash Erase */ | |
126 | +#define CFG_FLASH_WRITE_TOUT (2 * CFG_HZ) /* Timeout for Flash Write */ | |
127 | + | |
128 | +#define CFG_ENV_IS_NOWHERE 1 | |
129 | + | |
130 | +/* Address and size of Primary Environment Sector */ | |
131 | +#define CFG_ENV_ADDR 0xB0030000 | |
132 | +#define CFG_ENV_SIZE 0x10000 | |
133 | + | |
134 | +#define CONFIG_FLASH_16BIT | |
135 | + | |
136 | +#define CONFIG_NR_DRAM_BANKS 2 | |
137 | + | |
138 | +#define CONFIG_NET_MULTI | |
139 | + | |
140 | +#define CONFIG_MEMSIZE_IN_BYTES | |
141 | + | |
142 | +/*---ATA PCMCIA ------------------------------------*/ | |
143 | +#define CFG_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */ | |
144 | + | |
145 | +#define CFG_PCMCIA_MEM_ADDR 0x20000000 | |
146 | +#define CFG_PCMCIA_IO_BASE 0x28000000 | |
147 | +#define CFG_PCMCIA_ATTR_BASE 0x30000000 | |
148 | + | |
149 | +#define CONFIG_PCMCIA_SLOT_A | |
150 | + | |
151 | +#define CONFIG_ATAPI 1 | |
152 | +#define CONFIG_MAC_PARTITION 1 | |
153 | + | |
154 | +/* We run CF in "true ide" mode or a harddrive via pcmcia */ | |
155 | +#define CONFIG_IDE_PCMCIA 1 | |
156 | + | |
157 | +/* We only support one slot for now */ | |
158 | +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ | |
159 | +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
160 | + | |
161 | +#undef CONFIG_IDE_LED /* LED for ide not supported */ | |
162 | +#undef CONFIG_IDE_RESET /* reset for ide not supported */ | |
163 | + | |
164 | +#define CFG_ATA_IDE0_OFFSET 0 | |
165 | + | |
166 | +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_IO_BASE | |
167 | + | |
168 | +/* Offset for data I/O */ | |
169 | +#define CFG_ATA_DATA_OFFSET 0 | |
170 | + | |
171 | +/* Offset for normal register accesses */ | |
172 | +#define CFG_ATA_REG_OFFSET 0 | |
173 | + | |
174 | +/* Offset for alternate registers */ | |
175 | +#define CFG_ATA_ALT_OFFSET 0x0200 | |
176 | + | |
177 | +/*----------------------------------------------------------------------- | |
178 | + * Cache Configuration | |
179 | + */ | |
180 | +#define CFG_DCACHE_SIZE 16384 | |
181 | +#define CFG_ICACHE_SIZE 16384 | |
182 | +#define CFG_CACHELINE_SIZE 32 | |
183 | + | |
184 | +#define GPIO_CACONFIG (1<<0) | |
185 | +#define GPIO_DPACONFIG (1<<6) | |
186 | +#define GPIO_ERESET (1<<11) | |
187 | +#define GPIO_EEDQ (1<<17) | |
188 | +#define GPIO_WDI (1<<18) | |
189 | +#define GPIO_RJ1LY (1<<22) | |
190 | +#define GPIO_RJ1LG (1<<23) | |
191 | +#define GPIO_LEDCLK (1<<29) | |
192 | +#define GPIO_LEDD (1<<30) | |
193 | +#define GPIO_CPU_LED (1<<31) | |
194 | + | |
195 | +#endif /* __CONFIG_H */ |
include/configs/spieval.h
... | ... | @@ -191,16 +191,6 @@ |
191 | 191 | |
192 | 192 | #undef CONFIG_BOOTARGS |
193 | 193 | |
194 | -#if defined (CONFIG_TQM5200_AA) | |
195 | -# define CONFIG_U_BOOT_SUFFIX "-AA\0" | |
196 | -#elif defined (CONFIG_TQM5200_AB) | |
197 | -# define CONFIG_U_BOOT_SUFFIX "-AB\0" | |
198 | -#elif defined (CONFIG_TQM5200_AC) | |
199 | -# define CONFIG_U_BOOT_SUFFIX "-AC\0" | |
200 | -#else | |
201 | -# define CONFIG_U_BOOT_SUFFIX "\0" | |
202 | -#endif | |
203 | - | |
204 | 194 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
205 | 195 | "netdev=eth0\0" \ |
206 | 196 | "rootpath=/opt/eldk/ppc_6xx\0" \ |
... | ... | @@ -217,7 +207,7 @@ |
217 | 207 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ |
218 | 208 | "bootfile=/tftpboot/tqm5200/uImage\0" \ |
219 | 209 | "load=tftp 200000 ${u-boot}\0" \ |
220 | - "u-boot=/tftpboot/tqm5200/u-boot.bin" CONFIG_U_BOOT_SUFFIX \ | |
210 | + "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \ | |
221 | 211 | "update=protect off FC000000 FC05FFFF;" \ |
222 | 212 | "erase FC000000 FC05FFFF;" \ |
223 | 213 | "cp.b 200000 FC000000 ${filesize};" \ |
... | ... | @@ -283,13 +273,6 @@ |
283 | 273 | #endif |
284 | 274 | |
285 | 275 | /* List of I2C addresses to be verified by POST */ |
286 | -#if defined (CONFIG_TQM5200_AA) || defined (CONFIG_TQM5200_AB) | |
287 | -#define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \ | |
288 | - CFG_I2C_SLAVE } | |
289 | -#elif defined (CONFIG_TQM5200_AC) | |
290 | -#define I2C_ADDR_LIST { CFG_I2C_SLAVE } | |
291 | -#endif | |
292 | - | |
293 | 276 | #if defined (CONFIG_MINIFAP) |
294 | 277 | #undef I2C_ADDR_LIST |
295 | 278 | #define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \ |
296 | 279 | |
297 | 280 | |
... | ... | @@ -478,13 +461,9 @@ |
478 | 461 | * SRAM - Do not map below 2 GB in address space, because this area is used |
479 | 462 | * for SDRAM autosizing. |
480 | 463 | */ |
481 | -#if defined CONFIG_TQM5200_AB || defined (CONFIG_CS_AUTOCONF) | |
464 | +#if defined (CONFIG_CS_AUTOCONF) | |
482 | 465 | #define CFG_CS2_START 0xE5000000 |
483 | -#ifdef CONFIG_TQM5200_AB | |
484 | -#define CFG_CS2_SIZE 0x80000 /* 512 kByte */ | |
485 | -#else /* CONFIG_CS_AUTOCONF */ | |
486 | 466 | #define CFG_CS2_SIZE 0x100000 /* 1 MByte */ |
487 | -#endif | |
488 | 467 | #define CFG_CS2_CFG 0x0004D930 |
489 | 468 | #endif |
490 | 469 | |
... | ... | @@ -492,8 +471,7 @@ |
492 | 471 | * Grafic controller - Do not map below 2 GB in address space, because this |
493 | 472 | * area is used for SDRAM autosizing. |
494 | 473 | */ |
495 | -#if defined (CONFIG_TQM5200_AB) || defined (CONFIG_TQM5200_AC) || \ | |
496 | - defined (CONFIG_CS_AUTOCONF) | |
474 | +#if defined (CONFIG_CS_AUTOCONF) | |
497 | 475 | #define SM501_FB_BASE 0xE0000000 |
498 | 476 | #define CFG_CS1_START (SM501_FB_BASE) |
499 | 477 | #define CFG_CS1_SIZE 0x4000000 /* 64 MByte */ |
include/configs/trab.h
... | ... | @@ -160,7 +160,6 @@ |
160 | 160 | CFG_CMD_DATE | \ |
161 | 161 | CFG_CMD_DHCP | \ |
162 | 162 | CFG_CMD_FAT | \ |
163 | - CFG_CMD_JFFS2 | \ | |
164 | 163 | CFG_CMD_NFS | \ |
165 | 164 | CFG_CMD_SNTP | \ |
166 | 165 | CFG_CMD_USB ) |
... | ... | @@ -174,7 +173,6 @@ |
174 | 173 | CFG_CMD_DATE | \ |
175 | 174 | CFG_CMD_DHCP | \ |
176 | 175 | CFG_CMD_FAT | \ |
177 | - CFG_CMD_JFFS2 | \ | |
178 | 176 | CFG_CMD_NFS | \ |
179 | 177 | CFG_CMD_SNTP | \ |
180 | 178 | CFG_CMD_USB ) |
181 | 179 | |
... | ... | @@ -384,10 +382,10 @@ |
384 | 382 | #define MTDIDS_DEFAULT "nor0=0" |
385 | 383 | |
386 | 384 | /* production flash layout */ |
387 | -#define MTDPARTS_DEFAULT "mtdparts=0:32k(Firmware1)ro," \ | |
385 | +#define MTDPARTS_DEFAULT "mtdparts=0:16k(Firmware1)ro," \ | |
388 | 386 | "16k(Env1)," \ |
389 | 387 | "16k(Env2)," \ |
390 | - "320k(Firmware2)ro," \ | |
388 | + "336k(Firmware2)ro," \ | |
391 | 389 | "896k(Kernel)," \ |
392 | 390 | "5376k(Root-FS)," \ |
393 | 391 | "1408k(JFFS2)," \ |
include/serial.h
... | ... | @@ -23,7 +23,7 @@ |
23 | 23 | extern struct serial_device * default_serial_console (void); |
24 | 24 | |
25 | 25 | #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \ |
26 | - || defined(CONFIG_405EP) | |
26 | + || defined(CONFIG_405EP) || defined(CONFIG_MPC5xxx) | |
27 | 27 | extern struct serial_device serial0_device; |
28 | 28 | extern struct serial_device serial1_device; |
29 | 29 | #endif |