Eric Lee / smarc-uboot

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Commit 90f87fb5258c57bbb8497ac23454e659169483e4

Authored by Marek Vasut
Committed by Stefano Babic
1 parent 33f794be36
Exists in smarc_8mq_lf_v2020.04 and in 9 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

pci: imx: Fix potential 64bit memory access clamping 

The driver limits the config space base to 32bit, however it can be
64bit on 64bit iMX hardware too. Remove that limitation. This patch
has no impact on the iMX6, which is the only SoC currently supported
by this driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Showing 1 changed file with 11 additions and 9 deletions Side-by-side Diff

drivers/pci/pcie_imx.c
Diff comments   View file @ 90f87fb
... ... @@ -307,9 +307,11 @@
307 307 /* Region #0 is used for Outbound CFG space access. */
308 308 writel(0, priv->dbi_base + PCIE_ATU_VIEWPORT);
309 309  
310   - writel((u32)priv->cfg_base, priv->dbi_base + PCIE_ATU_LOWER_BASE);
311   - writel(0, priv->dbi_base + PCIE_ATU_UPPER_BASE);
312   - writel((u32)priv->cfg_base + MX6_ROOT_SIZE,
  310 + writel(lower_32_bits((uintptr_t)priv->cfg_base),
  311 + priv->dbi_base + PCIE_ATU_LOWER_BASE);
  312 + writel(upper_32_bits((uintptr_t)priv->cfg_base),
  313 + priv->dbi_base + PCIE_ATU_UPPER_BASE);
  314 + writel(lower_32_bits((uintptr_t)priv->cfg_base + MX6_ROOT_SIZE),
313 315 priv->dbi_base + PCIE_ATU_LIMIT);
314 316  
315 317 writel(0, priv->dbi_base + PCIE_ATU_LOWER_TARGET);
316 318  
... ... @@ -323,9 +325,9 @@
323 325 /*
324 326 * PCI Express accessors
325 327 */
326   -static uint32_t get_bus_address(pci_dev_t d, int where)
  328 +static void __iomem *get_bus_address(pci_dev_t d, int where)
327 329 {
328   - uint32_t va_address;
  330 + void __iomem *va_address;
329 331  
330 332 /* Reconfigure Region #0 */
331 333 writel(0, priv->dbi_base + PCIE_ATU_VIEWPORT);
332 334  
... ... @@ -336,10 +338,10 @@
336 338 writel(PCIE_ATU_TYPE_CFG1, priv->dbi_base + PCIE_ATU_CR1);
337 339  
338 340 if (PCI_BUS(d) == 0) {
339   - va_address = (u32)priv->dbi_base;
  341 + va_address = priv->dbi_base;
340 342 } else {
341 343 writel(d << 8, priv->dbi_base + PCIE_ATU_LOWER_TARGET);
342   - va_address = (u32)priv->cfg_base;
  344 + va_address = priv->cfg_base;
343 345 }
344 346  
345 347 va_address += (where & ~0x3);
... ... @@ -390,7 +392,7 @@
390 392 static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
391 393 int where, u32 *val)
392 394 {
393   - uint32_t va_address;
  395 + void __iomem *va_address;
394 396 int ret;
395 397  
396 398 ret = imx_pcie_addr_valid(d);
... ... @@ -419,7 +421,7 @@
419 421 static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
420 422 int where, u32 val)
421 423 {
422   - uint32_t va_address = 0;
  424 + void __iomem *va_address = NULL;
423 425 int ret;
424 426  
425 427 ret = imx_pcie_addr_valid(d);