Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit 92c427b18982167064de454ae5248ec466998919

Authored by Jon Loeliger
2 parents 281f69ede2 34c3c0e01d
Exists in master and in 55 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Merge branch 'mpc85xx' 

Conflicts:

	include/ft_build.h
	include/pci.h

Resolved, though.

Showing 32 changed files Side-by-side Diff

... ... @@ -447,6 +447,11 @@
447 447 Board code has addition modification that it wants to make
448 448 to the flat device tree before handing it off to the kernel
449 449  
  450 + CONFIG_OF_BOOT_CPU
  451 +
  452 + This define fills in the correct boot cpu in the boot
  453 + param header, the default value is zero if undefined.
  454 +
450 455 - Serial Ports:
451 456 CFG_PL010_SERIAL
452 457  
... ... @@ -3018,6 +3023,55 @@
3018 3023 VFS: Mounted root (ext2 filesystem).
3019 3024  
3020 3025 bash#
  3026 +
  3027 +Boot Linux and pass a flat device tree:
  3028 +-----------
  3029 +
  3030 +First, U-Boot must be compiled with the appropriate defines. See the section
  3031 +titled "Linux Kernel Interface" above for a more in depth explanation. The
  3032 +following is an example of how to start a kernel and pass an updated
  3033 +flat device tree:
  3034 +
  3035 +=> print oftaddr
  3036 +oftaddr=0x300000
  3037 +=> print oft
  3038 +oft=oftrees/mpc8540ads.dtb
  3039 +=> tftp $oftaddr $oft
  3040 +Speed: 1000, full duplex
  3041 +Using TSEC0 device
  3042 +TFTP from server 192.168.1.1; our IP address is 192.168.1.101
  3043 +Filename 'oftrees/mpc8540ads.dtb'.
  3044 +Load address: 0x300000
  3045 +Loading: #
  3046 +done
  3047 +Bytes transferred = 4106 (100a hex)
  3048 +=> tftp $loadaddr $bootfile
  3049 +Speed: 1000, full duplex
  3050 +Using TSEC0 device
  3051 +TFTP from server 192.168.1.1; our IP address is 192.168.1.2
  3052 +Filename 'uImage'.
  3053 +Load address: 0x200000
  3054 +Loading:############
  3055 +done
  3056 +Bytes transferred = 1029407 (fb51f hex)
  3057 +=> print loadaddr
  3058 +loadaddr=200000
  3059 +=> print oftaddr
  3060 +oftaddr=0x300000
  3061 +=> bootm $loadaddr - $oftaddr
  3062 +## Booting image at 00200000 ...
  3063 + Image Name: Linux-2.6.17-dirty
  3064 + Image Type: PowerPC Linux Kernel Image (gzip compressed)
  3065 + Data Size: 1029343 Bytes = 1005.2 kB
  3066 + Load Address: 00000000
  3067 + Entry Point: 00000000
  3068 + Verifying Checksum ... OK
  3069 + Uncompressing Kernel Image ... OK
  3070 +Booting using flat device tree at 0x300000
  3071 +Using MPC85xx ADS machine description
  3072 +Memory CAM mapping: CAM0=256Mb, CAM1=256Mb, CAM2=0Mb residual: 0Mb
  3073 +[snip]
  3074 +
3021 3075  
3022 3076 More About U-Boot Image Types:
3023 3077 ------------------------------
board/cds/common/ft_board.c
Diff comments   View file @ 92c427b
  1 +/*
  2 + * Copyright 2004 Freescale Semiconductor.
  3 + *
  4 + * See file CREDITS for list of people who contributed to this
  5 + * project.
  6 + *
  7 + * This program is free software; you can redistribute it and/or
  8 + * modify it under the terms of the GNU General Public License as
  9 + * published by the Free Software Foundation; either version 2 of
  10 + * the License, or (at your option) any later version.
  11 + *
  12 + * This program is distributed in the hope that it will be useful,
  13 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 + * GNU General Public License for more details.
  16 + *
  17 + * You should have received a copy of the GNU General Public License
  18 + * along with this program; if not, write to the Free Software
  19 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 + * MA 02111-1307 USA
  21 + */
  22 +
  23 +#include <common.h>
  24 +
  25 +#if defined(CONFIG_OF_FLAT_TREE)
  26 +#include <ft_build.h>
  27 +extern void ft_cpu_setup(void *blob, bd_t *bd);
  28 +#endif
  29 +
  30 +
  31 +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
  32 +void
  33 +ft_board_setup(void *blob, bd_t *bd)
  34 +{
  35 + u32 *p;
  36 + int len;
  37 +
  38 +#ifdef CONFIG_PCI
  39 + ft_pci_setup(blob, bd);
  40 +#endif
  41 + ft_cpu_setup(blob, bd);
  42 +
  43 + p = ft_get_prop(blob, "/memory/reg", &len);
  44 + if (p != NULL) {
  45 + *p++ = cpu_to_be32(bd->bi_memstart);
  46 + *p = cpu_to_be32(bd->bi_memsize);
  47 + }
  48 +}
  49 +#endif
board/cds/common/via.c
Diff comments   View file @ 92c427b
  1 +/*
  2 + * Copyright 2006 Freescale Semiconductor.
  3 + *
  4 + * See file CREDITS for list of people who contributed to this
  5 + * project.
  6 + *
  7 + * This program is free software; you can redistribute it and/or
  8 + * modify it under the terms of the GNU General Public License as
  9 + * published by the Free Software Foundation; either version 2 of
  10 + * the License, or (at your option) any later version.
  11 + *
  12 + * This program is distributed in the hope that it will be useful,
  13 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 + * GNU General Public License for more details.
  16 + *
  17 + * You should have received a copy of the GNU General Public License
  18 + * along with this program; if not, write to the Free Software
  19 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 + * MA 02111-1307 USA
  21 + */
  22 +
  23 +#include <common.h>
  24 +#include <pci.h>
  25 +
  26 +/* Config the VIA chip */
  27 +void mpc85xx_config_via(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab)
  28 +{
  29 + pci_dev_t bridge;
  30 +
  31 + /* Enable USB and IDE functions */
  32 + pci_hose_write_config_byte(hose, dev, 0x48, 0x08);
  33 +
  34 + pciauto_config_device(hose, dev);
  35 +
  36 + /*
  37 + * Force the backplane P2P bridge to have a window
  38 + * open from 0x00000000-0x00001fff in PCI I/O space.
  39 + * This allows legacy I/O (i8259, etc) on the VIA
  40 + * southbridge to be accessed.
  41 + */
  42 + bridge = PCI_BDF(0,17,0);
  43 + pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0);
  44 + pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0);
  45 + pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10);
  46 + pci_hose_write_config_word(hose, bridge, PCI_IO_LIMIT_UPPER16, 0);
  47 +}
  48 +
  49 +/* Function 1, IDE */
  50 +void mpc85xx_config_via_usbide(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab)
  51 +{
  52 + pciauto_config_device(hose, dev);
  53 + /*
  54 + * Since the P2P window was forced to cover the fixed
  55 + * legacy I/O addresses, it is necessary to manually
  56 + * place the base addresses for the IDE and USB functions
  57 + * within this window.
  58 + */
  59 + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1ff8);
  60 + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1ff4);
  61 + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1fe8);
  62 + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_3, 0x1fe4);
  63 + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fd0);
  64 +}
  65 +
  66 +/* Function 2, USB ports 0-1 */
  67 +void mpc85xx_config_via_usb(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab)
  68 +{
  69 + pciauto_config_device(hose, dev);
  70 +
  71 + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fa0);
  72 +}
  73 +
  74 +/* Function 3, USB ports 2-3 */
  75 +void mpc85xx_config_via_usb2(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab)
  76 +{
  77 + pciauto_config_device(hose, dev);
  78 +
  79 + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1f80);
  80 +}
  81 +
  82 +/* Function 5, Power Management */
  83 +void mpc85xx_config_via_power(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab)
  84 +{
  85 + pciauto_config_device(hose, dev);
  86 +
  87 + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1e00);
  88 + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1dfc);
  89 + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1df8);
  90 +}
  91 +
  92 +/* Function 6, AC97 Interface */
  93 +void mpc85xx_config_via_ac97(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab)
  94 +{
  95 + pciauto_config_device(hose, dev);
  96 +
  97 + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1c00);
  98 +}
board/cds/common/via.h
Diff comments   View file @ 92c427b
  1 +#ifndef _MPC85xx_VIA_H
  2 +void mpc85xx_config_via(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
  3 +
  4 +/* Function 1, IDE */
  5 +void mpc85xx_config_via_usbide(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
  6 +
  7 +/* Function 2, USB ports 0-1 */
  8 +void mpc85xx_config_via_usb(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
  9 +
  10 +/* Function 3, USB ports 2-3 */
  11 +void mpc85xx_config_via_usb2(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
  12 +
  13 +/* Function 5, Power Management */
  14 +void mpc85xx_config_via_power(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
  15 +
  16 +/* Function 6, AC97 Interface */
  17 +void mpc85xx_config_via_ac97(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
  18 +#endif /* _MPC85xx_VIA_H */
board/cds/mpc8541cds/Makefile
Diff comments   View file @ 92c427b
... ... @@ -28,7 +28,9 @@
28 28  
29 29 OBJS := $(BOARD).o \
30 30 ../common/cadmus.o \
31   - ../common/eeprom.o
  31 + ../common/eeprom.o \
  32 + ../common/ft_board.o \
  33 + ../common/via.o
32 34  
33 35 SOBJS := init.o
34 36  
board/cds/mpc8541cds/init.S
Diff comments   View file @ 92c427b
... ... @@ -210,8 +210,8 @@
210 210 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
211 211 * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
212 212 * 0xe000_0000 0xe000_ffff CCSR 1M
213   - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
214   - * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
  213 + * 0xe200_0000 0xe20f_ffff PCI1 IO 1M
  214 + * 0xe210_0000 0xe21f_ffff PCI2 IO 1M
215 215 * 0xf000_0000 0xf7ff_ffff SDRAM 128M
216 216 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
217 217 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
218 218  
... ... @@ -234,11 +234,11 @@
234 234 #define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
235 235 #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
236 236  
237   -#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
238   -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
  237 +#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
  238 +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
239 239  
240   -#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff)
241   -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))
  240 +#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff)
  241 +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
242 242  
243 243 /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
244 244 #define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
board/cds/mpc8541cds/mpc8541cds.c
Diff comments   View file @ 92c427b
... ... @@ -31,6 +31,7 @@
31 31  
32 32 #include "../common/cadmus.h"
33 33 #include "../common/eeprom.h"
  34 +#include "../common/via.h"
34 35  
35 36 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
36 37 extern void ddr_enable_ecc(unsigned int dram_size);
37 38  
38 39  
39 40  
40 41  
41 42  
... ... @@ -468,26 +469,25 @@
468 469 #endif
469 470  
470 471 #if defined(CONFIG_PCI)
471   -
472   -/*
473   - * Initialize PCI Devices, report devices found.
  472 +/* For some reason the Tundra PCI bridge shows up on itself as a
  473 + * different device. Work around that by refusing to configure it.
474 474 */
  475 +void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
475 476  
476   -#ifndef CONFIG_PCI_PNP
477 477 static struct pci_config_table pci_mpc85xxcds_config_table[] = {
478   - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
479   - PCI_IDSEL_NUMBER, PCI_ANY_ID,
480   - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
481   - PCI_ENET0_MEMADDR,
482   - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
483   - } },
484   - { }
  478 + {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
  479 + {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
  480 + {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}},
  481 + {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
  482 + {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
  483 + {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}},
  484 + {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}
485 485 };
486   -#endif
487 486  
488   -static struct pci_controller hose = {
489   -#ifndef CONFIG_PCI_PNP
490   - config_table: pci_mpc85xxcds_config_table,
  487 +static struct pci_controller hose[] = {
  488 + { config_table: pci_mpc85xxcds_config_table,},
  489 +#ifdef CONFIG_MPC85XX_PCI2
  490 + {},
491 491 #endif
492 492 };
493 493  
... ... @@ -497,7 +497,7 @@
497 497 pci_init_board(void)
498 498 {
499 499 #ifdef CONFIG_PCI
500   - extern void pci_mpc85xx_init(struct pci_controller *hose);
  500 + extern void pci_mpc85xx_init(struct pci_controller **hose);
501 501  
502 502 pci_mpc85xx_init(&hose);
503 503 #endif
board/cds/mpc8548cds/Makefile
Diff comments   View file @ 92c427b
... ... @@ -28,7 +28,9 @@
28 28  
29 29 OBJS := $(BOARD).o \
30 30 ../common/cadmus.o \
31   - ../common/eeprom.o
  31 + ../common/eeprom.o \
  32 + ../common/ft_board.o \
  33 + ../common/via.o
32 34  
33 35 SOBJS := init.o
34 36  
board/cds/mpc8548cds/init.S
Diff comments   View file @ 92c427b
... ... @@ -210,8 +210,8 @@
210 210 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
211 211 * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
212 212 * 0xe000_0000 0xe000_ffff CCSR 1M
213   - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
214   - * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
  213 + * 0xe200_0000 0xe20f_ffff PCI1 IO 1M
  214 + * 0xe210_0000 0xe21f_ffff PCI2 IO 1M
215 215 * 0xf000_0000 0xf7ff_ffff SDRAM 128M
216 216 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
217 217 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
218 218  
... ... @@ -234,11 +234,11 @@
234 234 #define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
235 235 #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
236 236  
237   -#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
238   -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
  237 +#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
  238 +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
239 239  
240   -#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff)
241   -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))
  240 +#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff)
  241 +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
242 242  
243 243 /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
244 244 #define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
board/cds/mpc8548cds/mpc8548cds.c
Diff comments   View file @ 92c427b
... ... @@ -30,6 +30,7 @@
30 30  
31 31 #include "../common/cadmus.h"
32 32 #include "../common/eeprom.h"
  33 +#include "../common/via.h"
33 34  
34 35 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
35 36 extern void ddr_enable_ecc(unsigned int dram_size);
36 37  
37 38  
38 39  
39 40  
40 41  
... ... @@ -293,26 +294,25 @@
293 294 #endif
294 295  
295 296 #if defined(CONFIG_PCI)
296   -
297   -/*
298   - * Initialize PCI Devices, report devices found.
  297 +/* For some reason the Tundra PCI bridge shows up on itself as a
  298 + * different device. Work around that by refusing to configure it.
299 299 */
  300 +void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
300 301  
301   -#ifndef CONFIG_PCI_PNP
302 302 static struct pci_config_table pci_mpc85xxcds_config_table[] = {
303   - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
304   - PCI_IDSEL_NUMBER, PCI_ANY_ID,
305   - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
306   - PCI_ENET0_MEMADDR,
307   - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
308   - } },
309   - { }
  303 + {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
  304 + {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
  305 + {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}},
  306 + {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
  307 + {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
  308 + {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}},
  309 + {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}
310 310 };
311   -#endif
312 311  
313   -static struct pci_controller hose = {
314   -#ifndef CONFIG_PCI_PNP
315   - config_table: pci_mpc85xxcds_config_table,
  312 +static struct pci_controller hose[] = {
  313 + { config_table: pci_mpc85xxcds_config_table,},
  314 +#ifdef CONFIG_MPC85XX_PCI2
  315 + {},
316 316 #endif
317 317 };
318 318  
... ... @@ -322,7 +322,7 @@
322 322 pci_init_board(void)
323 323 {
324 324 #ifdef CONFIG_PCI
325   - extern void pci_mpc85xx_init(struct pci_controller *hose);
  325 + extern void pci_mpc85xx_init(struct pci_controller **hose);
326 326  
327 327 pci_mpc85xx_init(&hose);
328 328 #endif
board/cds/mpc8555cds/Makefile
Diff comments   View file @ 92c427b
... ... @@ -28,7 +28,9 @@
28 28  
29 29 OBJS := $(BOARD).o \
30 30 ../common/cadmus.o \
31   - ../common/eeprom.o
  31 + ../common/eeprom.o \
  32 + ../common/ft_board.o \
  33 + ../common/via.o
32 34  
33 35 SOBJS := init.o
34 36  
board/cds/mpc8555cds/init.S
Diff comments   View file @ 92c427b
... ... @@ -210,8 +210,8 @@
210 210 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
211 211 * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
212 212 * 0xe000_0000 0xe000_ffff CCSR 1M
213   - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
214   - * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
  213 + * 0xe200_0000 0xe20f_ffff PCI1 IO 1M
  214 + * 0xe210_0000 0xe21f_ffff PCI2 IO 1M
215 215 * 0xf000_0000 0xf7ff_ffff SDRAM 128M
216 216 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
217 217 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
218 218  
... ... @@ -234,11 +234,11 @@
234 234 #define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
235 235 #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
236 236  
237   -#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
238   -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
  237 +#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
  238 +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
239 239  
240   -#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff)
241   -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))
  240 +#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff)
  241 +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
242 242  
243 243 /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
244 244 #define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
board/cds/mpc8555cds/mpc8555cds.c
Diff comments   View file @ 92c427b
... ... @@ -29,6 +29,7 @@
29 29  
30 30 #include "../common/cadmus.h"
31 31 #include "../common/eeprom.h"
  32 +#include "../common/via.h"
32 33  
33 34 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
34 35 extern void ddr_enable_ecc(unsigned int dram_size);
35 36  
36 37  
37 38  
38 39  
39 40  
40 41  
41 42  
... ... @@ -464,31 +465,33 @@
464 465 }
465 466 #endif
466 467  
467   -#if defined(CONFIG_PCI)
468   -
469   -/*
470   - * Initialize PCI Devices, report devices found.
  468 +#ifdef CONFIG_PCI
  469 +/* For some reason the Tundra PCI bridge shows up on itself as a
  470 + * different device. Work around that by refusing to configure it
471 471 */
  472 +void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
472 473  
473   -#ifndef CONFIG_PCI_PNP
474 474 static struct pci_config_table pci_mpc85xxcds_config_table[] = {
475   - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
476   - PCI_IDSEL_NUMBER, PCI_ANY_ID,
477   - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
478   - PCI_ENET0_MEMADDR,
479   - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
480   - } },
481   - { }
  475 + {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
  476 + {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
  477 + {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}},
  478 + {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
  479 + {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
  480 + {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}},
  481 + {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}
482 482 };
483   -#endif
484 483  
485   -static struct pci_controller hose = {
486   -#ifndef CONFIG_PCI_PNP
  484 +
  485 +static struct pci_controller hose[] = {
  486 + {
487 487 config_table: pci_mpc85xxcds_config_table,
  488 + },
  489 +#ifdef CONFIG_MPC85XX_PCI2
  490 + { }
488 491 #endif
489 492 };
490 493  
491   -#endif /* CONFIG_PCI */
  494 +#endif
492 495  
493 496 void
494 497 pci_init_board(void)
... ... @@ -496,7 +499,7 @@
496 499 #ifdef CONFIG_PCI
497 500 extern void pci_mpc85xx_init(struct pci_controller *hose);
498 501  
499   - pci_mpc85xx_init(&hose);
  502 + pci_mpc85xx_init(hose);
500 503 #endif
501 504 }
board/mpc8540ads/mpc8540ads.c
Diff comments   View file @ 92c427b
... ... @@ -31,6 +31,12 @@
31 31 #include <asm/immap_85xx.h>
32 32 #include <spd.h>
33 33  
  34 +#if defined(CONFIG_OF_FLAT_TREE)
  35 +#include <ft_build.h>
  36 +extern void ft_cpu_setup(void *blob, bd_t *bd);
  37 +#endif
  38 +
  39 +
34 40 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
35 41 extern void ddr_enable_ecc(unsigned int dram_size);
36 42 #endif
37 43  
38 44  
... ... @@ -311,25 +317,9 @@
311 317 * Initialize PCI Devices, report devices found.
312 318 */
313 319  
314   -#ifndef CONFIG_PCI_PNP
315   -static struct pci_config_table pci_mpc85xxads_config_table[] = {
316   - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
317   - PCI_IDSEL_NUMBER, PCI_ANY_ID,
318   - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
319   - PCI_ENET0_MEMADDR,
320   - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
321   - } },
322   - { }
323   -};
324   -#endif
325 320  
  321 +static struct pci_controller hose;
326 322  
327   -static struct pci_controller hose = {
328   -#ifndef CONFIG_PCI_PNP
329   - config_table: pci_mpc85xxads_config_table,
330   -#endif
331   -};
332   -
333 323 #endif /* CONFIG_PCI */
334 324  
335 325  
... ... @@ -342,4 +332,25 @@
342 332 pci_mpc85xx_init(&hose);
343 333 #endif /* CONFIG_PCI */
344 334 }
  335 +
  336 +
  337 +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
  338 +void
  339 +ft_board_setup(void *blob, bd_t *bd)
  340 +{
  341 + u32 *p;
  342 + int len;
  343 +
  344 +#ifdef CONFIG_PCI
  345 + ft_pci_setup(blob, bd);
  346 +#endif
  347 + ft_cpu_setup(blob, bd);
  348 +
  349 + p = ft_get_prop(blob, "/memory/reg", &len);
  350 + if (p != NULL) {
  351 + *p++ = cpu_to_be32(bd->bi_memstart);
  352 + *p = cpu_to_be32(bd->bi_memsize);
  353 + }
  354 +}
  355 +#endif
board/mpc8560ads/mpc8560ads.c
Diff comments   View file @ 92c427b
... ... @@ -544,4 +544,13 @@
544 544 pci_mpc85xx_init(&hose);
545 545 #endif /* CONFIG_PCI */
546 546 }
  547 +
  548 +
  549 +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
  550 +void
  551 +ft_board_setup(void *blob, bd_t *bd)
  552 +{
  553 + ft_cpu_setup(blob, bd);
  554 +}
  555 +#endif
board/stxxtc/Makefile
Diff comments   View file @ 92c427b
... ... @@ -25,18 +25,10 @@
25 25  
26 26 LIB = lib$(BOARD).a
27 27  
28   -OBJS = $(BOARD).o oftree.o
  28 +OBJS = $(BOARD).o
29 29  
30 30 $(LIB): .depend $(OBJS)
31 31 $(AR) crv $@ $(OBJS)
32   -
33   -%.dtb: %.dts
34   - dtc -f -V 0x10 -I dts -O dtb $< >$@
35   -
36   -%.c: %.dtb
37   - xxd -i $< \
38   - | sed -e "s/^unsigned char/const unsigned char/g" \
39   - | sed -e "s/^unsigned int/const unsigned int/g" > $@
40 32  
41 33 #########################################################################
42 34  
board/stxxtc/oftree.dts
View file @ 92c427b
1   -/ {
2   - model = "STXXTC V1";
3   - compatible = "STXXTC";
4   - #address-cells = <2>;
5   - #size-cells = <2>;
6   -
7   - cpus {
8   - linux,phandle = <1>;
9   - #address-cells = <1>;
10   - #size-cells = <0>;
11   - PowerPC,MPC870@0 {
12   - linux,phandle = <3>;
13   - name = "PowerPC,MPC870";
14   - device_type = "cpu";
15   - reg = <0>;
16   - clock-frequency = <0>; /* place-holder for runtime fillup */
17   - timebase-frequency = <0>; /* dido */
18   - linux,boot-cpu;
19   - i-cache-size = <2000>;
20   - d-cache-size = <2000>;
21   - 32-bit;
22   - };
23   - };
24   -
25   - memory@0 {
26   - device_type = "memory";
27   - reg = <00000000 00000000 00000000 20000000>;
28   - };
29   -
30   - /* copy of the bd_t information (place-holders) */
31   - bd_t {
32   - memstart = <0>;
33   - memsize = <0>;
34   - flashstart = <0>;
35   - flashsize = <0>;
36   - flashoffset = <0>;
37   - sramstart = <0>;
38   - sramsize = <0>;
39   -
40   - immr_base = <0>;
41   -
42   - bootflags = <0>;
43   - ip_addr = <0>;
44   - enetaddr = [ 00 00 00 00 00 00 ];
45   - ethspeed = <0>;
46   - intfreq = <0>;
47   - busfreq = <0>;
48   -
49   - baudrate = <0>;
50   - };
51   -
52   -};
... ... @@ -465,6 +465,13 @@
465 465 "[addr [arg ...]]\n - boot application image stored in memory\n"
466 466 "\tpassing arguments 'arg ...'; when booting a Linux kernel,\n"
467 467 "\t'arg' can be the address of an initrd image\n"
  468 +#ifdef CONFIG_OF_FLAT_TREE
  469 + "\tWhen booting a Linux kernel which requires a flat device-tree\n"
  470 + "\ta third argument is required which is the address of the of the\n"
  471 + "\tdevice-tree blob. To boot that kernel without an initrd image,\n"
  472 + "\tuse a '-' for the second argument. If you do not pass a third\n"
  473 + "\ta bd_info struct will be passed instead\n"
  474 +#endif
468 475 );
469 476  
470 477 #ifdef CONFIG_SILENT_CONSOLE
... ... @@ -500,11 +507,6 @@
500 507 }
501 508 #endif /* CONFIG_SILENT_CONSOLE */
502 509  
503   -#ifdef CONFIG_OF_FLAT_TREE
504   -extern const unsigned char oftree_dtb[];
505   -extern const unsigned int oftree_dtb_len;
506   -#endif
507   -
508 510 #ifdef CONFIG_PPC
509 511 static void
510 512 do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
511 513  
... ... @@ -616,7 +618,17 @@
616 618 /*
617 619 * Check if there is an initrd image
618 620 */
  621 +
  622 +#ifdef CONFIG_OF_FLAT_TREE
  623 + /* Look for a '-' which indicates to ignore the ramdisk argument */
  624 + if (argc >= 3 && strcmp(argv[2], "-") == 0) {
  625 + debug ("Skipping initrd\n");
  626 + data = 0;
  627 + }
  628 + else
  629 +#endif
619 630 if (argc >= 3) {
  631 + debug ("Not skipping initrd\n");
620 632 SHOW_BOOT_PROGRESS (9);
621 633  
622 634 addr = simple_strtoul(argv[2], NULL, 16);
... ... @@ -724,6 +736,15 @@
724 736 len = data = 0;
725 737 }
726 738  
  739 +#ifdef CONFIG_OF_FLAT_TREE
  740 + if (argc >= 3)
  741 + {
  742 + of_flat_tree = (char *) simple_strtoul(argv[3], NULL, 16);
  743 + printf ("Booting using flat device tree at 0x%x\n",
  744 + of_flat_tree);
  745 + }
  746 +#endif
  747 +
727 748 if (!data) {
728 749 debug ("No initrd\n");
729 750 }
... ... @@ -793,15 +814,6 @@
793 814 initrd_end = 0;
794 815 }
795 816  
796   -#ifdef CONFIG_OF_FLAT_TREE
797   - if (initrd_start == 0)
798   - of_flat_tree = (char *)(((ulong)kbd - OF_FLAT_TREE_MAX_SIZE -
799   - sizeof(bd_t)) & ~0xF);
800   - else
801   - of_flat_tree = (char *)((initrd_start - OF_FLAT_TREE_MAX_SIZE -
802   - sizeof(bd_t)) & ~0xF);
803   -#endif
804   -
805 817 debug ("## Transferring control to Linux (at address %08lx) ...\n",
806 818 (ulong)kernel);
807 819  
... ... @@ -824,7 +836,7 @@
824 836 (*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end);
825 837  
826 838 #else
827   - ft_setup(of_flat_tree, OF_FLAT_TREE_MAX_SIZE, kbd, initrd_start, initrd_end);
  839 + ft_setup(of_flat_tree, kbd, initrd_start, initrd_end);
828 840 /* ft_dump_blob(of_flat_tree); */
829 841  
830 842 #if defined(CFG_INIT_RAM_LOCK) && (!defined(CONFIG_E500)||!defined(CONFIG_MPC86xx))
1 1 /*
2 2 * OF flat tree builder
  3 + * Written by: Pantelis Antoniou <pantelis.antoniou@gmail.com>
  4 + * Updated by: Matthew McClintock <msm@freescale.com>
  5 + *
  6 + * This program is free software; you can redistribute it and/or
  7 + * modify it under the terms of the GNU General Public License as
  8 + * published by the Free Software Foundation; either version 2 of
  9 + * the License, or (at your option) any later version.
  10 + *
  11 + * This program is distributed in the hope that it will be useful,
  12 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14 + * GNU General Public License for more details.
  15 + *
  16 + * You should have received a copy of the GNU General Public License
  17 + * along with this program; if not, write to the Free Software
  18 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19 + * MA 02111-1307 USA
3 20 */
4 21  
5 22 #include <common.h>
6 23  
7 24  
8 25  
9 26  
10 27  
11 28  
12 29  
13 30  
14 31  
... ... @@ -13,44 +30,39 @@
13 30  
14 31 #include <ft_build.h>
15 32  
  33 +#undef DEBUG
  34 +
16 35 /* align addr on a size boundary - adjust address up if needed -- Cort */
17 36 #define _ALIGN(addr,size) (((addr)+(size)-1)&(~((size)-1)))
  37 +#ifndef CONFIG_OF_BOOT_CPU
  38 +#define CONFIG_OF_BOOT_CPU 0
  39 +#endif
  40 +#define SIZE_OF_RSVMAP_ENTRY (2*sizeof(u64))
18 41  
19 42 static void ft_put_word(struct ft_cxt *cxt, u32 v)
20 43 {
21   - if (cxt->overflow) /* do nothing */
22   - return;
  44 + memmove(cxt->p + sizeof(u32), cxt->p, cxt->p_end - cxt->p);
23 45  
24   - /* check for overflow */
25   - if (cxt->p + 4 > cxt->pstr) {
26   - cxt->overflow = 1;
27   - return;
28   - }
29   -
30 46 *(u32 *) cxt->p = cpu_to_be32(v);
31   - cxt->p += 4;
  47 + cxt->p += sizeof(u32);
  48 + cxt->p_end += sizeof(u32);
32 49 }
33 50  
34 51 static inline void ft_put_bin(struct ft_cxt *cxt, const void *data, int sz)
35 52 {
36   - u8 *p;
  53 + int aligned_size = ((u8 *)_ALIGN((unsigned long)cxt->p + sz,
  54 + sizeof(u32))) - cxt->p;
37 55  
38   - if (cxt->overflow) /* do nothing */
39   - return;
  56 + memmove(cxt->p + aligned_size, cxt->p, cxt->p_end - cxt->p);
40 57  
41   - /* next pointer pos */
42   - p = (u8 *) _ALIGN((unsigned long)cxt->p + sz, 4);
  58 + /* make sure the last bytes are zeroed */
  59 + memset(cxt->p + aligned_size - (aligned_size % sizeof(u32)), 0,
  60 + (aligned_size % sizeof(u32)));
43 61  
44   - /* check for overflow */
45   - if (p > cxt->pstr) {
46   - cxt->overflow = 1;
47   - return;
48   - }
49   -
50 62 memcpy(cxt->p, data, sz);
51   - if ((sz & 3) != 0)
52   - memset(cxt->p + sz, 0, 4 - (sz & 3));
53   - cxt->p = p;
  63 +
  64 + cxt->p += aligned_size;
  65 + cxt->p_end += aligned_size;
54 66 }
55 67  
56 68 void ft_begin_node(struct ft_cxt *cxt, const char *name)
57 69  
... ... @@ -73,10 +85,10 @@
73 85 {
74 86 u8 *p;
75 87  
76   - p = cxt->pstr;
77   - while (p < cxt->pstr_begin) {
  88 + p = cxt->p;
  89 + while (p < cxt->p_end) {
78 90 if (strcmp(p, name) == 0)
79   - return p - cxt->p_begin;
  91 + return p - cxt->p;
80 92 p += strlen(p) + 1;
81 93 }
82 94  
83 95  
84 96  
... ... @@ -85,24 +97,13 @@
85 97  
86 98 void ft_prop(struct ft_cxt *cxt, const char *name, const void *data, int sz)
87 99 {
88   - int len, off;
  100 + int off = 0;
89 101  
90   - if (cxt->overflow)
91   - return;
92   -
93   - len = strlen(name) + 1;
94   -
95 102 off = lookup_string(cxt, name);
96 103 if (off == -1) {
97   - /* check if we have space */
98   - if (cxt->p + 12 + sz + len > cxt->pstr) {
99   - cxt->overflow = 1;
100   - return;
101   - }
102   -
103   - cxt->pstr -= len;
104   - memcpy(cxt->pstr, name, len);
105   - off = cxt->pstr - cxt->p_begin;
  104 + memcpy(cxt->p_end, name, strlen(name) + 1);
  105 + off = cxt->p_end - cxt->p;
  106 + cxt->p_end += strlen(name) + 2;
106 107 }
107 108  
108 109 /* now put offset from beginning of *STRUCTURE* */
109 110  
110 111  
111 112  
112 113  
113 114  
114 115  
115 116  
116 117  
117 118  
118 119  
119 120  
120 121  
121 122  
122 123  
123 124  
124 125  
... ... @@ -122,138 +123,63 @@
122 123 {
123 124 u32 v = cpu_to_be32((u32) val);
124 125  
125   - ft_prop(cxt, name, &v, 4);
  126 + ft_prop(cxt, name, &v, sizeof(u32));
126 127 }
127 128  
128   -/* start construction of the flat OF tree */
129   -void ft_begin(struct ft_cxt *cxt, void *blob, int max_size)
  129 +/* pick up and start working on a tree in place */
  130 +void ft_init_cxt(struct ft_cxt *cxt, void *blob)
130 131 {
131 132 struct boot_param_header *bph = blob;
132   - u32 off;
133 133  
134   - /* clear the cxt */
135 134 memset(cxt, 0, sizeof(*cxt));
136 135  
137 136 cxt->bph = bph;
138   - cxt->max_size = max_size;
  137 + bph->boot_cpuid_phys = CONFIG_OF_BOOT_CPU;
139 138  
140   - /* zero everything in the header area */
141   - memset(bph, 0, sizeof(*bph));
  139 + /* find beginning and end of reserve map table (zeros in last entry) */
  140 + cxt->p_rsvmap = (u8 *)bph + bph->off_mem_rsvmap;
  141 + while ( ((uint64_t *)cxt->p_rsvmap)[0] != 0 &&
  142 + ((uint64_t *)cxt->p_rsvmap)[1] != 0 ) {
  143 + cxt->p_rsvmap += SIZE_OF_RSVMAP_ENTRY;
  144 + }
142 145  
143   - bph->magic = cpu_to_be32(OF_DT_HEADER);
144   - bph->version = cpu_to_be32(0x10);
145   - bph->last_comp_version = cpu_to_be32(0x10);
146   -
147   - /* start pointers */
148   - cxt->pres_begin = (u8 *) _ALIGN((unsigned long)(bph + 1), 8);
149   - cxt->pres = cxt->pres_begin;
150   -
151   - off = (unsigned long)cxt->pres_begin - (unsigned long)bph;
152   - bph->off_mem_rsvmap = cpu_to_be32(off);
153   -
154   - ((u64 *) cxt->pres)[0] = 0; /* phys = 0, size = 0, terminate */
155   - ((u64 *) cxt->pres)[1] = 0;
156   -
157   - cxt->p_anchor = cxt->pres + 16; /* over the terminator */
  146 + cxt->p_start = (char*)bph + bph->off_dt_struct;
  147 + cxt->p_end = (char *)bph + bph->totalsize;
  148 + cxt->p = (char *)bph + bph->off_dt_strings;
158 149 }
159 150  
160 151 /* add a reserver physical area to the rsvmap */
161   -void ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size)
  152 +void ft_add_rsvmap(struct ft_cxt *cxt, u64 physstart, u64 physend)
162 153 {
163   - ((u64 *) cxt->pres)[0] = cpu_to_be64(physaddr); /* phys = 0, size = 0, terminate */
164   - ((u64 *) cxt->pres)[1] = cpu_to_be64(size);
  154 + memmove(cxt->p_rsvmap + SIZE_OF_RSVMAP_ENTRY, cxt->p_rsvmap,
  155 + cxt->p_end - cxt->p_rsvmap);
165 156  
166   - cxt->pres += 16; /* advance */
  157 + ((u64 *)cxt->p_rsvmap)[0] = cpu_to_be64(physstart);
  158 + ((u64 *)cxt->p_rsvmap)[1] = cpu_to_be64(physend);
  159 + ((u64 *)cxt->p_rsvmap)[2] = 0;
  160 + ((u64 *)cxt->p_rsvmap)[3] = 0;
167 161  
168   - ((u64 *) cxt->pres)[0] = 0; /* phys = 0, size = 0, terminate */
169   - ((u64 *) cxt->pres)[1] = 0;
170   -
171   - /* keep track of size */
172   - cxt->res_size = cxt->pres + 16 - cxt->pres_begin;
173   -
174   - cxt->p_anchor = cxt->pres + 16; /* over the terminator */
  162 + cxt->p_rsvmap += SIZE_OF_RSVMAP_ENTRY;
  163 + cxt->p_start += SIZE_OF_RSVMAP_ENTRY;
  164 + cxt->p += SIZE_OF_RSVMAP_ENTRY;
  165 + cxt->p_end += SIZE_OF_RSVMAP_ENTRY;
175 166 }
176 167  
177   -void ft_begin_tree(struct ft_cxt *cxt)
  168 +void ft_end_tree(struct ft_cxt *cxt)
178 169 {
179   - cxt->p_begin = cxt->p_anchor;
180   - cxt->pstr_begin = (char *)cxt->bph + cxt->max_size; /* point at the end */
181   -
182   - cxt->p = cxt->p_begin;
183   - cxt->pstr = cxt->pstr_begin;
  170 + ft_put_word(cxt, OF_DT_END);
184 171 }
185 172  
186   -int ft_end_tree(struct ft_cxt *cxt)
187   -{
  173 +/* update the boot param header with correct values */
  174 +void ft_finalize_tree(struct ft_cxt *cxt) {
188 175 struct boot_param_header *bph = cxt->bph;
189   - int off, sz, sz1;
190   - u32 tag, v;
191   - u8 *p;
192 176  
193   - ft_put_word(cxt, OF_DT_END);
194   -
195   - if (cxt->overflow)
196   - return -ENOMEM;
197   -
198   - /* size of the areas */
199   - cxt->struct_size = cxt->p - cxt->p_begin;
200   - cxt->strings_size = cxt->pstr_begin - cxt->pstr;
201   -
202   - /* the offset we must move */
203   - off = (cxt->pstr_begin - cxt->p_begin) - cxt->strings_size;
204   -
205   - /* the new strings start */
206   - cxt->pstr_begin = cxt->p_begin + cxt->struct_size;
207   -
208   - /* move the whole string area */
209   - memmove(cxt->pstr_begin, cxt->pstr, cxt->strings_size);
210   -
211   - /* now perform the fixup of the strings */
212   - p = cxt->p_begin;
213   - while ((tag = be32_to_cpu(*(u32 *) p)) != OF_DT_END) {
214   - p += 4;
215   -
216   - if (tag == OF_DT_BEGIN_NODE) {
217   - p = (u8 *) _ALIGN((unsigned long)p + strlen(p) + 1, 4);
218   - continue;
219   - }
220   -
221   - if (tag == OF_DT_END_NODE || tag == OF_DT_NOP)
222   - continue;
223   -
224   - if (tag != OF_DT_PROP)
225   - return -EINVAL;
226   -
227   - sz = be32_to_cpu(*(u32 *) p);
228   - p += 4;
229   -
230   - v = be32_to_cpu(*(u32 *) p);
231   - v -= off;
232   - *(u32 *) p = cpu_to_be32(v); /* move down */
233   - p += 4;
234   -
235   - p = (u8 *) _ALIGN((unsigned long)p + sz, 4);
236   - }
237   -
238   - /* fix sizes */
239   - p = (char *)cxt->bph;
240   - sz = (cxt->pstr_begin + cxt->strings_size) - p;
241   - sz1 = _ALIGN(sz, 16); /* align at 16 bytes */
242   - if (sz != sz1)
243   - memset(p + sz, 0, sz1 - sz);
244   - bph->totalsize = cpu_to_be32(sz1);
245   - bph->off_dt_struct = cpu_to_be32(cxt->p_begin - p);
246   - bph->off_dt_strings = cpu_to_be32(cxt->pstr_begin - p);
247   -
248   - /* the new strings start */
249   - cxt->pstr_begin = cxt->p_begin + cxt->struct_size;
250   - cxt->pstr = cxt->pstr_begin + cxt->strings_size;
251   -
252   - return 0;
  177 + bph->totalsize = cxt->p_end - (u8 *)bph;
  178 + bph->off_dt_struct = cxt->p_start - (u8 *)bph;
  179 + bph->off_dt_strings = cxt->p - (u8 *)bph;
  180 + bph->dt_strings_size = cxt->p_end - cxt->p;
253 181 }
254 182  
255   -/**********************************************************************/
256   -
257 183 static inline int isprint(int c)
258 184 {
259 185 return c >= 0x20 && c <= 0x7e;
... ... @@ -381,8 +307,8 @@
381 307 }
382 308  
383 309 if (tag != OF_DT_PROP) {
384   - fprintf(stderr, "%*s ** Unknown tag 0x%08x\n",
385   - depth * shift, "", tag);
  310 + fprintf(stderr, "%*s ** Unknown tag 0x%08x at 0x%x\n",
  311 + depth * shift, "", tag, --p);
386 312 break;
387 313 }
388 314 sz = be32_to_cpu(*p++);
389 315  
390 316  
391 317  
... ... @@ -397,64 +323,15 @@
397 323  
398 324 void ft_backtrack_node(struct ft_cxt *cxt)
399 325 {
400   - if (be32_to_cpu(*(u32 *) (cxt->p - 4)) != OF_DT_END_NODE)
401   - return; /* XXX only for node */
  326 + int i = 4;
402 327  
403   - cxt->p -= 4;
404   -}
  328 + while (be32_to_cpu(*(u32 *) (cxt->p - i)) != OF_DT_END_NODE)
  329 + i += 4;
405 330  
406   -/* note that the root node of the blob is "peeled" off */
407   -void ft_merge_blob(struct ft_cxt *cxt, void *blob)
408   -{
409   - struct boot_param_header *bph = (struct boot_param_header *)blob;
410   - u32 *p_struct = (u32 *) ((char *)bph + be32_to_cpu(bph->off_dt_struct));
411   - u32 *p_strings =
412   - (u32 *) ((char *)bph + be32_to_cpu(bph->off_dt_strings));
413   - u32 tag, *p;
414   - char *s, *t;
415   - int depth, sz;
  331 + memmove (cxt->p - i, cxt->p, cxt->p_end - cxt->p);
416 332  
417   - if (be32_to_cpu(*(u32 *) (cxt->p - 4)) != OF_DT_END_NODE)
418   - return; /* XXX only for node */
419   -
420   - cxt->p -= 4;
421   -
422   - depth = 0;
423   - p = p_struct;
424   - while ((tag = be32_to_cpu(*p++)) != OF_DT_END) {
425   -
426   - /* printf("tag: 0x%08x (%d) - %d\n", tag, p - p_struct, depth); */
427   -
428   - if (tag == OF_DT_BEGIN_NODE) {
429   - s = (char *)p;
430   - p = (u32 *) _ALIGN((unsigned long)p + strlen(s) + 1, 4);
431   -
432   - if (depth++ > 0)
433   - ft_begin_node(cxt, s);
434   -
435   - continue;
436   - }
437   -
438   - if (tag == OF_DT_END_NODE) {
439   - ft_end_node(cxt);
440   - if (--depth == 0)
441   - break;
442   - continue;
443   - }
444   -
445   - if (tag == OF_DT_NOP)
446   - continue;
447   -
448   - if (tag != OF_DT_PROP)
449   - break;
450   -
451   - sz = be32_to_cpu(*p++);
452   - s = (char *)p_strings + be32_to_cpu(*p++);
453   - t = (char *)p;
454   - p = (u32 *) _ALIGN((unsigned long)p + sz, 4);
455   -
456   - ft_prop(cxt, s, t, sz);
457   - }
  333 + cxt->p_end -= i;
  334 + cxt->p -= i;
458 335 }
459 336  
460 337 void *ft_get_prop(void *bphp, const char *propname, int *szp)
... ... @@ -521,9 +398,6 @@
521 398  
522 399 /********************************************************************/
523 400  
524   -extern unsigned char oftree_dtb[];
525   -extern unsigned int oftree_dtb_len;
526   -
527 401 /* Function that returns a character from the environment */
528 402 extern uchar(*env_get_char) (int);
529 403  
... ... @@ -577,7 +451,7 @@
577 451 };
578 452 #endif
579 453  
580   -void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_end)
  454 +void ft_setup(void *blob, bd_t * bd, ulong initrd_start, ulong initrd_end)
581 455 {
582 456 u32 *p;
583 457 int len;
584 458  
585 459  
... ... @@ -600,20 +474,16 @@
600 474 return;
601 475 }
602 476  
603   - ft_begin(&cxt, blob, size);
  477 +#ifdef DEBUG
  478 + printf ("recieved oftree\n");
  479 + ft_dump_blob(blob);
  480 +#endif
604 481  
  482 + ft_init_cxt(&cxt, blob);
  483 +
605 484 if (initrd_start && initrd_end)
606 485 ft_add_rsvmap(&cxt, initrd_start, initrd_end - initrd_start + 1);
607 486  
608   - ft_begin_tree(&cxt);
609   -
610   - ft_begin_node(&cxt, "");
611   -
612   - ft_end_node(&cxt);
613   -
614   - /* copy RO tree */
615   - ft_merge_blob(&cxt, oftree_dtb);
616   -
617 487 /* back into root */
618 488 ft_backtrack_node(&cxt);
619 489  
620 490  
... ... @@ -642,8 +512,8 @@
642 512 #endif
643 513  
644 514 ft_begin_node(&cxt, "chosen");
645   -
646 515 ft_prop_str(&cxt, "name", "chosen");
  516 +
647 517 ft_prop_str(&cxt, "bootargs", getenv("bootargs"));
648 518 ft_prop_int(&cxt, "linux,platform", 0x600); /* what is this? */
649 519 if (initrd_start && initrd_end) {
650 520  
... ... @@ -659,12 +529,8 @@
659 529 ft_end_node(&cxt); /* end root */
660 530  
661 531 ft_end_tree(&cxt);
  532 + ft_finalize_tree(&cxt);
662 533  
663   - /*
664   - printf("merged OF-tree\n");
665   - ft_dump_blob(blob);
666   - */
667   -
668 534 #ifdef CONFIG_OF_HAS_BD_T
669 535 /* paste the bd_t at the end of the flat tree */
670 536 end = (char *)blob +
671 537  
672 538  
... ... @@ -712,12 +578,13 @@
712 578 ft_board_setup(blob, bd);
713 579 #endif
714 580  
715   - /*
716   - printf("final OF-tree\n");
717   - ft_dump_blob(blob);
718   - */
  581 + /* in case the size changed in the platform code */
  582 + ft_finalize_tree(&cxt);
719 583  
  584 +#ifdef DEBUG
  585 + printf("final OF-tree\n");
  586 + ft_dump_blob(blob);
  587 +#endif
720 588 }
721   -
722 589 #endif
... ... @@ -30,8 +30,11 @@
30 30 #include <command.h>
31 31 #include <asm/cache.h>
32 32  
33   -/* ------------------------------------------------------------------------- */
  33 +#if defined(CONFIG_OF_FLAT_TREE)
  34 +#include <ft_build.h>
  35 +#endif
34 36  
  37 +
35 38 int checkcpu (void)
36 39 {
37 40 sys_info_t sysinfo;
... ... @@ -225,6 +228,51 @@
225 228 dma->mr0 = 0xf000005;
226 229 asm("sync;isync;msync");
227 230 return dma_check();
  231 +}
  232 +#endif
  233 +
  234 +
  235 +#ifdef CONFIG_OF_FLAT_TREE
  236 +void
  237 +ft_cpu_setup(void *blob, bd_t *bd)
  238 +{
  239 + u32 *p;
  240 + ulong clock;
  241 + int len;
  242 +
  243 + clock = bd->bi_busfreq;
  244 + p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
  245 + if (p != NULL)
  246 + *p = cpu_to_be32(clock);
  247 +
  248 + p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
  249 + if (p != NULL)
  250 + *p = cpu_to_be32(clock);
  251 +
  252 + p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
  253 + if (p != NULL)
  254 + *p = cpu_to_be32(clock);
  255 +
  256 +#if defined(CONFIG_MPC85XX_TSEC1)
  257 + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
  258 + memcpy(p, bd->bi_enetaddr, 6);
  259 +#endif
  260 +
  261 +#if defined(CONFIG_HAS_ETH1)
  262 + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
  263 + memcpy(p, bd->bi_enet1addr, 6);
  264 +#endif
  265 +
  266 +#if defined(CONFIG_HAS_ETH2)
  267 + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len);
  268 + memcpy(p, bd->bi_enet2addr, 6);
  269 +#endif
  270 +
  271 +#if defined(CONFIG_HAS_ETH3)
  272 + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len);
  273 + memcpy(p, bd->bi_enet3addr, 6);
  274 +#endif
  275 +
228 276 }
229 277 #endif
cpu/mpc85xx/cpu_init.c
Diff comments   View file @ 92c427b
... ... @@ -32,6 +32,7 @@
32 32  
33 33 DECLARE_GLOBAL_DATA_PTR;
34 34  
  35 +
35 36 #ifdef CONFIG_CPM2
36 37 static void config_8560_ioports (volatile immap_t * immr)
37 38 {
... ... @@ -32,67 +32,94 @@
32 32  
33 33 #if defined(CONFIG_PCI)
34 34  
  35 +static struct pci_controller *pci_hose;
  36 +
35 37 void
36   -pci_mpc85xx_init(struct pci_controller *hose)
  38 +pci_mpc85xx_init(struct pci_controller *board_hose)
37 39 {
  40 + u16 reg16;
  41 + u32 dev;
  42 +
38 43 volatile immap_t *immap = (immap_t *)CFG_CCSRBAR;
39 44 volatile ccsr_pcix_t *pcix = &immap->im_pcix;
  45 + volatile ccsr_pcix_t *pcix2 = &immap->im_pcix2;
  46 + volatile ccsr_gur_t *gur = &immap->im_gur;
  47 + struct pci_controller * hose;
40 48  
41   - u16 reg16;
  49 + pci_hose = board_hose;
42 50  
  51 + hose = &pci_hose[0];
  52 +
43 53 hose->first_busno = 0;
44 54 hose->last_busno = 0xff;
45 55  
46   - pci_set_region(hose->regions + 0,
47   - CFG_PCI1_MEM_BASE,
48   - CFG_PCI1_MEM_PHYS,
49   - CFG_PCI1_MEM_SIZE,
50   - PCI_REGION_MEM);
51   -
52   - pci_set_region(hose->regions + 1,
53   - CFG_PCI1_IO_BASE,
54   - CFG_PCI1_IO_PHYS,
55   - CFG_PCI1_IO_SIZE,
56   - PCI_REGION_IO);
57   -
58   - hose->region_count = 2;
59   -
60 56 pci_setup_indirect(hose,
61 57 (CFG_IMMR+0x8000),
62 58 (CFG_IMMR+0x8004));
63 59  
  60 + /*
  61 + * Hose scan.
  62 + */
  63 + dev = PCI_BDF(hose->first_busno, 0, 0);
  64 + pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
  65 + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
  66 + pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
  67 +
  68 + /*
  69 + * Clear non-reserved bits in status register.
  70 + */
  71 + pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
  72 +
  73 + if (!(gur->pordevsr & PORDEVSR_PCI)) {
  74 + /* PCI-X init */
  75 + if (CONFIG_SYS_CLK_FREQ < 66000000)
  76 + printf("PCI-X will only work at 66 MHz\n");
  77 +
  78 + reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
  79 + | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
  80 + pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16);
  81 + }
  82 +
64 83 pcix->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
65 84 pcix->potear1 = 0x00000000;
66   - pcix->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
  85 + pcix->powbar1 = (CFG_PCI1_MEM_PHYS >> 12) & 0x000fffff;
67 86 pcix->powbear1 = 0x00000000;
68   - pcix->powar1 = 0x8004401c; /* 512M MEM space */
  87 + pcix->powar1 = (POWAR_EN | POWAR_MEM_READ |
  88 + POWAR_MEM_WRITE | POWAR_MEM_512M);
69 89  
70   - pcix->potar2 = 0x00000000;
  90 + pcix->potar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
71 91 pcix->potear2 = 0x00000000;
72   - pcix->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
  92 + pcix->powbar2 = (CFG_PCI1_IO_PHYS >> 12) & 0x000fffff;
73 93 pcix->powbear2 = 0x00000000;
74   - pcix->powar2 = 0x80088017; /* 16M IO space */
  94 + pcix->powar2 = (POWAR_EN | POWAR_IO_READ |
  95 + POWAR_IO_WRITE | POWAR_IO_1M);
75 96  
76 97 pcix->pitar1 = 0x00000000;
77 98 pcix->piwbar1 = 0x00000000;
78   - pcix->piwar1 = 0xa0f5501e; /* Enable, Prefetch, Local Mem,
79   - * Snoop R/W, 2G */
  99 + pcix->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
  100 + PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);
80 101  
81   - /*
82   - * Hose scan.
83   - */
84   - pci_register_hose(hose);
  102 + pcix->powar3 = 0;
  103 + pcix->powar4 = 0;
  104 + pcix->piwar2 = 0;
  105 + pcix->piwar3 = 0;
85 106  
86   - pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
87   - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
88   - pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
  107 + pci_set_region(hose->regions + 0,
  108 + CFG_PCI1_MEM_BASE,
  109 + CFG_PCI1_MEM_PHYS,
  110 + CFG_PCI1_MEM_SIZE,
  111 + PCI_REGION_MEM);
89 112  
90   - /*
91   - * Clear non-reserved bits in status register.
92   - */
93   - pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
94   - pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
  113 + pci_set_region(hose->regions + 1,
  114 + CFG_PCI1_IO_BASE,
  115 + CFG_PCI1_IO_PHYS,
  116 + CFG_PCI1_IO_SIZE,
  117 + PCI_REGION_IO);
95 118  
  119 + hose->region_count = 2;
  120 +
  121 + pci_register_hose(hose);
  122 +
96 123 #if defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8541CDS)
97 124 /*
98 125 * This is a SW workaround for an apparent HW problem
99 126  
... ... @@ -117,7 +144,95 @@
117 144 #endif
118 145  
119 146 hose->last_busno = pci_hose_scan(hose);
  147 +
  148 +#ifdef CONFIG_MPC85XX_PCI2
  149 + hose = &pci_hose[1];
  150 +
  151 + hose->first_busno = pci_hose[0].last_busno + 1;
  152 + hose->last_busno = 0xff;
  153 +
  154 + pci_setup_indirect(hose,
  155 + (CFG_IMMR+0x9000),
  156 + (CFG_IMMR+0x9004));
  157 +
  158 + dev = PCI_BDF(hose->first_busno, 0, 0);
  159 + pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
  160 + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
  161 + pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
  162 +
  163 + /*
  164 + * Clear non-reserved bits in status register.
  165 + */
  166 + pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
  167 +
  168 + pcix2->potar1 = (CFG_PCI2_MEM_BASE >> 12) & 0x000fffff;
  169 + pcix2->potear1 = 0x00000000;
  170 + pcix2->powbar1 = (CFG_PCI2_MEM_PHYS >> 12) & 0x000fffff;
  171 + pcix2->powbear1 = 0x00000000;
  172 + pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ |
  173 + POWAR_MEM_WRITE | POWAR_MEM_512M);
  174 +
  175 + pcix2->potar2 = (CFG_PCI2_IO_BASE >> 12) & 0x000fffff;
  176 + pcix2->potear2 = 0x00000000;
  177 + pcix2->powbar2 = (CFG_PCI2_IO_PHYS >> 12) & 0x000fffff;
  178 + pcix2->powbear2 = 0x00000000;
  179 + pcix2->powar2 = (POWAR_EN | POWAR_IO_READ |
  180 + POWAR_IO_WRITE | POWAR_IO_1M);
  181 +
  182 + pcix2->pitar1 = 0x00000000;
  183 + pcix2->piwbar1 = 0x00000000;
  184 + pcix2->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
  185 + PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);
  186 +
  187 + pcix2->powar3 = 0;
  188 + pcix2->powar4 = 0;
  189 + pcix2->piwar2 = 0;
  190 + pcix2->piwar3 = 0;
  191 +
  192 + pci_set_region(hose->regions + 0,
  193 + CFG_PCI2_MEM_BASE,
  194 + CFG_PCI2_MEM_PHYS,
  195 + CFG_PCI2_MEM_SIZE,
  196 + PCI_REGION_MEM);
  197 +
  198 + pci_set_region(hose->regions + 1,
  199 + CFG_PCI2_IO_BASE,
  200 + CFG_PCI2_IO_PHYS,
  201 + CFG_PCI2_IO_SIZE,
  202 + PCI_REGION_IO);
  203 +
  204 + hose->region_count = 2;
  205 +
  206 + /*
  207 + * Hose scan.
  208 + */
  209 + pci_register_hose(hose);
  210 +
  211 + hose->last_busno = pci_hose_scan(hose);
  212 +#endif
120 213 }
121 214  
  215 +#ifdef CONFIG_OF_FLAT_TREE
  216 +void
  217 +ft_pci_setup(void *blob, bd_t *bd)
  218 +{
  219 + u32 *p;
  220 + int len;
  221 +
  222 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
  223 + if (p != NULL) {
  224 + p[0] = pci_hose[0].first_busno;
  225 + p[1] = pci_hose[0].last_busno;
  226 + }
  227 +
  228 +#ifdef CONFIG_MPC85XX_PCI2
  229 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@9000/bus-range", &len);
  230 + if (p != NULL) {
  231 + p[0] = pci_hose[1].first_busno;
  232 + p[1] = pci_hose[1].last_busno;
  233 + }
  234 +#endif
  235 +}
  236 +#endif /* CONFIG_OF_FLAT_TREE */
122 237 #endif /* CONFIG_PCI */
doc/README.mpc85xxads
Diff comments   View file @ 92c427b
... ... @@ -100,6 +100,9 @@
100 100 SW7[1:4] = 0101 = 5 => 5 x 66 = 330 CCB Sysclk
101 101 SW7[5:6] = 01 => 5:2 x 330 = 825 Core clock
102 102  
  103 + In order to use PCI-X (only in the first PCI slot. The one with
  104 + the RIO connector), you need to set SW1[4] (config) to 1 (off).
  105 + Also, configure the board to run PCI at 66 MHz.
103 106  
104 107 2. MEMORY MAP TO WORK WITH LINUX KERNEL
105 108  
... ... @@ -187,7 +187,7 @@
187 187 } else {
188 188 /* We don't support prefetchable memory for now, so disable */
189 189 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
190   - pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1000);
  190 + pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
191 191 }
192 192  
193 193 if (pci_io) {
include/asm-ppc/immap_85xx.h
Diff comments   View file @ 92c427b
... ... @@ -246,7 +246,6 @@
246 246  
247 247 /*
248 248 * PCI Registers(0x8000-0x9000)
249   - * Omitting Reserved(0x9000-0x2_0000)
250 249 */
251 250 typedef struct ccsr_pcix {
252 251 uint cfg_addr; /* 0x8000 - PCIX Configuration Address Register */
253 252  
... ... @@ -309,9 +308,27 @@
309 308 uint peextaddrcr; /* 0x8e14 - PCIX Error Extended Address Capture Register */
310 309 uint pedlcr; /* 0x8e18 - PCIX Error Data Low Capture Register */
311 310 uint pedhcr; /* 0x8e1c - PCIX Error Error Data High Capture Register */
312   - char res11[94688];
  311 + uint gas_timr; /* 0x8e20 - PCIX Gasket Timer Register */
  312 + char res11[476];
313 313 } ccsr_pcix_t;
314 314  
  315 +#define PCIX_COMMAND 0x62
  316 +#define POWAR_EN 0x80000000
  317 +#define POWAR_IO_READ 0x00080000
  318 +#define POWAR_MEM_READ 0x00040000
  319 +#define POWAR_IO_WRITE 0x00008000
  320 +#define POWAR_MEM_WRITE 0x00004000
  321 +#define POWAR_MEM_512M 0x0000001c
  322 +#define POWAR_IO_1M 0x00000013
  323 +
  324 +#define PIWAR_EN 0x80000000
  325 +#define PIWAR_PF 0x20000000
  326 +#define PIWAR_LOCAL 0x00f00000
  327 +#define PIWAR_READ_SNOOP 0x00050000
  328 +#define PIWAR_WRITE_SNOOP 0x00005000
  329 +#define PIWAR_MEM_2G 0x0000001e
  330 +
  331 +
315 332 /*
316 333 * L2 Cache Registers(0x2_0000-0x2_1000)
317 334 */
... ... @@ -1572,6 +1589,8 @@
1572 1589 char res15[61651];
1573 1590 } ccsr_gur_t;
1574 1591  
  1592 +#define PORDEVSR_PCI (0x00800000) /* PCI Mode */
  1593 +
1575 1594 typedef struct immap {
1576 1595 ccsr_local_ecm_t im_local_ecm;
1577 1596 ccsr_ddr_t im_ddr;
... ... @@ -1579,6 +1598,8 @@
1579 1598 ccsr_duart_t im_duart;
1580 1599 ccsr_lbc_t im_lbc;
1581 1600 ccsr_pcix_t im_pcix;
  1601 + ccsr_pcix_t im_pcix2;
  1602 + char reserved[90112];
1582 1603 ccsr_l2cache_t im_l2cache;
1583 1604 ccsr_dma_t im_dma;
1584 1605 ccsr_tsec_t im_tsec1;
include/configs/MPC8540ADS.h
Diff comments   View file @ 92c427b
... ... @@ -68,6 +68,10 @@
68 68 * The board, however, can run at 66MHz. In any event, this value
69 69 * must match the settings of some switches. Details can be found
70 70 * in the README.mpc85xxads.
  71 + *
  72 + * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to
  73 + * 33MHz to accommodate, based on a PCI pin.
  74 + * Note that PCI-X won't work at 33MHz.
71 75 */
72 76  
73 77 #ifndef CONFIG_SYS_CLK_FREQ
... ... @@ -293,6 +297,21 @@
293 297 #define CFG_PROMPT_HUSH_PS2 "> "
294 298 #endif
295 299  
  300 +/* pass open firmware flat tree */
  301 +#define CONFIG_OF_FLAT_TREE 1
  302 +#define CONFIG_OF_BOARD_SETUP 1
  303 +
  304 +/* maximum size of the flat tree (8K) */
  305 +#define OF_FLAT_TREE_MAX_SIZE 8192
  306 +
  307 +#define OF_CPU "PowerPC,8540@0"
  308 +#define OF_SOC "soc8540@e0000000"
  309 +#define OF_TBCLK (bd->bi_busfreq / 8)
  310 +#define OF_STDOUT_PATH "/soc8540@e0000000/serial@4500"
  311 +
  312 +#define CFG_64BIT_VSPRINTF 1
  313 +#define CFG_64BIT_STRTOUL 1
  314 +
296 315 /* I2C */
297 316 #define CONFIG_HARD_I2C /* I2C with hardware support*/
298 317 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
... ... @@ -312,9 +331,10 @@
312 331 #define CFG_PCI1_MEM_BASE 0x80000000
313 332 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
314 333 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
315   -#define CFG_PCI1_IO_BASE 0xe2000000
316   -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
317   -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
  334 +
  335 +#define CFG_PCI1_IO_BASE 0x0
  336 +#define CFG_PCI1_IO_PHYS 0xe2000000
  337 +#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */
318 338  
319 339 #if defined(CONFIG_PCI)
320 340  
include/configs/MPC8541CDS.h
Diff comments   View file @ 92c427b
... ... @@ -308,6 +308,18 @@
308 308 #define CFG_PROMPT_HUSH_PS2 "> "
309 309 #endif
310 310  
  311 +/* pass open firmware flat tree */
  312 +#define CONFIG_OF_FLAT_TREE 1
  313 +#define CONFIG_OF_BOARD_SETUP 1
  314 +
  315 +/* maximum size of the flat tree (8K) */
  316 +#define OF_FLAT_TREE_MAX_SIZE 8192
  317 +
  318 +#define OF_CPU "PowerPC,8541@0"
  319 +#define OF_SOC "soc8541@e0000000"
  320 +#define OF_TBCLK (bd->bi_busfreq / 8)
  321 +#define OF_STDOUT_PATH "/soc8541@e0000000/serial@4600"
  322 +
311 323 /* I2C */
312 324 #define CONFIG_HARD_I2C /* I2C with hardware support */
313 325 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
314 326  
315 327  
316 328  
... ... @@ -323,31 +335,26 @@
323 335 #define CFG_PCI1_MEM_BASE 0x80000000
324 336 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
325 337 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
326   -#define CFG_PCI1_IO_BASE 0xe2000000
327   -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
328   -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
  338 +#define CFG_PCI1_IO_BASE 0x00000000
  339 +#define CFG_PCI1_IO_PHYS 0xe2000000
  340 +#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */
329 341  
330 342 #define CFG_PCI2_MEM_BASE 0xa0000000
331 343 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
332 344 #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
333   -#define CFG_PCI2_IO_BASE 0xe3000000
334   -#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE
335   -#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
  345 +#define CFG_PCI2_IO_BASE 0x00000000
  346 +#define CFG_PCI2_IO_PHYS 0xe2100000
  347 +#define CFG_PCI2_IO_SIZE 0x100000 /* 1M */
336 348  
337 349  
338 350 #if defined(CONFIG_PCI)
339 351  
  352 +#define CONFIG_MPC85XX_PCI2
340 353 #define CONFIG_NET_MULTI
341 354 #define CONFIG_PCI_PNP /* do pci plug-and-play */
342 355  
343 356 #undef CONFIG_EEPRO100
344 357 #undef CONFIG_TULIP
345   -
346   -#if !defined(CONFIG_PCI_PNP)
347   - #define PCI_ENET0_IOADDR 0xe0000000
348   - #define PCI_ENET0_MEMADDR 0xe0000000
349   - #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/
350   -#endif
351 358  
352 359 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
353 360 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
include/configs/MPC8548CDS.h
Diff comments   View file @ 92c427b
... ... @@ -314,6 +314,18 @@
314 314 #define CFG_PROMPT_HUSH_PS2 "> "
315 315 #endif
316 316  
  317 +/* pass open firmware flat tree */
  318 +#define CONFIG_OF_FLAT_TREE 1
  319 +#define CONFIG_OF_BOARD_SETUP 1
  320 +
  321 +/* maximum size of the flat tree (8K) */
  322 +#define OF_FLAT_TREE_MAX_SIZE 8192
  323 +
  324 +#define OF_CPU "PowerPC,8548@0"
  325 +#define OF_SOC "soc8548@e0000000"
  326 +#define OF_TBCLK (bd->bi_busfreq / 8)
  327 +#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4600"
  328 +
317 329 /* I2C */
318 330 #define CONFIG_HARD_I2C /* I2C with hardware support */
319 331 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
320 332  
321 333  
322 334  
... ... @@ -329,32 +341,27 @@
329 341 #define CFG_PCI1_MEM_BASE 0x80000000
330 342 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
331 343 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
332   -#define CFG_PCI1_IO_BASE 0xe2000000
333   -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
334   -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
  344 +#define CFG_PCI1_IO_BASE 0x00000000
  345 +#define CFG_PCI1_IO_PHYS 0xe2000000
  346 +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
335 347  
336 348 #define CFG_PCI2_MEM_BASE 0xa0000000
337 349 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
338 350 #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
339   -#define CFG_PCI2_IO_BASE 0xe3000000
340   -#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE
341   -#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
  351 +#define CFG_PCI2_IO_BASE 0x00000000
  352 +#define CFG_PCI2_IO_PHYS 0xe2100000
  353 +#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
342 354  
343 355  
344 356 #if defined(CONFIG_PCI)
345 357  
346 358 #define CONFIG_NET_MULTI
347 359 #define CONFIG_PCI_PNP /* do pci plug-and-play */
  360 +#define CONFIG_85XX_PCI2
348 361  
349 362 #undef CONFIG_EEPRO100
350 363 #undef CONFIG_TULIP
351 364  
352   -#if !defined(CONFIG_PCI_PNP)
353   - #define PCI_ENET0_IOADDR 0xe0000000
354   - #define PCI_ENET0_MEMADDR 0xe0000000
355   - #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/
356   -#endif
357   -
358 365 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
359 366 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
360 367  
... ... @@ -374,7 +381,7 @@
374 381 #define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1"
375 382 #define CONFIG_MPC85XX_TSEC3 1
376 383 #define CONFIG_MPC85XX_TSEC3_NAME "eTSEC2"
377   -#define CONFIG_MPC85XX_TSEC4 1
  384 +#undef CONFIG_MPC85XX_TSEC4
378 385 #define CONFIG_MPC85XX_TSEC4_NAME "eTSEC3"
379 386 #undef CONFIG_MPC85XX_FEC
380 387  
include/configs/MPC8555CDS.h
Diff comments   View file @ 92c427b
... ... @@ -308,6 +308,18 @@
308 308 #define CFG_PROMPT_HUSH_PS2 "> "
309 309 #endif
310 310  
  311 +/* pass open firmware flat tree */
  312 +#define CONFIG_OF_FLAT_TREE 1
  313 +#define CONFIG_OF_BOARD_SETUP 1
  314 +
  315 +/* maximum size of the flat tree (8K) */
  316 +#define OF_FLAT_TREE_MAX_SIZE 8192
  317 +
  318 +#define OF_CPU "PowerPC,8555@0"
  319 +#define OF_SOC "soc8555@e0000000"
  320 +#define OF_TBCLK (bd->bi_busfreq / 8)
  321 +#define OF_STDOUT_PATH "/soc8555@e0000000/serial@4600"
  322 +
311 323 /* I2C */
312 324 #define CONFIG_HARD_I2C /* I2C with hardware support */
313 325 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
314 326  
315 327  
316 328  
... ... @@ -323,33 +335,28 @@
323 335 #define CFG_PCI1_MEM_BASE 0x80000000
324 336 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
325 337 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
326   -#define CFG_PCI1_IO_BASE 0xe2000000
327   -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
328   -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
  338 +#define CFG_PCI1_IO_BASE 0x00000000
  339 +#define CFG_PCI1_IO_PHYS 0xe2000000
  340 +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
329 341  
330 342 #define CFG_PCI2_MEM_BASE 0xa0000000
331 343 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
332 344 #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
333   -#define CFG_PCI2_IO_BASE 0xe3000000
334   -#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE
335   -#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
  345 +#define CFG_PCI2_IO_BASE 0x00000000
  346 +#define CFG_PCI2_IO_PHYS 0xe2100000
  347 +#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
336 348  
337 349  
338 350 #if defined(CONFIG_PCI)
339 351  
340 352 #define CONFIG_NET_MULTI
341 353 #define CONFIG_PCI_PNP /* do pci plug-and-play */
  354 +#define CONFIG_MPC85XX_PCI2
342 355  
343 356 #undef CONFIG_EEPRO100
344 357 #undef CONFIG_TULIP
345 358  
346   -#if !defined(CONFIG_PCI_PNP)
347   - #define PCI_ENET0_IOADDR 0xe0000000
348   - #define PCI_ENET0_MEMADDR 0xe0000000
349   - #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/
350   -#endif
351   -
352   -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  359 +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
353 360 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
354 361  
355 362 #endif /* CONFIG_PCI */
include/configs/MPC8560ADS.h
Diff comments   View file @ 92c427b
... ... @@ -290,6 +290,18 @@
290 290 #define CFG_PROMPT_HUSH_PS2 "> "
291 291 #endif
292 292  
  293 +/* pass open firmware flat tree */
  294 +#define CONFIG_OF_FLAT_TREE 1
  295 +#define CONFIG_OF_BOARD_SETUP 1
  296 +
  297 +/* maximum size of the flat tree (8K) */
  298 +#define OF_FLAT_TREE_MAX_SIZE 8192
  299 +
  300 +#define OF_CPU "PowerPC,8560@0"
  301 +#define OF_SOC "soc8560@e0000000"
  302 +#define OF_TBCLK (bd->bi_busfreq / 8)
  303 +#define OF_STDOUT_PATH "/soc8560@e0000000/serial@4500"
  304 +
293 305 /* I2C */
294 306 #define CONFIG_HARD_I2C /* I2C with hardware support*/
295 307 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
... ... @@ -36,19 +36,18 @@
36 36  
37 37 struct ft_cxt {
38 38 struct boot_param_header *bph;
39   - int max_size; /* maximum size of tree */
40   - int overflow; /* set when this happens */
41   - u8 *p, *pstr, *pres; /* running pointers */
42   - u8 *p_begin, *pstr_begin, *pres_begin; /* starting pointers */
43   - u8 *p_anchor; /* start of constructed area */
44   - int struct_size, strings_size, res_size;
  39 + u8 *p_rsvmap;
  40 + u8 *p_start; /* pointer to beginning of dt_struct */
  41 + u8 *p_end; /* pointer to end of dt_strings */
  42 + u8 *p; /* pointer to end of dt_struct and beginning of dt_strings */
45 43 };
46 44  
47 45 void ft_begin_node(struct ft_cxt *cxt, const char *name);
  46 +void ft_init_cxt(struct ft_cxt *cxt, void *blob);
48 47 void ft_end_node(struct ft_cxt *cxt);
49 48  
50   -void ft_begin_tree(struct ft_cxt *cxt);
51   -int ft_end_tree(struct ft_cxt *cxt);
  49 +void ft_end_tree(struct ft_cxt *cxt);
  50 +void ft_finalize_tree(struct ft_cxt *cxt);
52 51  
53 52 void ft_nop(struct ft_cxt *cxt);
54 53 void ft_prop(struct ft_cxt *cxt, const char *name, const void *data, int sz);
55 54  
56 55  
... ... @@ -57,15 +56,15 @@
57 56 void ft_begin(struct ft_cxt *cxt, void *blob, int max_size);
58 57 void ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size);
59 58  
60   -void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_end);
61   -#ifdef CONFIG_OF_BOARD_SETUP
62   -void ft_board_setup(void *blob, bd_t *bd);
63   -#endif
  59 +void ft_setup(void *blob, bd_t * bd, ulong initrd_start, ulong initrd_end);
  60 +
64 61 void ft_dump_blob(const void *bphp);
65 62 void ft_merge_blob(struct ft_cxt *cxt, void *blob);
66 63 void *ft_get_prop(void *bphp, const char *propname, int *szp);
67 64  
  65 +#ifdef CONFIG_OF_BOARD_SETUP
68 66 void ft_board_setup(void *blob, bd_t *bd);
  67 +#endif
69 68  
70 69 #endif
... ... @@ -271,10 +271,13 @@
271 271 #define PCI_AGP_SIZEOF 12
272 272  
273 273 /* PCI-X registers */
274   -#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */+#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
  274 +
  275 +#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
  276 +#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
275 277 #define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */
276 278 #define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */
277 279 #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
  280 +
278 281  
279 282 /* Slot Identification */
280 283