ppc4xx: Add initial 460SX reference board (redwood) config file and defines.

Signed-off-by: Feng Kan <fkan@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>

ppc4xx: Add initial 460SX reference board (redwood) config file and defines.
Signed-off-by: Feng Kan <fkan@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
Feng Kan · Stefan Roese
1 parent 7d30793685
Showing 5 changed files with 207 additions and 9 deletions Side-by-side Diff
include/asm-ppc/ppc4xx-sdram.h
include/asm-ppc/processor.h
include/configs/redwood.h
include/ppc440.h
include/ppc4xx.h
@@ -282,7 +282,8 @@
  * Memory Bank 0-7 configuration
  */
 #if defined(CONFIG_440SPE) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_460SX)
 #define SDRAM_RXBAS_SDBA_MASK		0xFFE00000	/* Base address	*/
 #define SDRAM_RXBAS_SDBA_ENCODE(n)	((u32)(((phys_size_t)(n) >> 2) & 0xFFE00000))
 #define SDRAM_RXBAS_SDBA_DECODE(n)	((((phys_size_t)(n)) & 0xFFE00000) << 2)
@@ -810,6 +810,10 @@
 #define PVR_460EX_RA	0x130218A3 /* 460EX rev A without Security Engine */
 #define PVR_460GT_SE_RA	0x130218A0 /* 460GT rev A with Security Engine	  */
 #define PVR_460GT_RA	0x130218A1 /* 460GT rev A without Security Engine */
+#define PVR_460SX_RA    0x13541800 /* 460SX rev A                   */
+#define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */
+#define PVR_460GX_RA    0x13541802 /* 460GX rev A                   */
+#define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */
 #define PVR_601		0x00010000
 #define PVR_602		0x00050000
 #define PVR_603		0x00030000
+/*
+ * Configuration for AMCC 460SX Ref (redwood)
+ *
+ * (C) Copyright 2008
+ * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_4xx			1	/* ... PPC4xx family	*/
+#define CONFIG_440			1	/* ... PPC460 family	*/
+#define CONFIG_460SX			1	/* ... PPC460 family	*/
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init	*/
+
+/*-----------------------------------------------------------------------
+ * Include common defines/options for all AMCC boards
+ *----------------------------------------------------------------------*/
+#define CONFIG_HOSTNAME		redwood
+
+#include "amcc-common.h"
+
+#define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll	*/
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_BASE		0xfff00000	/* start of FLASH	*/
+#define CFG_PERIPHERAL_BASE	0xa0000000	/* internal peripherals	*/
+#define CFG_ISRAM_BASE		0x90000000	/* internal SRAM	*/
+
+#define CFG_PCI_BASE		0xd0000000	/* internal PCI regs	*/
+
+#define CFG_PCIE_MEMBASE        0x90000000      /* mapped PCIe memory   */
+#define CFG_PCIE0_MEMBASE       0x90000000      /* mapped PCIe memory   */
+#define CFG_PCIE1_MEMBASE       0xa0000000      /* mapped PCIe memory   */
+#define CFG_PCIE_MEMSIZE        0x01000000
+
+#define CFG_PCIE0_XCFGBASE      0xb0000000
+#define CFG_PCIE1_XCFGBASE      0xb2000000
+#define CFG_PCIE2_XCFGBASE      0xb4000000
+#define CFG_PCIE0_CFGBASE       0xb6000000
+#define CFG_PCIE1_CFGBASE       0xb8000000
+#define CFG_PCIE2_CFGBASE       0xba000000
+
+/* PCIe mapped UTL registers */
+#define CFG_PCIE0_REGBASE   0xd0000000
+#define CFG_PCIE1_REGBASE   0xd0010000
+#define CFG_PCIE2_REGBASE   0xd0020000
+
+/* System RAM mapped to PCI space */
+#define CONFIG_PCI_SYS_MEM_BUS	CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS	CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_SIZE	(1024 * 1024 * 1024)
+
+#define CFG_FPGA_BASE		0xe2000000	/* epld			*/
+#define CFG_OPER_FLASH		0xe7000000	/* SRAM - OPER Flash	*/
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_TEMP_STACK_OCM	1
+#define CFG_OCM_DATA_ADDR	CFG_ISRAM_BASE
+#define CFG_INIT_RAM_ADDR	CFG_ISRAM_BASE	/* Initial RAM address	*/
+#define CFG_INIT_RAM_END	0x2000		/* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
+
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 0x4)
+#define CFG_INIT_SP_OFFSET	CFG_POST_WORD_ADDR
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SPD_EEPROM	1	/* Use SPD EEPROM for setup	*/
+#define CONFIG_DDR_ECC		1	/* with ECC support		*/
+
+#define CFG_SPD_MAX_DIMMS       2
+
+/* SPD i2c spd addresses */
+#define SPD_EEPROM_ADDRESS     {IIC0_DIMM0_ADDR, IIC0_DIMM1_ADDR}
+#define IIC0_DIMM0_ADDR                0x53
+#define IIC0_DIMM1_ADDR                0x52
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CFG_I2C_SPEED           400000  /* I2C speed                    */
+
+#define IIC0_BOOTPROM_ADDR	0x50
+#define IIC0_ALT_BOOTPROM_ADDR	0x54
+
+/* Don't probe these addrs */
+#define CFG_I2C_NOPROBES	{0x50, 0x52, 0x53, 0x54}
+
+#define CFG_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address		*/
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#undef  CFG_ENV_IS_IN_NVRAM		/* ... not in NVRAM		*/
+#define	CFG_ENV_IS_IN_FLASH	1	/* Environment uses flash	*/
+#undef	CFG_ENV_IS_IN_EEPROM		/* ... not in EEPROM		*/
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV                                             \
+        CONFIG_AMCC_DEF_ENV_POWERPC                                     \
+        CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
+        CONFIG_AMCC_DEF_ENV_NAND_UPD                                    \
+        "kernel_addr=fc000000\0"                                        \
+        "fdt_addr=fc1e0000\0"                                           \
+        "ramdisk_addr=fc200000\0"                                       \
+	""
+
+/*----------------------------------------------------------------------------+
+| Commands in addition to amcc-common.h
++----------------------------------------------------------------------------*/
+#define CONFIG_CMD_SDRAM
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define	CONFIG_IBM_EMAC4_V4	1
+#define CONFIG_PHY_RESET        1	/* reset phy upon startup	*/
+#define CONFIG_PHY_RESET_DELAY	1000
+#define CONFIG_M88E1141_PHY	1	/* Enable phy */
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_PHY_ADDR		0	/* PHY address, See schematics	*/
+#define CONFIG_PHY1_ADDR	1	/* PHY address, See schematics	*/
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_CFI                   /* The flash is CFI compatible  */
+#define CFG_FLASH_CFI_DRIVER            /* Use common CFI driver        */
+#define CFG_FLASH_CFI_AMD_RESET 1       /* Use AMD (Spansion) reset cmd */
+
+#define CFG_MAX_FLASH_BANKS	3	/* number of banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* sectors per device		*/
+
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE	0x10000	/* size of one complete sector	*/
+#define CFG_ENV_ADDR		0xfffa0000
+#define CFG_ENV_SIZE		0x10000	/* Size of Environment vars	*/
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+/*---------------------------------------------------------------------------*/
+
+#endif	/* __CONFIG_H */
@@ -749,7 +749,8 @@
  +----------------------------------------------------------------------------*/
 #if defined (CONFIG_440GX) || \
     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_460SX)
 #define L2_CACHE_BASE	0x030
 #define l2_cache_cfg	(L2_CACHE_BASE+0x00)	/* L2 Cache Config	*/
 #define l2_cache_cmd	(L2_CACHE_BASE+0x01)	/* L2 Cache Command	*/
@@ -837,7 +838,8 @@
 /*-----------------------------------------------------------------------------
  | Clocking, Power Management and Chip Control
  +----------------------------------------------------------------------------*/
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_460SX)
 #define CNTRL_DCR_BASE 0x160
 #else
 #define CNTRL_DCR_BASE 0x0b0
@@ -896,7 +898,8 @@
  
 #if defined(CONFIG_440SPE) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_460SX)
 #define UIC2_DCR_BASE 0xe0
 #define uic2sr	(UIC2_DCR_BASE+0x0)   /* UIC2 status-Read Clear		*/
 #define uic2srs	(UIC2_DCR_BASE+0x1)   /* UIC2 status-Read Set */
@@ -1608,7 +1611,8 @@
 #define UICB0_ALL	(UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \
 			 UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI)
  
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+      defined(CONFIG_460SX)
  
 #define UICB0_UIC1NCI	0x00000002	/* UIC1 Noncritical Interrupt	    */
 #define UICB0_UIC1CI	0x00000001	/* UIC1 Critical Interrupt	    */
@@ -1855,7 +1859,7 @@
 #define SDR0_DDR0_TUNE_DECODE(n)	((((unsigned long)(n))>>0)&0x2FF)
 #endif
  
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440SPE) || defined(CONFIG_460SX)
 #define SDR0_CP440			0x0180
 #define SDR0_CP440_ERPN_MASK		0x30000000
 #define SDR0_CP440_ERPN_MASK_HI		0x3000
@@ -2793,7 +2797,8 @@
 /*-----------------------------------------------------------------------------+
 |  Clocking
 +-----------------------------------------------------------------------------*/
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_460SX)
 #define PLLSYS0_FWD_DIV_A_MASK	0x000000f0	/* Fwd Div A */
 #define PLLSYS0_FWD_DIV_B_MASK	0x0000000f	/* Fwd Div B */
 #define PLLSYS0_FB_DIV_MASK	0x0000ff00	/* Feedback divisor */
@@ -3145,7 +3150,8 @@
  * GPIO macro register defines
  ******************************************************************************/
 #if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
-    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_460SX)
 #define GPIO0_BASE             (CFG_PERIPHERAL_BASE+0x00000700)
  
 #define GPIO0_OR               (GPIO0_BASE+0x0)
@@ -41,7 +41,8 @@
  
 #if defined(CONFIG_405EX) || \
     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_460SX)
 #define CONFIG_SDRAM_PPC4xx_IBM_DDR2	/* IBM DDR(2) controller */
 #endif
...	...	@@ -282,7 +282,8 @@
282	282	* Memory Bank 0-7 configuration
283	283	*/
284	284	#if defined(CONFIG_440SPE) \|\| \
285		- defined(CONFIG_460EX) \|\| defined(CONFIG_460GT)
	285	+ defined(CONFIG_460EX) \|\| defined(CONFIG_460GT) \|\| \
	286	+ defined(CONFIG_460SX)
286	287	#define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */
287	288	#define SDRAM_RXBAS_SDBA_ENCODE(n) ((u32)(((phys_size_t)(n) >> 2) & 0xFFE00000))
288	289	#define SDRAM_RXBAS_SDBA_DECODE(n) ((((phys_size_t)(n)) & 0xFFE00000) << 2)
...	...	@@ -810,6 +810,10 @@
810	810	#define PVR_460EX_RA 0x130218A3 /* 460EX rev A without Security Engine */
811	811	#define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */
812	812	#define PVR_460GT_RA 0x130218A1 /* 460GT rev A without Security Engine */
	813	+#define PVR_460SX_RA 0x13541800 /* 460SX rev A */
	814	+#define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */
	815	+#define PVR_460GX_RA 0x13541802 /* 460GX rev A */
	816	+#define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */
813	817	#define PVR_601 0x00010000
814	818	#define PVR_602 0x00050000
815	819	#define PVR_603 0x00030000
	1	+/*
	2	+ * Configuration for AMCC 460SX Ref (redwood)
	3	+ *
	4	+ * (C) Copyright 2008
	5	+ * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com
	6	+ *
	7	+ * See file CREDITS for list of people who contributed to this
	8	+ * project.
	9	+ *
	10	+ * This program is free software; you can redistribute it and/or
	11	+ * modify it under the terms of the GNU General Public License as
	12	+ * published by the Free Software Foundation; either version 2 of
	13	+ * the License, or (at your option) any later version.
	14	+ *
	15	+ * This program is distributed in the hope that it will be useful,
	16	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	+ * GNU General Public License for more details.
	19	+ *
	20	+ * You should have received a copy of the GNU General Public License
	21	+ * along with this program; if not, write to the Free Software
	22	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	+ * MA 02111-1307 USA
	24	+ */
	25	+#ifndef __CONFIG_H
	26	+#define __CONFIG_H
	27	+
	28	+/*-----------------------------------------------------------------------
	29	+ * High Level Configuration Options
	30	+ ----------------------------------------------------------------------/
	31	+#define CONFIG_4xx 1 /* ... PPC4xx family */
	32	+#define CONFIG_440 1 /* ... PPC460 family */
	33	+#define CONFIG_460SX 1 /* ... PPC460 family */
	34	+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
	35	+
	36	+/*-----------------------------------------------------------------------
	37	+ * Include common defines/options for all AMCC boards
	38	+ ----------------------------------------------------------------------/
	39	+#define CONFIG_HOSTNAME redwood
	40	+
	41	+#include "amcc-common.h"
	42	+
	43	+#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
	44	+
	45	+/*-----------------------------------------------------------------------
	46	+ * Base addresses -- Note these are effective addresses where the
	47	+ * actual resources get mapped (not physical addresses)
	48	+ ----------------------------------------------------------------------/
	49	+#define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */
	50	+#define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */
	51	+#define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */
	52	+
	53	+#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
	54	+
	55	+#define CFG_PCIE_MEMBASE 0x90000000 /* mapped PCIe memory */
	56	+#define CFG_PCIE0_MEMBASE 0x90000000 /* mapped PCIe memory */
	57	+#define CFG_PCIE1_MEMBASE 0xa0000000 /* mapped PCIe memory */
	58	+#define CFG_PCIE_MEMSIZE 0x01000000
	59	+
	60	+#define CFG_PCIE0_XCFGBASE 0xb0000000
	61	+#define CFG_PCIE1_XCFGBASE 0xb2000000
	62	+#define CFG_PCIE2_XCFGBASE 0xb4000000
	63	+#define CFG_PCIE0_CFGBASE 0xb6000000
	64	+#define CFG_PCIE1_CFGBASE 0xb8000000
	65	+#define CFG_PCIE2_CFGBASE 0xba000000
	66	+
	67	+/* PCIe mapped UTL registers */
	68	+#define CFG_PCIE0_REGBASE 0xd0000000
	69	+#define CFG_PCIE1_REGBASE 0xd0010000
	70	+#define CFG_PCIE2_REGBASE 0xd0020000
	71	+
	72	+/* System RAM mapped to PCI space */
	73	+#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
	74	+#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
	75	+#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
	76	+
	77	+#define CFG_FPGA_BASE 0xe2000000 /* epld */
	78	+#define CFG_OPER_FLASH 0xe7000000 /* SRAM - OPER Flash */
	79	+
	80	+/*-----------------------------------------------------------------------
	81	+ * Initial RAM & stack pointer (placed in internal SRAM)
	82	+ ----------------------------------------------------------------------/
	83	+#define CFG_TEMP_STACK_OCM 1
	84	+#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE
	85	+#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
	86	+#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
	87	+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
	88	+
	89	+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	90	+#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
	91	+#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
	92	+
	93	+/*-----------------------------------------------------------------------
	94	+ * DDR SDRAM
	95	+ ----------------------------------------------------------------------/
	96	+#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
	97	+#define CONFIG_DDR_ECC 1 /* with ECC support */
	98	+
	99	+#define CFG_SPD_MAX_DIMMS 2
	100	+
	101	+/* SPD i2c spd addresses */
	102	+#define SPD_EEPROM_ADDRESS {IIC0_DIMM0_ADDR, IIC0_DIMM1_ADDR}
	103	+#define IIC0_DIMM0_ADDR 0x53
	104	+#define IIC0_DIMM1_ADDR 0x52
	105	+
	106	+/*-----------------------------------------------------------------------
	107	+ * I2C
	108	+ ----------------------------------------------------------------------/
	109	+#define CFG_I2C_SPEED 400000 /* I2C speed */
	110	+
	111	+#define IIC0_BOOTPROM_ADDR 0x50
	112	+#define IIC0_ALT_BOOTPROM_ADDR 0x54
	113	+
	114	+/* Don't probe these addrs */
	115	+#define CFG_I2C_NOPROBES {0x50, 0x52, 0x53, 0x54}
	116	+
	117	+#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
	118	+
	119	+/*-----------------------------------------------------------------------
	120	+ * Environment
	121	+ ----------------------------------------------------------------------/
	122	+#undef CFG_ENV_IS_IN_NVRAM /* ... not in NVRAM */
	123	+#define CFG_ENV_IS_IN_FLASH 1 /* Environment uses flash */
	124	+#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
	125	+
	126	+#define CONFIG_PREBOOT "echo;" \
	127	+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	128	+ "echo"
	129	+
	130	+#undef CONFIG_BOOTARGS
	131	+
	132	+#define CONFIG_EXTRA_ENV_SETTINGS \
	133	+ CONFIG_AMCC_DEF_ENV \
	134	+ CONFIG_AMCC_DEF_ENV_POWERPC \
	135	+ CONFIG_AMCC_DEF_ENV_NOR_UPD \
	136	+ CONFIG_AMCC_DEF_ENV_NAND_UPD \
	137	+ "kernel_addr=fc000000\0" \
	138	+ "fdt_addr=fc1e0000\0" \
	139	+ "ramdisk_addr=fc200000\0" \
	140	+ ""
	141	+
	142	+/*----------------------------------------------------------------------------+
	143	+\| Commands in addition to amcc-common.h
	144	++----------------------------------------------------------------------------*/
	145	+#define CONFIG_CMD_SDRAM
	146	+
	147	+#define CONFIG_BOOTCOMMAND "run flash_self"
	148	+
	149	+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	150	+
	151	+#define CONFIG_IBM_EMAC4_V4 1
	152	+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
	153	+#define CONFIG_PHY_RESET_DELAY 1000
	154	+#define CONFIG_M88E1141_PHY 1 /* Enable phy */
	155	+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
	156	+
	157	+#define CONFIG_HAS_ETH0
	158	+#define CONFIG_HAS_ETH1
	159	+#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
	160	+#define CONFIG_PHY1_ADDR 1 /* PHY address, See schematics */
	161	+
	162	+#undef CONFIG_WATCHDOG /* watchdog disabled */
	163	+
	164	+/*-----------------------------------------------------------------------
	165	+ * FLASH related
	166	+ ----------------------------------------------------------------------/
	167	+#define CFG_FLASH_CFI /* The flash is CFI compatible */
	168	+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
	169	+#define CFG_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */
	170	+
	171	+#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
	172	+#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
	173	+
	174	+#undef CFG_FLASH_CHECKSUM
	175	+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	176	+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	177	+
	178	+#ifdef CFG_ENV_IS_IN_FLASH
	179	+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
	180	+#define CFG_ENV_ADDR 0xfffa0000
	181	+#define CFG_ENV_SIZE 0x10000 /* Size of Environment vars */
	182	+#endif /* CFG_ENV_IS_IN_FLASH */
	183	+
	184	+/---------------------------------------------------------------------------/
	185	+
	186	+#endif /* __CONFIG_H */
...	...	@@ -749,7 +749,8 @@
749	749	+----------------------------------------------------------------------------*/
750	750	#if defined (CONFIG_440GX) \|\| \
751	751	defined(CONFIG_440SP) \|\| defined(CONFIG_440SPE) \|\| \
752		- defined(CONFIG_460EX) \|\| defined(CONFIG_460GT)
	752	+ defined(CONFIG_460EX) \|\| defined(CONFIG_460GT) \|\| \
	753	+ defined(CONFIG_460SX)
753	754	#define L2_CACHE_BASE 0x030
754	755	#define l2_cache_cfg (L2_CACHE_BASE+0x00) /* L2 Cache Config */
755	756	#define l2_cache_cmd (L2_CACHE_BASE+0x01) /* L2 Cache Command */
...	...	@@ -837,7 +838,8 @@
837	838	/*-----------------------------------------------------------------------------
838	839	\| Clocking, Power Management and Chip Control
839	840	+----------------------------------------------------------------------------*/
840		-#if defined(CONFIG_460EX) \|\| defined(CONFIG_460GT)
	841	+#if defined(CONFIG_460EX) \|\| defined(CONFIG_460GT) \|\| \
	842	+ defined(CONFIG_460SX)
841	843	#define CNTRL_DCR_BASE 0x160
842	844	#else
843	845	#define CNTRL_DCR_BASE 0x0b0
...	...	@@ -896,7 +898,8 @@
896	898
897	899	#if defined(CONFIG_440SPE) \|\| \
898	900	defined(CONFIG_440EPX) \|\| defined(CONFIG_440GRX) \|\| \
899		- defined(CONFIG_460EX) \|\| defined(CONFIG_460GT)
	901	+ defined(CONFIG_460EX) \|\| defined(CONFIG_460GT) \|\| \
	902	+ defined(CONFIG_460SX)
900	903	#define UIC2_DCR_BASE 0xe0
901	904	#define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */
902	905	#define uic2srs (UIC2_DCR_BASE+0x1) /* UIC2 status-Read Set */
...	...	@@ -1608,7 +1611,8 @@
1608	1611	#define UICB0_ALL (UICB0_UIC0CI \| UICB0_UIC0NCI \| UICB0_UIC1CI \| \
1609	1612	UICB0_UIC1NCI \| UICB0_UIC2CI \| UICB0_UIC2NCI)
1610	1613
1611		-#elif defined(CONFIG_460EX) \|\| defined(CONFIG_460GT)
	1614	+#elif defined(CONFIG_460EX) \|\| defined(CONFIG_460GT) \|\| \
	1615	+ defined(CONFIG_460SX)
1612	1616
1613	1617	#define UICB0_UIC1NCI 0x00000002 /* UIC1 Noncritical Interrupt */
1614	1618	#define UICB0_UIC1CI 0x00000001 /* UIC1 Critical Interrupt */
...	...	@@ -1855,7 +1859,7 @@
1855	1859	#define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF)
1856	1860	#endif
1857	1861
1858		-#if defined(CONFIG_440SPE)
	1862	+#if defined(CONFIG_440SPE) \|\| defined(CONFIG_460SX)
1859	1863	#define SDR0_CP440 0x0180
1860	1864	#define SDR0_CP440_ERPN_MASK 0x30000000
1861	1865	#define SDR0_CP440_ERPN_MASK_HI 0x3000
...	...	@@ -2793,7 +2797,8 @@
2793	2797	/*-----------------------------------------------------------------------------+
2794	2798	\| Clocking
2795	2799	+-----------------------------------------------------------------------------*/
2796		-#if defined(CONFIG_460EX) \|\| defined(CONFIG_460GT)
	2800	+#if defined(CONFIG_460EX) \|\| defined(CONFIG_460GT) \|\| \
	2801	+ defined(CONFIG_460SX)
2797	2802	#define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */
2798	2803	#define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */
2799	2804	#define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */
...	...	@@ -3145,7 +3150,8 @@
3145	3150	* GPIO macro register defines
3146	3151	******************************************************************************/
3147	3152	#if defined(CONFIG_440GP) \|\| defined(CONFIG_440GX) \|\| \
3148		- defined(CONFIG_440SP) \|\| defined(CONFIG_440SPE)
	3153	+ defined(CONFIG_440SP) \|\| defined(CONFIG_440SPE) \|\| \
	3154	+ defined(CONFIG_460SX)
3149	3155	#define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000700)
3150	3156
3151	3157	#define GPIO0_OR (GPIO0_BASE+0x0)
...	...	@@ -41,7 +41,8 @@
41	41
42	42	#if defined(CONFIG_405EX) \|\| \
43	43	defined(CONFIG_440SP) \|\| defined(CONFIG_440SPE) \|\| \
44		- defined(CONFIG_460EX) \|\| defined(CONFIG_460GT)
	44	+ defined(CONFIG_460EX) \|\| defined(CONFIG_460GT) \|\| \
	45	+ defined(CONFIG_460SX)
45	46	#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */
46	47	#endif
47	48