Eric Lee / smarc-uboot

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Commit 9aea95307fdb0ffe0d3a98a17ac73e5040c9756a

Authored by wdenk
1 parent 281e00a3be
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Patch by Jon Loeliger, 16 Jul 2004: 

- support larger DDR memories up to 2G on the PC8540/8560ADS and
  STXGP3 boards
- Made MPC8540/8560ADS be 33Mhz PCI by default.
- Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16
  and CONFIG_L2_INIT_RAM options.
- Refactor Local Bus initialization out of SDRAM setup.
- Re-implement new version of LBC11/DDR11 errata workarounds.
- Moved board specific PCI init parts out of CPU directory.
- Added TLB entry for PCI-1 IO Memory
- Updated README.mpc85xxads

Showing 19 changed files with 1630 additions and 1483 deletions Side-by-side Diff

... ... @@ -2,6 +2,18 @@
2 2 Changes since U-Boot 1.1.1:
3 3 ======================================================================
4 4  
  5 +* Patch by Jon Loeliger, 16 Jul 2004:
  6 + - support larger DDR memories up to 2G on the PC8540/8560ADS and
  7 + STXGP3 boards
  8 + - Made MPC8540/8560ADS be 33Mhz PCI by default.
  9 + - Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16
  10 + and CONFIG_L2_INIT_RAM options.
  11 + - Refactor Local Bus initialization out of SDRAM setup.
  12 + - Re-implement new version of LBC11/DDR11 errata workarounds.
  13 + - Moved board specific PCI init parts out of CPU directory.
  14 + - Added TLB entry for PCI-1 IO Memory
  15 + - Updated README.mpc85xxads
  16 +
5 17 * Patch by Sascha Hauer, 28 Jun:
6 18 - add generic support for Motorola i.MX architecture
7 19 - add support for mx1ads, mx1fs2 and scb9328 boards
board/mpc8540ads/flash.c
Diff comments   View file @ 9aea953
... ... @@ -86,14 +86,12 @@
86 86  
87 87 flash_info[0].size = size;
88 88  
89   -#if !defined(CONFIG_RAM_AS_FLASH)
90 89 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
91 90 /* monitor protection ON by default */
92 91 flash_protect(FLAG_PROTECT_SET,
93 92 CFG_MONITOR_BASE,
94 93 CFG_MONITOR_BASE+monitor_flash_len-1,
95 94 &flash_info[0]);
96   -#endif
97 95  
98 96 #ifdef CFG_ENV_IS_IN_FLASH
99 97 /* ENV protection ON by default */
board/mpc8540ads/init.S
Diff comments   View file @ 9aea953
1 1 /*
2 2 * Copyright 2004 Freescale Semiconductor.
3   -* Copyright (C) 2002,2003, Motorola Inc.
4   -* Xianghua Xiao <X.Xiao@motorola.com>
5   -*
6   -* See file CREDITS for list of people who contributed to this
7   -* project.
8   -*
9   -* This program is free software; you can redistribute it and/or
10   -* modify it under the terms of the GNU General Public License as
11   -* published by the Free Software Foundation; either version 2 of
12   -* the License, or (at your option) any later version.
13   -*
14   -* This program is distributed in the hope that it will be useful,
15   -* but WITHOUT ANY WARRANTY; without even the implied warranty of
16   -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17   -* GNU General Public License for more details.
18   -*
19   -* You should have received a copy of the GNU General Public License
20   -* along with this program; if not, write to the Free Software
21   -* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22   -* MA 02111-1307 USA
23   -*/
  3 + * Copyright (C) 2002,2003, Motorola Inc.
  4 + * Xianghua Xiao <X.Xiao@motorola.com>
  5 + *
  6 + * See file CREDITS for list of people who contributed to this
  7 + * project.
  8 + *
  9 + * This program is free software; you can redistribute it and/or
  10 + * modify it under the terms of the GNU General Public License as
  11 + * published by the Free Software Foundation; either version 2 of
  12 + * the License, or (at your option) any later version.
  13 + *
  14 + * This program is distributed in the hope that it will be useful,
  15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17 + * GNU General Public License for more details.
  18 + *
  19 + * You should have received a copy of the GNU General Public License
  20 + * along with this program; if not, write to the Free Software
  21 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 + * MA 02111-1307 USA
  23 + */
24 24  
25 25 #include <ppc_asm.tmpl>
26 26 #include <ppc_defs.h>
... ... @@ -29,6 +29,24 @@
29 29 #include <config.h>
30 30 #include <mpc85xx.h>
31 31  
  32 +
  33 +/*
  34 + * TLB0 and TLB1 Entries
  35 + *
  36 + * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
  37 + * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
  38 + * these TLB entries are established.
  39 + *
  40 + * The TLB entries for DDR are dynamically setup in spd_sdram()
  41 + * and use TLB1 Entries 8 through 15 as needed according to the
  42 + * size of DDR memory.
  43 + *
  44 + * MAS0: tlbsel, esel, nv
  45 + * MAS1: valid, iprot, tid, ts, tsize
  46 + * MAS2: epn, sharen, x0, x1, w, i, m, g, e
  47 + * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
  48 + */
  49 +
32 50 #define entry_start \
33 51 mflr r1 ; \
34 52 bl 0f ;
35 53  
36 54  
37 55  
38 56  
39 57  
40 58  
41 59  
42 60  
43 61  
44 62  
45 63  
46 64  
47 65  
48 66  
49 67  
50 68  
51 69  
52 70  
... ... @@ -38,119 +56,174 @@
38 56 mtlr r1 ; \
39 57 blr ;
40 58  
41   -/* TLB1 entries configuration: */
42 59  
43 60 .section .bootpg, "ax"
44 61 .globl tlb1_entry
45 62 tlb1_entry:
46 63 entry_start
47 64  
48   - /* Number of entries in the following table */
49   - .long 0x0c
  65 + /*
  66 + * Number of TLB0 and TLB1 entries in the following table
  67 + */
  68 + .long 13
50 69  
51   - .long TLB1_MAS0(1,1,0)
52   - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
53   - .long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
54   - .long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  70 +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
  71 + /*
  72 + * TLB0 4K Non-cacheable, guarded
  73 + * 0xff700000 4K Initial CCSRBAR mapping
  74 + *
  75 + * This ends up at a TLB0 Index==0 entry, and must not collide
  76 + * with other TLB0 Entries.
  77 + */
  78 + .long TLB1_MAS0(0, 0, 0)
  79 + .long TLB1_MAS1(1, 0, 0, 0, 0)
  80 + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
  81 + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
  82 +#else
  83 +#error("Update the number of table entries in tlb1_entry")
  84 +#endif
55 85  
56   - #if defined(CFG_FLASH_PORT_WIDTH_16)
57   - .long TLB1_MAS0(1,2,0)
58   - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
59   - .long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
60   - .long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  86 + /*
  87 + * TLB0 16K Cacheable, non-guarded
  88 + * 0xd001_0000 16K Temporary Global data for initialization
  89 + *
  90 + * Use four 4K TLB0 entries. These entries must be cacheable
  91 + * as they provide the bootstrap memory before the memory
  92 + * controler and real memory have been configured.
  93 + *
  94 + * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
  95 + * and must not collide with other TLB0 entries.
  96 + */
  97 + .long TLB1_MAS0(0, 0, 0)
  98 + .long TLB1_MAS1(1, 0, 0, 0, 0)
  99 + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
  100 + 0,0,0,0,0,0,0,0)
  101 + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
  102 + 0,0,0,0,0,1,0,1,0,1)
61 103  
62   - .long TLB1_MAS0(1,3,0)
63   - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
64   - .long TLB1_MAS2((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,1,0,1,0)
65   - .long TLB1_MAS3((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1)
66   - #else
67   - .long TLB1_MAS0(1,2,0)
68   - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16M)
69   - .long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
70   - .long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  104 + .long TLB1_MAS0(0, 0, 0)
  105 + .long TLB1_MAS1(1, 0, 0, 0, 0)
  106 + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
  107 + 0,0,0,0,0,0,0,0)
  108 + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
  109 + 0,0,0,0,0,1,0,1,0,1)
71 110  
72   - .long TLB1_MAS0(1,3,0)
73   - .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
74   - .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
75   - .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
76   - #endif
  111 + .long TLB1_MAS0(0, 0, 0)
  112 + .long TLB1_MAS1(1, 0, 0, 0, 0)
  113 + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
  114 + 0,0,0,0,0,0,0,0)
  115 + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
  116 + 0,0,0,0,0,1,0,1,0,1)
77 117  
78   - #if !defined(CONFIG_SPD_EEPROM)
79   - .long TLB1_MAS0(1,4,0)
80   - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
81   - .long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
82   - .long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  118 + .long TLB1_MAS0(0, 0, 0)
  119 + .long TLB1_MAS1(1, 0, 0, 0, 0)
  120 + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
  121 + 0,0,0,0,0,0,0,0)
  122 + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
  123 + 0,0,0,0,0,1,0,1,0,1)
83 124  
84   - .long TLB1_MAS0(1,5,0)
85   - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
86   - .long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0)
87   - .long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
88   - #else
89   - .long TLB1_MAS0(1,4,0)
90   - .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
91   - .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
92   - .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
93 125  
94   - .long TLB1_MAS0(1,5,0)
95   - .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
96   - .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
97   - .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
98   - #endif
  126 + /*
  127 + * TLB 0: 16M Non-cacheable, guarded
  128 + * 0xff000000 16M FLASH
  129 + * Out of reset this entry is only 4K.
  130 + */
  131 + .long TLB1_MAS0(1, 0, 0)
  132 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
  133 + .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
  134 + .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
99 135  
100   - .long TLB1_MAS0(1,6,0)
101   - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
102   - #if defined(CONFIG_RAM_AS_FLASH)
103   - .long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
104   - #else
105   - .long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
106   - #endif
107   - .long TLB1_MAS3(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  136 + /*
  137 + * TLB 1: 256M Non-cacheable, guarded
  138 + * 0x80000000 256M PCI1 MEM First half
  139 + */
  140 + .long TLB1_MAS0(1, 1, 0)
  141 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
  142 + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
  143 + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
108 144  
109   - .long TLB1_MAS0(1,7,0)
110   - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
111   - #ifdef CONFIG_L2_INIT_RAM
112   - .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0)
113   - #else
114   - .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0)
115   - #endif
116   - .long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  145 + /*
  146 + * TLB 2: 256M Non-cacheable, guarded
  147 + * 0x90000000 256M PCI1 MEM Second half
  148 + */
  149 + .long TLB1_MAS0(1, 2, 0)
  150 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
  151 + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
  152 + 0,0,0,0,1,0,1,0)
  153 + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
  154 + 0,0,0,0,0,1,0,1,0,1)
117 155  
118   - .long TLB1_MAS0(1,8,0)
119   - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
120   - .long TLB1_MAS2(((CFG_PCI1_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
121   - .long TLB1_MAS3(((CFG_PCI1_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  156 + /*
  157 + * TLB 3: 256M Non-cacheable, guarded
  158 + * 0xc0000000 256M Rapid IO MEM First half
  159 + */
  160 + .long TLB1_MAS0(1, 3, 0)
  161 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
  162 + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
  163 + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
122 164  
123   - .long TLB1_MAS0(1,9,0)
124   - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
125   - .long TLB1_MAS2(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
126   - .long TLB1_MAS3(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  165 + /*
  166 + * TLB 4: 256M Non-cacheable, guarded
  167 + * 0xd0000000 256M Rapid IO MEM Second half
  168 + */
  169 + .long TLB1_MAS0(1, 4, 0)
  170 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
  171 + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),
  172 + 0,0,0,0,1,0,1,0)
  173 + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),
  174 + 0,0,0,0,0,1,0,1,0,1)
127 175  
128 176 /*
129   - * RapidIO MMU for 512M
130   - * Two entries, 10 and 11
  177 + * TLB 5: 64M Non-cacheable, guarded
  178 + * 0xe000_0000 1M CCSRBAR
  179 + * 0xe200_0000 16M PCI1 IO
131 180 */
132   - .long TLB1_MAS0(1,10,0)
133   - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
134   - .long TLB1_MAS2(((CFG_RIO_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
135   - .long TLB1_MAS3(((CFG_RIO_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  181 + .long TLB1_MAS0(1, 5, 0)
  182 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
  183 + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
  184 + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
136 185  
137   - .long TLB1_MAS0(1,11,0)
138   - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
139   - .long TLB1_MAS2(((CFG_RIO_MEM_BASE+0x10000000>>12) & 0xfffff),0,0,0,0,1,0,1,0)
140   - .long TLB1_MAS3(((CFG_RIO_MEM_BASE+0x10000000>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  186 + /*
  187 + * TLB 6: 64M Cacheable, non-guarded
  188 + * 0xf000_0000 64M LBC SDRAM
  189 + */
  190 + .long TLB1_MAS0(1, 6, 0)
  191 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
  192 + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
  193 + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
141 194  
  195 + /*
  196 + * TLB 7: 16K Non-cacheable, guarded
  197 + * 0xf8000000 16K BCSR registers
  198 + */
  199 + .long TLB1_MAS0(1, 7, 0)
  200 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K)
  201 + .long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR), 0,0,0,0,1,0,1,0)
  202 + .long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR), 0,0,0,0,0,1,0,1,0,1)
142 203  
143   -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
144   - .long TLB1_MAS0(1,15,0)
145   - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
146   - .long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
147   - .long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
148   -#else
149   - .long TLB1_MAS0(1,15,0)
150   - .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
151   - .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
152   - .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
  204 +#if !defined(CONFIG_SPD_EEPROM)
  205 + /*
  206 + * TLB 8, 9: 128M DDR
  207 + * 0x00000000 64M DDR System memory
  208 + * 0x04000000 64M DDR System memory
  209 + * Without SPD EEPROM configured DDR, this must be setup manually.
  210 + * Make sure the TLB count at the top of this table is correct.
  211 + * Likely it needs to be increased by two for these entries.
  212 + */
  213 +#error("Update the number of table entries in tlb1_entry")
  214 + .long TLB1_MAS0(1, 8, 0)
  215 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
  216 + .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
  217 + .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
  218 +
  219 + .long TLB1_MAS0(1, 9, 0)
  220 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
  221 + .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000),
  222 + 0,0,0,0,0,0,0,0)
  223 + .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000),
  224 + 0,0,0,0,0,1,0,1,0,1)
153 225 #endif
  226 +
154 227 entry_end
155 228  
156 229 /*
157 230  
... ... @@ -184,13 +257,8 @@
184 257 /*
185 258 * This is not so much the SDRAM map as it is the whole localbus map.
186 259 */
187   -#if !defined(CONFIG_RAM_AS_FLASH)
188 260 #define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
189 261 #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
190   -#else
191   -#define LAWBAR2 0
192   -#define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
193   -#endif
194 262  
195 263 #define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
196 264 #define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))
board/mpc8540ads/mpc8540ads.c
Diff comments   View file @ 9aea953
... ... @@ -26,6 +26,7 @@
26 26  
27 27  
28 28 #include <common.h>
  29 +#include <pci.h>
29 30 #include <asm/processor.h>
30 31 #include <asm/immap_85xx.h>
31 32 #include <spd.h>
... ... @@ -36,6 +37,7 @@
36 37  
37 38 extern long int spd_sdram(void);
38 39  
  40 +void local_bus_init(void);
39 41 void sdram_init(void);
40 42 long int fixed_sdram(void);
41 43  
42 44  
43 45  
... ... @@ -43,13 +45,13 @@
43 45 int board_early_init_f (void)
44 46 {
45 47 #if defined(CONFIG_PCI)
46   - volatile immap_t *immr = (immap_t *) CFG_IMMR;
47   - volatile ccsr_pcix_t *pci = &immr->im_pcix;
  48 + volatile immap_t *immr = (immap_t *)CFG_IMMR;
  49 + volatile ccsr_pcix_t *pci = &immr->im_pcix;
48 50  
49   - pci->peer &= 0xffffffdf; /* disable master abort */
  51 + pci->peer &= 0xffffffdf; /* disable master abort */
50 52 #endif
51 53  
52   - return 0;
  54 + return 0;
53 55 }
54 56  
55 57 int checkboard (void)
... ... @@ -63,6 +65,11 @@
63 65 printf(" PCI1: disabled\n");
64 66 #endif
65 67  
  68 + /*
  69 + * Initialize local bus.
  70 + */
  71 + local_bus_init();
  72 +
66 73 return 0;
67 74 }
68 75  
69 76  
... ... @@ -78,15 +85,15 @@
78 85  
79 86 #if defined(CONFIG_DDR_DLL)
80 87 {
81   - volatile ccsr_gur_t *gur= &immap->im_gur;
82   - uint temp_ddrdll = 0;
  88 + volatile ccsr_gur_t *gur= &immap->im_gur;
  89 + uint temp_ddrdll = 0;
83 90  
84   - /*
85   - * Work around to stabilize DDR DLL
86   - */
87   - temp_ddrdll = gur->ddrdllcr;
88   - gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
89   - asm("sync;isync;msync");
  91 + /*
  92 + * Work around to stabilize DDR DLL
  93 + */
  94 + temp_ddrdll = gur->ddrdllcr;
  95 + gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
  96 + asm("sync;isync;msync");
90 97 }
91 98 #endif
92 99  
93 100  
94 101  
95 102  
96 103  
97 104  
98 105  
99 106  
100 107  
101 108  
102 109  
103 110  
104 111  
105 112  
106 113  
107 114  
108 115  
109 116  
110 117  
111 118  
112 119  
113 120  
114 121  
115 122  
116 123  
117 124  
118 125  
... ... @@ -114,102 +121,124 @@
114 121  
115 122  
116 123 /*
117   - * Initialize SDRAM memory on the Local Bus.
  124 + * Initialize Local Bus
118 125 */
119 126  
120   -void sdram_init (void)
  127 +void
  128 +local_bus_init(void)
121 129 {
122   -#if !defined(CONFIG_RAM_AS_FLASH)
123   - sys_info_t sysinfo;
124   - volatile immap_t *immap = (immap_t *) CFG_IMMR;
  130 + volatile immap_t *immap = (immap_t *)CFG_IMMR;
  131 + volatile ccsr_gur_t *gur = &immap->im_gur;
125 132 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
126   - uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE;
127 133  
128   - puts (" SDRAM: ");
129   - print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
  134 + uint clkdiv;
  135 + uint lbc_hz;
  136 + sys_info_t sysinfo;
130 137  
131 138 /*
132   - * LocalBus SDRAM is not emulating flash.
133   - */
134   -
135   - /*
136   - * Fix Local Bus clock glitch. Errata LBC11.
  139 + * Errata LBC11.
  140 + * Fix Local Bus clock glitch when DLL is enabled.
137 141 *
138   - * If localbus freq is less than 66Mhz, use bypass mode,
139   - * otherwise use DLL.
140   - * lcrr is the local-bus clock ratio register.
  142 + * If localbus freq is < 66Mhz, DLL bypass mode must be used.
  143 + * If localbus freq is > 133Mhz, DLL can be safely enabled.
  144 + * Between 66 and 133, the DLL is enabled with an override workaround.
141 145 */
142   - get_sys_info (&sysinfo);
143   - if (sysinfo.freqSystemBus / (CFG_LBC_LCRR & 0x0f) < 66000000) {
144   - lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff) | 0x80000000;
145 146  
  147 + get_sys_info(&sysinfo);
  148 + clkdiv = lbc->lcrr & 0x0f;
  149 + lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
  150 +
  151 + if (lbc_hz < 66) {
  152 + lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
  153 +
  154 + } else if (lbc_hz >= 133) {
  155 + lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
  156 +
146 157 } else {
147 158 /*
148 159 * On REV1 boards, need to change CLKDIV before enable DLL.
149 160 * Default CLKDIV is 8, change it to 4 temporarily.
150 161 */
151   - volatile ccsr_gur_t *gur = &immap->im_gur;
152   - uint pvr = get_pvr ();
  162 + uint pvr = get_pvr();
153 163 uint temp_lbcdll = 0;
154 164  
155 165 if (pvr == PVR_85xx_REV1) {
  166 + /* FIXME: Justify the high bit here. */
156 167 lbc->lcrr = 0x10000004;
157 168 }
158 169  
159   - /* FIXME: jdl Should lcrr have 0x8000000 OR'ed in here too? */
160   - lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
161   - udelay (200);
  170 + lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
  171 + udelay(200);
  172 +
  173 + /*
  174 + * Sample LBC DLL ctrl reg, upshift it to set the
  175 + * override bits.
  176 + */
162 177 temp_lbcdll = gur->lbcdllcr;
163   - gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16) | 0x80000000;
164   - asm ("sync;isync;msync");
  178 + gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
  179 + asm("sync;isync;msync");
165 180 }
  181 +}
166 182  
  183 +
  184 +/*
  185 + * Initialize SDRAM memory on the Local Bus.
  186 + */
  187 +
  188 +void
  189 +sdram_init(void)
  190 +{
  191 + volatile immap_t *immap = (immap_t *)CFG_IMMR;
  192 + volatile ccsr_lbc_t *lbc= &immap->im_lbc;
  193 + uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
  194 +
  195 + puts(" SDRAM: ");
  196 + print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
  197 +
167 198 /*
168 199 * Setup SDRAM Base and Option Registers
169 200 */
170 201 lbc->or2 = CFG_OR2_PRELIM;
171 202 lbc->br2 = CFG_BR2_PRELIM;
172 203 lbc->lbcr = CFG_LBC_LBCR;
173   - asm ("msync");
  204 + asm("msync");
174 205  
175 206 lbc->lsrt = CFG_LBC_LSRT;
176 207 lbc->mrtpr = CFG_LBC_MRTPR;
177   - asm ("sync");
  208 + asm("sync");
178 209  
179 210 /*
180 211 * Configure the SDRAM controller.
181 212 */
182 213 lbc->lsdmr = CFG_LBC_LSDMR_1;
183   - asm ("sync");
  214 + asm("sync");
184 215 *sdram_addr = 0xff;
185   - ppcDcbf ((unsigned long) sdram_addr);
186   - udelay (100);
  216 + ppcDcbf((unsigned long) sdram_addr);
  217 + udelay(100);
187 218  
188 219 lbc->lsdmr = CFG_LBC_LSDMR_2;
189   - asm ("sync");
  220 + asm("sync");
190 221 *sdram_addr = 0xff;
191   - ppcDcbf ((unsigned long) sdram_addr);
192   - udelay (100);
  222 + ppcDcbf((unsigned long) sdram_addr);
  223 + udelay(100);
193 224  
194 225 lbc->lsdmr = CFG_LBC_LSDMR_3;
195   - asm ("sync");
  226 + asm("sync");
196 227 *sdram_addr = 0xff;
197   - ppcDcbf ((unsigned long) sdram_addr);
198   - udelay (100);
  228 + ppcDcbf((unsigned long) sdram_addr);
  229 + udelay(100);
199 230  
200 231 lbc->lsdmr = CFG_LBC_LSDMR_4;
201   - asm ("sync");
  232 + asm("sync");
202 233 *sdram_addr = 0xff;
203   - ppcDcbf ((unsigned long) sdram_addr);
204   - udelay (100);
  234 + ppcDcbf((unsigned long) sdram_addr);
  235 + udelay(100);
205 236  
206 237 lbc->lsdmr = CFG_LBC_LSDMR_5;
207   - asm ("sync");
  238 + asm("sync");
208 239 *sdram_addr = 0xff;
209   - ppcDcbf ((unsigned long) sdram_addr);
210   - udelay (100);
211   -
212   -#endif
  240 + ppcDcbf((unsigned long) sdram_addr);
  241 + udelay(100);
213 242 }
214 243  
215 244  
... ... @@ -282,4 +311,42 @@
282 311 return CFG_SDRAM_SIZE * 1024 * 1024;
283 312 }
284 313 #endif /* !defined(CONFIG_SPD_EEPROM) */
  314 +
  315 +
  316 +#if defined(CONFIG_PCI)
  317 +/*
  318 + * Initialize PCI Devices, report devices found.
  319 + */
  320 +
  321 +#ifndef CONFIG_PCI_PNP
  322 +static struct pci_config_table pci_mpc85xxads_config_table[] = {
  323 + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  324 + PCI_IDSEL_NUMBER, PCI_ANY_ID,
  325 + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
  326 + PCI_ENET0_MEMADDR,
  327 + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
  328 + } },
  329 + { }
  330 +};
  331 +#endif
  332 +
  333 +
  334 +static struct pci_controller hose = {
  335 +#ifndef CONFIG_PCI_PNP
  336 + config_table: pci_mpc85xxads_config_table,
  337 +#endif
  338 +};
  339 +
  340 +#endif /* CONFIG_PCI */
  341 +
  342 +
  343 +void
  344 +pci_init_board(void)
  345 +{
  346 +#ifdef CONFIG_PCI
  347 + extern void pci_mpc85xx_init(struct pci_controller *hose);
  348 +
  349 + pci_mpc85xx_init(&hose);
  350 +#endif /* CONFIG_PCI */
  351 +}
board/mpc8560ads/flash.c
Diff comments   View file @ 9aea953
... ... @@ -86,14 +86,12 @@
86 86  
87 87 flash_info[0].size = size;
88 88  
89   -#if !defined(CONFIG_RAM_AS_FLASH)
90 89 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
91 90 /* monitor protection ON by default */
92 91 flash_protect(FLAG_PROTECT_SET,
93 92 CFG_MONITOR_BASE,
94 93 CFG_MONITOR_BASE+monitor_flash_len-1,
95 94 &flash_info[0]);
96   -#endif
97 95  
98 96 #ifdef CFG_ENV_IS_IN_FLASH
99 97 /* ENV protection ON by default */
board/mpc8560ads/init.S
Diff comments   View file @ 9aea953
1 1 /*
2 2 * Copyright 2004 Freescale Semiconductor.
3   -* Copyright (C) 2002,2003, Motorola Inc.
4   -* Xianghua Xiao <X.Xiao@motorola.com>
5   -*
6   -* See file CREDITS for list of people who contributed to this
7   -* project.
8   -*
9   -* This program is free software; you can redistribute it and/or
10   -* modify it under the terms of the GNU General Public License as
11   -* published by the Free Software Foundation; either version 2 of
12   -* the License, or (at your option) any later version.
13   -*
14   -* This program is distributed in the hope that it will be useful,
15   -* but WITHOUT ANY WARRANTY; without even the implied warranty of
16   -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17   -* GNU General Public License for more details.
18   -*
19   -* You should have received a copy of the GNU General Public License
20   -* along with this program; if not, write to the Free Software
21   -* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22   -* MA 02111-1307 USA
23   -*/
  3 + * Copyright (C) 2002,2003, Motorola Inc.
  4 + * Xianghua Xiao <X.Xiao@motorola.com>
  5 + *
  6 + * See file CREDITS for list of people who contributed to this
  7 + * project.
  8 + *
  9 + * This program is free software; you can redistribute it and/or
  10 + * modify it under the terms of the GNU General Public License as
  11 + * published by the Free Software Foundation; either version 2 of
  12 + * the License, or (at your option) any later version.
  13 + *
  14 + * This program is distributed in the hope that it will be useful,
  15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17 + * GNU General Public License for more details.
  18 + *
  19 + * You should have received a copy of the GNU General Public License
  20 + * along with this program; if not, write to the Free Software
  21 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 + * MA 02111-1307 USA
  23 + */
24 24  
25 25 #include <ppc_asm.tmpl>
26 26 #include <ppc_defs.h>
... ... @@ -29,6 +29,24 @@
29 29 #include <config.h>
30 30 #include <mpc85xx.h>
31 31  
  32 +
  33 +/*
  34 + * TLB0 and TLB1 Entries
  35 + *
  36 + * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
  37 + * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
  38 + * these TLB entries are established.
  39 + *
  40 + * The TLB entries for DDR are dynamically setup in spd_sdram()
  41 + * and use TLB1 Entries 8 through 15 as needed according to the
  42 + * size of DDR memory.
  43 + *
  44 + * MAS0: tlbsel, esel, nv
  45 + * MAS1: valid, iprot, tid, ts, tsize
  46 + * MAS2: epn, sharen, x0, x1, w, i, m, g, e
  47 + * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
  48 + */
  49 +
32 50 #define entry_start \
33 51 mflr r1 ; \
34 52 bl 0f ;
35 53  
36 54  
37 55  
38 56  
39 57  
40 58  
41 59  
42 60  
43 61  
44 62  
45 63  
46 64  
47 65  
48 66  
49 67  
50 68  
51 69  
52 70  
... ... @@ -38,119 +56,174 @@
38 56 mtlr r1 ; \
39 57 blr ;
40 58  
41   -/* TLB1 entries configuration: */
42 59  
43 60 .section .bootpg, "ax"
44 61 .globl tlb1_entry
45 62 tlb1_entry:
46 63 entry_start
47 64  
48   - /* Number of entries in the following table */
49   - .long 0x0c
  65 + /*
  66 + * Number of TLB0 and TLB1 entries in the following table
  67 + */
  68 + .long 13
50 69  
51   - .long TLB1_MAS0(1,1,0)
52   - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
53   - .long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
54   - .long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  70 +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
  71 + /*
  72 + * TLB0 4K Non-cacheable, guarded
  73 + * 0xff700000 4K Initial CCSRBAR mapping
  74 + *
  75 + * This ends up at a TLB0 Index==0 entry, and must not collide
  76 + * with other TLB0 Entries.
  77 + */
  78 + .long TLB1_MAS0(0, 0, 0)
  79 + .long TLB1_MAS1(1, 0, 0, 0, 0)
  80 + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
  81 + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
  82 +#else
  83 +#error("Update the number of table entries in tlb1_entry")
  84 +#endif
55 85  
56   - #if defined(CFG_FLASH_PORT_WIDTH_16)
57   - .long TLB1_MAS0(1,2,0)
58   - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
59   - .long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
60   - .long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  86 + /*
  87 + * TLB0 16K Cacheable, non-guarded
  88 + * 0xd001_0000 16K Temporary Global data for initialization
  89 + *
  90 + * Use four 4K TLB0 entries. These entries must be cacheable
  91 + * as they provide the bootstrap memory before the memory
  92 + * controler and real memory have been configured.
  93 + *
  94 + * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
  95 + * and must not collide with other TLB0 entries.
  96 + */
  97 + .long TLB1_MAS0(0, 0, 0)
  98 + .long TLB1_MAS1(1, 0, 0, 0, 0)
  99 + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
  100 + 0,0,0,0,0,0,0,0)
  101 + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
  102 + 0,0,0,0,0,1,0,1,0,1)
61 103  
62   - .long TLB1_MAS0(1,3,0)
63   - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
64   - .long TLB1_MAS2((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,1,0,1,0)
65   - .long TLB1_MAS3((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1)
66   - #else
67   - .long TLB1_MAS0(1,2,0)
68   - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16M)
69   - .long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
70   - .long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  104 + .long TLB1_MAS0(0, 0, 0)
  105 + .long TLB1_MAS1(1, 0, 0, 0, 0)
  106 + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
  107 + 0,0,0,0,0,0,0,0)
  108 + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
  109 + 0,0,0,0,0,1,0,1,0,1)
71 110  
72   - .long TLB1_MAS0(1,3,0)
73   - .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
74   - .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
75   - .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
76   - #endif
  111 + .long TLB1_MAS0(0, 0, 0)
  112 + .long TLB1_MAS1(1, 0, 0, 0, 0)
  113 + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
  114 + 0,0,0,0,0,0,0,0)
  115 + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
  116 + 0,0,0,0,0,1,0,1,0,1)
77 117  
78   - #if !defined(CONFIG_SPD_EEPROM)
79   - .long TLB1_MAS0(1,4,0)
80   - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
81   - .long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
82   - .long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  118 + .long TLB1_MAS0(0, 0, 0)
  119 + .long TLB1_MAS1(1, 0, 0, 0, 0)
  120 + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
  121 + 0,0,0,0,0,0,0,0)
  122 + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
  123 + 0,0,0,0,0,1,0,1,0,1)
83 124  
84   - .long TLB1_MAS0(1,5,0)
85   - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
86   - .long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0)
87   - .long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
88   - #else
89   - .long TLB1_MAS0(1,4,0)
90   - .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
91   - .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
92   - .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
93 125  
94   - .long TLB1_MAS0(1,5,0)
95   - .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
96   - .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
97   - .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
98   - #endif
  126 + /*
  127 + * TLB 0: 16M Non-cacheable, guarded
  128 + * 0xff000000 16M FLASH
  129 + * Out of reset this entry is only 4K.
  130 + */
  131 + .long TLB1_MAS0(1, 0, 0)
  132 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
  133 + .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
  134 + .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
99 135  
100   - .long TLB1_MAS0(1,6,0)
101   - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
102   - #if defined(CONFIG_RAM_AS_FLASH)
103   - .long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
104   - #else
105   - .long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
106   - #endif
107   - .long TLB1_MAS3(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  136 + /*
  137 + * TLB 1: 256M Non-cacheable, guarded
  138 + * 0x80000000 256M PCI1 MEM First half
  139 + */
  140 + .long TLB1_MAS0(1, 1, 0)
  141 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
  142 + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
  143 + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
108 144  
109   - .long TLB1_MAS0(1,7,0)
110   - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
111   - #ifdef CONFIG_L2_INIT_RAM
112   - .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0)
113   - #else
114   - .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0)
115   - #endif
116   - .long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  145 + /*
  146 + * TLB 2: 256M Non-cacheable, guarded
  147 + * 0x90000000 256M PCI1 MEM Second half
  148 + */
  149 + .long TLB1_MAS0(1, 2, 0)
  150 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
  151 + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
  152 + 0,0,0,0,1,0,1,0)
  153 + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
  154 + 0,0,0,0,0,1,0,1,0,1)
117 155  
118   - .long TLB1_MAS0(1,8,0)
119   - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
120   - .long TLB1_MAS2(((CFG_PCI1_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
121   - .long TLB1_MAS3(((CFG_PCI1_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  156 + /*
  157 + * TLB 3: 256M Non-cacheable, guarded
  158 + * 0xc0000000 256M Rapid IO MEM First half
  159 + */
  160 + .long TLB1_MAS0(1, 3, 0)
  161 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
  162 + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
  163 + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
122 164  
123   - .long TLB1_MAS0(1,9,0)
124   - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
125   - .long TLB1_MAS2(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
126   - .long TLB1_MAS3(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  165 + /*
  166 + * TLB 4: 256M Non-cacheable, guarded
  167 + * 0xd0000000 256M Rapid IO MEM Second half
  168 + */
  169 + .long TLB1_MAS0(1, 4, 0)
  170 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
  171 + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),
  172 + 0,0,0,0,1,0,1,0)
  173 + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),
  174 + 0,0,0,0,0,1,0,1,0,1)
127 175  
128 176 /*
129   - * RapidIO MMU for 512M
130   - * Two entries, 10 and 11
  177 + * TLB 5: 64M Non-cacheable, guarded
  178 + * 0xe000_0000 1M CCSRBAR
  179 + * 0xe200_0000 16M PCI1 IO
131 180 */
132   - .long TLB1_MAS0(1,10,0)
133   - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
134   - .long TLB1_MAS2(((CFG_RIO_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
135   - .long TLB1_MAS3(((CFG_RIO_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  181 + .long TLB1_MAS0(1, 5, 0)
  182 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
  183 + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
  184 + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
136 185  
137   - .long TLB1_MAS0(1,11,0)
138   - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
139   - .long TLB1_MAS2(((CFG_RIO_MEM_BASE+0x10000000>>12) & 0xfffff),0,0,0,0,1,0,1,0)
140   - .long TLB1_MAS3(((CFG_RIO_MEM_BASE+0x10000000>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  186 + /*
  187 + * TLB 6: 64M Cacheable, non-guarded
  188 + * 0xf000_0000 64M LBC SDRAM
  189 + */
  190 + .long TLB1_MAS0(1, 6, 0)
  191 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
  192 + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
  193 + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
141 194  
  195 + /*
  196 + * TLB 7: 16K Non-cacheable, guarded
  197 + * 0xf8000000 16K BCSR registers
  198 + */
  199 + .long TLB1_MAS0(1, 7, 0)
  200 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K)
  201 + .long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR), 0,0,0,0,1,0,1,0)
  202 + .long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR), 0,0,0,0,0,1,0,1,0,1)
142 203  
143   -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
144   - .long TLB1_MAS0(1,15,0)
145   - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
146   - .long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
147   - .long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
148   -#else
149   - .long TLB1_MAS0(1,15,0)
150   - .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
151   - .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
152   - .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
  204 +#if !defined(CONFIG_SPD_EEPROM)
  205 + /*
  206 + * TLB 8, 9: 128M DDR
  207 + * 0x00000000 64M DDR System memory
  208 + * 0x04000000 64M DDR System memory
  209 + * Without SPD EEPROM configured DDR, this must be setup manually.
  210 + * Make sure the TLB count at the top of this table is correct.
  211 + * Likely it needs to be increased by two for these entries.
  212 + */
  213 +#error("Update the number of table entries in tlb1_entry")
  214 + .long TLB1_MAS0(1, 8, 0)
  215 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
  216 + .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
  217 + .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
  218 +
  219 + .long TLB1_MAS0(1, 9, 0)
  220 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
  221 + .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000),
  222 + 0,0,0,0,0,0,0,0)
  223 + .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000),
  224 + 0,0,0,0,0,1,0,1,0,1)
153 225 #endif
  226 +
154 227 entry_end
155 228  
156 229 /*
157 230  
... ... @@ -184,13 +257,8 @@
184 257 /*
185 258 * This is not so much the SDRAM map as it is the whole localbus map.
186 259 */
187   -#if !defined(CONFIG_RAM_AS_FLASH)
188 260 #define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
189 261 #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
190   -#else
191   -#define LAWBAR2 0
192   -#define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
193   -#endif
194 262  
195 263 #define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
196 264 #define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))
board/mpc8560ads/mpc8560ads.c
Diff comments   View file @ 9aea953
... ... @@ -26,6 +26,7 @@
26 26  
27 27  
28 28 #include <common.h>
  29 +#include <pci.h>
29 30 #include <asm/processor.h>
30 31 #include <asm/immap_85xx.h>
31 32 #include <ioports.h>
... ... @@ -38,6 +39,7 @@
38 39  
39 40 extern long int spd_sdram(void);
40 41  
  42 +void local_bus_init(void);
41 43 void sdram_init(void);
42 44 long int fixed_sdram(void);
43 45  
44 46  
45 47  
46 48  
... ... @@ -209,16 +211,17 @@
209 211 volatile unsigned char bcsr5;
210 212 } bcsr_t;
211 213  
  214 +
212 215 int board_early_init_f (void)
213 216 {
214 217 #if defined(CONFIG_PCI)
215   - volatile immap_t *immr = (immap_t *) CFG_IMMR;
216   - volatile ccsr_pcix_t *pci = &immr->im_pcix;
  218 + volatile immap_t *immr = (immap_t *)CFG_IMMR;
  219 + volatile ccsr_pcix_t *pci = &immr->im_pcix;
217 220  
218   - pci->peer &= 0xffffffdf; /* disable master abort */
  221 + pci->peer &= 0xffffffdf; /* disable master abort */
219 222 #endif
220 223  
221   - return 0;
  224 + return 0;
222 225 }
223 226  
224 227 void reset_phy (void)
... ... @@ -247,6 +250,7 @@
247 250 #endif /* CONFIG_MII */
248 251 }
249 252  
  253 +
250 254 int checkboard (void)
251 255 {
252 256 puts("Board: ADS\n");
... ... @@ -257,6 +261,12 @@
257 261 #else
258 262 printf(" PCI1: disabled\n");
259 263 #endif
  264 +
  265 + /*
  266 + * Initialize local bus.
  267 + */
  268 + local_bus_init();
  269 +
260 270 return 0;
261 271 }
262 272  
263 273  
... ... @@ -272,15 +282,15 @@
272 282  
273 283 #if defined(CONFIG_DDR_DLL)
274 284 {
275   - volatile ccsr_gur_t *gur= &immap->im_gur;
276   - uint temp_ddrdll = 0;
  285 + volatile ccsr_gur_t *gur= &immap->im_gur;
  286 + uint temp_ddrdll = 0;
277 287  
278   - /*
279   - * Work around to stabilize DDR DLL
280   - */
281   - temp_ddrdll = gur->ddrdllcr;
282   - gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
283   - asm("sync;isync;msync");
  288 + /*
  289 + * Work around to stabilize DDR DLL
  290 + */
  291 + temp_ddrdll = gur->ddrdllcr;
  292 + gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
  293 + asm("sync;isync;msync");
284 294 }
285 295 #endif
286 296  
287 297  
288 298  
289 299  
290 300  
291 301  
292 302  
293 303  
294 304  
295 305  
296 306  
297 307  
298 308  
299 309  
300 310  
301 311  
302 312  
303 313  
304 314  
305 315  
306 316  
307 317  
308 318  
309 319  
310 320  
311 321  
312 322  
... ... @@ -308,102 +318,124 @@
308 318  
309 319  
310 320 /*
311   - * Initialize SDRAM memory on the Local Bus.
  321 + * Initialize Local Bus
312 322 */
313 323  
314   -void sdram_init (void)
  324 +void
  325 +local_bus_init(void)
315 326 {
316   -#if !defined(CONFIG_RAM_AS_FLASH)
317   - sys_info_t sysinfo;
318   - volatile immap_t *immap = (immap_t *) CFG_IMMR;
  327 + volatile immap_t *immap = (immap_t *)CFG_IMMR;
  328 + volatile ccsr_gur_t *gur = &immap->im_gur;
319 329 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
320   - uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE;
321 330  
322   - puts (" SDRAM: ");
323   - print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
  331 + uint clkdiv;
  332 + uint lbc_hz;
  333 + sys_info_t sysinfo;
324 334  
325 335 /*
326   - * LocalBus SDRAM is not emulating flash.
327   - */
328   -
329   - /*
330   - * Fix Local Bus clock glitch. Errata LBC11.
  336 + * Errata LBC11.
  337 + * Fix Local Bus clock glitch when DLL is enabled.
331 338 *
332   - * If localbus freq is less than 66Mhz, use bypass mode,
333   - * otherwise use DLL.
334   - * lcrr is the local-bus clock ratio register.
  339 + * If localbus freq is < 66Mhz, DLL bypass mode must be used.
  340 + * If localbus freq is > 133Mhz, DLL can be safely enabled.
  341 + * Between 66 and 133, the DLL is enabled with an override workaround.
335 342 */
336   - get_sys_info (&sysinfo);
337   - if (sysinfo.freqSystemBus / (CFG_LBC_LCRR & 0x0f) < 66000000) {
338   - lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff) | 0x80000000;
339 343  
  344 + get_sys_info(&sysinfo);
  345 + clkdiv = lbc->lcrr & 0x0f;
  346 + lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
  347 +
  348 + if (lbc_hz < 66) {
  349 + lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
  350 +
  351 + } else if (lbc_hz >= 133) {
  352 + lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
  353 +
340 354 } else {
341 355 /*
342 356 * On REV1 boards, need to change CLKDIV before enable DLL.
343 357 * Default CLKDIV is 8, change it to 4 temporarily.
344 358 */
345   - volatile ccsr_gur_t *gur = &immap->im_gur;
346   - uint pvr = get_pvr ();
  359 + uint pvr = get_pvr();
347 360 uint temp_lbcdll = 0;
348 361  
349 362 if (pvr == PVR_85xx_REV1) {
  363 + /* FIXME: Justify the high bit here. */
350 364 lbc->lcrr = 0x10000004;
351 365 }
352 366  
353   - /* FIXME: jdl Should lcrr have 0x8000000 OR'ed in here too? */
354   - lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
355   - udelay (200);
  367 + lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);/* DLL Enabled */
  368 + udelay(200);
  369 +
  370 + /*
  371 + * Sample LBC DLL ctrl reg, upshift it to set the
  372 + * override bits.
  373 + */
356 374 temp_lbcdll = gur->lbcdllcr;
357   - gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16) | 0x80000000;
358   - asm ("sync;isync;msync");
  375 + gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
  376 + asm("sync;isync;msync");
359 377 }
  378 +}
360 379  
  380 +
  381 +/*
  382 + * Initialize SDRAM memory on the Local Bus.
  383 + */
  384 +
  385 +void
  386 +sdram_init(void)
  387 +{
  388 + volatile immap_t *immap = (immap_t *)CFG_IMMR;
  389 + volatile ccsr_lbc_t *lbc= &immap->im_lbc;
  390 + uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
  391 +
  392 + puts(" SDRAM: ");
  393 + print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
  394 +
361 395 /*
362 396 * Setup SDRAM Base and Option Registers
363 397 */
364 398 lbc->or2 = CFG_OR2_PRELIM;
365 399 lbc->br2 = CFG_BR2_PRELIM;
366 400 lbc->lbcr = CFG_LBC_LBCR;
367   - asm ("msync");
  401 + asm("msync");
368 402  
369 403 lbc->lsrt = CFG_LBC_LSRT;
370 404 lbc->mrtpr = CFG_LBC_MRTPR;
371   - asm ("sync");
  405 + asm("sync");
372 406  
373 407 /*
374 408 * Configure the SDRAM controller.
375 409 */
376 410 lbc->lsdmr = CFG_LBC_LSDMR_1;
377   - asm ("sync");
  411 + asm("sync");
378 412 *sdram_addr = 0xff;
379   - ppcDcbf ((unsigned long) sdram_addr);
380   - udelay (100);
  413 + ppcDcbf((unsigned long) sdram_addr);
  414 + udelay(100);
381 415  
382 416 lbc->lsdmr = CFG_LBC_LSDMR_2;
383   - asm ("sync");
  417 + asm("sync");
384 418 *sdram_addr = 0xff;
385   - ppcDcbf ((unsigned long) sdram_addr);
386   - udelay (100);
  419 + ppcDcbf((unsigned long) sdram_addr);
  420 + udelay(100);
387 421  
388 422 lbc->lsdmr = CFG_LBC_LSDMR_3;
389   - asm ("sync");
  423 + asm("sync");
390 424 *sdram_addr = 0xff;
391   - ppcDcbf ((unsigned long) sdram_addr);
392   - udelay (100);
  425 + ppcDcbf((unsigned long) sdram_addr);
  426 + udelay(100);
393 427  
394 428 lbc->lsdmr = CFG_LBC_LSDMR_4;
395   - asm ("sync");
  429 + asm("sync");
396 430 *sdram_addr = 0xff;
397   - ppcDcbf ((unsigned long) sdram_addr);
398   - udelay (100);
  431 + ppcDcbf((unsigned long) sdram_addr);
  432 + udelay(100);
399 433  
400 434 lbc->lsdmr = CFG_LBC_LSDMR_5;
401   - asm ("sync");
  435 + asm("sync");
402 436 *sdram_addr = 0xff;
403   - ppcDcbf ((unsigned long) sdram_addr);
404   - udelay (100);
405   -
406   -#endif
  437 + ppcDcbf((unsigned long) sdram_addr);
  438 + udelay(100);
407 439 }
408 440  
409 441  
... ... @@ -476,4 +508,42 @@
476 508 return CFG_SDRAM_SIZE * 1024 * 1024;
477 509 }
478 510 #endif /* !defined(CONFIG_SPD_EEPROM) */
  511 +
  512 +
  513 +#if defined(CONFIG_PCI)
  514 +/*
  515 + * Initialize PCI Devices, report devices found.
  516 + */
  517 +
  518 +#ifndef CONFIG_PCI_PNP
  519 +static struct pci_config_table pci_mpc85xxads_config_table[] = {
  520 + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  521 + PCI_IDSEL_NUMBER, PCI_ANY_ID,
  522 + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
  523 + PCI_ENET0_MEMADDR,
  524 + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
  525 + } },
  526 + { }
  527 +};
  528 +#endif
  529 +
  530 +
  531 +static struct pci_controller hose = {
  532 +#ifndef CONFIG_PCI_PNP
  533 + config_table: pci_mpc85xxads_config_table,
  534 +#endif
  535 +};
  536 +
  537 +#endif /* CONFIG_PCI */
  538 +
  539 +
  540 +void
  541 +pci_init_board(void)
  542 +{
  543 +#ifdef CONFIG_PCI
  544 + extern void pci_mpc85xx_init(struct pci_controller *hose);
  545 +
  546 + pci_mpc85xx_init(&hose);
  547 +#endif /* CONFIG_PCI */
  548 +}
board/stxgp3/flash.c
Diff comments   View file @ 9aea953
... ... @@ -92,14 +92,12 @@
92 92  
93 93 flash_info[0].size = size;
94 94  
95   -#if !defined(CONFIG_RAM_AS_FLASH)
96 95 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
97 96 /* monitor protection ON by default */
98 97 flash_protect(FLAG_PROTECT_SET,
99 98 CFG_MONITOR_BASE,
100 99 CFG_MONITOR_BASE+monitor_flash_len-1,
101 100 &flash_info[0]);
102   -#endif
103 101  
104 102 #ifdef CFG_ENV_IS_IN_FLASH
105 103 /* ENV protection ON by default */
1 1 /*
2   - * Copyright (C) 2003 Embedded Edge, LLC
  2 + * Copyright (C) 2004 Embedded Edge, LLC
3 3 * Dan Malek <dan@embeddededge.com>
4 4 * Copied from ADS85xx.
5 5 * Updates for Silicon Tx GP3 8560. We only support 32-bit flash
6 6 * and DDR with SPD EEPROM configuration.
7 7 *
  8 + * Copyright 2004 Freescale Semiconductor.
8 9 * Copyright (C) 2002,2003, Motorola Inc.
9 10 * Xianghua Xiao <X.Xiao@motorola.com>
10 11 *
... ... @@ -34,6 +35,24 @@
34 35 #include <config.h>
35 36 #include <mpc85xx.h>
36 37  
  38 +
  39 +/*
  40 + * TLB0 and TLB1 Entries
  41 + *
  42 + * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
  43 + * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
  44 + * these TLB entries are established.
  45 + *
  46 + * The TLB entries for DDR are dynamically setup in spd_sdram()
  47 + * and use TLB1 Entries 8 through 15 as needed according to the
  48 + * size of DDR memory.
  49 + *
  50 + * MAS0: tlbsel, esel, nv
  51 + * MAS1: valid, iprot, tid, ts, tsize
  52 + * MAS2: epn, sharen, x0, x1, w, i, m, g, e
  53 + * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
  54 + */
  55 +
37 56 #define entry_start \
38 57 mflr r1 ; \
39 58 bl 0f ;
40 59  
41 60  
42 61  
43 62  
44 63  
45 64  
46 65  
47 66  
48 67  
49 68  
50 69  
51 70  
52 71  
53 72  
54 73  
55 74  
56 75  
57 76  
58 77  
... ... @@ -43,112 +62,226 @@
43 62 mtlr r1 ; \
44 63 blr ;
45 64  
46   -/* TLB1 entries configuration: */
47 65  
48 66 .section .bootpg, "ax"
49 67 .globl tlb1_entry
50 68 tlb1_entry:
51 69 entry_start
52 70  
53   - /* If RAMBOOT, we are testing and the BDI has set up
54   - * much of the MMU already.
55   - * TLB 4,5 SDRAM
56   - * TLB 15 is default CCSRBAR.
57   - */
58   - .long 0x09 /* the following data table uses a few of 16 TLB entries */
  71 + /*
  72 + * Number of TLB0 and TLB1 entries in the following table
  73 + */
  74 + .long 13
59 75  
60   - .long TLB1_MAS0(1,1,0)
61   - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
62   - .long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
63   - .long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  76 +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
  77 + /*
  78 + * TLB0 4K Non-cacheable, guarded
  79 + * 0xff700000 4K Initial CCSRBAR mapping
  80 + *
  81 + * This ends up at a TLB0 Index==0 entry, and must not collide
  82 + * with other TLB0 Entries.
  83 + */
  84 + .long TLB1_MAS0(0, 0, 0)
  85 + .long TLB1_MAS1(1, 0, 0, 0, 0)
  86 + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
  87 + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
  88 +#else
  89 +#error("Update the number of table entries in tlb1_entry")
  90 +#endif
64 91  
65   - .long TLB1_MAS0(1,2,0)
66   - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16M)
67   - .long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
68   - .long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  92 + /*
  93 + * TLB0 16K Cacheable, non-guarded
  94 + * 0xd001_0000 16K Temporary Global data for initialization
  95 + *
  96 + * Use four 4K TLB0 entries. These entries must be cacheable
  97 + * as they provide the bootstrap memory before the memory
  98 + * controler and real memory have been configured.
  99 + *
  100 + * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
  101 + * and must not collide with other TLB0 entries.
  102 + */
  103 + .long TLB1_MAS0(0, 0, 0)
  104 + .long TLB1_MAS1(1, 0, 0, 0, 0)
  105 + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), \
  106 + 0,0,0,0,0,0,0,0)
  107 + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), \
  108 + 0,0,0,0,0,1,0,1,0,1)
69 109  
70   - .long TLB1_MAS0(1,3,0)
71   - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
72   - .long TLB1_MAS2(((CFG_LBC_LCLDEVS_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
73   - .long TLB1_MAS3(((CFG_LBC_LCLDEVS_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
74   - .long TLB1_MAS0(1,4,0)
75   - .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
76   - .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
77   - .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
  110 + .long TLB1_MAS0(0, 0, 0)
  111 + .long TLB1_MAS1(1, 0, 0, 0, 0)
  112 + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), \
  113 + 0,0,0,0,0,0,0,0)
  114 + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), \
  115 + 0,0,0,0,0,1,0,1,0,1)
78 116  
79   - .long TLB1_MAS0(1,5,0)
80   - .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
81   - .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
82   - .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
  117 + .long TLB1_MAS0(0, 0, 0)
  118 + .long TLB1_MAS1(1, 0, 0, 0, 0)
  119 + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), \
  120 + 0,0,0,0,0,0,0,0)
  121 + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), \
  122 + 0,0,0,0,0,1,0,1,0,1)
83 123  
84   - .long TLB1_MAS0(1,6,0)
85   - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
86   -#if defined(CONFIG_RAM_AS_FLASH)
87   - .long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
88   -#else
89   - .long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
90   -#endif
91   - .long TLB1_MAS3(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  124 + .long TLB1_MAS0(0, 0, 0)
  125 + .long TLB1_MAS1(1, 0, 0, 0, 0)
  126 + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), \
  127 + 0,0,0,0,0,0,0,0)
  128 + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), \
  129 + 0,0,0,0,0,1,0,1,0,1)
92 130  
93   - .long TLB1_MAS0(1,7,0)
94   - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
95   -#ifdef CONFIG_L2_INIT_RAM
96   - .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0)
97   -#else
98   - .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0)
99   -#endif
100   - .long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
101 131  
102   - .long TLB1_MAS0(1,8,0)
103   - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
104   - .long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
105   - .long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  132 + /*
  133 + * TLB 0: 16M Non-cacheable, guarded
  134 + * 0xff000000 16M FLASH
  135 + * Out of reset this entry is only 4K.
  136 + */
  137 + .long TLB1_MAS0(1, 0, 0)
  138 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
  139 + .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
  140 + .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
106 141  
107   -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
108   - .long TLB1_MAS0(1,15,0)
109   - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
110   - .long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
111   - .long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
112   -#else
113   - .long TLB1_MAS0(1,15,0)
114   - .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
115   - .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
116   - .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
  142 + /*
  143 + * TLB 1: 256M Non-cacheable, guarded
  144 + * 0x80000000 256M PCI1 MEM First half
  145 + */
  146 + .long TLB1_MAS0(1, 1, 0)
  147 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
  148 + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
  149 + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
  150 +
  151 + /*
  152 + * TLB 2: 256M Non-cacheable, guarded
  153 + * 0x90000000 256M PCI1 MEM Second half
  154 + */
  155 + .long TLB1_MAS0(1, 2, 0)
  156 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
  157 + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), \
  158 + 0,0,0,0,1,0,1,0)
  159 + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), \
  160 + 0,0,0,0,0,1,0,1,0,1)
  161 +
  162 + /*
  163 + * TLB 3: 256M Non-cacheable, guarded
  164 + * 0xc0000000 256M Rapid IO MEM First half
  165 + */
  166 + .long TLB1_MAS0(1, 3, 0)
  167 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
  168 + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
  169 + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
  170 +
  171 + /*
  172 + * TLB 4: 256M Non-cacheable, guarded
  173 + * 0xd0000000 256M Rapid IO MEM Second half
  174 + */
  175 + .long TLB1_MAS0(1, 4, 0)
  176 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
  177 + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000), \
  178 + 0,0,0,0,1,0,1,0)
  179 + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000), \
  180 + 0,0,0,0,0,1,0,1,0,1)
  181 +
  182 + /*
  183 + * TLB 5: 64M Non-cacheable, guarded
  184 + * 0xe000_0000 1M CCSRBAR
  185 + * 0xe200_0000 16M PCI1 IO
  186 + */
  187 + .long TLB1_MAS0(1, 5, 0)
  188 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
  189 + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
  190 + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
  191 +
  192 + /*
  193 + * TLB 6: 64M Cacheable, non-guarded
  194 + * 0xf000_0000 64M LBC SDRAM
  195 + */
  196 + .long TLB1_MAS0(1, 6, 0)
  197 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
  198 + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
  199 + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
  200 +
  201 + /*
  202 + * TLB 7: 16K Non-cacheable, guarded
  203 + * 0xfc000000 16K Configuration Latch register
  204 + */
  205 + .long TLB1_MAS0(1, 7, 0)
  206 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64K)
  207 + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_LCLDEVS_BASE), 0,0,0,0,1,0,1,0)
  208 + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_LCLDEVS_BASE), 0,0,0,0,0,1,0,1,0,1)
  209 +
  210 +#if !defined(CONFIG_SPD_EEPROM)
  211 + /*
  212 + * TLB 8, 9: 128M DDR
  213 + * 0x00000000 64M DDR System memory
  214 + * 0x04000000 64M DDR System memory
  215 + * Without SPD EEPROM configured DDR, this must be setup manually.
  216 + * Make sure the TLB count at the top of this table is correct.
  217 + * Likely it needs to be increased by two for these entries.
  218 + */
  219 +#error("Update the number of table entries in tlb1_entry")
  220 + .long TLB1_MAS0(1, 8, 0)
  221 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
  222 + .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
  223 + .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
  224 +
  225 + .long TLB1_MAS0(1, 9, 0)
  226 + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
  227 + .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000),
  228 + 0,0,0,0,0,0,0,0)
  229 + .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000),
  230 + 0,0,0,0,0,1,0,1,0,1)
117 231 #endif
  232 +
118 233 entry_end
119 234  
120   -/* LAW(Local Access Window) configuration:
121   - * 0000_0000-8000_0000: Up to 2G DDR
122   - * f000_0000-f3ff_ffff: PCI(256M)
123   - * f400_0000-f7ff_ffff: RapidIO(128M)
124   - * f800_0000-ffff_ffff: localbus(128M)
125   - * f800_0000-fbff_ffff: LBC SDRAM(64M)
126   - * fc00_0000-fcff_ffff: LBC BCSR (1M, Chip select 1)
127   - * fdf0_0000-fdff_ffff: CCSRBAR(1M)
128   - * ff00_0000-ffff_ffff: Flash(16M)
129   - * We don't need a local window for CCSRBAR and flash because they
130   - * reside in their default mapped spaces.
  235 +/*
  236 + * LAW(Local Access Window) configuration:
  237 + *
  238 + * 0x0000_0000 0x7fff_ffff DDR 2G
  239 + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
  240 + * 0xc000_0000 0xdfff_ffff RapidIO 512M
  241 + * 0xe000_0000 0xe000_ffff CCSR 1M
  242 + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
  243 + * 0xf000_0000 0xf7ff_ffff SDRAM 128M
  244 + * 0xfc00_0000 0xfc00_ffff Config Latch 64K
  245 + * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M
  246 + *
  247 + * Notes:
  248 + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
  249 + * If flash is 8M at default position (last 8M), no LAW needed.
131 250 */
132 251  
  252 +#if !defined(CONFIG_SPD_EEPROM)
  253 +#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
  254 +#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
  255 +#else
133 256 #define LAWBAR0 0
134   -#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_2G)) & ~LAWAR_EN)
  257 +#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
  258 +#endif
135 259  
136   -#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff)
137   -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M))
  260 +#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
  261 +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
138 262  
139   -#if !defined(CONFIG_RAM_AS_FLASH)
  263 +/*
  264 + * This is not so much the SDRAM map as it is the whole localbus map.
  265 + */
140 266 #define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
141   -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M))
142   -#else
143   -#define LAWBAR2 0
144   -#define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
145   -#endif
  267 +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
146 268  
  269 +#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
  270 +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))
  271 +
  272 +/*
  273 + * Rapid IO at 0xc000_0000 for 512 M
  274 + */
  275 +#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
  276 +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
  277 +
  278 +
147 279 .section .bootpg, "ax"
148   - .globl law_entry
  280 + .globl law_entry
149 281 law_entry:
150 282 entry_start
151   - .long 0x03
152   - .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2
  283 + .long 0x05
  284 + .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
  285 + .long LAWBAR4,LAWAR4
153 286 entry_end
board/stxgp3/stxgp3.c
Diff comments   View file @ 9aea953
... ... @@ -32,6 +32,7 @@
32 32 extern long int spd_sdram (void);
33 33  
34 34 #include <common.h>
  35 +#include <pci.h>
35 36 #include <asm/processor.h>
36 37 #include <asm/immap_85xx.h>
37 38 #include <ioports.h>
... ... @@ -198,7 +199,8 @@
198 199 static uint64_t next_led_update;
199 200 static uint led_bit;
200 201  
201   -int board_pre_init (void)
  202 +int
  203 +board_early_init_f(void)
202 204 {
203 205 #if defined(CONFIG_PCI)
204 206 volatile immap_t *immr = (immap_t *)CFG_IMMR;
... ... @@ -209,7 +211,8 @@
209 211 return 0;
210 212 }
211 213  
212   -void reset_phy (void)
  214 +void
  215 +reset_phy(void)
213 216 {
214 217 volatile uint *blatch;
215 218  
216 219  
217 220  
... ... @@ -243,25 +246,10 @@
243 246 #endif
244 247 }
245 248  
246   -int checkboard (void)
  249 +int
  250 +checkboard(void)
247 251 {
248   - sys_info_t sysinfo;
249   -
250   - get_sys_info (&sysinfo);
251   -
252 252 printf ("Board: Silicon Tx GPPP 8560 Board\n");
253   - printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
254   - printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
255   - printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
256   - if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
257   - || (CFG_LBC_LCRR & 0x0f) == 8) {
258   - printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CFG_LBC_LCRR & 0x0f));
259   - } else {
260   - printf("\tLBC: unknown\n");
261   - }
262   - printf("\tCPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
263   - printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
264   -
265 253 return (0);
266 254 }
267 255  
268 256  
269 257  
270 258  
... ... @@ -285,68 +273,31 @@
285 273 next_led_update += (get_tbclk() / 4);
286 274 }
287 275  
288   -long int initdram (int board_type)
  276 +long int
  277 +initdram (int board_type)
289 278 {
290 279 long dram_size = 0;
291 280 extern long spd_sdram (void);
292 281 volatile immap_t *immap = (immap_t *)CFG_IMMR;
293 282  
294 283 #if defined(CONFIG_DDR_DLL)
295   - volatile ccsr_gur_t *gur= &immap->im_gur;
296   - uint temp_ddrdll = 0;
  284 + {
  285 + volatile ccsr_gur_t *gur= &immap->im_gur;
  286 + uint temp_ddrdll = 0;
297 287  
298   - /* Work around to stabilize DDR DLL */
299   - temp_ddrdll = gur->ddrdllcr;
300   - gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
301   - asm("sync;isync;msync");
  288 + /* Work around to stabilize DDR DLL */
  289 + temp_ddrdll = gur->ddrdllcr;
  290 + gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
  291 + asm("sync;isync;msync");
  292 + }
302 293 #endif
303 294  
304 295 dram_size = spd_sdram ();
305 296  
306 297 #if defined(CONFIG_DDR_ECC)
307   - {
308   - /* Initialize all of memory for ECC, then
309   - * enable errors */
310   - uint *p = 0;
311   - uint i = 0;
312   - volatile immap_t *immap = (immap_t *)CFG_IMMR;
313   - volatile ccsr_ddr_t *ddr= &immap->im_ddr;
314   - dma_init();
315   - for (*p = 0; p < (uint *)(8 * 1024); p++) {
316   - if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
317   - *p = (unsigned int)0xdeadbeef;
318   - if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
319   - }
320   -
321   - /* 8K */
322   - dma_xfer((uint *)0x2000,0x2000,(uint *)0);
323   - /* 16K */
324   - dma_xfer((uint *)0x4000,0x4000,(uint *)0);
325   - /* 32K */
326   - dma_xfer((uint *)0x8000,0x8000,(uint *)0);
327   - /* 64K */
328   - dma_xfer((uint *)0x10000,0x10000,(uint *)0);
329   - /* 128k */
330   - dma_xfer((uint *)0x20000,0x20000,(uint *)0);
331   - /* 256k */
332   - dma_xfer((uint *)0x40000,0x40000,(uint *)0);
333   - /* 512k */
334   - dma_xfer((uint *)0x80000,0x80000,(uint *)0);
335   - /* 1M */
336   - dma_xfer((uint *)0x100000,0x100000,(uint *)0);
337   - /* 2M */
338   - dma_xfer((uint *)0x200000,0x200000,(uint *)0);
339   - /* 4M */
340   - dma_xfer((uint *)0x400000,0x400000,(uint *)0);
341   -
342   - for (i = 1; i < dram_size / 0x800000; i++) {
343   - dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
344   - }
345   -
346   - /* Enable errors for ECC */
347   - ddr->err_disable = 0x00000000;
348   - asm("sync;isync;msync");
349   - }
  298 + /* Initialize and enable DDR ECC.
  299 + */
  300 + ddr_enable_ecc(dram_size);
350 301 #endif
351 302  
352 303 return dram_size;
353 304  
354 305  
355 306  
... ... @@ -387,38 +338,41 @@
387 338 }
388 339 #endif
389 340  
390   -#if !defined(CONFIG_SPD_EEPROM)
391   -/*************************************************************************
392   - * fixed sdram init -- doesn't use serial presence detect.
393   - ************************************************************************/
394   -long int fixed_sdram (void)
  341 +#if defined(CONFIG_PCI)
  342 +
  343 +/*
  344 + * Initialize PCI Devices, report devices found.
  345 + */
  346 +
  347 +#ifndef CONFIG_PCI_PNP
  348 +static struct pci_config_table pci_stxgp3_config_table[] = {
  349 + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  350 + PCI_IDSEL_NUMBER, PCI_ANY_ID,
  351 + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
  352 + PCI_ENET0_MEMADDR,
  353 + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
  354 + } },
  355 + { }
  356 +};
  357 +#endif
  358 +
  359 +
  360 +static struct pci_controller hose = {
  361 +#ifndef CONFIG_PCI_PNP
  362 + config_table: pci_stxgp3_config_table,
  363 +#endif
  364 +};
  365 +
  366 +#endif /* CONFIG_PCI */
  367 +
  368 +
  369 +void
  370 +pci_init_board(void)
395 371 {
396   - #ifndef CFG_RAMBOOT
397   - volatile immap_t *immap = (immap_t *)CFG_IMMR;
398   - volatile ccsr_ddr_t *ddr= &immap->im_ddr;
  372 +#ifdef CONFIG_PCI
  373 + extern void pci_mpc85xx_init(struct pci_controller *hose);
399 374  
400   - ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
401   - ddr->cs0_config = CFG_DDR_CS0_CONFIG;
402   - ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
403   - ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
404   - ddr->sdram_mode = CFG_DDR_MODE;
405   - ddr->sdram_interval = CFG_DDR_INTERVAL;
406   - #if defined (CONFIG_DDR_ECC)
407   - ddr->err_disable = 0x0000000D;
408   - ddr->err_sbe = 0x00ff0000;
409   - #endif
410   - asm("sync;isync;msync");
411   - udelay(500);
412   - #if defined (CONFIG_DDR_ECC)
413   - /* Enable ECC checking */
414   - ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
415   - #else
416   - ddr->sdram_cfg = CFG_DDR_CONTROL;
417   - #endif
418   - asm("sync; isync; msync");
419   - udelay(500);
420   - #endif
421   - return ( CFG_SDRAM_SIZE * 1024 * 1024);
  375 + pci_mpc85xx_init(&hose);
  376 +#endif /* CONFIG_PCI */
422 377 }
423   -#endif /* !defined(CONFIG_SPD_EEPROM) */
... ... @@ -32,34 +32,10 @@
32 32  
33 33 #if defined(CONFIG_PCI)
34 34  
35   -
36   -/*
37   - * Initialize PCI Devices, report devices found.
38   - */
39   -
40   -#ifndef CONFIG_PCI_PNP
41   -static struct pci_config_table pci_mpc85xxads_config_table[] = {
42   - {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
43   - PCI_IDSEL_NUMBER, PCI_ANY_ID,
44   - pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
45   - PCI_ENET0_MEMADDR,
46   - PCI_COMMAND_MEMORY |
47   - PCI_COMMAND_MASTER}},
48   - {}
49   -};
50   -#endif
51   -
52   -struct pci_controller local_hose = {
53   -#ifndef CONFIG_PCI_PNP
54   - config_table: pci_mpc85xxads_config_table,
55   -#endif
56   -};
57   -
58   -
59   -void pci_init_board (void)
  35 +void
  36 +pci_mpc85xx_init(struct pci_controller *hose)
60 37 {
61   - struct pci_controller *hose = (struct pci_controller *) &local_hose;
62   - volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
  38 + volatile immap_t *immap = (immap_t *)CFG_CCSRBAR;
63 39 volatile ccsr_pcix_t *pcix = &immap->im_pcix;
64 40  
65 41 u16 reg16;
66 42  
67 43  
68 44  
69 45  
70 46  
71 47  
72 48  
73 49  
74 50  
... ... @@ -67,39 +43,45 @@
67 43 hose->first_busno = 0;
68 44 hose->last_busno = 0xff;
69 45  
70   - pci_set_region (hose->regions + 0,
71   - CFG_PCI1_MEM_BASE,
72   - CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_SIZE, PCI_REGION_MEM);
  46 + pci_set_region(hose->regions + 0,
  47 + CFG_PCI1_MEM_BASE,
  48 + CFG_PCI1_MEM_PHYS,
  49 + CFG_PCI1_MEM_SIZE,
  50 + PCI_REGION_MEM);
73 51  
74   - pci_set_region (hose->regions + 1,
75   - CFG_PCI1_IO_BASE,
76   - CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
  52 + pci_set_region(hose->regions + 1,
  53 + CFG_PCI1_IO_BASE,
  54 + CFG_PCI1_IO_PHYS,
  55 + CFG_PCI1_IO_SIZE,
  56 + PCI_REGION_IO);
77 57  
78 58 hose->region_count = 2;
79 59  
80   - pci_setup_indirect (hose, (CFG_IMMR + 0x8000), (CFG_IMMR + 0x8004));
  60 + pci_setup_indirect(hose,
  61 + (CFG_IMMR+0x8000),
  62 + (CFG_IMMR+0x8004));
81 63  
82   - pci_read_config_word (PCI_BDF (0, 0, 0), PCI_COMMAND, &reg16);
  64 + pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
83 65 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
84   - pci_write_config_word (PCI_BDF (0, 0, 0), PCI_COMMAND, reg16);
  66 + pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
85 67  
86 68 /*
87 69 * Clear non-reserved bits in status register.
88 70 */
89   - pci_write_config_word (PCI_BDF (0, 0, 0), PCI_STATUS, 0xffff);
90   - pci_write_config_byte (PCI_BDF (0, 0, 0), PCI_LATENCY_TIMER, 0x80);
  71 + pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
  72 + pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
91 73  
92   - pcix->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
93   - pcix->potear1 = 0x00000000;
94   - pcix->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
  74 + pcix->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
  75 + pcix->potear1 = 0x00000000;
  76 + pcix->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
95 77 pcix->powbear1 = 0x00000000;
96   - pcix->powar1 = 0x8004401c; /* 512M MEM space */
  78 + pcix->powar1 = 0x8004401c; /* 512M MEM space */
97 79  
98   - pcix->potar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
99   - pcix->potear2 = 0x00000000;
100   - pcix->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
  80 + pcix->potar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
  81 + pcix->potear2 = 0x00000000;
  82 + pcix->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
101 83 pcix->powbear2 = 0x00000000;
102   - pcix->powar2 = 0x80088017; /* 16M IO space */
  84 + pcix->powar2 = 0x80088017; /* 16M IO space */
103 85  
104 86 pcix->pitar1 = 0x00000000;
105 87 pcix->piwbar1 = 0x00000000;
... ... @@ -108,8 +90,8 @@
108 90 /*
109 91 * Hose scan.
110 92 */
111   - pci_register_hose (hose);
112   - hose->last_busno = pci_hose_scan (hose);
  93 + pci_register_hose(hose);
  94 + hose->last_busno = pci_hose_scan(hose);
113 95 }
114 96  
115 97 #endif /* CONFIG_PCI */
cpu/mpc85xx/spd_sdram.c
Diff comments   View file @ 9aea953
... ... @@ -30,133 +30,171 @@
30 30  
31 31 #ifdef CONFIG_SPD_EEPROM
32 32  
33   -#define ns2clk(ns) ((ns) / (2000000000 /get_bus_freq(0) + 1) + 1)
34 33  
35   -long int spd_sdram(void) {
36   - volatile immap_t *immap = (immap_t *)CFG_IMMR;
37   - volatile ccsr_ddr_t *ddr = &immap->im_ddr;
  34 +#if defined(CONFIG_DDR_ECC)
  35 +extern void dma_init(void);
  36 +extern uint dma_check(void);
  37 +extern int dma_xfer(void *dest, uint count, void *src);
  38 +#endif
  39 +
  40 +
  41 +#ifndef CFG_READ_SPD
  42 +#define CFG_READ_SPD i2c_read
  43 +#endif
  44 +
  45 +
  46 +/*
  47 + * Convert picoseconds into clock cycles (rounding up if needed).
  48 + */
  49 +
  50 +int
  51 +picos_to_clk(int picos)
  52 +{
  53 + int clks;
  54 +
  55 + clks = picos / (2000000000 / (get_bus_freq(0) / 1000));
  56 + if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) {
  57 + clks++;
  58 + }
  59 +
  60 + return clks;
  61 +}
  62 +
  63 +
  64 +unsigned int
  65 +banksize(unsigned char row_dens)
  66 +{
  67 + return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
  68 +}
  69 +
  70 +
  71 +long int
  72 +spd_sdram(void)
  73 +{
  74 + volatile immap_t *immap = (immap_t *)CFG_IMMR;
  75 + volatile ccsr_ddr_t *ddr = &immap->im_ddr;
38 76 volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
39   - spd_eeprom_t spd;
40   - unsigned int memsize,tmp,tmp1,tmp2;
  77 + spd_eeprom_t spd;
  78 + unsigned tmp, tmp1;
  79 + unsigned int memsize;
  80 + unsigned int tlb_size;
  81 + unsigned int law_size;
41 82 unsigned char caslat;
  83 + unsigned int ram_tlb_index;
  84 + unsigned int ram_tlb_address;
42 85  
43   - i2c_read (SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
  86 + CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
44 87  
45   - if ( spd.nrows > 2 ) {
46   - printf("DDR:Only two chip selects are supported on ADS.\n");
  88 + if (spd.nrows > 2) {
  89 + puts("DDR:Only two chip selects are supported on ADS.\n");
47 90 return 0;
48 91 }
49 92  
50   - if ( spd.nrow_addr < 12 || spd.nrow_addr > 14 || spd.ncol_addr < 8 || spd.ncol_addr > 11) {
51   - printf("DDR:Row or Col number unsupported.\n");
  93 + if (spd.nrow_addr < 12
  94 + || spd.nrow_addr > 14
  95 + || spd.ncol_addr < 8
  96 + || spd.ncol_addr > 11) {
  97 + puts("DDR:Row or Col number unsupported.\n");
52 98 return 0;
53 99 }
54 100  
55   - ddr->cs0_bnds = ((spd.row_dens>>2) - 1);
56   - ddr->cs0_config = ( 1<<31 | (spd.nrow_addr-12)<<8 | (spd.ncol_addr-8) );
57   - debug ("\n");
58   - debug ("cs0_bnds = 0x%08x\n",ddr->cs0_bnds);
59   - debug ("cs0_config = 0x%08x\n",ddr->cs0_config);
60   - if ( spd.nrows == 2 ) {
61   - ddr->cs1_bnds = ((spd.row_dens<<14) | ((spd.row_dens>>1) - 1));
62   - ddr->cs1_config = ( 1<<31 | (spd.nrow_addr-12)<<8 | (spd.ncol_addr-8) );
63   - debug ("cs1_bnds = 0x%08x\n",ddr->cs1_bnds);
64   - debug ("cs1_config = 0x%08x\n",ddr->cs1_config);
  101 + ddr->cs0_bnds = (banksize(spd.row_dens) >> 24) - 1;
  102 + ddr->cs0_config = ( 1 << 31
  103 + | (spd.nrow_addr - 12) << 8
  104 + | (spd.ncol_addr - 8) );
  105 + debug("\n");
  106 + debug("cs0_bnds = 0x%08x\n",ddr->cs0_bnds);
  107 + debug("cs0_config = 0x%08x\n",ddr->cs0_config);
  108 +
  109 + if (spd.nrows == 2) {
  110 + ddr->cs1_bnds = ( (banksize(spd.row_dens) >> 8)
  111 + | ((banksize(spd.row_dens) >> 23) - 1) );
  112 + ddr->cs1_config = ( 1<<31
  113 + | (spd.nrow_addr-12) << 8
  114 + | (spd.ncol_addr-8) );
  115 + debug("cs1_bnds = 0x%08x\n",ddr->cs1_bnds);
  116 + debug("cs1_config = 0x%08x\n",ddr->cs1_config);
65 117 }
66 118  
67   - memsize = spd.nrows * (4 * spd.row_dens);
68   - if( spd.mem_type != 0x07 ) {
69   - printf("No DDR module found!\n");
  119 + if (spd.mem_type != 0x07) {
  120 + puts("No DDR module found!\n");
70 121 return 0;
71 122 }
72 123  
  124 + /*
  125 + * Figure out memory size in Megabytes.
  126 + */
  127 + memsize = spd.nrows * banksize(spd.row_dens) / 0x100000;
  128 +
  129 + /*
  130 + * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. Fnord.
  131 + */
  132 + law_size = 19 + __ilog2(memsize);
  133 +
  134 + /*
  135 + * Determine size of each TLB1 entry.
  136 + */
73 137 switch (memsize) {
74 138 case 16:
75   - tmp = 7; /* TLB size */
76   - tmp1 = 1; /* TLB entry number */
77   - tmp2 = 23; /* Local Access Window size */
78   - break;
79 139 case 32:
80   - tmp = 7;
81   - tmp1 = 2;
82   - tmp2 = 24;
  140 + tlb_size = BOOKE_PAGESZ_16M;
83 141 break;
84 142 case 64:
85   - tmp = 8;
86   - tmp1 = 1;
87   - tmp2 = 25;
88   - break;
89 143 case 128:
90   - tmp = 8;
91   - tmp1 = 2;
92   - tmp2 = 26;
  144 + tlb_size = BOOKE_PAGESZ_64M;
93 145 break;
94 146 case 256:
95   - tmp = 9;
96   - tmp1 = 1;
97   - tmp2 = 27;
98   - break;
99 147 case 512:
100   - tmp = 9;
101   - tmp1 = 2;
102   - tmp2 = 28;
103   - break;
104 148 case 1024:
105   - tmp = 10;
106   - tmp1 = 1;
107   - tmp2 = 29;
  149 + case 2048:
  150 + tlb_size = BOOKE_PAGESZ_256M;
108 151 break;
109 152 default:
110   - printf ("DDR:we only added support 16M,32M,64M,128M,256M,512M and 1G DDR I.\n");
  153 + puts("DDR: only 16M,32M,64M,128M,256M,512M,1G and 2G DDR I are supported.\n");
111 154 return 0;
112 155 break;
113 156 }
114 157  
115   - /* configure DDR TLB to TLB1 Entry 4,5 */
116   - mtspr(MAS0, TLB1_MAS0(1,4,0));
117   - mtspr(MAS1, TLB1_MAS1(1,1,0,0,tmp));
118   - mtspr(MAS2, TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0));
119   - mtspr(MAS3, TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1));
120   - asm volatile("isync;msync;tlbwe;isync");
121   - debug ("DDR:MAS0=0x%08x\n",TLB1_MAS0(1,4,0));
122   - debug ("DDR:MAS1=0x%08x\n",TLB1_MAS1(1,1,0,0,tmp));
123   - debug ("DDR:MAS2=0x%08x\n",TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) \
124   - & 0xfffff),0,0,0,0,0,0,0,0));
125   - debug ("DDR:MAS3=0x%08x\n",TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) \
126   - & 0xfffff),0,0,0,0,0,1,0,1,0,1));
127   -
128   - if(tmp1 == 2) {
129   - mtspr(MAS0, TLB1_MAS0(1,5,0));
130   - mtspr(MAS1, TLB1_MAS1(1,1,0,0,tmp));
131   - mtspr(MAS2, TLB1_MAS2((((CFG_DDR_SDRAM_BASE+(memsize*1024*1024)/2)>>12) \
132   - & 0xfffff),0,0,0,0,0,0,0,0));
133   - mtspr(MAS3, TLB1_MAS3((((CFG_DDR_SDRAM_BASE+(memsize*1024*1024)/2)>>12) \
134   - & 0xfffff),0,0,0,0,0,1,0,1,0,1));
  158 + /*
  159 + * Configure DDR TLB1 entries.
  160 + * Starting at TLB1 8, use no more than 8 TLB1 entries.
  161 + */
  162 + ram_tlb_index = 8;
  163 + ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE;
  164 + while (ram_tlb_address < (memsize * 1024 * 1024)
  165 + && ram_tlb_index < 16) {
  166 + mtspr(MAS0, TLB1_MAS0(1, ram_tlb_index, 0));
  167 + mtspr(MAS1, TLB1_MAS1(1, 1, 0, 0, tlb_size));
  168 + mtspr(MAS2, TLB1_MAS2(E500_TLB_EPN(ram_tlb_address),
  169 + 0, 0, 0, 0, 0, 0, 0, 0));
  170 + mtspr(MAS3, TLB1_MAS3(E500_TLB_RPN(ram_tlb_address),
  171 + 0, 0, 0, 0, 0, 1, 0, 1, 0, 1));
135 172 asm volatile("isync;msync;tlbwe;isync");
136   - debug ("DDR:MAS0=0x%08x\n",TLB1_MAS0(1,5,0));
137   - debug ("DDR:MAS1=0x%08x\n",TLB1_MAS1(1,1,0,0,tmp));
138   - debug ("DDR:MAS2=0x%08x\n",TLB1_MAS2((((CFG_DDR_SDRAM_BASE \
139   - +(memsize*1024*1024)/2)>>12) & 0xfffff),0,0,0,0,0,0,0,0));
140   - debug ("DDR:MAS3=0x%08x\n",TLB1_MAS3((((CFG_DDR_SDRAM_BASE \
141   - +(memsize*1024*1024)/2)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1));
  173 +
  174 + debug("DDR:MAS0=0x%08x\n", TLB1_MAS0(1, ram_tlb_index, 0));
  175 + debug("DDR:MAS1=0x%08x\n", TLB1_MAS1(1, 1, 0, 0, tlb_size));
  176 + debug("DDR:MAS2=0x%08x\n",
  177 + TLB1_MAS2(E500_TLB_EPN(ram_tlb_address),
  178 + 0, 0, 0, 0, 0, 0, 0, 0));
  179 + debug("DDR:MAS3=0x%08x\n",
  180 + TLB1_MAS3(E500_TLB_RPN(ram_tlb_address),
  181 + 0, 0, 0, 0, 0, 1, 0, 1, 0, 1));
  182 +
  183 + ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2));
  184 + ram_tlb_index++;
142 185 }
143 186  
144   -#if defined(CONFIG_RAM_AS_FLASH)
145   - ecm->lawbar2 = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
146   - ecm->lawar2 = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & tmp2));
147   - debug ("DDR:LAWBAR2=0x%08x\n",ecm->lawbar2);
148   - debug ("DDR:LARAR2=0x%08x\n",ecm->lawar2);
149   -#else
  187 + /*
  188 + * Set up LAWBAR for all of DDR.
  189 + */
150 190 ecm->lawbar1 = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
151   - ecm->lawar1 = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & tmp2));
152   - debug ("DDR:LAWBAR1=0x%08x\n",ecm->lawbar1);
153   - debug ("DDR:LARAR1=0x%08x\n",ecm->lawar1);
154   -#endif
  191 + ecm->lawar1 = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
  192 + debug("DDR:LAWBAR1=0x%08x\n", ecm->lawbar1);
  193 + debug("DDR:LARAR1=0x%08x\n", ecm->lawar1);
155 194  
156   - tmp = 20000/(((spd.clk_cycle & 0xF0) >> 4) * 10 + (spd.clk_cycle & 0x0f));
157   - debug ("DDR:Module maximum data rate is: %dMhz\n",tmp);
158   -
159   - /* find the largest CAS */
  195 + /*
  196 + * find the largest CAS
  197 + */
160 198 if(spd.cas_lat & 0x40) {
161 199 caslat = 7;
162 200 } else if (spd.cas_lat & 0x20) {
163 201  
164 202  
165 203  
166 204  
167 205  
168 206  
169 207  
170 208  
... ... @@ -172,46 +210,65 @@
172 210 } else if (spd.cas_lat & 0x01) {
173 211 caslat = 1;
174 212 } else {
175   - printf("DDR:no valid CAS Latency information.\n");
  213 + puts("DDR:no valid CAS Latency information.\n");
176 214 return 0;
177 215 }
178 216  
179   - tmp1 = get_bus_freq(0)/1000000;
180   - if(tmp1<230 && tmp1>=90 && tmp>=230) {
  217 + tmp = 20000 / (((spd.clk_cycle & 0xF0) >> 4) * 10
  218 + + (spd.clk_cycle & 0x0f));
  219 + debug("DDR:Module maximum data rate is: %dMhz\n", tmp);
  220 +
  221 + tmp1 = get_bus_freq(0) / 1000000;
  222 + if (tmp1 < 230 && tmp1 >= 90 && tmp >= 230) {
181 223 /* 90~230 range, treated as DDR 200 */
182   - if(spd.clk_cycle3 == 0xa0) caslat -= 2;
183   - else if(spd.clk_cycle2 == 0xa0) caslat--;
184   - } else if(tmp1<280 && tmp1>=230 && tmp>=280) {
  224 + if (spd.clk_cycle3 == 0xa0)
  225 + caslat -= 2;
  226 + else if(spd.clk_cycle2 == 0xa0)
  227 + caslat--;
  228 + } else if (tmp1 < 280 && tmp1 >= 230 && tmp >= 280) {
185 229 /* 230-280 range, treated as DDR 266 */
186   - if(spd.clk_cycle3 == 0x75) caslat -= 2;
187   - else if(spd.clk_cycle2 == 0x75) caslat--;
188   - } else if(tmp1<350 && tmp1>=280 && tmp>=350) {
  230 + if (spd.clk_cycle3 == 0x75)
  231 + caslat -= 2;
  232 + else if (spd.clk_cycle2 == 0x75)
  233 + caslat--;
  234 + } else if (tmp1 < 350 && tmp1 >= 280 && tmp >= 350) {
189 235 /* 280~350 range, treated as DDR 333 */
190   - if(spd.clk_cycle3 == 0x60) caslat -= 2;
191   - else if(spd.clk_cycle2 == 0x60) caslat--;
192   - } else if(tmp1<90 || tmp1 >=350) { /* DDR rate out-of-range */
193   - printf("DDR:platform frequency is not fit for DDR rate\n");
  236 + if (spd.clk_cycle3 == 0x60)
  237 + caslat -= 2;
  238 + else if (spd.clk_cycle2 == 0x60)
  239 + caslat--;
  240 + } else if (tmp1 < 90 || tmp1 >= 350) {
  241 + /* DDR rate out-of-range */
  242 + puts("DDR:platform frequency is not fit for DDR rate\n");
194 243 return 0;
195 244 }
196 245  
197   - /* note: caslat must also be programmed into ddr->sdram_mode
198   - register */
199   - /* note: WRREC(Twr) and WRTORD(Twtr) are not in SPD,use
200   - conservative value here */
201   - ddr->timing_cfg_1 = (((ns2clk(spd.trp/4) & 0x07) << 28 ) | \
202   - ((ns2clk(spd.tras) & 0x0f ) << 24 ) | \
203   - ((ns2clk(spd.trcd/4) & 0x07) << 20 ) | \
204   - ((caslat & 0x07)<< 16 ) | \
205   - (((ns2clk(spd.sset[6]) - 8) & 0x0f) << 12 ) | \
206   - ( 0x300 ) | \
207   - ((ns2clk(spd.trrd/4) & 0x07) << 4) | 1);
  246 + /*
  247 + * note: caslat must also be programmed into ddr->sdram_mode
  248 + * register.
  249 + *
  250 + * note: WRREC(Twr) and WRTORD(Twtr) are not in SPD,
  251 + * use conservative value here.
  252 + */
  253 + ddr->timing_cfg_1 =
  254 + (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) |
  255 + ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) |
  256 + ((picos_to_clk(spd.trcd * 250) & 0x07) << 20 ) |
  257 + ((caslat & 0x07) << 16 ) |
  258 + (((picos_to_clk(spd.sset[6] * 1000) - 8) & 0x0f) << 12 ) |
  259 + ( 0x300 ) |
  260 + ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | 1);
208 261  
209   - debug ("DDR:timing_cfg_1=0x%08x\n",ddr->timing_cfg_1);
210   -
211 262 ddr->timing_cfg_2 = 0x00000800;
212   - debug ("DDR:timing_cfg_2=0x%08x\n",ddr->timing_cfg_2);
213 263  
214   - /* only DDR I is supported, DDR I and II have different mode-register-set definition */
  264 + debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
  265 + debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
  266 +
  267 + /*
  268 + * Only DDR I is supported
  269 + * DDR I and II have different mode-register-set definition
  270 + */
  271 +
215 272 /* burst length is always 4 */
216 273 switch(caslat) {
217 274 case 2:
218 275  
219 276  
220 277  
221 278  
222 279  
223 280  
224 281  
225 282  
226 283  
227 284  
228 285  
229 286  
... ... @@ -227,53 +284,58 @@
227 284 ddr->sdram_mode = 0x32; /* 3.0 */
228 285 break;
229 286 default:
230   - printf("DDR:only CAS Latency 1.5,2.0,2.5,3.0 is supported.\n");
  287 + puts("DDR:only CAS Latency 1.5, 2.0, 2.5, 3.0 is supported.\n");
231 288 return 0;
232 289 }
233   - debug ("DDR:sdram_mode=0x%08x\n",ddr->sdram_mode);
  290 + debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
234 291  
235 292 switch(spd.refresh) {
236 293 case 0x00:
237 294 case 0x80:
238   - tmp = ns2clk(15625);
  295 + tmp = picos_to_clk(15625000);
239 296 break;
240 297 case 0x01:
241 298 case 0x81:
242   - tmp = ns2clk(3900);
  299 + tmp = picos_to_clk(3900000);
243 300 break;
244 301 case 0x02:
245 302 case 0x82:
246   - tmp = ns2clk(7800);
  303 + tmp = picos_to_clk(7800000);
247 304 break;
248 305 case 0x03:
249 306 case 0x83:
250   - tmp = ns2clk(31300);
  307 + tmp = picos_to_clk(31300000);
251 308 break;
252 309 case 0x04:
253 310 case 0x84:
254   - tmp = ns2clk(62500);
  311 + tmp = picos_to_clk(62500000);
255 312 break;
256 313 case 0x05:
257 314 case 0x85:
258   - tmp = ns2clk(125000);
  315 + tmp = picos_to_clk(125000000);
259 316 break;
260 317 default:
261 318 tmp = 0x512;
262 319 break;
263 320 }
264 321  
265   - /* set BSTOPRE to 0x100 for page mode, if auto-charge is used, set BSTOPRE = 0 */
  322 + /*
  323 + * Set BSTOPRE to 0x100 for page mode
  324 + * If auto-charge is used, set BSTOPRE = 0
  325 + */
266 326 ddr->sdram_interval = ((tmp & 0x3fff) << 16) | 0x100;
267   - debug ("DDR:sdram_interval=0x%08x\n",ddr->sdram_interval);
  327 + debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
268 328  
269   - /* is this an ECC DDR chip? */
  329 + /*
  330 + * Is this an ECC DDR chip?
  331 + */
270 332 #if defined(CONFIG_DDR_ECC)
271   - if(spd.config == 0x02) {
  333 + if (spd.config == 0x02) {
272 334 ddr->err_disable = 0x0000000d;
273 335 ddr->err_sbe = 0x00ff0000;
274 336 }
275   - debug ("DDR:err_disable=0x%08x\n",ddr->err_disable);
276   - debug ("DDR:err_sbe=0x%08x\n",ddr->err_sbe);
  337 + debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
  338 + debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
277 339 #endif
278 340 asm("sync;isync;msync");
279 341  
... ... @@ -287,7 +349,8 @@
287 349 ddr->sdram_clk_cntl = 0x83000000;
288 350 #endif
289 351  
290   - /* Figure out the settings for the sdram_cfg register. Build up
  352 + /*
  353 + * Figure out the settings for the sdram_cfg register. Build up
291 354 * the entire register in 'tmp' before writing since the write into
292 355 * the register will actually enable the memory controller, and all
293 356 * settings must be done before enabling.
... ... @@ -298,7 +361,8 @@
298 361 */
299 362 tmp = 0xc2000000;
300 363  
301   - /* sdram_cfg[3] = RD_EN - registered DIMM enable
  364 + /*
  365 + * sdram_cfg[3] = RD_EN - registered DIMM enable
302 366 * A value of 0x26 indicates micron registered DIMMS (micron.com)
303 367 */
304 368 if (spd.mod_attr == 0x26) {
305 369  
... ... @@ -306,13 +370,14 @@
306 370 }
307 371  
308 372 #if defined(CONFIG_DDR_ECC)
309   - /* If the user wanted ECC (enabled via sdram_cfg[2]) */
  373 + /*
  374 + * If the user wanted ECC (enabled via sdram_cfg[2])
  375 + */
310 376 if (spd.config == 0x02) {
311 377 tmp |= 0x20000000;
312 378 }
313 379 #endif
314 380  
315   -
316 381 /*
317 382 * REV1 uses 1T timing.
318 383 * REV2 may use 1T or 2T as configured by the user.
319 384  
320 385  
321 386  
... ... @@ -333,13 +398,72 @@
333 398 ddr->sdram_cfg = tmp;
334 399  
335 400 asm("sync;isync;msync");
336   -
337 401 udelay(500);
338 402  
339   - debug ("DDR:sdram_cfg=0x%08x\n",ddr->sdram_cfg);
  403 + debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
340 404  
341   - return (memsize*1024*1024);
  405 + return memsize * 1024 * 1024;
342 406 }
343 407  
344 408 #endif /* CONFIG_SPD_EEPROM */
  409 +
  410 +
  411 +#if defined(CONFIG_DDR_ECC)
  412 +/*
  413 + * Initialize all of memory for ECC, then enable errors.
  414 + */
  415 +
  416 +void
  417 +ddr_enable_ecc(unsigned int dram_size)
  418 +{
  419 + uint *p = 0;
  420 + uint i = 0;
  421 + volatile immap_t *immap = (immap_t *)CFG_IMMR;
  422 + volatile ccsr_ddr_t *ddr= &immap->im_ddr;
  423 +
  424 + dma_init();
  425 +
  426 + for (*p = 0; p < (uint *)(8 * 1024); p++) {
  427 + if (((unsigned int)p & 0x1f) == 0) {
  428 + ppcDcbz((unsigned long) p);
  429 + }
  430 + *p = (unsigned int)0xdeadbeef;
  431 + if (((unsigned int)p & 0x1c) == 0x1c) {
  432 + ppcDcbf((unsigned long) p);
  433 + }
  434 + }
  435 +
  436 + /* 8K */
  437 + dma_xfer((uint *)0x2000, 0x2000, (uint *)0);
  438 + /* 16K */
  439 + dma_xfer((uint *)0x4000, 0x4000, (uint *)0);
  440 + /* 32K */
  441 + dma_xfer((uint *)0x8000, 0x8000, (uint *)0);
  442 + /* 64K */
  443 + dma_xfer((uint *)0x10000, 0x10000, (uint *)0);
  444 + /* 128k */
  445 + dma_xfer((uint *)0x20000, 0x20000, (uint *)0);
  446 + /* 256k */
  447 + dma_xfer((uint *)0x40000, 0x40000, (uint *)0);
  448 + /* 512k */
  449 + dma_xfer((uint *)0x80000, 0x80000, (uint *)0);
  450 + /* 1M */
  451 + dma_xfer((uint *)0x100000, 0x100000, (uint *)0);
  452 + /* 2M */
  453 + dma_xfer((uint *)0x200000, 0x200000, (uint *)0);
  454 + /* 4M */
  455 + dma_xfer((uint *)0x400000, 0x400000, (uint *)0);
  456 +
  457 + for (i = 1; i < dram_size / 0x800000; i++) {
  458 + dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
  459 + }
  460 +
  461 + /*
  462 + * Enable errors for ECC.
  463 + */
  464 + ddr->err_disable = 0x00000000;
  465 + asm("sync;isync;msync");
  466 +}
  467 +
  468 +#endif /* CONFIG_DDR_ECC */
... ... @@ -218,7 +218,19 @@
218 218 mtspr MMUCSR0, r2
219 219 isync
220 220  
221   - /* After reset, CCSRBAR is located at CFG_CCSRBAR_DEFAULT, i.e.
  221 + /*
  222 + * Invalidate all TLB0 entries.
  223 + */
  224 + li r3,4
  225 + li r4,0
  226 + tlbivax r4,r3
  227 + /*
  228 + * To avoid REV1 Errata CPU6 issues, make sure
  229 + * the instruction following tlbivax is not a store.
  230 + */
  231 +
  232 + /*
  233 + * After reset, CCSRBAR is located at CFG_CCSRBAR_DEFAULT, i.e.
222 234 * 0xff700000-0xff800000. We need add a TLB1 entry for this 1MB
223 235 * region before we can access any CCSR registers such as L2
224 236 * registers, Local Access Registers,etc. We will also re-allocate
... ... @@ -230,7 +242,7 @@
230 242 */
231 243 bl tlb1_entry
232 244 mr r5,r0
233   - li r1,0x000f /* max 16 TLB1 entries */
  245 + li r1,0x0020 /* max 16 TLB1 plus some TLB0 entries */
234 246 mtctr r1
235 247 lwzu r4,0(r5) /* how many TLB1 entries we actually use */
236 248  
237 249  
238 250  
239 251  
240 252  
... ... @@ -273,37 +285,19 @@
273 285 isync
274 286 #endif
275 287  
276   - /* invalidate all TLB0 entries */
277   - li r3,4
278   - li r4,0
279   - tlbivax r4,r3
280   - /*
281   - * To avoid REV1 Errata CPU6 issues, make sure
282   - * the instruction following tlbivax is not a store.
283   - */
284 288  
285   -
286 289 /* set up local access windows, defined at board/<boardname>/init.S */
287 290 lis r7,CFG_CCSRBAR@h
288 291 ori r7,r7,CFG_CCSRBAR@l
289 292  
290 293 bl law_entry
291 294 mr r6,r0
292   -#if defined(CONFIG_RAM_AS_FLASH)
293   - li r1,0x0006
294   -#else
295   - li r1,0x0007 /*we have 8 LAWs, but reseve one for boot-over-rio-or-pci */
296   -#endif
  295 + li r1,0x0007 /* 8 LAWs, but reserve one for boot-over-rio-or-pci */
297 296 mtctr r1
298 297 lwzu r5,0(r6) /* how many windows we actually use */
299 298  
300   -#if defined(CONFIG_RAM_AS_FLASH)
301   - li r2,0x0c48
302   - li r1,0x0c50
303   -#else
304 299 li r2,0x0c28 /* the first pair is reserved for boot-over-rio-or-pci */
305 300 li r1,0x0c30
306   -#endif
307 301  
308 302 0: cmpwi r5,0
309 303 beq 1f
... ... @@ -22,7 +22,7 @@
22 22 *
23 23 * This program is distributed in the hope that it will be useful,
24 24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  25 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 26 * GNU General Public License for more details.
27 27 *
28 28 * You should have received a copy of the GNU General Public License
29 29  
... ... @@ -46,9 +46,10 @@
46 46 /* Returns 0 if exception not found and fixup otherwise. */
47 47 extern unsigned long search_exception_table(unsigned long);
48 48  
49   -/* THIS NEEDS CHANGING to use the board info structure.
  49 +/*
  50 + * End of memory as shown by board info and determined by DDR setup.
50 51 */
51   -#define END_OF_MEM (CFG_SDRAM_SIZE * 1024 * 1024)
  52 +#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize)
52 53  
53 54  
54 55 static __inline__ void set_tsr(unsigned long val)
... ... @@ -82,6 +83,7 @@
82 83 void
83 84 print_backtrace(unsigned long *sp)
84 85 {
  86 + DECLARE_GLOBAL_DATA_PTR;
85 87 int cnt = 0;
86 88 unsigned long i;
87 89  
... ... @@ -261,7 +263,7 @@
261 263 #endif
262 264 }
263 265  
264   -/* Probe an address by reading. If not present, return -1, otherwise
  266 +/* Probe an address by reading. If not present, return -1, otherwise
265 267 * return 0.
266 268 */
267 269 int
doc/README.mpc85xxads
Diff comments   View file @ 9aea953
1 1 Motorola MPC8540ADS and MPC8560ADS board
2 2  
3   -Xianghua Xiao(X.Xiao@motorola.com)
4   -Created 10/15/03
  3 +Created 10/15/03 Xianghua Xiao
  4 +Updated 13-July-2004 Jon Loeliger
5 5 -----------------------------------------
6 6  
7 7 0. Toolchain
8   -The Binutils in ELDK toolchain 3.0 or earlier does not support the
9   -MPC85xx chip. You need use the newest binutils-2.14.tar.bz2 from
10   -http://ftp.gnu.org/gnu/binutils.
11 8  
  9 + The Binutils in current ELDK toolchain will not support MPC85xx
  10 + chip. You need use the newest binutils-2.14.tar.bz2 from
  11 + http://ftp.gnu.org/gnu/binutils.
  12 +
  13 + The 8540/8560 ADS code base is known to compile using:
  14 + gcc (GCC) 3.2.2 20030217 (Yellow Dog Linux 3.0 3.2.2-2a)
  15 +
  16 +
12 17 1. SWITCH SETTINGS & JUMPERS
13 18  
14   -1.1 First, make sure the board default setting is consistent with the document
  19 +1.0 Nomenclature
  20 +
  21 + For some reason, the HW designers describe the switch settings
  22 + in terms of 0 and 1, and then map that to physical switches where
  23 + the label "On" refers to logic 0 and "Off" (unlabeled) is logic 1.
  24 + Luckily, we're SW types and virtual settings are handled daily.
  25 +
  26 + The switches for the Rev A board are numbered differently than
  27 + for the Pilot board. Oh yeah.
  28 +
  29 + Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
  30 + bits may contribute to signals that are numbered based at 0,
  31 + and some of those signals may be high-bit-number-0 too. Heed
  32 + well the names and labels and do not get confused.
  33 +
  34 + "Off" == 1
  35 + "On" == 0
  36 +
  37 + SW18 is switch 18 as silk-screened onto the board.
  38 + SW4[8] is the bit labled 8 on Switch 4.
  39 + SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2
  40 + SW3[7:1] refers to bits labeled 7 through 1 in order on switch 3
  41 +
  42 +1.1 For the MPC85xxADS Pilot Board
  43 +
  44 + First, make sure the board default setting is consistent with the document
15 45 shipped with your board. Then apply the following changes:
16   - SW3[1-6]="all OFF" (boot from 32bit flash, no boot sequence is used)
  46 + SW3[1-6]="all OFF" (boot from 32bit flash, no boot sequence is used)
17 47 SW10[2-6]="all OFF" (turn on CPM SCC for serial port,works for 8540/8560)
18 48 SW11[2]='OFF for 8560, ON for 8540' (toggle 8540.8560 mode)
19 49 SW11[7]='ON' (rev2), 'OFF' (rev1)
20 50  
21 51  
22 52  
23 53  
... ... @@ -22,32 +52,69 @@
22 52 SW5[1-10[="ON ON OFF OFF OFF OFF OFF OFF OFF OFF"
23 53 J1 = "Enable Prog" (Make sure your flash is programmable for development)
24 54  
25   -1.2 If you want to test PCI functionality with a 33Mhz PCI card, you will
  55 + If you want to test PCI functionality with a 33Mhz PCI card, you will
26 56 have to change the system clock from the default 66Mhz to 33Mhz by
27 57 setting SW15[1]="OFF" and SW17[8]="OFF". After that you may also need
28 58 double your platform clock(SW6) because the system clock is now only
29 59 half of its original value. For example, if at 66MHz your system
30 60 clock showed SW6[0:1] = 01, then at 33MHz SW6[0:1] it should be 10.
31 61  
32   -1.3 SW6 is a very important switch, it decides your platform clock and CPU
33   - clock based on the on-board system clock(default 66MHz). Check the
34   - document along with your board for details.
  62 + SW17[8] ------+ SW6
  63 + SW15[1] ----+ | [0:1]
  64 + V V V V
  65 + 33MHz 1 1 1 0
  66 + 66MHz 0 0 0 1
35 67  
  68 + Hmmm... That SW6 setting description is incomplete but it works.
36 69  
  70 +
  71 +1.3 For the MPC85xxADS Rev A Board
  72 +
  73 + As shipped, the board should be a 33MHz PCI bus with a CPU Clock
  74 + rate of 825 +/- fuzz:
  75 +
  76 + Clocks: CPU: 825 MHz, CCB: 330 MHz, DDR: 165 MHz, LBC: 82 MHz
  77 +
  78 + For 33MHz PCI, the switch settings should be like this:
  79 +
  80 + SW18[7:1] = 0100001 = M==33 => 33MHz
  81 + SW18[8] = 1 => PWD Divider == 16
  82 + SW16[1:2] = 11 => N == 16 as PWD==1
  83 +
  84 + Use the magical formula:
  85 + Fout (MHz) = 16 * M / N = 16 * 33 / 16 = 33 MHz
  86 +
  87 + SW7[1:4] = 1010 = 10 => 10 x 33 = 330 CCB Sysclk
  88 + SW7[5:6] = 01 => 5:2 x 330 = 825 Core clock
  89 +
  90 +
  91 + For 66MHz PCI, the switch settings should be like this:
  92 +
  93 + SW18[7:1] = 0100001 = M==33 => 33MHz
  94 + SW18[8] = 0 => PWD Divider == 1
  95 + SW16[1:2] = 01 => N == 8 as PWD == 0
  96 +
  97 + Use the magical formula:
  98 + Fout (MHz) = 16 * M / N = 16 * 33 / 8 = 66 MHz
  99 +
  100 + SW7[1:4] = 0101 = 5 => 5 x 66 = 330 CCB Sysclk
  101 + SW7[5:6] = 01 => 5:2 x 330 = 825 Core clock
  102 +
  103 +
37 104 2. MEMORY MAP TO WORK WITH LINUX KERNEL
38 105  
39 106 2.1. For the initial bringup, we adopted a consistent memory scheme
40 107 between u-boot and linux kernel, you can customize it based on your
41 108 system requirements:
42 109  
43   - 0x0000_0000 0x7fff_ffff DDR 2G
44   - 0x8000_0000 0x9fff_ffff PCI MEM 512M
45   - 0xc000_0000 0xdfff_ffff Rapid IO 512M
46   - 0xe000_0000 0xe00f_ffff CCSR 1M
47   - 0xe200_0000 0xe2ff_ffff PCI IO 16M
48   - 0xf000_0000 0xf7ff_ffff SDRAM 128M
49   - 0xf800_0000 0xf80f_ffff BCSR 1M
50   - 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M
  110 + 0x0000_0000 0x7fff_ffff DDR 2G
  111 + 0x8000_0000 0x9fff_ffff PCI MEM 512M
  112 + 0xc000_0000 0xdfff_ffff Rapid IO 512M
  113 + 0xe000_0000 0xe00f_ffff CCSR 1M
  114 + 0xe200_0000 0xe2ff_ffff PCI IO 16M
  115 + 0xf000_0000 0xf7ff_ffff SDRAM 128M
  116 + 0xf800_0000 0xf80f_ffff BCSR 1M
  117 + 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M
51 118  
52 119 2.2 We are submitting Linux kernel patches for MPC8540 and MPC8560. You
53 120 can download them from linuxppc-2.4 public source. Please make sure the
54 121  
55 122  
... ... @@ -63,27 +130,20 @@
63 130 include/configs/MPC8540ADS.h
64 131 include/configs/MPC8560ADS.h
65 132  
66   - CONFIG_BOOKE BOOKE(e.g. Motorola MPC85xx, IBM 440, etc)
67   - CONFIG_E500 BOOKE e500 family(Motorola)
68   - CONFIG_MPC85xx MPC8540,MPC8560 and their derivatives
69   - CONFIG_MPC8540 MPC8540 specific
70   - CONFIG_MPC8560 MPC8560 specific
71   - CONFIG_MPC8540ADS MPC8540ADS board specific
72   - CONFIG_MPC8560ADS MPC8560ADS board specific
73   - CONFIG_TSEC_ENET Use on-chip 10/100/1000 ethernet for networking
74   - CONFIG_SPD_EEPROM Use SPD EEPROM for DDR auto configuration, you can
75   - also manual config the DDR after undef this
  133 + CONFIG_BOOKE BOOKE(e.g. Motorola MPC85xx, IBM 440, etc)
  134 + CONFIG_E500 BOOKE e500 family(Motorola)
  135 + CONFIG_MPC85xx MPC8540,MPC8560 and their derivatives
  136 + CONFIG_MPC8540 MPC8540 specific
  137 + CONFIG_MPC8560 MPC8560 specific
  138 + CONFIG_MPC8540ADS MPC8540ADS board specific
  139 + CONFIG_MPC8560ADS MPC8560ADS board specific
  140 + CONFIG_TSEC_ENET Use on-chip 10/100/1000 ethernet for networking
  141 + CONFIG_SPD_EEPROM Use SPD EEPROM for DDR auto configuration, you can
  142 + also manual config the DDR after undef this
76 143 definition.
77   - CONFIG_DDR_ECC only for ECC DDR module
78   - CONFIG_DDR_DLL DLL fix on some ADS boards needed for more
  144 + CONFIG_DDR_ECC only for ECC DDR module
  145 + CONFIG_DDR_DLL DLL fix on some ADS boards needed for more
79 146 stability.
80   - CONFIG_RAM_AS_FLASH after define this, you can load U-Boot into
81   - localbus SDRAM and treat localbus SDRAM as a
82   - flash. We use this memory based U-Boot
83   - before flash is working while Metrowerks and
84   - Windriver are still working on their
85   - flash/JTAG tools. if you can program the
86   - flash directly, undef this.
87 147  
88 148 Other than the above definitions, the rest in the config files are
89 149 straightforward.
90 150  
91 151  
92 152  
... ... @@ -139,25 +199,26 @@
139 199  
140 200 4.5 Reflash U-Boot with a BDI-2000
141 201  
142   - BDI> erase 0xFFF80000 0x2000 0x40
  202 + BDI> erase 0xFFF80000 0x4000 0x20
143 203 BDI> prog 0xfff80000 u-boot.bin.8560ads
144 204 BDI> verify
145 205  
146 206  
147   -5. Screen dump:
148   -5.1 MPC8540ADS board
149   -U-Boot 1.0.0-pre (Oct 15 2003 - 13:40:33)
  207 +5. Screen dump MPC8540ADS board
150 208  
151   -Motorola PowerPC ProcessorID=00000000 Rev. PVR=80200010
152   -Board: Motorola MPC8540ADS Board
153   - CPU: 792 MHz
154   - CCB: 264 MHz
155   - DDR: 132 MHz
156   - LBC: 66 MHz
157   -L1 D-cache 32KB, L1 I-cache 32KB enabled.
  209 +U-Boot 1.1.2(pq3-20040707-0) (Jul 6 2004 - 17:34:25)
  210 +
  211 +Freescale PowerPC
  212 + Core: E500, Version: 2.0, (0x80200020)
  213 + System: 8540, Version: 2.0, (0x80300020)
  214 + Clocks: CPU: 825 MHz, CCB: 330 MHz, DDR: 165 MHz, LBC: 82 MHz
  215 + L1 D-cache 32KB, L1 I-cache 32KB enabled.
  216 +Board: ADS
  217 + PCI1: 32 bit, 66 MHz (compiled)
158 218 I2C: ready
159   -DRAM: DDR module detected, total size:128MB.
160   -128 MB
  219 +DRAM: Initializing
  220 + SDRAM: 64 MB
  221 + DDR: 256 MB
161 222 FLASH: 16 MB
162 223 L2 cache enabled: 256KB
163 224 *** Warning - bad CRC, using default environment
164 225  
165 226  
166 227  
167 228  
168 229  
169 230  
170 231  
171 232  
172 233  
173 234  
174 235  
... ... @@ -165,431 +226,76 @@
165 226 In: serial
166 227 Out: serial
167 228 Err: serial
168   -Net: MOTOROLA ETHERNE
  229 +Net: MOTO ENET0: PHY is Marvell 88E1011S (1410c62)
  230 +MOTO ENET1: PHY is Marvell 88E1011S (1410c62)
  231 +MOTO ENET2: PHY is Davicom DM9161E (181b881)
  232 +MOTO ENET0, MOTO ENET1, MOTO ENET2
169 233 Hit any key to stop autoboot: 0
170   -MPC8540ADS=> fli
  234 +=>
  235 +=> fli
171 236  
172 237 Bank # 1: Intel 28F640J3A (64 Mbit, 64 x 128K)
173 238 Size: 16 MB in 64 Sectors
174 239 Sector Start Addresses:
175   - FF000000 FF040000 FF080000 FF0C0000 FF100000
176   - FF140000 FF180000 FF1C0000 FF200000 FF240000
177   - FF280000 FF2C0000 FF300000 FF340000 FF380000
178   - FF3C0000 FF400000 FF440000 FF480000 FF4C0000
179   - FF500000 FF540000 FF580000 FF5C0000 FF600000
180   - FF640000 FF680000 FF6C0000 FF700000 FF740000
181   - FF780000 FF7C0000 FF800000 FF840000 FF880000
182   - FF8C0000 FF900000 FF940000 FF980000 FF9C0000
183   - FFA00000 FFA40000 FFA80000 FFAC0000 FFB00000
184   - FFB40000 FFB80000 FFBC0000 FFC00000 FFC40000
185   - FFC80000 FFCC0000 FFD00000 FFD40000 FFD80000
186   - FFDC0000 FFE00000 FFE40000 FFE80000 FFEC0000
187   - FFF00000 FFF40000 FFF80000 (RO) FFFC0000 (RO)
188   -MPC8540ADS=> imi ff000000
  240 + FF000000 FF040000 FF080000 FF0C0000 FF100000
  241 + FF140000 FF180000 FF1C0000 FF200000 FF240000
  242 + FF280000 FF2C0000 FF300000 FF340000 FF380000
  243 + FF3C0000 FF400000 FF440000 FF480000 FF4C0000
  244 + FF500000 FF540000 FF580000 FF5C0000 FF600000
  245 + FF640000 FF680000 FF6C0000 FF700000 FF740000
  246 + FF780000 FF7C0000 FF800000 FF840000 FF880000
  247 + FF8C0000 FF900000 FF940000 FF980000 FF9C0000
  248 + FFA00000 FFA40000 FFA80000 FFAC0000 FFB00000
  249 + FFB40000 FFB80000 FFBC0000 FFC00000 FFC40000
  250 + FFC80000 FFCC0000 FFD00000 FFD40000 FFD80000
  251 + FFDC0000 FFE00000 FFE40000 FFE80000 FFEC0000
  252 + FFF00000 FFF40000 FFF80000 (RO) FFFC0000 (RO)
189 253  
190   -## Checking Image at ff000000 ...
191   - Image Name: Linux-2.4.21-rc5
192   - Image Type: PowerPC Linux Kernel Image (gzip compressed)
193   - Data Size: 800594 Bytes = 781.8 kB
194   - Load Address: 00000000
195   - Entry Point: 00000000
196   - Verifying Checksum ... OK
197   -MPC8540ADS=> bdinfo
  254 +=> bdinfo
198 255 memstart = 0x00000000
199   -memsize = 0x08000000
  256 +memsize = 0x10000000
200 257 flashstart = 0xFF000000
201 258 flashsize = 0x01000000
202 259 flashoffset = 0x00000000
203 260 sramstart = 0x00000000
204 261 sramsize = 0x00000000
205   -immr_base = 0xFDF00000
206   -bootflags = 0x40003F80
207   -intfreq = 792 MHz
208   -busfreq = 264 MHz
209   -ethaddr = 00:01:AF:07:9B:8A
210   -eth1addr = 00:01:AF:07:9B:8B
211   -eth2addr = 00:01:AF:07:9B:8C
212   -IP addr = 10.82.0.105
  262 +immr_base = 0xE0000000
  263 +bootflags = 0xE4013F80
  264 +intfreq = 825 MHz
  265 +busfreq = 330 MHz
  266 +ethaddr = 00:E0:0C:00:00:FD
  267 +eth1addr = 00:E0:0C:00:01:FD
  268 +eth2addr = 00:E0:0C:00:02:FD
  269 +IP addr = 192.168.1.253
213 270 baudrate = 115200 bps
214   -MPC8540ADS=> printenv
215   -bootargs=root=/dev/nfs rw nfsroot=163.12.64.52:/localhome/r6aads/linuxppc/target ip=10.82.0.105:163.12.64.52:10.82.1.254:255.255.254.0:mpc8540ads-003:eth0:off console=ttyS0,115200
216   -bootcmd=bootm 0xff300000 0xff700000
217   -bootdelay=3
218   -baudrate=115200
219   -loads_echo=1
220   -ethaddr=00:01:af:07:9b:8a
221   -eth1addr=00:01:af:07:9b:8b
222   -eth2addr=00:01:af:07:9b:8c
223   -ipaddr=10.82.0.105
224   -serverip=163.12.64.52
225   -rootpath=/home/r6aads/mpclinux/eldk-2.0.2/ppc_82xx
226   -gatewayip=10.82.1.254
227   -netmask=255.255.254.0
228   -hostname=MPC8560ADS_PILOT_003
229   -bootfile=pImage
230   -stdin=serial
231   -stdout=serial
232   -stderr=serial
233 271  
234   -Environment size: 560/8188 bytes
235   -MPC8540ADS=> bootm ff000000
236   -## Booting image at ff000000 ...
237   - Image Name: Linux-2.4.21-rc5
238   - Image Type: PowerPC Linux Kernel Image (gzip compressed)
239   - Data Size: 800594 Bytes = 781.8 kB
240   - Load Address: 00000000
241   - Entry Point: 00000000
242   - Verifying Checksum ... OK
243   - Uncompressing Kernel Image ... OK
244   -mpc85xx_init(): exit
245   -id mach(): done
246   -MMU:enter
247   -Memory CAM mapping: CAM0=64Mb, CAM1=64Mb, CAM2=0Mb residual: 0Mb
248   -MMU:hw init
249   -MMU:mapin
250   -MMU:mapin_ram done
251   -MMU:setio
252   -MMU:exit
253   -Linux version 2.4.21-rc5 (@etest) (gcc version 2.95.3 20010315 (release)) #1 Wed Oct 15 09:05:42 CDT 2003
254   -setup_arch: enter
255   -setup_arch: bootmem
256   -mpc85xx_setup_arch
257   -Host Bridge Vendor ID = 1057
258   -Host Bridge Device ID = 3
259   -Host Bridge header = 0
260   -arch: exit
261   -On node 0 totalpages: 32768
262   -zone(0): 32768 pages.
263   -zone(1): 0 pages.
264   -zone(2): 0 pages.
265   -Kernel command line: root=/dev/nfs rw nfsroot=163.12.64.52:/localhome/r6aads/linuxppc/target ip=10.82.0.105:163.12.64.52:10.82.1.254:255.255.254.0:mpc8540ads-003:eth0:off console=ttyS0,115200
266   -openpic: enter
267   -OpenPIC Version 1.2 (1 CPUs and 44 IRQ sources) at fdf40000
268   -openpic: timer
269   -openpic: external
270   -openpic: spurious
271   -openpic: exit
272   -time_init: decrementer frequency = 33.000000 MHz
273   -Calibrating delay loop... 226.09 BogoMIPS
274   -Memory: 127488k available (1344k kernel code, 448k data, 248k init, 0k highmem)
275   -Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
276   -Inode cache hash table entries: 8192 (order: 4, 65536 bytes)
277   -Mount cache hash table entries: 512 (order: 0, 4096 bytes)
278   -Buffer-cache hash table entries: 8192 (order: 3, 32768 bytes)
279   -Page-cache hash table entries: 32768 (order: 5, 131072 bytes)
280   -POSIX conformance testing by UNIFIX
281   -PCI: Probing PCI hardware
282 272  
283   -Linux NET4.0 for Linux 2.4
284   -Based upon Swansea University Computer Society NET3.039
285   -Initializing RT netlink socket
286   -Starting kswapd
287   -Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
288   -pty: 256 Unix98 ptys configured
289   -Serial driver version 5.05c (2001-07-08) with MANY_PORTS SHARE_IRQ SERIAL_PCI enabled
290   -ttyS00 at 0xfdf04500 (irq = 90) is a 16550A
291   -ttyS01 at 0xfdf04600 (irq = 0) is a 16550A
292   -eth0: Three Speed Ethernet Controller Version 0.2, 00:01:af:07:9b:8a:
293   -eth1: Three Speed Ethernet Controller Version 0.2, 00:01:af:07:9b:8b:
294   -RAMDISK driver initialized: 16 RAM disks of 32768K size 1024 blocksize
295   -loop: loaded (max 8 devices)
296   -Intel(R) PRO/1000 Network Driver - version 5.0.43-k1
297   -Copyright (c) 1999-2003 Intel Corporation.
298   -PPP generic driver version 2.4.2
299   -PPP Deflate Compression module registered
300   -NET4: Linux TCP/IP 1.0 for NET4.0
301   -IP Protocols: ICMP, UDP, TCP, IGMP
302   -IP: routing cache hash table of 1024 buckets, 8Kbytes
303   -TCP: Hash tables configured (established 8192 bind 8192)
304   -IP-Config: Complete:
305   - device=eth0, addr=10.82.0.105, mask=255.255.254.0, gw=10.82.1.254,
306   - host=mpc8540ads-003, domain=, nis-domain=(none),
307   - bootserver=163.12.64.52, rootserver=163.12.64.52, rootpath=
308   -NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
309   -Looking up port of RPC 100003/2 on 163.12.64.52
310   -Looking up port of RPC 100005/1 on 163.12.64.52
311   -VFS: Mounted root (nfs filesystem).
312   -Freeing unused kernel memory: 248k init
313   -INIT: version 2.78 booting
314   -Activating swap...
315   -Checking all file systems...
316   -Parallelizing fsck version 1.22 (22-Jun-2001)
317   -Mounting local filesystems...
318   -nothing was mounted
319   -Cleaning: /etc/network/ifstate.
320   -Setting up IP spoofing protection: rp_filter.
321   -Disable TCP/IP Explicit Congestion Notification: done.
322   -Configuring network interfaces: done.
323   -Starting portmap daemon: portmap.
324   -Cleaning: /tmp /var/lock /var/run.
325   -INIT: Entering runlevel: 2
326   -Starting system log daemon: syslogd klogd.
327   -Starting internet superserver: inetd.
328   -
329   -mpc8540ads-003 login: root
330   -Last login: Thu Jan 1 00:00:07 1970 on console
331   -Linux mpc8540ads-003 2.4.21-rc5 #1 Wed Oct 15 09:05:42 CDT 2003 ppc unknown
332   -
333   -root@mpc8540ads-003:~# ls
334   -21142.o aa e100.o hello.o mii.o timer.o
335   -root@mpc8540ads-003:~# /sbin/ifconfig
336   -eth0 Link encap:Ethernet HWaddr 00:01:AF:07:9B:8A
337   - inet addr:10.82.0.105 Bcast:10.82.1.255 Mask:255.255.254.0
338   - UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1
339   - RX packets:4576 errors:0 dropped:0 overruns:0 frame:0
340   - TX packets:2587 errors:0 dropped:0 overruns:0 carrier:0
341   - collisions:0 txqueuelen:100
342   - RX bytes:4457023 (4.2 Mb) TX bytes:437770 (427.5 Kb)
343   - Base address:0x4000
344   -
345   -lo Link encap:Local Loopback
346   - inet addr:127.0.0.1 Mask:255.0.0.0
347   - UP LOOPBACK RUNNING MTU:16436 Metric:1
348   - RX packets:4 errors:0 dropped:0 overruns:0 frame:0
349   - TX packets:4 errors:0 dropped:0 overruns:0 carrier:0
350   - collisions:0 txqueuelen:0
351   - RX bytes:296 (296.0 b) TX bytes:296 (296.0 b)
352   -
353   -root@mpc8540ads-003:~# ping 163.12.64.52
354   -PING 163.12.64.52 (163.12.64.52): 56 data bytes
355   -64 bytes from 163.12.64.52: icmp_seq=0 ttl=63 time=0.2 ms
356   -64 bytes from 163.12.64.52: icmp_seq=1 ttl=63 time=0.1 ms
357   -64 bytes from 163.12.64.52: icmp_seq=2 ttl=63 time=0.1 ms
358   -
359   ---- 163.12.64.52 ping statistics ---
360   -3 packets transmitted, 3 packets received, 0% packet loss
361   -round-trip min/avg/max = 0.1/0.1/0.2 ms
362   -root@mpc8540ads-003:~#
363   -
364   -5.2 MPC8560ADS board
365   -U-Boot 1.0.0-pre (Oct 15 2003 - 13:42:04)
366   -
367   -Motorola PowerPC ProcessorID=00000000 Rev. PVR=80200010
368   -Board: Motorola MPC8560ADS Board
369   - CPU: 792 MHz
370   - CCB: 264 MHz
371   - DDR: 132 MHz
372   - LBC: 66 MHz
373   - CPM: 264 Mhz
374   -L1 D-cache 32KB, L1 I-cache 32KB enabled.
375   -I2C: ready
376   -DRAM: DDR module detected, total size:128MB.
377   -128 MB
378   -FLASH: 16 MB
379   -L2 cache enabled: 256KB
380   -*** Warning - bad CRC, using default environment
381   -
382   -In: serial
383   -Out: serial
384   -Err: serial
385   -Net: MOTOROLA ETHERNE
386   -Hit any key to stop autoboot: 3
387   -MPC8560ADS=> bdinfo
388   -memstart = 0x00000000
389   -memsize = 0x08000000
390   -flashstart = 0xFF000000
391   -flashsize = 0x01000000
392   -flashoffset = 0x00000000
393   -sramstart = 0x00000000
394   -sramsize = 0x00000000
395   -immr_base = 0xFDF00000
396   -bootflags = 0x00000000
397   -vco = 528 MHz
398   -sccfreq = 132 MHz
399   -brgfreq = 132 MHz
400   -intfreq = 792 MHz
401   -cpmfreq = 264 MHz
402   -busfreq = 264 MHz
403   -ethaddr = 00:01:AF:07:9B:8A
404   -eth1addr = 00:01:AF:07:9B:8B
405   -eth2addr = 00:01:AF:07:9B:8C
406   -IP addr = 10.82.0.105
407   -baudrate = 115200 bps
408   -MPC8560ADS=> printenv
409   -bootargs=root=/dev/nfs rw nfsroot=163.12.64.52:/localhome/r6aads/linuxppc/target ip=10.82.0.105:163.12.64.52:10.82.1.254:255.255.254.0:mpc8560ads-003:eth0:off console=ttyS0,115200
410   -bootcmd=bootm 0xff400000 0xff700000
411   -bootdelay=3
  273 +=> printenv
  274 +bootcmd=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;bootm $loadaddr
  275 +ramboot=setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;bootm $loadaddr $ramdiskaddr
  276 +nfsboot=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;bootm $loadaddr
  277 +bootdelay=10
412 278 baudrate=115200
413 279 loads_echo=1
414   -ethaddr=00:01:af:07:9b:8a
415   -eth1addr=00:01:af:07:9b:8b
416   -eth2addr=00:01:af:07:9b:8c
417   -ipaddr=10.82.0.105
418   -serverip=163.12.64.52
419   -rootpath=/home/r6aads/mpclinux/eldk-2.0.2/ppc_82xx
420   -gatewayip=10.82.1.254
421   -netmask=255.255.254.0
422   -hostname=MPC8560ADS_PILOT_003
423   -bootfile=pImage
  280 +ethaddr=00:E0:0C:00:00:FD
  281 +eth1addr=00:E0:0C:00:01:FD
  282 +eth2addr=00:E0:0C:00:02:FD
  283 +ipaddr=192.168.1.253
  284 +serverip=192.168.1.1
  285 +rootpath=/nfsroot
  286 +gatewayip=192.168.1.1
  287 +netmask=255.255.255.0
  288 +hostname=unknown
  289 +bootfile=your.uImage
  290 +loadaddr=200000
  291 +netdev=eth0
  292 +consoledev=ttyS0
  293 +ramdiskaddr=400000
  294 +ramdiskfile=your.ramdisk.u-boot
424 295 stdin=serial
425 296 stdout=serial
426 297 stderr=serial
  298 +ethact=MOTO ENET0
427 299  
428   -Environment size: 560/8188 bytes
429   -MPC8560ADS=> fli
430   -
431   -Bank # 1: Intel 28F640J3A (64 Mbit, 64 x 128K)
432   - Size: 16 MB in 64 Sectors
433   - Sector Start Addresses:
434   - FF000000 FF040000 FF080000 FF0C0000 FF100000
435   - FF140000 FF180000 FF1C0000 FF200000 FF240000
436   - FF280000 FF2C0000 FF300000 FF340000 FF380000
437   - FF3C0000 FF400000 FF440000 FF480000 FF4C0000
438   - FF500000 FF540000 FF580000 FF5C0000 FF600000
439   - FF640000 FF680000 FF6C0000 FF700000 FF740000
440   - FF780000 FF7C0000 FF800000 FF840000 FF880000
441   - FF8C0000 FF900000 FF940000 FF980000 FF9C0000
442   - FFA00000 FFA40000 FFA80000 FFAC0000 FFB00000
443   - FFB40000 FFB80000 FFBC0000 FFC00000 FFC40000
444   - FFC80000 FFCC0000 FFD00000 FFD40000 FFD80000
445   - FFDC0000 FFE00000 FFE40000 FFE80000 FFEC0000
446   - FFF00000 FFF40000 FFF80000 (RO) FFFC0000 (RO)
447   -MPC8560ADS=> imi ff100000
448   -
449   -## Checking Image at ff100000 ...
450   - Image Name: Linux-2.4.21-rc5
451   - Image Type: PowerPC Linux Kernel Image (gzip compressed)
452   - Data Size: 755361 Bytes = 737.7 kB
453   - Load Address: 00000000
454   - Entry Point: 00000000
455   - Verifying Checksum ... OK
456   -MPC8560ADS=> tftp 1000000 pImage.dracom.public
457   -TFTP from server 163.12.64.52; our IP address is 10.82.0.105; sending through gateway 10.82.1.254
458   -Filename 'pImage.dracom.public'.
459   -Load address: 0x1000000
460   -Loading: *#################################################################
461   - #################################################################
462   - ##################
463   -done
464   -Bytes transferred = 755425 (b86e1 hex)
465   -MPC8560ADS=> bootm ff100000
466   -## Booting image at ff100000 ...
467   - Image Name: Linux-2.4.21-rc5
468   - Image Type: PowerPC Linux Kernel Image (gzip compressed)
469   - Data Size: 755361 Bytes = 737.7 kB
470   - Load Address: 00000000
471   - Entry Point: 00000000
472   - Verifying Checksum ... OK
473   - Uncompressing Kernel Image ... OK
474   -mpc85xx_init(): exit
475   -id mach(): done
476   -MMU:enter
477   -Memory CAM mapping: CAM0=64Mb, CAM1=64Mb, CAM2=0Mb residual: 0Mb
478   -MMU:hw init
479   -MMU:mapin
480   -MMU:mapin_ram done
481   -MMU:setio
482   -MMU:exit
483   -Linux version 2.4.21-rc5 (@etest) (gcc version 2.95.3 20010315 (release)) #2 Wed Oct 15 09:13:46 CDT 2003
484   -setup_arch: enter
485   -setup_arch: bootmem
486   -mpc85xx_setup_arch
487   -Host Bridge Vendor ID = 1057
488   -Host Bridge Device ID = 3
489   -Host Bridge header = 0
490   -arch: exit
491   -On node 0 totalpages: 32768
492   -zone(0): 32768 pages.
493   -zone(1): 0 pages.
494   -zone(2): 0 pages.
495   -Kernel command line: root=/dev/nfs rw nfsroot=163.12.64.52:/localhome/r6aads/linuxppc/target ip=10.82.0.105:163.12.64.52:10.82.1.254:255.255.254.0:mpc8560ads-003:eth0:off console=ttyS0,115200
496   -openpic: enter
497   -OpenPIC Version 1.2 (1 CPUs and 44 IRQ sources) at fdf40000
498   -openpic: timer
499   -openpic: external
500   -openpic: spurious
501   -openpic: exit
502   -time_init: decrementer frequency = 33.000000 MHz
503   -Calibrating delay loop... 226.09 BogoMIPS
504   -Memory: 127624k available (1276k kernel code, 384k data, 236k init, 0k highmem)
505   -Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
506   -Inode cache hash table entries: 8192 (order: 4, 65536 bytes)
507   -Mount cache hash table entries: 512 (order: 0, 4096 bytes)
508   -Buffer-cache hash table entries: 8192 (order: 3, 32768 bytes)
509   -Page-cache hash table entries: 32768 (order: 5, 131072 bytes)
510   -POSIX conformance testing by UNIFIX
511   -PCI: Probing PCI hardware
512   -
513   -Linux NET4.0 for Linux 2.4
514   -Based upon Swansea University Computer Society NET3.039
515   -Initializing RT netlink socket
516   -Starting kswapd
517   -Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
518   -CPM UART driver version 0.01
519   -ttyS0 on SCC1 at 0x8000, BRG1
520   -UART interrupt installed(40)
521   -pty: 256 Unix98 ptys configured
522   -eth0: Three Speed Ethernet Controller Version 0.2, 00:01:af:07:9b:8a:
523   -eth1: Three Speed Ethernet Controller Version 0.2, 00:01:af:07:9b:8b:
524   -RAMDISK driver initialized: 16 RAM disks of 32768K size 1024 blocksize
525   -loop: loaded (max 8 devices)
526   -Intel(R) PRO/1000 Network Driver - version 5.0.43-k1
527   -Copyright (c) 1999-2003 Intel Corporation.
528   -PPP generic driver version 2.4.2
529   -PPP Deflate Compression module registered
530   -NET4: Linux TCP/IP 1.0 for NET4.0
531   -IP Protocols: ICMP, UDP, TCP, IGMP
532   -IP: routing cache hash table of 1024 buckets, 8Kbytes
533   -TCP: Hash tables configured (established 8192 bind 8192)
534   -IP-Config: Complete:
535   - device=eth0, addr=10.82.0.105, mask=255.255.254.0, gw=10.82.1.254,
536   - host=mpc8560ads-003, domain=, nis-domain=(none),
537   - bootserver=163.12.64.52, rootserver=163.12.64.52, rootpath=
538   -NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
539   -Looking up port of RPC 100003/2 on 163.12.64.52
540   -Looking up port of RPC 100005/1 on 163.12.64.52
541   -VFS: Mounted root (nfs filesystem).
542   -Freeing unused kernel memory: 236k init
543   -INIT: version 2.78 booting
544   -Activating swap...
545   -Checking all file systems...
546   -Parallelizing fsck version 1.22 (22-Jun-2001)
547   -Mounting local filesystems...
548   -nothing was mounted
549   -Cleaning: /etc/network/ifstate.
550   -Setting up IP spoofing protection: FAILED
551   -Configuring network interfaces: done.
552   -Starting portmap daemon: portmap.
553   -Cleaning: /tmp /var/lock /var/run.
554   -INIT: Entering runlevel: 2
555   -Starting system log daemon: syslogd klogd.
556   -Starting internet superserver: inetd.
557   -
558   -mpc8560ads-003 login: root
559   -Last login: Thu Jan 1 00:00:05 1970 on console
560   -Linux mpc8560ads-003 2.4.21-rc5 #2 Wed Oct 15 09:13:46 CDT 2003 ppc unknown
561   -
562   -root@mpc8560ads-003:~# ls
563   -21142.o aa e100.o hello.o mii.o timer.o
564   -root@mpc8560ads-003:~# cd /
565   -root@mpc8560ads-003:/# ls
566   -bin boot dev etc home lib mnt opt proc root sbin tmp usr var
567   -root@mpc8560ads-003:/# /sbin/ifconfig
568   -eth0 Link encap:Ethernet HWaddr 00:01:AF:07:9B:8A
569   - inet addr:10.82.0.105 Bcast:10.82.1.255 Mask:255.255.254.0
570   - UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1
571   - RX packets:4608 errors:0 dropped:0 overruns:0 frame:0
572   - TX packets:2610 errors:0 dropped:0 overruns:0 carrier:0
573   - collisions:0 txqueuelen:100
574   - RX bytes:4465943 (4.2 Mb) TX bytes:440944 (430.6 Kb)
575   - Base address:0x4000
576   -
577   -lo Link encap:Local Loopback
578   - inet addr:127.0.0.1 Mask:255.0.0.0
579   - UP LOOPBACK RUNNING MTU:16436 Metric:1
580   - RX packets:4 errors:0 dropped:0 overruns:0 frame:0
581   - TX packets:4 errors:0 dropped:0 overruns:0 carrier:0
582   - collisions:0 txqueuelen:0
583   - RX bytes:296 (296.0 b) TX bytes:296 (296.0 b)
584   -
585   -root@mpc8560ads-003:/# ping 163.12.64.52
586   -PING 163.12.64.52 (163.12.64.52): 56 data bytes
587   -64 bytes from 163.12.64.52: icmp_seq=0 ttl=63 time=0.1 ms
588   -64 bytes from 163.12.64.52: icmp_seq=1 ttl=63 time=0.1 ms
589   -64 bytes from 163.12.64.52: icmp_seq=2 ttl=63 time=0.1 ms
590   -
591   ---- 163.12.64.52 ping statistics ---
592   -3 packets transmitted, 3 packets received, 0% packet loss
593   -round-trip min/avg/max = 0.1/0.1/0.1 ms
594   -root@mpc8560ads-003:/#
  300 +Environment size: 1020/8188 bytes
include/configs/MPC8540ADS.h
Diff comments   View file @ 9aea953
... ... @@ -49,12 +49,6 @@
49 49 #define CONFIG_DDR_DLL /* possible DLL fix needed */
50 50 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
51 51  
52   -/*
53   - * Use Localbus SDRAM to emulate flash before we can program the flash.
54   - * Normally you need a flash-boot image(u-boot.bin).
55   - * If unsure #undef this.
56   - */
57   -#undef CONFIG_RAM_AS_FLASH
58 52  
59 53 /*
60 54 * sysclk for MPC85xx
61 55  
62 56  
... ... @@ -64,24 +58,17 @@
64 58 * 66000000
65 59 *
66 60 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
67   - * is likely the desired value here. The board, however, can run and
68   - * defaults to 66Mhz. In any event, this value must match the settings
69   - * of SW15[1] and SW17[8], and likely SW6[0:1], the SYSCLK as well.
70   - *
71   - * SW17[8] ------+ SW6
72   - * SW15[1] ----+ | [0:1]
73   - * V V V V
74   - * 33MHz 1 1 1 0
75   - * 66MHz 0 0 0 1
  61 + * is likely the desired value here, so that is now the default.
  62 + * The board, however, can run at 66MHz. In any event, this value
  63 + * must match the settings of some switches. Details can be found
  64 + * in the README.mpc85xxads.
76 65 */
77 66  
78   -#define CONFIG_SYS_CLK_FREQ 66000000
79   -
80   -
81   -#if !defined(CONFIG_SPD_EEPROM)
82   -#define CONFIG_DDR_SETTING /* manually set up DDR parameters */
  67 +#ifndef CONFIG_SYS_CLK_FREQ
  68 +#define CONFIG_SYS_CLK_FREQ 33000000
83 69 #endif
84 70  
  71 +
85 72 /*
86 73 * These can be toggled for performance analysis, otherwise use default.
87 74 */
88 75  
89 76  
90 77  
91 78  
92 79  
93 80  
... ... @@ -104,27 +91,42 @@
104 91 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
105 92 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
106 93  
  94 +
  95 +/*
  96 + * DDR Setup
  97 + */
107 98 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
108 99 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
109   -#define CFG_SDRAM_SIZE 128 /* DDR is 128MB */
110 100  
  101 +#if defined(CONFIG_SPD_EEPROM)
  102 + /*
  103 + * Determine DDR configuration from I2C interface.
  104 + */
  105 + #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
  106 +
  107 +#else
  108 + /*
  109 + * Manually set up DDR parameters
  110 + */
  111 + #define CFG_SDRAM_SIZE 128 /* DDR is 128MB */
  112 + #define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
  113 + #define CFG_DDR_CS0_CONFIG 0x80000002
  114 + #define CFG_DDR_TIMING_1 0x37344321
  115 + #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
  116 + #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
  117 + #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
  118 + #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
  119 +#endif
  120 +
  121 +
111 122 /*
112 123 * SDRAM on the Local Bus
113 124 */
114   -#if defined(CONFIG_RAM_AS_FLASH)
115   -#define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
116   -#else
117 125 #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
118   -#endif
119 126 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
120 127  
121   -#if defined(CONFIG_RAM_AS_FLASH)
122   -#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 16M */
123   -#define CFG_BR0_PRELIM 0xf8001801 /* port size 32bit */
124   -#else /* Boot from real Flash */
125 128 #define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */
126 129 #define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */
127   -#endif
128 130  
129 131 #define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
130 132 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */
131 133  
132 134  
... ... @@ -142,21 +144,10 @@
142 144 #undef CFG_RAMBOOT
143 145 #endif
144 146  
145   -#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
146 147  
147 148 #undef CONFIG_CLOCKS_IN_MHZ
148 149  
149   -#if defined(CONFIG_DDR_SETTING)
150   -#define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
151   -#define CFG_DDR_CS0_CONFIG 0x80000002
152   -#define CFG_DDR_TIMING_1 0x37344321
153   -#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
154   -#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
155   -#define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
156   -#define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
157   -#endif
158 150  
159   -
160 151 /*
161 152 * Local Bus Definitions
162 153 */
163 154  
164 155  
165 156  
166 157  
167 158  
168 159  
... ... @@ -244,28 +235,27 @@
244 235 * SDRAM Controller configuration sequence.
245 236 */
246 237 #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
247   - | CFG_LBC_LSDMR_OP_PCHALL) /*0x2861b723*/
  238 + | CFG_LBC_LSDMR_OP_PCHALL)
248 239 #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
249   - | CFG_LBC_LSDMR_OP_ARFRSH) /*0x0861b723*/
  240 + | CFG_LBC_LSDMR_OP_ARFRSH)
250 241 #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
251   - | CFG_LBC_LSDMR_OP_ARFRSH) /*0x0861b723*/
  242 + | CFG_LBC_LSDMR_OP_ARFRSH)
252 243 #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
253   - | CFG_LBC_LSDMR_OP_MRW) /*0x1861b723*/
  244 + | CFG_LBC_LSDMR_OP_MRW)
254 245 #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
255   - | CFG_LBC_LSDMR_OP_NORMAL) /*0x4061b723*/
  246 + | CFG_LBC_LSDMR_OP_NORMAL)
256 247  
257 248  
258   -#if defined(CONFIG_RAM_AS_FLASH)
259   -#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */
260   -#else
261   -#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */
262   -#endif
  249 +/*
  250 + * 32KB, 8-bit wide for ADS config reg
  251 + */
  252 +#define CFG_BR4_PRELIM 0xf8000801
263 253 #define CFG_OR4_PRELIM 0xffffe1f1
264 254 #define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000)
265 255  
266 256 #define CONFIG_L1_INIT_RAM
267 257 #define CFG_INIT_RAM_LOCK 1
268   -#define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */
  258 +#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
269 259 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
270 260  
271 261 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
... ... @@ -321,7 +311,7 @@
321 311 #if defined(CONFIG_PCI)
322 312  
323 313 #define CONFIG_NET_MULTI
324   -#define CONFIG_PCI_PNP /* do pci plug-and-play */
  314 +#define CONFIG_PCI_PNP /* do pci plug-and-play */
325 315  
326 316 #undef CONFIG_EEPRO100
327 317 #undef CONFIG_TULIP
328 318  
329 319  
330 320  
... ... @@ -347,13 +337,15 @@
347 337 #define CONFIG_MII 1 /* MII PHY management */
348 338 #define CONFIG_MPC85XX_TSEC1 1
349 339 #define CONFIG_MPC85XX_TSEC2 1
350   -#define CONFIG_MPC85XX_FEC 1
351 340 #define TSEC1_PHY_ADDR 0
352 341 #define TSEC2_PHY_ADDR 1
353   -#define FEC_PHY_ADDR 3
354 342 #define TSEC1_PHYIDX 0
355 343 #define TSEC2_PHYIDX 0
  344 +
  345 +#define CONFIG_MPC85XX_FEC 1
  346 +#define FEC_PHY_ADDR 3
356 347 #define FEC_PHYIDX 0
  348 +
357 349 #define CONFIG_ETHPRIME "MOTO ENET0"
358 350  
359 351 #endif /* CONFIG_TSEC_ENET */
360 352  
361 353  
362 354  
... ... @@ -363,27 +355,21 @@
363 355 * Environment
364 356 */
365 357 #ifndef CFG_RAMBOOT
366   - #if defined(CONFIG_RAM_AS_FLASH)
367   - #define CFG_ENV_IS_NOWHERE
368   - #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000)
369   - #define CFG_ENV_SIZE 0x2000
370   - #else
371 358 #define CFG_ENV_IS_IN_FLASH 1
372 359 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
373 360 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
374   - #endif
375 361 #define CFG_ENV_SIZE 0x2000
376 362 #else
377   -#define CFG_NO_FLASH 1 /* Flash is not usable now */
378   -#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
379   -#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
380   -#define CFG_ENV_SIZE 0x2000
  363 + #define CFG_NO_FLASH 1 /* Flash is not usable now */
  364 + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
  365 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
  366 + #define CFG_ENV_SIZE 0x2000
381 367 #endif
382 368  
383 369 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
384 370 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
385 371  
386   -#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
  372 +#if defined(CFG_RAMBOOT)
387 373 #if defined(CONFIG_PCI)
388 374 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
389 375 | CFG_CMD_PING \
390 376  
... ... @@ -462,10 +448,11 @@
462 448 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
463 449 #endif
464 450  
465   -/*****************************/
466   -/* Environment Configuration */
467   -/*****************************/
468 451  
  452 +/*
  453 + * Environment Configuration
  454 + */
  455 +
469 456 /* The mac addresses for all ethernet interface */
470 457 #if defined(CONFIG_TSEC_ENET)
471 458 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD
472 459  
... ... @@ -490,13 +477,13 @@
490 477  
491 478 #define CONFIG_BAUDRATE 115200
492 479  
493   -#define CONFIG_EXTRA_ENV_SETTINGS \
  480 +#define CONFIG_EXTRA_ENV_SETTINGS \
494 481 "netdev=eth0\0" \
495 482 "consoledev=ttyS0\0" \
496 483 "ramdiskaddr=400000\0" \
497 484 "ramdiskfile=your.ramdisk.u-boot\0"
498 485  
499   -#define CONFIG_NFSBOOTCOMMAND \
  486 +#define CONFIG_NFSBOOTCOMMAND \
500 487 "setenv bootargs root=/dev/nfs rw " \
501 488 "nfsroot=$serverip:$rootpath " \
502 489 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
include/configs/MPC8560ADS.h
Diff comments   View file @ 9aea953
... ... @@ -45,17 +45,11 @@
45 45 #define CONFIG_TSEC_ENET /* tsec ethernet support */
46 46 #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
47 47 #define CONFIG_ENV_OVERWRITE
48   -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
  48 +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
49 49 #define CONFIG_DDR_ECC /* only for ECC DDR module */
50   -#define CONFIG_DDR_DLL /* possible DLL fix needed */
51   -#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
  50 +#define CONFIG_DDR_DLL /* possible DLL fix needed */
  51 +#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
52 52  
53   -/*
54   - * Use Localbus SDRAM to emulate flash before we can program the flash.
55   - * Normally you need a flash-boot image(u-boot.bin).
56   - * If unsure #undef this.
57   - */
58   -#undef CONFIG_RAM_AS_FLASH
59 53  
60 54 /*
61 55 * sysclk for MPC85xx
62 56  
63 57  
... ... @@ -65,24 +59,17 @@
65 59 * 66000000
66 60 *
67 61 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
68   - * is likely the desired value here. The board, however, can run and
69   - * defaults to 66Mhz. In any event, this value must match the settings
70   - * of SW15[1] and SW17[8], and likely SW6[0:1], the SYSCLK as well.
71   - *
72   - * SW17[8] ------+ SW6
73   - * SW15[1] ----+ | [0:1]
74   - * V V V V
75   - * 33MHz 1 1 1 0
76   - * 66MHz 0 0 0 1
  62 + * is likely the desired value here, so that is now the default.
  63 + * The board, however, can run at 66MHz. In any event, this value
  64 + * must match the settings of some switches. Details can be found
  65 + * in the README.mpc85xxads.
77 66 */
78 67  
79   -#define CONFIG_SYS_CLK_FREQ 66000000
80   -
81   -
82   -#if !defined(CONFIG_SPD_EEPROM)
83   -#define CONFIG_DDR_SETTING /* manually set up DDR parameters */
  68 +#ifndef CONFIG_SYS_CLK_FREQ
  69 +#define CONFIG_SYS_CLK_FREQ 33000000
84 70 #endif
85 71  
  72 +
86 73 /*
87 74 * These can be toggled for performance analysis, otherwise use default.
88 75 */
... ... @@ -94,7 +81,7 @@
94 81  
95 82 #define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
96 83  
97   -#undef CFG_DRAM_TEST /* memory test, takes time */
  84 +#undef CFG_DRAM_TEST /* memory test, takes time */
98 85 #define CFG_MEMTEST_START 0x00200000 /* memtest region */
99 86 #define CFG_MEMTEST_END 0x00400000
100 87  
101 88  
102 89  
103 90  
104 91  
105 92  
106 93  
107 94  
... ... @@ -104,30 +91,45 @@
104 91 * actual resources get mapped (not physical addresses)
105 92 */
106 93 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
107   -#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
  94 +#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
108 95 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
109 96  
  97 +
  98 +/*
  99 + * DDR Setup
  100 + */
110 101 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
111 102 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
112   -#define CFG_SDRAM_SIZE 128 /* DDR is 128MB */
113 103  
  104 +#if defined(CONFIG_SPD_EEPROM)
  105 + /*
  106 + * Determine DDR configuration from I2C interface.
  107 + */
  108 + #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
  109 +
  110 +#else
  111 + /*
  112 + * Manually set up DDR parameters
  113 + */
  114 + #define CFG_SDRAM_SIZE 128 /* DDR is 128MB */
  115 + #define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
  116 + #define CFG_DDR_CS0_CONFIG 0x80000002
  117 + #define CFG_DDR_TIMING_1 0x37344321
  118 + #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
  119 + #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
  120 + #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
  121 + #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
  122 +#endif
  123 +
  124 +
114 125 /*
115 126 * SDRAM on the Local Bus
116 127 */
117   -#if defined(CONFIG_RAM_AS_FLASH)
118   -#define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
119   -#else
120 128 #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
121   -#endif
122 129 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
123 130  
124   -#if defined(CONFIG_RAM_AS_FLASH)
125   -#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 16M */
126   -#define CFG_BR0_PRELIM 0xf8001801 /* port size 32bit */
127   -#else /* Boot from real Flash */
128 131 #define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */
129 132 #define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */
130   -#endif
131 133  
132 134 #define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
133 135 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */
134 136  
135 137  
... ... @@ -145,21 +147,10 @@
145 147 #undef CFG_RAMBOOT
146 148 #endif
147 149  
148   -#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
149 150  
150 151 #undef CONFIG_CLOCKS_IN_MHZ
151 152  
152   -#if defined(CONFIG_DDR_SETTING)
153   -#define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
154   -#define CFG_DDR_CS0_CONFIG 0x80000002
155   -#define CFG_DDR_TIMING_1 0x37344321
156   -#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
157   -#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
158   -#define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
159   -#define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
160   -#endif
161 153  
162   -
163 154 /*
164 155 * Local Bus Definitions
165 156 */
166 157  
167 158  
168 159  
169 160  
170 161  
171 162  
... ... @@ -247,28 +238,27 @@
247 238 * SDRAM Controller configuration sequence.
248 239 */
249 240 #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
250   - | CFG_LBC_LSDMR_OP_PCHALL) /*0x2861b723*/
  241 + | CFG_LBC_LSDMR_OP_PCHALL)
251 242 #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
252   - | CFG_LBC_LSDMR_OP_ARFRSH) /*0x0861b723*/
  243 + | CFG_LBC_LSDMR_OP_ARFRSH)
253 244 #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
254   - | CFG_LBC_LSDMR_OP_ARFRSH) /*0x0861b723*/
  245 + | CFG_LBC_LSDMR_OP_ARFRSH)
255 246 #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
256   - | CFG_LBC_LSDMR_OP_MRW) /*0x1861b723*/
  247 + | CFG_LBC_LSDMR_OP_MRW)
257 248 #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
258   - | CFG_LBC_LSDMR_OP_NORMAL) /*0x4061b723*/
  249 + | CFG_LBC_LSDMR_OP_NORMAL)
259 250  
260 251  
261   -#if defined(CONFIG_RAM_AS_FLASH)
262   -#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */
263   -#else
264   -#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */
265   -#endif
  252 +/*
  253 + * 32KB, 8-bit wide for ADS config reg
  254 + */
  255 +#define CFG_BR4_PRELIM 0xf8000801
266 256 #define CFG_OR4_PRELIM 0xffffe1f1
267 257 #define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000)
268 258  
269 259 #define CONFIG_L1_INIT_RAM
270 260 #define CFG_INIT_RAM_LOCK 1
271   -#define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */
  261 +#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
272 262 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
273 263  
274 264 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
275 265  
... ... @@ -295,11 +285,11 @@
295 285 #endif
296 286  
297 287 /* I2C */
298   -#define CONFIG_HARD_I2C /* I2C with hardware support*/
  288 +#define CONFIG_HARD_I2C /* I2C with hardware support*/
299 289 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
300 290 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
301 291 #define CFG_I2C_SLAVE 0x7F
302   -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
  292 +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
303 293  
304 294 /* RapidIO MMU */
305 295 #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
... ... @@ -320,7 +310,7 @@
320 310 #if defined(CONFIG_PCI)
321 311  
322 312 #define CONFIG_NET_MULTI
323   -#define CONFIG_PCI_PNP /* do pci plug-and-play */
  313 +#define CONFIG_PCI_PNP /* do pci plug-and-play */
324 314  
325 315 #undef CONFIG_EEPRO100
326 316 #undef CONFIG_TULIP
327 317  
328 318  
329 319  
330 320  
331 321  
332 322  
... ... @@ -402,34 +392,28 @@
402 392 * Environment
403 393 */
404 394 #ifndef CFG_RAMBOOT
405   - #if defined(CONFIG_RAM_AS_FLASH)
406   - #define CFG_ENV_IS_NOWHERE
407   - #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000)
408   - #define CFG_ENV_SIZE 0x2000
409   - #else
410 395 #define CFG_ENV_IS_IN_FLASH 1
411 396 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
412 397 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
413   - #endif
414 398 #define CFG_ENV_SIZE 0x2000
415 399 #else
416   -#define CFG_NO_FLASH 1 /* Flash is not usable now */
417   -#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
418   -#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
419   -#define CFG_ENV_SIZE 0x2000
  400 + #define CFG_NO_FLASH 1 /* Flash is not usable now */
  401 + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
  402 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
  403 + #define CFG_ENV_SIZE 0x2000
420 404 #endif
421 405  
422 406 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
423 407 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
424 408  
425   -#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
  409 +#if defined(CFG_RAMBOOT)
426 410 #if defined(CONFIG_PCI)
427 411 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
428   - | CFG_CMD_PCI \
429 412 | CFG_CMD_PING \
  413 + | CFG_CMD_PCI \
430 414 | CFG_CMD_I2C) \
431 415 & \
432   - ~(CFG_CMD_ENV \
  416 + ~(CFG_CMD_ENV \
433 417 | CFG_CMD_LOADS))
434 418 #elif defined(CONFIG_TSEC_ENET)
435 419 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
... ... @@ -510,6 +494,11 @@
510 494 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
511 495 #endif
512 496  
  497 +
  498 +/*
  499 + * Environment Configuration
  500 + */
  501 +
513 502 /* The mac addresses for all ethernet interface */
514 503 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
515 504 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD
516 505  
517 506  
... ... @@ -529,18 +518,18 @@
529 518  
530 519 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
531 520  
532   -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
  521 +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
533 522 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
534 523  
535 524 #define CONFIG_BAUDRATE 115200
536 525  
537   -#define CONFIG_EXTRA_ENV_SETTINGS \
  526 +#define CONFIG_EXTRA_ENV_SETTINGS \
538 527 "netdev=eth0\0" \
539 528 "consoledev=ttyS0\0" \
540 529 "ramdiskaddr=400000\0" \
541 530 "ramdiskfile=your.ramdisk.u-boot\0"
542 531  
543   -#define CONFIG_NFSBOOTCOMMAND \
  532 +#define CONFIG_NFSBOOTCOMMAND \
544 533 "setenv bootargs root=/dev/nfs rw " \
545 534 "nfsroot=$serverip:$rootpath " \
546 535 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
include/configs/stxgp3.h
Diff comments   View file @ 9aea953
... ... @@ -39,7 +39,6 @@
39 39 #define CONFIG_BOOKE 1 /* BOOKE */
40 40 #define CONFIG_E500 1 /* BOOKE e500 family */
41 41 #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
42   -#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
43 42 #define CONFIG_MPC8560 1 /* MPC8560 specific */
44 43 #define CONFIG_STXGP3 1 /* Silicon Tx GPPP board specific*/
45 44  
46 45  
47 46  
48 47  
... ... @@ -49,15 +48,12 @@
49 48 #define CONFIG_ENV_OVERWRITE
50 49 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
51 50 #undef CONFIG_DDR_ECC /* only for ECC DDR module */
52   -
53   -#if defined(CONFIG_MPC85xx_REV1)
54 51 #define CONFIG_DDR_DLL /* possible DLL fix needed */
55   -#endif
  52 +#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
56 53  
57   -/* Using Localbus SDRAM to emulate flash before we can program the flash,
58   - * normally you need a flash-boot image(u-boot.bin), if so undef this.
  54 +
  55 +/* sysclk for MPC85xx
59 56 */
60   -#undef CONFIG_RAM_AS_FLASH
61 57  
62 58 #define CONFIG_SYS_CLK_FREQ 33333333 /* most pci cards are 33Mhz */
63 59  
64 60  
65 61  
66 62  
67 63  
68 64  
69 65  
70 66  
... ... @@ -65,55 +61,29 @@
65 61 */
66 62 #define CONFIG_SHOW_ACTIVITY 1
67 63  
68   -#if !defined(CONFIG_SPD_EEPROM) /* manually set up DDR parameters */
69   -#define CONFIG_DDR_SETTING
70   -#endif
71   -
72   -/* below can be toggled for performance analysis. otherwise use default */
  64 +/*
  65 + * These can be toggled for performance analysis, otherwise use default.
  66 + */
73 67 #define CONFIG_L2_CACHE /* toggle L2 cache */
74   -#undef CONFIG_BTB /* toggle branch predition */
75   -#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */
  68 +#define CONFIG_BTB /* toggle branch predition */
  69 +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
76 70  
77   -#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */
  71 +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
78 72  
79 73 #undef CFG_DRAM_TEST /* memory test, takes time */
80 74 #define CFG_MEMTEST_START 0x00200000 /* memtest region */
81 75 #define CFG_MEMTEST_END 0x00400000
82 76  
83   -#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
84   - defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
85   - defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
86   -#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
87   -#endif
88 77  
89   -/*
90   - * Base addresses -- Note these are effective addresses where the
91   - * actual resources get mapped (not physical addresses)
  78 +/* Localbus SDRAM is an option, not all boards have it.
  79 + * This address, however, is used to configure a 256M local bus
  80 + * window that includes the Config latch below.
92 81 */
93   -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
94   -#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
  82 +#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
  83 +#define CFG_LBC_SDRAM_SIZE 256 /* LBC SDRAM is 64MB */
95 84  
96   -/* GPPP supports up to 2G of DRAM. Allocate up to 1G until we get
97   - * a chance to try it out. Actual size is always read from sdram eeprom.
98   - */
99   -#define CFG_SDRAM_SIZE 1024 /* DDR is 1GB */
100   -
101   -/* Localbus SDRAM is an option, not all boards have it.
102   -*/
103   -#if defined(CONFIG_RAM_AS_FLASH)
104   -#define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
105   -#else
106   -#define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */
107   -#endif
108   -#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
109   -
110   -#if defined(CONFIG_RAM_AS_FLASH)
111   -#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 16M */
112   -#define CFG_BR0_PRELIM 0xf8001801 /* port size 32bit */
113   -#else /* Boot from real Flash */
114 85 #define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */
115 86 #define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */
116   -#endif
117 87  
118 88 #define CFG_OR0_PRELIM 0xff000ff7 /* 16 MB Flash */
119 89 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */
... ... @@ -123,7 +93,7 @@
123 93 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
124 94  
125 95 /* The configuration latch is Chip Select 1.
126   - * It's an 8-bit latch in the upper 8 bits of the word.
  96 + * It's an 8-bit latch in the lower 8 bits of the word.
127 97 */
128 98 #define CFG_BR1_PRELIM 0xfc001801 /* 32-bit port */
129 99 #define CFG_OR1_PRELIM 0xffff0ff7 /* 64K is enough */
130 100  
131 101  
... ... @@ -146,18 +116,19 @@
146 116 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
147 117  
148 118  
149   -#define SPD_EEPROM_ADDRESS 0x54 /* DDR DIMM */
  119 +/*
  120 + * DDR Setup
  121 + */
150 122  
151   -#if defined(CONFIG_DDR_SETTING)
152   -#define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
153   -#define CFG_DDR_CS0_CONFIG 0x80000002
154   -#define CFG_DDR_TIMING_1 0x37344321
155   -#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning*/
156   -#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR*/
157   -#define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
158   -#define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page*/
159   -#endif
  123 +/*
  124 + * Base addresses -- Note these are effective addresses where the
  125 + * actual resources get mapped (not physical addresses)
  126 + */
  127 +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
  128 +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
160 129  
  130 +#define SPD_EEPROM_ADDRESS 0x54 /* DDR DIMM */
  131 +
161 132 #undef CONFIG_CLOCKS_IN_MHZ
162 133  
163 134 /* local bus definitions */
164 135  
165 136  
166 137  
167 138  
168 139  
169 140  
170 141  
171 142  
172 143  
173 144  
... ... @@ -213,37 +184,65 @@
213 184 #undef CFG_I2C_NOPROBES
214 185 #endif
215 186  
216   -#define CFG_PCI_MEM_BASE 0xe0000000
217   -#define CFG_PCI_MEM_PHYS 0xe0000000
218   -#define CFG_PCI_MEM_SIZE 0x10000000
  187 +/* RapdIO Map configuration, mapped 1:1.
  188 +*/
  189 +#define CFG_RIO_MEM_BASE 0xc0000000
  190 +#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
  191 +#define CFG_RIO_MEM_SIZE 0x200000000 /* 512 M */
219 192  
  193 +/* Standard 8560 PCI addressing, mapped 1:1.
  194 +*/
  195 +#define CFG_PCI1_MEM_BASE 0x80000000
  196 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
  197 +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
  198 +#define CFG_PCI1_IO_BASE 0xe2000000
  199 +#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
  200 +#define CFG_PCI1_IO_SIZE 0x01000000 /* 16 M */
  201 +
220 202 #if defined(CONFIG_PCI) /* PCI Ethernet card */
  203 +
221 204 #define CONFIG_NET_MULTI
222   -#define CONFIG_EEPRO100
223   -#undef CONFIG_TULIP
224 205 #define CONFIG_PCI_PNP /* do pci plug-and-play */
225   - #if !defined(CONFIG_PCI_PNP)
  206 +
  207 +#undef CONFIG_EEPRO100
  208 +#undef CONFIG_TULIP
  209 +
  210 +#if !defined(CONFIG_PCI_PNP)
226 211 #define PCI_ENET0_IOADDR 0xe0000000
227 212 #define PCI_ENET0_MEMADDR 0xe0000000
228 213 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
229   - #endif
230   -#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
231   -#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
232   -#if defined(CONFIG_MPC85xx_REV1) /* Errata PCI 7 */
233   - #define CFG_PCI_SUBSYS_DEVICEID 0x0003
234   -#else
235   - #define CFG_PCI_SUBSYS_DEVICEID 0x0009
236 214 #endif
237   -#elif defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */
  215 +
  216 +#undef CONFIG_PCI_SCAN_SHOW
  217 +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
  218 +
  219 +#endif /* CONFIG_PCI */
  220 +
  221 +#if defined(CONFIG_TSEC_ENET)
  222 +
  223 +#ifndef CONFIG_NET_MULTI
238 224 #define CONFIG_NET_MULTI 1
239   -#define CONFIG_PHY_M88E1011 1 /* GigaBit Ether PHY */
  225 +#endif
  226 +
240 227 #define CONFIG_MII 1 /* MII PHY management */
241   -#define CONFIG_PHY_ADDR 8 /* PHY address */
  228 +
  229 +#define CONFIG_MPC85XX_TSEC1 1
  230 +#define CONFIG_MPC85XX_TSEC2 1
  231 +#undef CONFIG_MPS85XX_FEC
  232 +
  233 +#define TSEC1_PHY_ADDR 2
  234 +#define TSEC2_PHY_ADDR 4
  235 +#define TSEC1_PHYIDX 0
  236 +#define TSEC2_PHYIDX 0
  237 +#define CONFIG_ETHPRIME "MOTO ENET0"
  238 +
242 239 #elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
  240 +
243 241 #define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */
244 242 #undef CONFIG_ETHER_NONE /* define if ether on something else */
245 243 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */
246   - #if (CONFIG_ETHER_INDEX == 2)
  244 +
  245 +#if (CONFIG_ETHER_INDEX == 2)
247 246 /*
248 247 * - Rx-CLK is CLK13
249 248 * - Tx-CLK is CLK14
250 249  
251 250  
252 251  
253 252  
254 253  
255 254  
256 255  
257 256  
258 257  
... ... @@ -259,59 +258,41 @@
259 258 #define CFG_FCC_PSMR 0
260 259 #endif
261 260 #define FETH2_RST 0x01
262   - #elif (CONFIG_ETHER_INDEX == 3)
  261 +#elif (CONFIG_ETHER_INDEX == 3)
263 262 /* need more definitions here for FE3 */
264 263 #define FETH3_RST 0x80
265   - #endif /* CONFIG_ETHER_INDEX */
  264 +#endif /* CONFIG_ETHER_INDEX */
  265 +
  266 +/* MDIO is done through the TSEC0 control.
  267 +*/
266 268 #define CONFIG_MII /* MII PHY management */
267 269 #undef CONFIG_BITBANGMII /* bit-bang MII PHY management */
268   -/*
269   - * GPIO pins used for bit-banged MII communications
270   - */
271   -#define MDIO_PORT 2 /* Port C */
272   -#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
273   -#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
274   -#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
275 270  
276   -#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
277   - else iop->pdat &= ~0x00400000
278   -
279   -#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
280   - else iop->pdat &= ~0x00200000
281   -
282   -#define MIIDELAY udelay(1)
283 271 #endif
284 272  
285 273 /* Environment */
286 274 /* We use the top boot sector flash, so we have some 16K sectors for env
287   - * But....functions don't seem smart enough yet.
288 275 */
289 276 #ifndef CFG_RAMBOOT
290   - #if defined(CONFIG_RAM_AS_FLASH)
291   - #define CFG_ENV_IS_NOWHERE
292   - #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000)
293   - #define CFG_ENV_SIZE 0x2000
294   - #else
295 277 #define CFG_ENV_IS_IN_FLASH 1
296 278 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x60000)
297 279 #define CFG_ENV_SECT_SIZE 0x4000 /* 16K (one top sector) for env */
298   - #endif
299 280 #define CFG_ENV_SIZE 0x2000
300 281 #else
301   -#define CFG_NO_FLASH 1 /* Flash is not usable now */
302   -#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
303   -#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
304   -#define CFG_ENV_SIZE 0x2000
  282 + #define CFG_NO_FLASH 1 /* Flash is not usable now */
  283 + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
  284 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
  285 + #define CFG_ENV_SIZE 0x2000
305 286 #endif
306 287  
307 288 #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,38400"
308   -#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xff900000"
  289 +#define CONFIG_BOOTCOMMAND "bootm 0xff000000 0xff100000"
309 290 #define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
310 291  
311 292 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
312 293 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
313 294  
314   -#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
  295 +#if defined(CFG_RAMBOOT)
315 296 #if defined(CONFIG_PCI)
316 297 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \
317 298 CFG_CMD_PING | CFG_CMD_I2C) & \
318 299  
319 300  
... ... @@ -329,13 +310,13 @@
329 310 #else
330 311 #if defined(CONFIG_PCI)
331 312 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \
332   - CFG_CMD_PING | CFG_CMD_I2C)
  313 + CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C)
333 314 #elif defined(CONFIG_TSEC_ENET)
334 315 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | \
335   - CFG_CMD_MII | CFG_CMD_I2C)
  316 + CFG_CMD_ELF | CFG_CMD_MII | CFG_CMD_I2C)
336 317 #elif defined(CONFIG_ETHER_ON_FCC)
337 318 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \
338   - CFG_CMD_PING | CFG_CMD_I2C)
  319 + CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C)
339 320 #endif
340 321 #endif
341 322 #include <cmd_confdefs.h>
... ... @@ -387,9 +368,9 @@
387 368  
388 369 /*Note: change below for your network setting!!! */
389 370 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
390   -#define CONFIG_ETHADDR 00:01:af:07:9b:8a
391   -#define CONFIG_ETH1ADDR 00:01:af:07:9b:8b
392   -#define CONFIG_ETH2ADDR 00:01:af:07:9b:8c
  371 +#define CONFIG_ETHADDR 00:e0:0c:07:9b:8a
  372 +#define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b
  373 +#define CONFIG_ETH2ADDR 00:e0:0c:07:9b:8c
393 374 #endif
394 375  
395 376 #define CONFIG_SERVERIP 192.168.85.1
... ... @@ -399,6 +380,7 @@
399 380 #define CONFIG_HOSTNAME STX_GP3
400 381 #define CONFIG_ROOTPATH /gppproot
401 382 #define CONFIG_BOOTFILE uImage
  383 +#define CONFIG_LOADADDR 0x1000000
402 384  
403 385 #endif /* __CONFIG_H */
... ... @@ -20,13 +20,28 @@
20 20 * initial memory mapping like legacy BAT registers do. Usually we
21 21 * use four MAS registers(MAS0-3) to operate on TLB1 entries.
22 22 *
  23 + * While there are 16 Entries with variable Page Sizes in TLB1,
  24 + * there are also 256 Entries with fixed 4K pages in TLB0.
  25 + *
23 26 * We also need LAWs(Local Access Window) to associate a range of
24 27 * the local 32-bit address space with a particular target interface
25 28 * such as PCI/PCI-X, RapidIO, Local Bus and DDR SDRAM.
26 29 *
27 30 * We put TLB1/LAW code here because memory mapping is board-specific
28 31 * instead of cpu-specific.
  32 + *
  33 + * While these macros are all nominally for TLB1 by name, they can
  34 + * also be used for TLB0 as well.
29 35 */
  36 +
  37 +
  38 +/*
  39 + * Convert addresses to Effective and Real Page Numbers.
  40 + * Grab the high 20-bits and shift 'em down, dropping the "byte offset".
  41 + */
  42 +#define E500_TLB_EPN(addr) (((addr) >> 12) & 0xfffff)
  43 +#define E500_TLB_RPN(addr) (((addr) >> 12) & 0xfffff)
  44 +
30 45  
31 46 /* MAS0
32 47 * tlbsel(TLB Select):0,1