Eric Lee / smarc-uboot

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Commit 9d0fc8110e7e755239329c26f300d5fc9946d3ec

Authored by Dirk Behme
Committed by Jean-Christophe PLAGNIOL-VILLARD
1 parent f904cdbb68
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

OMAP3: Add Overo board 

Add Overo board support.

Signed-off-by: Steve Sakoman <sakoman@gmail.com>
Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
Signed-off-by: Jason Kridner <jkridner@beagleboard.org>

Showing 11 changed files with 949 additions and 2 deletions Side-by-side Diff

... ... @@ -599,6 +599,10 @@
599 599  
600 600 nmdk8815 ARM926EJS (Nomadik 8815 Soc)
601 601  
  602 +Steve Sakoman <sakoman@gmail.com>
  603 +
  604 + omap3_overo ARM CORTEX-A8 (OMAP3xx SoC)
  605 +
602 606 Robert Schwebel <r.schwebel@pengutronix.de>
603 607  
604 608 csb226 xscale
... ... @@ -549,6 +549,7 @@
549 549 #########################################################################
550 550 LIST_ARM_CORTEX_A8=" \
551 551 omap3_beagle \
  552 + omap3_overo \
552 553 "
553 554  
554 555 #########################################################################
... ... @@ -2911,6 +2911,9 @@
2911 2911 omap3_beagle_config : unconfig
2912 2912 @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 beagle omap3 omap3
2913 2913  
  2914 +omap3_overo_config : unconfig
  2915 + @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 overo omap3 omap3
  2916 +
2914 2917 #########################################################################
2915 2918 ## XScale Systems
2916 2919 #########################################################################
board/omap3/common/Makefile
Diff comments   View file @ 9d0fc81
... ... @@ -30,6 +30,7 @@
30 30 LIB = $(obj)lib$(VENDOR).a
31 31  
32 32 COBJS-$(CONFIG_OMAP3_BEAGLE) += power.o
  33 +COBJS-$(CONFIG_OMAP3_OVERO) += power.o
33 34  
34 35 COBJS := $(COBJS-y)
35 36 SRCS := $(COBJS:.o=.c)
board/omap3/overo/Makefile
Diff comments   View file @ 9d0fc81
  1 +#
  2 +# (C) Copyright 2000, 2001, 2002
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# See file CREDITS for list of people who contributed to this
  6 +# project.
  7 +#
  8 +# This program is free software; you can redistribute it and/or
  9 +# modify it under the terms of the GNU General Public License as
  10 +# published by the Free Software Foundation; either version 2 of
  11 +# the License, or (at your option) any later version.
  12 +#
  13 +# This program is distributed in the hope that it will be useful,
  14 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 +# GNU General Public License for more details.
  17 +#
  18 +# You should have received a copy of the GNU General Public License
  19 +# along with this program; if not, write to the Free Software
  20 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 +# MA 02111-1307 USA
  22 +#
  23 +
  24 +include $(TOPDIR)/config.mk
  25 +
  26 +LIB = $(obj)lib$(BOARD).a
  27 +
  28 +COBJS := overo.o
  29 +
  30 +SRCS := $(COBJS:.o=.c)
  31 +OBJS := $(addprefix $(obj),$(COBJS))
  32 +
  33 +$(LIB): $(obj).depend $(OBJS)
  34 + $(AR) $(ARFLAGS) $@ $(OBJS)
  35 +
  36 +clean:
  37 + rm -f $(OBJS)
  38 +
  39 +distclean: clean
  40 + rm -f $(LIB) core *.bak $(obj).depend
  41 +
  42 +#########################################################################
  43 +
  44 +# defines $(obj).depend target
  45 +include $(SRCTREE)/rules.mk
  46 +
  47 +sinclude $(obj).depend
board/omap3/overo/config.mk
Diff comments   View file @ 9d0fc81
  1 +#
  2 +# Overo uses OMAP3 (ARM-CortexA8) cpu
  3 +#
  4 +# See file CREDITS for list of people who contributed to this
  5 +# project.
  6 +#
  7 +# This program is free software; you can redistribute it and/or
  8 +# modify it under the terms of the GNU General Public License as
  9 +# published by the Free Software Foundation; either version 2 of
  10 +# the License, or (at your option) any later version.
  11 +#
  12 +# This program is distributed in the hope that it will be useful,
  13 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 +# GNU General Public License for more details.
  16 +#
  17 +# You should have received a copy of the GNU General Public License
  18 +# along with this program; if not, write to the Free Software
  19 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 +# MA 02111-1307 USA
  21 +#
  22 +# Physical Address:
  23 +# 8000'0000 (bank0)
  24 +# A000/0000 (bank1)
  25 +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
  26 +# (mem base + reserved)
  27 +
  28 +# For use with external or internal boots.
  29 +TEXT_BASE = 0x80e80000
board/omap3/overo/overo.c
Diff comments   View file @ 9d0fc81
  1 +/*
  2 + * Maintainer : Steve Sakoman <steve@sakoman.com>
  3 + *
  4 + * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by
  5 + * Richard Woodruff <r-woodruff2@ti.com>
  6 + * Syed Mohammed Khasim <khasim@ti.com>
  7 + * Sunil Kumar <sunilsaini05@gmail.com>
  8 + * Shashi Ranjan <shashiranjanmca05@gmail.com>
  9 + *
  10 + * (C) Copyright 2004-2008
  11 + * Texas Instruments, <www.ti.com>
  12 + *
  13 + * See file CREDITS for list of people who contributed to this
  14 + * project.
  15 + *
  16 + * This program is free software; you can redistribute it and/or
  17 + * modify it under the terms of the GNU General Public License as
  18 + * published by the Free Software Foundation; either version 2 of
  19 + * the License, or (at your option) any later version.
  20 + *
  21 + * This program is distributed in the hope that it will be useful,
  22 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24 + * GNU General Public License for more details.
  25 + *
  26 + * You should have received a copy of the GNU General Public License
  27 + * along with this program; if not, write to the Free Software
  28 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29 + * MA 02111-1307 USA
  30 + */
  31 +#include <common.h>
  32 +#include <asm/io.h>
  33 +#include <asm/arch/mux.h>
  34 +#include <asm/arch/sys_proto.h>
  35 +#include <asm/mach-types.h>
  36 +#include "overo.h"
  37 +
  38 +/******************************************************************************
  39 + * Routine: board_init
  40 + * Description: Early hardware init.
  41 + *****************************************************************************/
  42 +int board_init(void)
  43 +{
  44 + DECLARE_GLOBAL_DATA_PTR;
  45 +
  46 + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
  47 + /* board id for Linux */
  48 + gd->bd->bi_arch_number = MACH_TYPE_OVERO;
  49 + /* boot param addr */
  50 + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
  51 +
  52 + return 0;
  53 +}
  54 +
  55 +/******************************************************************************
  56 + * Routine: misc_init_r
  57 + * Description: Configure board specific parts
  58 + *****************************************************************************/
  59 +int misc_init_r(void)
  60 +{
  61 + gpio_t *gpio5_base = (gpio_t *)OMAP34XX_GPIO5_BASE;
  62 + gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE;
  63 +
  64 + power_init_r();
  65 +
  66 + /* Configure GPIOs to output */
  67 + writel(~((GPIO10) | GPIO9 | GPIO3 | GPIO2), &gpio6_base->oe);
  68 + writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
  69 + GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe);
  70 +
  71 + /* Set GPIOs */
  72 + writel(GPIO10 | GPIO9 | GPIO3 | GPIO2, &gpio6_base->setdataout);
  73 + writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
  74 + GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);
  75 +
  76 + return 0;
  77 +}
  78 +
  79 +/******************************************************************************
  80 + * Routine: set_muxconf_regs
  81 + * Description: Setting up the configuration Mux registers specific to the
  82 + * hardware. Many pins need to be moved from protect to primary
  83 + * mode.
  84 + *****************************************************************************/
  85 +void set_muxconf_regs(void)
  86 +{
  87 + MUX_OVERO();
  88 +}
board/omap3/overo/overo.h
Diff comments   View file @ 9d0fc81
  1 +/*
  2 + * (C) Copyright 2008
  3 + * Steve Sakoman <steve@sakoman.com>
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +#ifndef _OVERO_H_
  24 +#define _OVERO_H_
  25 +
  26 +const omap3_sysinfo sysinfo = {
  27 + SDP_3430_V1,
  28 + SDP_3430_V2,
  29 + DDR_STACKED,
  30 + "3503",
  31 + "Gumstix Overo board",
  32 +#if defined(CONFIG_ENV_IS_IN_ONENAND)
  33 + "OneNAND",
  34 +#else
  35 + "NAND",
  36 +#endif
  37 +};
  38 +
  39 +/*
  40 + * IEN - Input Enable
  41 + * IDIS - Input Disable
  42 + * PTD - Pull type Down
  43 + * PTU - Pull type Up
  44 + * DIS - Pull type selection is inactive
  45 + * EN - Pull type selection is active
  46 + * M0 - Mode 0
  47 + * The commented string gives the final mux configuration for that pin
  48 + */
  49 +#define MUX_OVERO() \
  50 + /*SDRC*/\
  51 + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
  52 + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
  53 + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
  54 + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
  55 + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
  56 + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
  57 + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
  58 + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
  59 + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
  60 + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
  61 + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
  62 + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
  63 + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
  64 + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
  65 + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
  66 + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
  67 + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
  68 + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
  69 + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
  70 + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
  71 + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
  72 + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
  73 + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
  74 + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
  75 + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
  76 + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
  77 + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
  78 + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
  79 + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
  80 + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
  81 + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
  82 + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
  83 + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
  84 + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
  85 + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
  86 + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
  87 + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
  88 + /*GPMC*/\
  89 + MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
  90 + MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
  91 + MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
  92 + MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
  93 + MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
  94 + MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
  95 + MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
  96 + MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
  97 + MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
  98 + MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
  99 + MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
  100 + MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
  101 + MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
  102 + MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
  103 + MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
  104 + MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
  105 + MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
  106 + MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
  107 + MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
  108 + MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
  109 + MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
  110 + MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
  111 + MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
  112 + MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
  113 + MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
  114 + MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
  115 + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
  116 + MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
  117 + MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
  118 + MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /*GPIO_54*/\
  119 + /* - MMC1_WP*/\
  120 + MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
  121 + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\
  122 + MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) /*GPMC_nCS6*/\
  123 + MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) /*GPMC_nCS7*/\
  124 + MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nCS3*/\
  125 + MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
  126 + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
  127 + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
  128 + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
  129 + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
  130 + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
  131 + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
  132 + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
  133 + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPMC_nCS3*/\
  134 + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_nCS3*/\
  135 + /*DSS*/\
  136 + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
  137 + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
  138 + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
  139 + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
  140 + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
  141 + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
  142 + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
  143 + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
  144 + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
  145 + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
  146 + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
  147 + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
  148 + MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
  149 + MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
  150 + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
  151 + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
  152 + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
  153 + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
  154 + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
  155 + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
  156 + MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
  157 + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
  158 + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
  159 + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
  160 + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
  161 + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
  162 + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
  163 + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
  164 + /*CAMERA*/\
  165 + MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
  166 + MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
  167 + MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
  168 + MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
  169 + MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*CAM_FLD*/\
  170 + MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
  171 + MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
  172 + MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
  173 + MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
  174 + MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
  175 + MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
  176 + MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
  177 + MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
  178 + MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
  179 + MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
  180 + MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
  181 + MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
  182 + MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
  183 + MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M0)) /*CAM_WEN*/\
  184 + MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
  185 + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
  186 + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
  187 + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
  188 + MUX_VAL(CP(CSI2_DY1), (IEN | PTU | EN | M4)) /*GPIO_115*/\
  189 + /*Audio Interface */\
  190 + MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
  191 + MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
  192 + MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
  193 + MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
  194 + /*Expansion card */\
  195 + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
  196 + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
  197 + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
  198 + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
  199 + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
  200 + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
  201 + MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
  202 + MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
  203 + MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
  204 + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
  205 + /*Wireless LAN */\
  206 + MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
  207 + MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
  208 + MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
  209 + MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
  210 + MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
  211 + MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
  212 + MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT0*/\
  213 + MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT1*/\
  214 + MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) /*MMC2_DIR_CMD*/\
  215 + MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)) /*MMC2_CLKIN*/\
  216 + /*Bluetooth*/\
  217 + MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\
  218 + MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
  219 + MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
  220 + MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\
  221 + MUX_VAL(CP(UART2_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_144 - LCD_EN*/\
  222 + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_145*/\
  223 + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M4)) /*GPIO_146*/\
  224 + MUX_VAL(CP(UART2_RX), (IDIS | PTD | DIS | M4)) /*GPIO_147*/\
  225 + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
  226 + MUX_VAL(CP(UART1_RTS), (IEN | PTU | DIS | M4)) /*GPIO_149*/ \
  227 + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M4)) /*GPIO_150-MMC3_WP*/\
  228 + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
  229 + MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M0)) /*McBSP4_CLKX*/\
  230 + MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M0)) /*McBSP4_DR*/\
  231 + MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M0)) /*McBSP4_DX*/\
  232 + MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M0)) /*McBSP4_FSX*/\
  233 + MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) /*McBSP1_CLKR*/\
  234 + MUX_VAL(CP(MCBSP1_FSR), (IEN | PTD | DIS | M0)) /*McBSP1_FSR*/\
  235 + MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M0)) /*McBSP1_DX*/\
  236 + MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) /*McBSP1_DR*/\
  237 + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\
  238 + MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) /*McBSP1_FSX*/\
  239 + MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) /*McBSP1_CLKX*/\
  240 + /*Serial Interface*/\
  241 + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\
  242 + MUX_VAL(CP(UART3_RTS_SD), (IEN | PTU | EN | M4)) /*GPIO_164 W2W_*/\
  243 + /* BT_NRESET*/\
  244 + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTU | EN | M0)) /*UART3_RX_IRRX*/\
  245 + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
  246 + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
  247 + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
  248 + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
  249 + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
  250 + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
  251 + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
  252 + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
  253 + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
  254 + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
  255 + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
  256 + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
  257 + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
  258 + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
  259 + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
  260 + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M4)) /*GPIO_168*/\
  261 + /* - USBH_CPEN*/\
  262 + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\
  263 + /* - USBH_RESET*/\
  264 + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
  265 + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
  266 + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
  267 + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
  268 + MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*HDQ_SIO*/\
  269 + MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\
  270 + MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO */\
  271 + MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI */\
  272 + MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\
  273 + MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\
  274 + MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\
  275 + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA2*/\
  276 + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA7*/\
  277 + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA4*/\
  278 + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA5*/\
  279 + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA6*/\
  280 + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA3*/\
  281 + /*Control and debug */\
  282 + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
  283 + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
  284 + MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
  285 + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
  286 + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
  287 + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\
  288 + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
  289 + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
  290 + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
  291 + MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
  292 + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
  293 + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
  294 + MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
  295 + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M2)) /*MMC3_CLK*/\
  296 + MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /*MMC3_CMD*/\
  297 + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT4*/\
  298 + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M4)) /*GPIO_15 - X_GATE*/\
  299 + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M4)) /*GPIO_16*/\
  300 + /* - W2W_NRESET*/\
  301 + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT3*/\
  302 + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT0*/\
  303 + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT1*/\
  304 + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT2*/\
  305 + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT7*/\
  306 + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT6*/\
  307 + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT5*/\
  308 + MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\
  309 + MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | EN | M3)) /*HSUSB2_STP*/\
  310 + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DIR*/\
  311 + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_NXT*/\
  312 + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA0*/\
  313 + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA1*/\
  314 + /* die to die */\
  315 + MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
  316 + MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
  317 + MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
  318 + MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
  319 + MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
  320 + MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
  321 + MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
  322 + MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
  323 + MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
  324 + MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
  325 + MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
  326 + MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
  327 + MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
  328 + MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
  329 + MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
  330 + MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
  331 + MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
  332 + MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
  333 + MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
  334 + MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
  335 + MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
  336 + MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
  337 + MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
  338 + MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
  339 + MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
  340 + MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
  341 + MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
  342 + MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
  343 + MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
  344 + MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
  345 + MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
  346 + MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
  347 + MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
  348 + MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
  349 + MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
  350 + MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
  351 + MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\
  352 + MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
  353 + MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\
  354 + MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\
  355 + MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
  356 + MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
  357 + MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
  358 + MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\
  359 + MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\
  360 + MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\
  361 + MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\
  362 + MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\
  363 + MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
  364 + MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
  365 + MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
  366 + MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
  367 + MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\
  368 + MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
  369 + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\
  370 + MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\
  371 + MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\
  372 + MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
  373 + MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
  374 + MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
  375 + MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
  376 + MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
  377 + MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\
  378 + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
  379 + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1*/
  380 +
  381 +#endif
board/omap3/overo/u-boot.lds
Diff comments   View file @ 9d0fc81
  1 +/*
  2 + * January 2004 - Changed to support H4 device
  3 + * Copyright (c) 2004 Texas Instruments
  4 + *
  5 + * (C) Copyright 2002
  6 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
  7 + *
  8 + * See file CREDITS for list of people who contributed to this
  9 + * project.
  10 + *
  11 + * This program is free software; you can redistribute it and/or
  12 + * modify it under the terms of the GNU General Public License as
  13 + * published by the Free Software Foundation; either version 2 of
  14 + * the License, or (at your option) any later version.
  15 + *
  16 + * This program is distributed in the hope that it will be useful,
  17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19 + * GNU General Public License for more details.
  20 + *
  21 + * You should have received a copy of the GNU General Public License
  22 + * along with this program; if not, write to the Free Software
  23 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 + * MA 02111-1307 USA
  25 + */
  26 +
  27 +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
  28 +OUTPUT_ARCH(arm)
  29 +ENTRY(_start)
  30 +SECTIONS
  31 +{
  32 + . = 0x00000000;
  33 +
  34 + . = ALIGN(4);
  35 + .text :
  36 + {
  37 + cpu/arm_cortexa8/start.o (.text)
  38 + *(.text)
  39 + }
  40 +
  41 + . = ALIGN(4);
  42 + .rodata : { *(.rodata) }
  43 +
  44 + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) }
  45 + __exidx_start = .;
  46 + .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) }
  47 + __exidx_end = .;
  48 +
  49 + . = ALIGN(4);
  50 + .data : { *(.data) }
  51 +
  52 + . = ALIGN(4);
  53 + .got : { *(.got) }
  54 +
  55 + __u_boot_cmd_start = .;
  56 + .u_boot_cmd : { *(.u_boot_cmd) }
  57 + __u_boot_cmd_end = .;
  58 +
  59 + . = ALIGN(4);
  60 + __bss_start = .;
  61 + .bss : { *(.bss) }
  62 + _end = .;
  63 +}
... ... @@ -11,6 +11,8 @@
11 11  
12 12 * OMAP3530 BeagleBoard [2]
13 13  
  14 +* Gumstix Overo [3]
  15 +
14 16 Toolchain
15 17 =========
16 18  
... ... @@ -26,6 +28,11 @@
26 28 make omap3_beagle_config
27 29 make
28 30  
  31 +* Gumstix Overo:
  32 +
  33 +make omap3_overo_config
  34 +make
  35 +
29 36 Custom commands
30 37 ===============
31 38  
... ... @@ -52,7 +59,7 @@
52 59 Acknowledgements
53 60 ================
54 61  
55   -OMAP3 U-Boot is based on U-Boot tar ball [3] for BeagleBoard and EVM done by
  62 +OMAP3 U-Boot is based on U-Boot tar ball [4] for BeagleBoard and EVM done by
56 63 several TI employees.
57 64  
58 65 Links
... ... @@ -67,7 +74,11 @@
67 74  
68 75 http://beagleboard.org/
69 76  
70   -[3] TI OMAP3 U-Boot:
  77 +[3] Gumstix Overo:
  78 +
  79 +http://www.gumstix.net/Overo/
  80 +
  81 +[4] TI OMAP3 U-Boot:
71 82  
72 83 http://beagleboard.googlecode.com/files/u-boot_beagle_revb.tar.gz
include/configs/omap3_overo.h
Diff comments   View file @ 9d0fc81
  1 +/*
  2 + * Configuration settings for the Gumstix Overo board.
  3 + *
  4 + * This program is free software; you can redistribute it and/or
  5 + * modify it under the terms of the GNU General Public License as
  6 + * published by the Free Software Foundation; either version 2 of
  7 + * the License, or (at your option) any later version.
  8 + *
  9 + * This program is distributed in the hope that it will be useful,
  10 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12 + * GNU General Public License for more details.
  13 + *
  14 + * You should have received a copy of the GNU General Public License
  15 + * along with this program; if not, write to the Free Software
  16 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  17 + * MA 02111-1307 USA
  18 + */
  19 +
  20 +#ifndef __CONFIG_H
  21 +#define __CONFIG_H
  22 +#include <asm/sizes.h>
  23 +
  24 +/*
  25 + * High Level Configuration Options
  26 + */
  27 +#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
  28 +#define CONFIG_OMAP 1 /* in a TI OMAP core */
  29 +#define CONFIG_OMAP34XX 1 /* which is a 34XX */
  30 +#define CONFIG_OMAP3430 1 /* which is in a 3430 */
  31 +#define CONFIG_OMAP3_OVERO 1 /* working with overo */
  32 +
  33 +#include <asm/arch/cpu.h> /* get chip and board defs */
  34 +#include <asm/arch/omap3.h>
  35 +
  36 +/* Clock Defines */
  37 +#define V_OSCK 26000000 /* Clock output from T2 */
  38 +#define V_SCLK (V_OSCK >> 1)
  39 +
  40 +#undef CONFIG_USE_IRQ /* no support for IRQs */
  41 +#define CONFIG_MISC_INIT_R
  42 +
  43 +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
  44 +#define CONFIG_SETUP_MEMORY_TAGS 1
  45 +#define CONFIG_INITRD_TAG 1
  46 +#define CONFIG_REVISION_TAG 1
  47 +
  48 +/*
  49 + * Size of malloc() pool
  50 + */
  51 +#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */
  52 + /* Sector */
  53 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K)
  54 +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
  55 + /* initial data */
  56 +
  57 +/*
  58 + * Hardware drivers
  59 + */
  60 +
  61 +/*
  62 + * NS16550 Configuration
  63 + */
  64 +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
  65 +
  66 +#define CONFIG_SYS_NS16550
  67 +#define CONFIG_SYS_NS16550_SERIAL
  68 +#define CONFIG_SYS_NS16550_REG_SIZE (-4)
  69 +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
  70 +
  71 +/*
  72 + * select serial console configuration
  73 + */
  74 +#define CONFIG_CONS_INDEX 3
  75 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
  76 +#define CONFIG_SERIAL3 3
  77 +
  78 +/* allow to overwrite serial and ethaddr */
  79 +#define CONFIG_ENV_OVERWRITE
  80 +#define CONFIG_BAUDRATE 115200
  81 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
  82 + 115200}
  83 +#define CONFIG_MMC 1
  84 +#define CONFIG_OMAP3_MMC 1
  85 +#define CONFIG_DOS_PARTITION 1
  86 +
  87 +/* commands to include */
  88 +#include <config_cmd_default.h>
  89 +
  90 +#define CONFIG_CMD_EXT2 /* EXT2 Support */
  91 +#define CONFIG_CMD_FAT /* FAT support */
  92 +#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
  93 +
  94 +#define CONFIG_CMD_I2C /* I2C serial bus support */
  95 +#define CONFIG_CMD_MMC /* MMC support */
  96 +#define CONFIG_CMD_NAND /* NAND support */
  97 +
  98 +#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
  99 +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
  100 +#undef CONFIG_CMD_IMI /* iminfo */
  101 +#undef CONFIG_CMD_IMLS /* List all found images */
  102 +#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
  103 +#undef CONFIG_CMD_NFS /* NFS support */
  104 +
  105 +#define CONFIG_SYS_NO_FLASH
  106 +#define CONFIG_SYS_I2C_SPEED 100000
  107 +#define CONFIG_SYS_I2C_SLAVE 1
  108 +#define CONFIG_SYS_I2C_BUS 0
  109 +#define CONFIG_SYS_I2C_BUS_SELECT 1
  110 +#define CONFIG_DRIVER_OMAP34XX_I2C 1
  111 +
  112 +/*
  113 + * Board NAND Info.
  114 + */
  115 +#define CONFIG_NAND_OMAP_GPMC
  116 +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
  117 + /* to access nand */
  118 +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
  119 + /* to access nand */
  120 + /* at CS0 */
  121 +#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
  122 +
  123 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
  124 + /* devices */
  125 +#define SECTORSIZE 512
  126 +
  127 +#define NAND_ALLOW_ERASE_ALL
  128 +#define ADDR_COLUMN 1
  129 +#define ADDR_PAGE 2
  130 +#define ADDR_COLUMN_PAGE 3
  131 +
  132 +#define NAND_ChipID_UNKNOWN 0x00
  133 +#define NAND_MAX_FLOORS 1
  134 +#define NAND_MAX_CHIPS 1
  135 +#define NAND_NO_RB 1
  136 +#define CONFIG_SYS_NAND_WP
  137 +
  138 +#define CONFIG_JFFS2_NAND
  139 +/* nand device jffs2 lives on */
  140 +#define CONFIG_JFFS2_DEV "nand0"
  141 +/* start of jffs2 partition */
  142 +#define CONFIG_JFFS2_PART_OFFSET 0x680000
  143 +#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
  144 + /* partition */
  145 +
  146 +/* Environment information */
  147 +#define CONFIG_BOOTDELAY 5
  148 +
  149 +#define CONFIG_EXTRA_ENV_SETTINGS \
  150 + "loadaddr=0x82000000\0" \
  151 + "console=ttyS2,115200n8\0" \
  152 + "videomode=1024x768@60,vxres=1024,vyres=768\0" \
  153 + "videospec=omapfb:vram:2M,vram:4M\0" \
  154 + "mmcargs=setenv bootargs console=${console} " \
  155 + "video=${videospec},mode:${videomode} " \
  156 + "root=/dev/mmcblk0p2 rw " \
  157 + "rootfstype=ext3 rootwait\0" \
  158 + "nandargs=setenv bootargs console=${console} " \
  159 + "video=${videospec},mode:${videomode} " \
  160 + "root=/dev/mtdblock4 rw " \
  161 + "rootfstype=jffs2\0" \
  162 + "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
  163 + "bootscript=echo Running bootscript from mmc ...; " \
  164 + "autoscr ${loadaddr}\0" \
  165 + "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
  166 + "mmcboot=echo Booting from mmc ...; " \
  167 + "run mmcargs; " \
  168 + "bootm ${loadaddr}\0" \
  169 + "nandboot=echo Booting from nand ...; " \
  170 + "run nandargs; " \
  171 + "nand read ${loadaddr} 280000 400000; " \
  172 + "bootm ${loadaddr}\0" \
  173 +
  174 +#define CONFIG_BOOTCOMMAND \
  175 + "if mmcinit; then " \
  176 + "if run loadbootscript; then " \
  177 + "run bootscript; " \
  178 + "else " \
  179 + "if run loaduimage; then " \
  180 + "run mmcboot; " \
  181 + "else run nandboot; " \
  182 + "fi; " \
  183 + "fi; " \
  184 + "else run nandboot; fi"
  185 +
  186 +#define CONFIG_AUTO_COMPLETE 1
  187 +/*
  188 + * Miscellaneous configurable options
  189 + */
  190 +#define V_PROMPT "Overo # "
  191 +
  192 +#define CONFIG_SYS_LONGHELP /* undef to save memory */
  193 +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
  194 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  195 +#define CONFIG_SYS_PROMPT V_PROMPT
  196 +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  197 +/* Print Buffer Size */
  198 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  199 + sizeof(CONFIG_SYS_PROMPT) + 16)
  200 +#define CONFIG_SYS_MAXARGS 16 /* max number of command */
  201 + /* args */
  202 +/* Boot Argument Buffer Size */
  203 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  204 +/* memtest works on */
  205 +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
  206 +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
  207 + 0x01F00000) /* 31MB */
  208 +
  209 +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, */
  210 + /* in Hz */
  211 +
  212 +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
  213 + /* address */
  214 +
  215 +/*
  216 + * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
  217 + * 32KHz clk, or from external sig. This rate is divided by a local divisor.
  218 + */
  219 +#define V_PVT 7
  220 +
  221 +#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
  222 +#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */
  223 +#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT))
  224 +
  225 +/*-----------------------------------------------------------------------
  226 + * Stack sizes
  227 + *
  228 + * The stack sizes are set up in start.S using the settings below
  229 + */
  230 +#define CONFIG_STACKSIZE SZ_128K /* regular stack */
  231 +#ifdef CONFIG_USE_IRQ
  232 +#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */
  233 +#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */
  234 +#endif
  235 +
  236 +/*-----------------------------------------------------------------------
  237 + * Physical Memory Map
  238 + */
  239 +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
  240 +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
  241 +#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */
  242 +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
  243 +
  244 +/* SDRAM Bank Allocation method */
  245 +#define SDRC_R_B_C 1
  246 +
  247 +/*-----------------------------------------------------------------------
  248 + * FLASH and environment organization
  249 + */
  250 +
  251 +/* **** PISMO SUPPORT *** */
  252 +
  253 +/* Configure the PISMO */
  254 +#define PISMO1_NAND_SIZE GPMC_SIZE_128M
  255 +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
  256 +
  257 +#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */
  258 + /* one chip */
  259 +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
  260 +#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */
  261 +
  262 +#define CONFIG_SYS_FLASH_BASE boot_flash_base
  263 +
  264 +/* Monitor at start of flash */
  265 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  266 +#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
  267 +
  268 +#define CONFIG_ENV_IS_IN_NAND 1
  269 +#define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */
  270 +#define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */
  271 +
  272 +#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
  273 +#define CONFIG_ENV_OFFSET boot_flash_off
  274 +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
  275 +
  276 +/*-----------------------------------------------------------------------
  277 + * CFI FLASH driver setup
  278 + */
  279 +/* timeout values are in ticks */
  280 +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
  281 +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
  282 +
  283 +/* Flash banks JFFS2 should use */
  284 +#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
  285 + CONFIG_SYS_MAX_NAND_DEVICE)
  286 +#define CONFIG_SYS_JFFS2_MEM_NAND
  287 +/* use flash_info[2] */
  288 +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
  289 +#define CONFIG_SYS_JFFS2_NUM_BANKS 1
  290 +
  291 +#ifndef __ASSEMBLY__
  292 +extern gpmc_csx_t *nand_cs_base;
  293 +extern gpmc_t *gpmc_cfg_base;
  294 +extern unsigned int boot_flash_base;
  295 +extern volatile unsigned int boot_flash_env_addr;
  296 +extern unsigned int boot_flash_off;
  297 +extern unsigned int boot_flash_sec;
  298 +extern unsigned int boot_flash_type;
  299 +#endif
  300 +
  301 +
  302 +#define WRITE_NAND_COMMAND(d, adr)\
  303 + writel(d, &nand_cs_base->nand_cmd)
  304 +#define WRITE_NAND_ADDRESS(d, adr)\
  305 + writel(d, &nand_cs_base->nand_adr)
  306 +#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
  307 +#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
  308 +
  309 +/* Other NAND Access APIs */
  310 +#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
  311 + while (0)
  312 +#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
  313 + while (0)
  314 +#define NAND_DISABLE_CE(nand)
  315 +#define NAND_ENABLE_CE(nand)
  316 +#define NAND_WAIT_READY(nand) udelay(10)
  317 +
  318 +#endif /* __CONFIG_H */