Eric Lee / smarc-uboot

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Commit d9303e79126526507441f59d8eafc90f70e56e85

Authored by Ye Li
1 parent 338223a98b
Exists in emb_lf_v2022.04

MLK-24958-3 video: mxsfb: Add iMX8DXL support to LCDIF driver 

Support iMX8DXL in mxsfb driver by below changes:
1. Enable iMX8 in lcdif registers file
2. Add u-boot clock driver support for iMX8
3. Change the FB buffer alignment to align it at allocation. So
   it won't overlay with other memory at mmu_set_region_dcache_behaviour

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 6f02d6894509e0aa79df9d1bdf5029136e1493b5)
(cherry picked from commit 9df950e79963c328b1b04d6eb42f43f41217e752)
(cherry picked from commit 082b8d3c6e17691edf902781d4bb5d978bcecaa5)
(cherry picked from commit 3367dd0c8e9a8a6b868a40e3b4b16523a078289e)

Showing 3 changed files with 66 additions and 9 deletions Side-by-side Diff

arch/arm/include/asm/arch-imx8/imx-regs.h
Diff comments   View file @ d9303e7
... ... @@ -6,6 +6,8 @@
6 6 #ifndef __ASM_ARCH_IMX8_REGS_H__
7 7 #define __ASM_ARCH_IMX8_REGS_H__
8 8  
  9 +#include <asm/mach-imx/regs-lcdif.h>
  10 +
9 11 #define ARCH_MXC
10 12  
11 13 #define LPUART_BASE 0x5A060000
arch/arm/include/asm/mach-imx/regs-lcdif.h
Diff comments   View file @ d9303e7
... ... @@ -22,7 +22,7 @@
22 22 defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
23 23 defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
24 24 defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
25   - defined(CONFIG_IMX8M) || defined(CONFIG_IMXRT)
  25 + defined(CONFIG_IMX8M) || defined(CONFIG_IMX8) || defined(CONFIG_IMXRT)
26 26 mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */
27 27 #endif
28 28 mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */
... ... @@ -61,7 +61,7 @@
61 61 defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
62 62 defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
63 63 defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
64   - defined(CONFIG_IMX8M) || defined(CONFIG_IMXRT)
  64 + defined(CONFIG_IMX8M) || defined(CONFIG_IMX8) || defined(CONFIG_IMXRT)
65 65 mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */
66 66 #endif
67 67 mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */
... ... @@ -73,7 +73,7 @@
73 73 defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
74 74 defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
75 75 defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
76   - defined(CONFIG_IMX8M)
  76 + defined(CONFIG_IMX8M) || defined(CONFIG_IMX8)
77 77 mxs_reg_32(hw_lcdif_thres)
78 78 mxs_reg_32(hw_lcdif_as_ctrl)
79 79 mxs_reg_32(hw_lcdif_as_buf)
drivers/video/mxsfb.c
Diff comments   View file @ d9303e7
... ... @@ -18,8 +18,11 @@
18 18 #include <malloc.h>
19 19 #include <video.h>
20 20 #include <video_fb.h>
21   -
  21 +#if CONFIG_IS_ENABLED(CLK) && IS_ENABLED(CONFIG_IMX8)
  22 +#include <clk.h>
  23 +#else
22 24 #include <asm/arch/clock.h>
  25 +#endif
23 26 #include <asm/arch/imx-regs.h>
24 27 #include <asm/arch/sys_proto.h>
25 28 #include <asm/global_data.h>
... ... @@ -81,8 +84,7 @@
81 84 uint8_t valid_data = 0;
82 85 uint32_t vdctrl0;
83 86  
84   -
85   -#if !CONFIG_IS_ENABLED(CLK)
  87 +#if !(CONFIG_IS_ENABLED(CLK) && IS_ENABLED(CONFIG_IMX8))
86 88 /* Kick in the LCDIF clock */
87 89 mxs_set_lcdclk((u32)reg_base, timings->pixelclock.typ / 1000);
88 90 #endif
... ... @@ -386,6 +388,12 @@
386 388 struct reset_ctl_bulk soft_resetn;
387 389 struct reset_ctl_bulk clk_enable;
388 390 #endif
  391 +
  392 +#if CONFIG_IS_ENABLED(CLK) && IS_ENABLED(CONFIG_IMX8)
  393 + struct clk lcdif_pix;
  394 + struct clk lcdif_disp_axi;
  395 + struct clk lcdif_axi;
  396 +#endif
389 397 };
390 398  
391 399 #if IS_ENABLED(CONFIG_DM_RESET)
... ... @@ -520,6 +528,38 @@
520 528 return ret;
521 529 timings.flags |= DISPLAY_FLAGS_DE_HIGH;
522 530  
  531 +#if CONFIG_IS_ENABLED(CLK) && IS_ENABLED(CONFIG_IMX8)
  532 + ret = clk_get_by_name(dev, "pix", &priv->lcdif_pix);
  533 + if (ret) {
  534 + printf("Failed to get pix clk\n");
  535 + return ret;
  536 + }
  537 +
  538 + ret = clk_get_by_name(dev, "disp_axi", &priv->lcdif_disp_axi);
  539 + if (ret) {
  540 + printf("Failed to get disp_axi clk\n");
  541 + return ret;
  542 + }
  543 +
  544 + ret = clk_get_by_name(dev, "axi", &priv->lcdif_axi);
  545 + if (ret) {
  546 + printf("Failed to get axi clk\n");
  547 + return ret;
  548 + }
  549 +
  550 + ret = clk_enable(&priv->lcdif_axi);
  551 + if (ret) {
  552 + printf("unable to enable lcdif_axi clock\n");
  553 + return ret;
  554 + }
  555 +
  556 + ret = clk_enable(&priv->lcdif_disp_axi);
  557 + if (ret) {
  558 + printf("unable to enable lcdif_disp_axi clock\n");
  559 + return ret;
  560 + }
  561 +#endif
  562 +
523 563 #if IS_ENABLED(CONFIG_DM_RESET)
524 564 ret = lcdif_of_parse_resets(dev);
525 565 if (!ret) {
... ... @@ -571,6 +611,20 @@
571 611 }
572 612 }
573 613  
  614 +#if CONFIG_IS_ENABLED(CLK) && IS_ENABLED(CONFIG_IMX8)
  615 + ret = clk_set_rate(&priv->lcdif_pix, timings.pixelclock.typ);
  616 + if (ret < 0) {
  617 + printf("Failed to set pix clk rate\n");
  618 + return ret;
  619 + }
  620 +
  621 + ret = clk_enable(&priv->lcdif_pix);
  622 + if (ret) {
  623 + printf("unable to enable lcdif_pix clock\n");
  624 + return ret;
  625 + }
  626 +#endif
  627 +
574 628 ret = mxs_probe_common(priv->reg_base, &timings, bpp, plat->base, enable_bridge);
575 629 if (ret)
576 630 return ret;
577 631  
... ... @@ -596,9 +650,9 @@
596 650 uc_priv->ysize = timings.vactive.typ;
597 651  
598 652 /* Enable dcache for the frame buffer */
599   - fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
  653 + fb_start = plat->base;
600 654 fb_end = plat->base + plat->size;
601   - fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
  655 +
602 656 mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
603 657 DCACHE_WRITEBACK);
604 658 video_set_flush_dcache(dev, true);
... ... @@ -612,7 +666,8 @@
612 666 struct video_uc_plat *plat = dev_get_uclass_plat(dev);
613 667  
614 668 /* Max size supported by LCDIF, because in bind, we can't probe panel */
615   - plat->size = 1920 * 1080 *4 * 2;
  669 + plat->size = ALIGN(1920 * 1080 *4 * 2, MMU_SECTION_SIZE);
  670 + plat->align = MMU_SECTION_SIZE;
616 671  
617 672 return 0;
618 673 }