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Commit 9ebde8849a37beff5eccb462a991e05b07f8a360

Authored by Biwen Li
Committed by Priyanka Jain
1 parent a0affb367a
Exists in smarc_8mq_lf_v2020.04 and in 9 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

dm: arm: ls1021a: add i2c DM support 

This supports i2c DM and enables CONFIG_DM_I2C
for SoC LS1021A

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>

Showing 29 changed files with 330 additions and 8 deletions Side-by-side Diff

board/freescale/common/dcu_sii9022a.c
Diff comments   View file @ 9ebde88
1 1 // SPDX-License-Identifier: GPL-2.0+
2 2 /*
3 3 * Copyright 2014 Freescale Semiconductor, Inc.
  4 + * Copyright 2019 NXP
4 5 */
5 6  
6 7 #include <asm/io.h>
7 8  
... ... @@ -63,7 +64,101 @@
63 64 u8 temp;
64 65 u16 temp1, temp2;
65 66 u32 temp3;
  67 +#ifdef CONFIG_DM_I2C
  68 + struct udevice *dev;
  69 + int ret;
66 70  
  71 + ret = i2c_get_chip_for_busnum(CONFIG_SYS_I2C_DVI_BUS_NUM,
  72 + CONFIG_SYS_I2C_DVI_ADDR,
  73 + 1, &dev);
  74 + if (ret) {
  75 + printf("%s: Cannot find udev for a bus %d\n", __func__,
  76 + CONFIG_SYS_I2C_DVI_BUS_NUM);
  77 + return ret;
  78 + }
  79 +
  80 + /* Enable TPI transmitter mode */
  81 + temp = TPI_TRANS_MODE_ENABLE;
  82 + dm_i2c_write(dev, TPI_TRANS_MODE_REG, &temp, 1);
  83 +
  84 + /* Enter into D0 state, full operation */
  85 + dm_i2c_read(dev, TPI_PWR_STAT_REG, &temp, 1);
  86 + temp &= ~TPI_PWR_STAT_MASK;
  87 + temp |= TPI_PWR_STAT_D0;
  88 + dm_i2c_write(dev, TPI_PWR_STAT_REG, &temp, 1);
  89 +
  90 + /* Enable source termination */
  91 + temp = TPI_SET_PAGE_SII9022A;
  92 + dm_i2c_write(dev, TPI_SET_PAGE_REG, &temp, 1);
  93 + temp = TPI_SET_OFFSET_SII9022A;
  94 + dm_i2c_write(dev, TPI_SET_OFFSET_REG, &temp, 1);
  95 +
  96 + dm_i2c_read(dev, TPI_RW_ACCESS_REG, &temp, 1);
  97 + temp |= TPI_RW_EN_SRC_TERMIN;
  98 + dm_i2c_write(dev, TPI_RW_ACCESS_REG, &temp, 1);
  99 +
  100 + /* Set TPI system control */
  101 + temp = TPI_SYS_TMDS_OUTPUT | TPI_SYS_AV_NORAML | TPI_SYS_DVI_MODE;
  102 + dm_i2c_write(dev, TPI_SYS_CTRL_REG, &temp, 1);
  103 +
  104 + /* Set pixel clock */
  105 + temp1 = PICOS2KHZ(videomode->pixclock) / 10;
  106 + temp = (u8)(temp1 & 0xFF);
  107 + dm_i2c_write(dev, PIXEL_CLK_LSB_REG, &temp, 1);
  108 + temp = (u8)(temp1 >> 8);
  109 + dm_i2c_write(dev, PIXEL_CLK_MSB_REG, &temp, 1);
  110 +
  111 + /* Set total pixels per line */
  112 + temp1 = videomode->hsync_len + videomode->left_margin +
  113 + videomode->xres + videomode->right_margin;
  114 + temp = (u8)(temp1 & 0xFF);
  115 + dm_i2c_write(dev, TOTAL_PIXELS_LSB_REG, &temp, 1);
  116 + temp = (u8)(temp1 >> 8);
  117 + dm_i2c_write(dev, TOTAL_PIXELS_MSB_REG, &temp, 1);
  118 +
  119 + /* Set total lines */
  120 + temp2 = videomode->vsync_len + videomode->upper_margin +
  121 + videomode->yres + videomode->lower_margin;
  122 + temp = (u8)(temp2 & 0xFF);
  123 + dm_i2c_write(dev, TOTAL_LINES_LSB_REG, &temp, 1);
  124 + temp = (u8)(temp2 >> 8);
  125 + dm_i2c_write(dev, TOTAL_LINES_MSB_REG, &temp, 1);
  126 +
  127 + /* Set vertical frequency in Hz */
  128 + temp3 = temp1 * temp2;
  129 + temp3 = (PICOS2KHZ(videomode->pixclock) * 1000) / temp3;
  130 + temp1 = (u16)temp3 * 100;
  131 + temp = (u8)(temp1 & 0xFF);
  132 + dm_i2c_write(dev, VERT_FREQ_LSB_REG, &temp, 1);
  133 + temp = (u8)(temp1 >> 8);
  134 + dm_i2c_write(dev, VERT_FREQ_MSB_REG, &temp, 1);
  135 +
  136 + /* Set TPI input bus and pixel repetition data */
  137 + temp = TPI_INBUS_CLOCK_RATIO_1 | TPI_INBUS_FULL_PIXEL_WIDE |
  138 + TPI_INBUS_RISING_EDGE;
  139 + dm_i2c_write(dev, TPI_INBUS_FMT_REG, &temp, 1);
  140 +
  141 + /* Set TPI AVI Input format data */
  142 + temp = TPI_INPUT_CLR_DEPTH_8BIT | TPI_INPUT_VRANGE_EXPAN_AUTO |
  143 + TPI_INPUT_CLR_RGB;
  144 + dm_i2c_write(dev, TPI_INPUT_FMT_REG, &temp, 1);
  145 +
  146 + /* Set TPI AVI Output format data */
  147 + temp = TPI_OUTPUT_CLR_DEPTH_8BIT | TPI_OUTPUT_VRANGE_COMPRE_AUTO |
  148 + TPI_OUTPUT_CLR_HDMI_RGB;
  149 + dm_i2c_write(dev, TPI_OUTPUT_FMT_REG, &temp, 1);
  150 +
  151 + /* Set TPI audio configuration write data */
  152 + temp = TPI_AUDIO_PASS_BASIC;
  153 + dm_i2c_write(dev, TPI_AUDIO_HANDING_REG, &temp, 1);
  154 +
  155 + temp = TPI_AUDIO_INTF_I2S | TPI_AUDIO_INTF_NORMAL |
  156 + TPI_AUDIO_TYPE_PCM;
  157 + dm_i2c_write(dev, TPI_AUDIO_INTF_REG, &temp, 1);
  158 +
  159 + temp = TPI_AUDIO_SAMP_SIZE_16BIT | TPI_AUDIO_SAMP_FREQ_44K;
  160 + dm_i2c_write(dev, TPI_AUDIO_FREQ_REG, &temp, 1);
  161 +#else
67 162 i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM);
68 163  
69 164 /* Enable TPI transmitter mode */
... ... @@ -147,6 +242,7 @@
147 242  
148 243 temp = TPI_AUDIO_SAMP_SIZE_16BIT | TPI_AUDIO_SAMP_FREQ_44K;
149 244 i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_AUDIO_FREQ_REG, 1, &temp, 1);
  245 +#endif
150 246  
151 247 return 0;
152 248 }
board/freescale/common/diu_ch7301.c
Diff comments   View file @ 9ebde88
1 1 // SPDX-License-Identifier: GPL-2.0+
2 2 /*
3 3 * Copyright 2014 Freescale Semiconductor, Inc.
  4 + * Copyright 2019 NXP
4 5 * Authors: Priyanka Jain <Priyanka.Jain@freescale.com>
5 6 * Wang Dongsheng <dongsheng.wang@freescale.com>
6 7 *
... ... @@ -51,6 +52,85 @@
51 52 u8 temp;
52 53  
53 54 temp = I2C_DVI_TEST_PATTERN_VAL;
  55 +#ifdef CONFIG_DM_I2C
  56 + struct udevice *dev;
  57 +
  58 + ret = i2c_get_chip_for_busnum(CONFIG_SYS_I2C_DVI_BUS_NUM,
  59 + CONFIG_SYS_I2C_DVI_ADDR,
  60 + 1, &dev);
  61 + if (ret) {
  62 + printf("%s: Cannot find udev for a bus %d\n", __func__,
  63 + CONFIG_SYS_I2C_DVI_BUS_NUM);
  64 + return ret;
  65 + }
  66 + ret = dm_i2c_write(dev, I2C_DVI_TEST_PATTERN_REG, &temp, 1);
  67 + if (ret) {
  68 + puts("I2C: failed to select proper dvi test pattern\n");
  69 + return ret;
  70 + }
  71 + temp = I2C_DVI_INPUT_DATA_FORMAT_VAL;
  72 + ret = dm_i2c_write(dev, I2C_DVI_INPUT_DATA_FORMAT_REG, &temp, 1);
  73 + if (ret) {
  74 + puts("I2C: failed to select dvi input data format\n");
  75 + return ret;
  76 + }
  77 +
  78 + /* Set Sync polarity register */
  79 + temp = I2C_DVI_SYNC_POLARITY_VAL;
  80 + ret = dm_i2c_write(dev, I2C_DVI_SYNC_POLARITY_REG, &temp, 1);
  81 + if (ret) {
  82 + puts("I2C: failed to select dvi syc polarity\n");
  83 + return ret;
  84 + }
  85 +
  86 + /* Set PLL registers based on pixel clock rate*/
  87 + if (pixclock > 65000000) {
  88 + temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL;
  89 + ret = dm_i2c_write(dev, I2C_DVI_PLL_CHARGE_CNTL_REG, &temp, 1);
  90 + if (ret) {
  91 + puts("I2C: failed to select dvi pll charge_cntl\n");
  92 + return ret;
  93 + }
  94 + temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL;
  95 + ret = dm_i2c_write(dev, I2C_DVI_PLL_DIVIDER_REG, &temp, 1);
  96 + if (ret) {
  97 + puts("I2C: failed to select dvi pll divider\n");
  98 + return ret;
  99 + }
  100 + temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL;
  101 + ret = dm_i2c_write(dev, I2C_DVI_PLL_FILTER_REG, &temp, 1);
  102 + if (ret) {
  103 + puts("I2C: failed to select dvi pll filter\n");
  104 + return ret;
  105 + }
  106 + } else {
  107 + temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL;
  108 + ret = dm_i2c_write(dev, I2C_DVI_PLL_CHARGE_CNTL_REG, &temp, 1);
  109 + if (ret) {
  110 + puts("I2C: failed to select dvi pll charge_cntl\n");
  111 + return ret;
  112 + }
  113 + temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL;
  114 + ret = dm_i2c_write(dev, I2C_DVI_PLL_DIVIDER_REG, &temp, 1);
  115 + if (ret) {
  116 + puts("I2C: failed to select dvi pll divider\n");
  117 + return ret;
  118 + }
  119 + temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL;
  120 + ret = dm_i2c_write(dev, I2C_DVI_PLL_FILTER_REG, &temp, 1);
  121 + if (ret) {
  122 + puts("I2C: failed to select dvi pll filter\n");
  123 + return ret;
  124 + }
  125 + }
  126 +
  127 + temp = I2C_DVI_POWER_MGMT_VAL;
  128 + ret = dm_i2c_write(dev, I2C_DVI_POWER_MGMT_REG, &temp, 1);
  129 + if (ret) {
  130 + puts("I2C: failed to select dvi power mgmt\n");
  131 + return ret;
  132 + }
  133 +#else
54 134 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1,
55 135 &temp, 1);
56 136 if (ret) {
... ... @@ -128,6 +208,7 @@
128 208 puts("I2C: failed to select dvi power mgmt\n");
129 209 return ret;
130 210 }
  211 +#endif
131 212  
132 213 udelay(500);
133 214  
board/freescale/ls1021aqds/dcu.c
Diff comments   View file @ 9ebde88
1 1 // SPDX-License-Identifier: GPL-2.0+
2 2 /*
3 3 * Copyright 2014 Freescale Semiconductor, Inc.
  4 + * Copyright 2019 NXP
4 5 *
5 6 * FSL DCU Framebuffer driver
6 7 */
7 8  
8 9  
9 10  
... ... @@ -15,11 +16,23 @@
15 16  
16 17 DECLARE_GLOBAL_DATA_PTR;
17 18  
18   -static int select_i2c_ch_pca9547(u8 ch)
  19 +static int select_i2c_ch_pca9547(u8 ch, int bus_num)
19 20 {
20 21 int ret;
  22 +#ifdef CONFIG_DM_I2C
  23 + struct udevice *dev;
21 24  
  25 + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
  26 + 1, &dev);
  27 + if (ret) {
  28 + printf("%s: Cannot find udev for a bus %d\n", __func__,
  29 + bus_num);
  30 + return ret;
  31 + }
  32 + ret = dm_i2c_write(dev, 0, &ch, 1);
  33 +#else
22 34 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  35 +#endif
23 36 if (ret) {
24 37 puts("PCA: failed to select proper channel\n");
25 38 return ret;
... ... @@ -51,6 +64,28 @@
51 64 u8 ch;
52 65  
53 66 /* Mux I2C3+I2C4 as HSYNC+VSYNC */
  67 +#ifdef CONFIG_DM_I2C
  68 + struct udevice *dev;
  69 +
  70 + /* QIXIS device mount on I2C1 bus*/
  71 + ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_QIXIS_ADDR,
  72 + 1, &dev);
  73 + if (ret) {
  74 + printf("%s: Cannot find udev for a bus %d\n", __func__,
  75 + 0);
  76 + return ret;
  77 + }
  78 + ret = dm_i2c_read(dev, QIXIS_DCU_BRDCFG5, &ch, 1);
  79 + if (ret) {
  80 + printf("Error: failed to read I2C @%02x\n",
  81 + CONFIG_SYS_I2C_QIXIS_ADDR);
  82 + return ret;
  83 + }
  84 + ch &= 0x1F;
  85 + ch |= 0xA0;
  86 + ret = dm_i2c_write(dev, QIXIS_DCU_BRDCFG5, &ch, 1);
  87 +
  88 +#else
54 89 ret = i2c_read(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5,
55 90 1, &ch, 1);
56 91 if (ret) {
... ... @@ -62,6 +97,7 @@
62 97 ch |= 0xA0;
63 98 ret = i2c_write(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5,
64 99 1, &ch, 1);
  100 +#endif
65 101 if (ret) {
66 102 printf("Error: failed to write I2C @%02x\n",
67 103 CONFIG_SYS_I2C_QIXIS_ADDR);
68 104  
69 105  
... ... @@ -76,10 +112,14 @@
76 112 pixval = 1000000000 / dcu_fb_videomode->pixclock;
77 113 pixval *= 1000;
78 114  
  115 +#ifndef CONFIG_DM_I2C
79 116 i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM);
80   - select_i2c_ch_pca9547(I2C_MUX_CH_CH7301);
  117 +#endif
  118 + select_i2c_ch_pca9547(I2C_MUX_CH_CH7301,
  119 + CONFIG_SYS_I2C_DVI_BUS_NUM);
81 120 diu_set_dvi_encoder(pixval);
82   - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  121 + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT,
  122 + CONFIG_SYS_I2C_DVI_BUS_NUM);
83 123 } else {
84 124 return 0;
85 125 }
board/freescale/ls1021aqds/ls1021aqds.c
Diff comments   View file @ 9ebde88
1 1 // SPDX-License-Identifier: GPL-2.0+
2 2 /*
3 3 * Copyright 2014 Freescale Semiconductor, Inc.
  4 + * Copyright 2019 NXP
4 5 */
5 6  
6 7 #include <common.h>
7 8  
8 9  
9 10  
... ... @@ -139,11 +140,23 @@
139 140 return 66666666;
140 141 }
141 142  
142   -int select_i2c_ch_pca9547(u8 ch)
  143 +int select_i2c_ch_pca9547(u8 ch, int bus_num)
143 144 {
144 145 int ret;
  146 +#ifdef CONFIG_DM_I2C
  147 + struct udevice *dev;
145 148  
  149 + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
  150 + 1, &dev);
  151 + if (ret) {
  152 + printf("%s: Cannot find udev for a bus %d\n", __func__,
  153 + bus_num);
  154 + return ret;
  155 + }
  156 + ret = dm_i2c_write(dev, 0, &ch, 1);
  157 +#else
146 158 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  159 +#endif
147 160 if (ret) {
148 161 puts("PCA: failed to select proper channel\n");
149 162 return ret;
150 163  
... ... @@ -158,8 +171,10 @@
158 171 * When resuming from deep sleep, the I2C channel may not be
159 172 * in the default channel. So, switch to the default channel
160 173 * before accessing DDR SPD.
  174 + *
  175 + * PCA9547(0x77) mount on I2C1 bus
161 176 */
162   - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  177 + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
163 178 return fsl_initdram();
164 179 }
165 180  
... ... @@ -408,7 +423,7 @@
408 423 erratum_a009942_check_cpo();
409 424 #endif
410 425  
411   - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  426 + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
412 427  
413 428 #ifndef CONFIG_SYS_FSL_NO_SERDES
414 429 fsl_serdes_init();
board/freescale/ls1021atwr/ls1021atwr.c
Diff comments   View file @ 9ebde88
1 1 // SPDX-License-Identifier: GPL-2.0+
2 2 /*
3 3 * Copyright 2014 Freescale Semiconductor, Inc.
  4 + * Copyright 2019 NXP
4 5 */
5 6  
6 7 #include <common.h>
7 8  
8 9  
... ... @@ -447,14 +448,37 @@
447 448 /* program the regulator (MC34VR500) to support deep sleep */
448 449 void ls1twr_program_regulator(void)
449 450 {
450   - unsigned int i2c_bus;
451 451 u8 i2c_device_id;
452 452  
453 453 #define LS1TWR_I2C_BUS_MC34VR500 1
454 454 #define MC34VR500_ADDR 0x8
455 455 #define MC34VR500_DEVICEID 0x4
456 456 #define MC34VR500_DEVICEID_MASK 0x0f
  457 +#ifdef CONFIG_DM_I2C
  458 + struct udevice *dev;
  459 + int ret;
457 460  
  461 + ret = i2c_get_chip_for_busnum(LS1TWR_I2C_BUS_MC34VR500, MC34VR500_ADDR,
  462 + 1, &dev);
  463 + if (ret) {
  464 + printf("%s: Cannot find udev for a bus %d\n", __func__,
  465 + LS1TWR_I2C_BUS_MC34VR500);
  466 + return;
  467 + }
  468 + i2c_device_id = dm_i2c_reg_read(dev, 0x0) &
  469 + MC34VR500_DEVICEID_MASK;
  470 + if (i2c_device_id != MC34VR500_DEVICEID) {
  471 + printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
  472 + return;
  473 + }
  474 +
  475 + dm_i2c_reg_write(dev, 0x31, 0x4);
  476 + dm_i2c_reg_write(dev, 0x4d, 0x4);
  477 + dm_i2c_reg_write(dev, 0x6d, 0x38);
  478 + dm_i2c_reg_write(dev, 0x6f, 0x37);
  479 + dm_i2c_reg_write(dev, 0x71, 0x30);
  480 +#else
  481 + unsigned int i2c_bus;
458 482 i2c_bus = i2c_get_bus_num();
459 483 i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500);
460 484 i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) &
... ... @@ -471,6 +495,7 @@
471 495 i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30);
472 496  
473 497 i2c_set_bus_num(i2c_bus);
  498 +#endif
474 499 }
475 500 #endif
476 501  
configs/ls1021aiot_qspi_defconfig
Diff comments   View file @ 9ebde88
... ... @@ -45,4 +45,6 @@
45 45 CONFIG_USB=y
46 46 CONFIG_USB_XHCI_HCD=y
47 47 CONFIG_USB_XHCI_DWC3=y
  48 +CONFIG_DM_I2C=y
  49 +CONFIG_DM_GPIO=y
configs/ls1021aiot_sdcard_defconfig
Diff comments   View file @ 9ebde88
... ... @@ -51,4 +51,6 @@
51 51 CONFIG_USB=y
52 52 CONFIG_USB_XHCI_HCD=y
53 53 CONFIG_USB_XHCI_DWC3=y
  54 +CONFIG_DM_I2C=y
  55 +CONFIG_DM_GPIO=y
configs/ls1021aqds_ddr4_nor_defconfig
Diff comments   View file @ 9ebde88
... ... @@ -67,4 +67,6 @@
67 67 CONFIG_VIDEO_FSL_DCU_FB=y
68 68 CONFIG_VIDEO=y
69 69 # CONFIG_VIDEO_SW_CURSOR is not set
  70 +CONFIG_DM_I2C=y
  71 +CONFIG_DM_GPIO=y
configs/ls1021aqds_ddr4_nor_lpuart_defconfig
Diff comments   View file @ 9ebde88
... ... @@ -67,4 +67,6 @@
67 67 CONFIG_VIDEO_FSL_DCU_FB=y
68 68 CONFIG_VIDEO=y
69 69 # CONFIG_VIDEO_SW_CURSOR is not set
  70 +CONFIG_DM_I2C=y
  71 +CONFIG_DM_GPIO=y
configs/ls1021aqds_nand_defconfig
Diff comments   View file @ 9ebde88
... ... @@ -82,4 +82,6 @@
82 82 CONFIG_VIDEO_FSL_DCU_FB=y
83 83 CONFIG_VIDEO=y
84 84 # CONFIG_VIDEO_SW_CURSOR is not set
  85 +CONFIG_DM_I2C=y
  86 +CONFIG_DM_GPIO=y
configs/ls1021aqds_nor_SECURE_BOOT_defconfig
Diff comments   View file @ 9ebde88
... ... @@ -66,4 +66,6 @@
66 66 # CONFIG_VIDEO_SW_CURSOR is not set
67 67 CONFIG_RSA=y
68 68 CONFIG_SPL_RSA=y
  69 +CONFIG_DM_I2C=y
  70 +CONFIG_DM_GPIO=y
configs/ls1021aqds_nor_defconfig
Diff comments   View file @ 9ebde88
... ... @@ -68,4 +68,6 @@
68 68 CONFIG_VIDEO_FSL_DCU_FB=y
69 69 CONFIG_VIDEO=y
70 70 # CONFIG_VIDEO_SW_CURSOR is not set
  71 +CONFIG_DM_I2C=y
  72 +CONFIG_DM_GPIO=y
configs/ls1021aqds_nor_lpuart_defconfig
Diff comments   View file @ 9ebde88
... ... @@ -68,4 +68,6 @@
68 68 CONFIG_VIDEO_FSL_DCU_FB=y
69 69 CONFIG_VIDEO=y
70 70 # CONFIG_VIDEO_SW_CURSOR is not set
  71 +CONFIG_DM_I2C=y
  72 +CONFIG_DM_GPIO=y
configs/ls1021aqds_qspi_defconfig
Diff comments   View file @ 9ebde88
... ... @@ -69,4 +69,6 @@
69 69 CONFIG_VIDEO_FSL_DCU_FB=y
70 70 CONFIG_VIDEO=y
71 71 # CONFIG_VIDEO_SW_CURSOR is not set
  72 +CONFIG_DM_I2C=y
  73 +CONFIG_DM_GPIO=y
configs/ls1021aqds_sdcard_ifc_defconfig
Diff comments   View file @ 9ebde88
... ... @@ -81,4 +81,6 @@
81 81 CONFIG_VIDEO_FSL_DCU_FB=y
82 82 CONFIG_VIDEO=y
83 83 # CONFIG_VIDEO_SW_CURSOR is not set
  84 +CONFIG_DM_I2C=y
  85 +CONFIG_DM_GPIO=y
configs/ls1021aqds_sdcard_qspi_defconfig
Diff comments   View file @ 9ebde88
... ... @@ -81,4 +81,6 @@
81 81 CONFIG_VIDEO_FSL_DCU_FB=y
82 82 CONFIG_VIDEO=y
83 83 # CONFIG_VIDEO_SW_CURSOR is not set
  84 +CONFIG_DM_I2C=y
  85 +CONFIG_DM_GPIO=y
configs/ls1021atsn_qspi_defconfig
Diff comments   View file @ 9ebde88
... ... @@ -57,4 +57,6 @@
57 57 CONFIG_DM_USB=y
58 58 CONFIG_USB_XHCI_HCD=y
59 59 CONFIG_USB_XHCI_DWC3=y
  60 +CONFIG_DM_I2C=y
  61 +CONFIG_DM_GPIO=y
configs/ls1021atsn_sdcard_defconfig
Diff comments   View file @ 9ebde88
... ... @@ -68,4 +68,6 @@
68 68 CONFIG_DM_USB=y
69 69 CONFIG_USB_XHCI_HCD=y
70 70 CONFIG_USB_XHCI_DWC3=y
  71 +CONFIG_DM_I2C=y
  72 +CONFIG_DM_GPIO=y
configs/ls1021atwr_nor_SECURE_BOOT_defconfig
Diff comments   View file @ 9ebde88
... ... @@ -60,4 +60,6 @@
60 60 # CONFIG_VIDEO_SW_CURSOR is not set
61 61 CONFIG_RSA=y
62 62 CONFIG_SPL_RSA=y
  63 +CONFIG_DM_I2C=y
  64 +CONFIG_DM_GPIO=y
configs/ls1021atwr_nor_defconfig
Diff comments   View file @ 9ebde88
... ... @@ -62,4 +62,6 @@
62 62 CONFIG_VIDEO_FSL_DCU_FB=y
63 63 CONFIG_VIDEO=y
64 64 # CONFIG_VIDEO_SW_CURSOR is not set
  65 +CONFIG_DM_I2C=y
  66 +CONFIG_DM_GPIO=y
configs/ls1021atwr_nor_lpuart_defconfig
Diff comments   View file @ 9ebde88
... ... @@ -63,4 +63,6 @@
63 63 CONFIG_VIDEO_FSL_DCU_FB=y
64 64 CONFIG_VIDEO=y
65 65 # CONFIG_VIDEO_SW_CURSOR is not set
  66 +CONFIG_DM_I2C=y
  67 +CONFIG_DM_GPIO=y
configs/ls1021atwr_qspi_defconfig
Diff comments   View file @ 9ebde88
... ... @@ -67,4 +67,6 @@
67 67 CONFIG_VIDEO_FSL_DCU_FB=y
68 68 CONFIG_VIDEO=y
69 69 # CONFIG_VIDEO_SW_CURSOR is not set
  70 +CONFIG_DM_I2C=y
  71 +CONFIG_DM_GPIO=y
configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
Diff comments   View file @ 9ebde88
... ... @@ -74,4 +74,6 @@
74 74 # CONFIG_VIDEO_SW_CURSOR is not set
75 75 CONFIG_RSA=y
76 76 CONFIG_SPL_RSA=y
  77 +CONFIG_DM_I2C=y
  78 +CONFIG_DM_GPIO=y
configs/ls1021atwr_sdcard_ifc_defconfig
Diff comments   View file @ 9ebde88
... ... @@ -75,4 +75,6 @@
75 75 CONFIG_VIDEO_FSL_DCU_FB=y
76 76 CONFIG_VIDEO=y
77 77 # CONFIG_VIDEO_SW_CURSOR is not set
  78 +CONFIG_DM_I2C=y
  79 +CONFIG_DM_GPIO=y
configs/ls1021atwr_sdcard_qspi_defconfig
Diff comments   View file @ 9ebde88
... ... @@ -78,4 +78,6 @@
78 78 CONFIG_VIDEO_FSL_DCU_FB=y
79 79 CONFIG_VIDEO=y
80 80 # CONFIG_VIDEO_SW_CURSOR is not set
  81 +CONFIG_DM_I2C=y
  82 +CONFIG_DM_GPIO=y
include/configs/ls1021aiot.h
Diff comments   View file @ 9ebde88
1 1 /* SPDX-License-Identifier: GPL-2.0+ */
2 2 /*
3 3 * Copyright 2016 Freescale Semiconductor, Inc.
  4 + * Copyright 2019 NXP
4 5 */
5 6  
6 7 #ifndef __CONFIG_H
7 8  
... ... @@ -97,7 +98,13 @@
97 98 * I2C
98 99 */
99 100 #define CONFIG_CMD_I2C
  101 +
  102 +#ifndef CONFIG_DM_I2C
100 103 #define CONFIG_SYS_I2C
  104 +#else
  105 +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
  106 +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
  107 +#endif
101 108 #define CONFIG_SYS_I2C_MXC
102 109 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
103 110 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
include/configs/ls1021aqds.h
Diff comments   View file @ 9ebde88
1 1 /* SPDX-License-Identifier: GPL-2.0+ */
2 2 /*
3 3 * Copyright 2014 Freescale Semiconductor, Inc.
  4 + * Copyright 2019 NXP
4 5 */
5 6  
6 7 #ifndef __CONFIG_H
7 8  
... ... @@ -331,7 +332,12 @@
331 332 /*
332 333 * I2C
333 334 */
  335 +#ifndef CONFIG_DM_I2C
334 336 #define CONFIG_SYS_I2C
  337 +#else
  338 +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
  339 +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
  340 +#endif
335 341 #define CONFIG_SYS_I2C_MXC
336 342 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
337 343 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
include/configs/ls1021atsn.h
Diff comments   View file @ 9ebde88
1 1 /* SPDX-License-Identifier: GPL-2.0
2   - * Copyright 2016-2018 NXP Semiconductors
  2 + * Copyright 2016-2019 NXP Semiconductors
3 3 * Copyright 2019 Vladimir Oltean <olteanv@gmail.com>
4 4 */
5 5  
6 6  
... ... @@ -107,7 +107,12 @@
107 107 #define CONFIG_BAUDRATE 115200
108 108  
109 109 /* I2C */
  110 +#ifndef CONFIG_DM_I2C
110 111 #define CONFIG_SYS_I2C
  112 +#else
  113 +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
  114 +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
  115 +#endif
111 116 #define CONFIG_SYS_I2C_MXC
112 117 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
113 118 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
include/configs/ls1021atwr.h
Diff comments   View file @ 9ebde88
1 1 /* SPDX-License-Identifier: GPL-2.0+ */
2 2 /*
3 3 * Copyright 2014 Freescale Semiconductor, Inc.
  4 + * Copyright 2019 NXP
4 5 */
5 6  
6 7 #ifndef __CONFIG_H
7 8  
... ... @@ -209,7 +210,12 @@
209 210 /*
210 211 * I2C
211 212 */
  213 +#ifndef CONFIG_DM_I2C
212 214 #define CONFIG_SYS_I2C
  215 +#else
  216 +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
  217 +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
  218 +#endif
213 219 #define CONFIG_SYS_I2C_MXC
214 220 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
215 221 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
... ... @@ -446,6 +452,7 @@
446 452  
447 453 #ifdef CONFIG_SPL_BUILD
448 454 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  455 +#undef CONFIG_DM_I2C
449 456 #else
450 457 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
451 458 #endif