Eric Lee / smarc-uboot

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Commit a039c86379815b550884858e37383d1f4c36c23f

Authored by Marek Vasut
Committed by Ye Li
1 parent 0579b85a2d
Exists in smarc_8mm-imx_v2019.04_4.19.35_1.1.0 and in 1 other branch smarc_8m-imx_v2019.04_4.19.35_1.1.0

pci: imx: Fix potential 64bit memory access clamping 

The driver limits the config space base to 32bit, however it can be
64bit on 64bit iMX hardware too. Remove that limitation. This patch
has no impact on the iMX6, which is the only SoC currently supported
by this driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
(cherry picked from commit 90f87fb5258c57bbb8497ac23454e659169483e4)

Showing 1 changed file with 11 additions and 9 deletions Side-by-side Diff

drivers/pci/pcie_imx.c
Diff comments   View file @ a039c86
... ... @@ -348,9 +348,11 @@
348 348 /* Region #0 is used for Outbound CFG space access. */
349 349 writel(0, priv->dbi_base + PCIE_ATU_VIEWPORT);
350 350  
351   - writel((u32)priv->cfg_base, priv->dbi_base + PCIE_ATU_LOWER_BASE);
352   - writel(0, priv->dbi_base + PCIE_ATU_UPPER_BASE);
353   - writel((u32)priv->cfg_base + MX6_ROOT_SIZE,
  351 + writel(lower_32_bits((uintptr_t)priv->cfg_base),
  352 + priv->dbi_base + PCIE_ATU_LOWER_BASE);
  353 + writel(upper_32_bits((uintptr_t)priv->cfg_base),
  354 + priv->dbi_base + PCIE_ATU_UPPER_BASE);
  355 + writel(lower_32_bits((uintptr_t)priv->cfg_base + MX6_ROOT_SIZE),
354 356 priv->dbi_base + PCIE_ATU_LIMIT);
355 357  
356 358 writel(0, priv->dbi_base + PCIE_ATU_LOWER_TARGET);
357 359  
... ... @@ -364,9 +366,9 @@
364 366 /*
365 367 * PCI Express accessors
366 368 */
367   -static uint32_t get_bus_address(pci_dev_t d, int where)
  369 +static void __iomem *get_bus_address(pci_dev_t d, int where)
368 370 {
369   - uint32_t va_address;
  371 + void __iomem *va_address;
370 372  
371 373 /* Reconfigure Region #0 */
372 374 writel(0, priv->dbi_base + PCIE_ATU_VIEWPORT);
373 375  
... ... @@ -377,10 +379,10 @@
377 379 writel(PCIE_ATU_TYPE_CFG1, priv->dbi_base + PCIE_ATU_CR1);
378 380  
379 381 if (PCI_BUS(d) == 0) {
380   - va_address = (u32)priv->dbi_base;
  382 + va_address = priv->dbi_base;
381 383 } else {
382 384 writel(d << 8, priv->dbi_base + PCIE_ATU_LOWER_TARGET);
383   - va_address = (u32)priv->cfg_base;
  385 + va_address = priv->cfg_base;
384 386 }
385 387  
386 388 va_address += (where & ~0x3);
... ... @@ -431,7 +433,7 @@
431 433 static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
432 434 int where, u32 *val)
433 435 {
434   - uint32_t va_address;
  436 + void __iomem *va_address;
435 437 int ret;
436 438  
437 439 ret = imx_pcie_addr_valid(d);
... ... @@ -460,7 +462,7 @@
460 462 static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
461 463 int where, u32 val)
462 464 {
463   - uint32_t va_address = 0;
  465 + void __iomem *va_address = NULL;
464 466 int ret;
465 467  
466 468 ret = imx_pcie_addr_valid(d);