Eric Lee / smarc-uboot

218
Download as
Browse Code ยป

Commit a0a37183bd75e74608bc78c8d0e2a34454f95a91

Authored by pekon gupta
Committed by Tom Rini
1 parent cd324a6dd2
Exists in v2017.01-smarct4x and in 40 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

ARM: omap: merge GPMC initialization code for all platform 

GPMC controller on TI's OMAP SoC is general purpose controller to interface
with different types of external devices like;
 - parallel NOR flash
 - parallel NAND flash
 - OneNand flash
 - SDR RAM
 - Ethernet Devices like LAN9220

Though GPMC configurations may be different for each platform depending on
clock-frequency and external device interfacing with controller. But
initialization sequence remains common across all platfoms.

Thus this patch merges gpmc_init() scattered in different arch-xx/mem.c
files into single omap-common/mem-common.c

However, actual platforms specific register config values are still sourced
from corresponding platform specific headers like;
 AM33xx: arch/arm/include/asm/arch-am33xx/mem.h
 OMAP3:  arch/arm/include/asm/arch-omap3/mem.h
 OMAP4:  arch/arm/include/asm/arch-omap4/mem.h
 OMAP4:  arch/arm/include/asm/arch-omap5/mem.h

Also, CONFIG_xx passed by board-profile decide config for which set of macros
need to be used for initialization
 CONFIG_NAND:    initialize GPMC for NAND device
 CONFIG_NOR:     initialize GPMC for NOR device
 CONFIG_ONENAND: initialize GPMC for ONENAND device

Signed-off-by: Pekon Gupta <pekon@ti.com>
[trini: define GPMC_SIZE_256M for omap3]
Signed-off-by: Tom Rini <trini@ti.com>

Showing 6 changed files with 112 additions and 110 deletions Side-by-side Diff

arch/arm/cpu/armv7/am33xx/Makefile
Diff comments   View file @ a0a3718
... ... @@ -14,7 +14,6 @@
14 14  
15 15 obj-$(CONFIG_TI816X) += clock_ti816x.o
16 16 obj-y += sys_info.o
17   -obj-y += mem.o
18 17 obj-y += ddr.o
19 18 obj-y += emif4.o
20 19 obj-y += board.o
arch/arm/cpu/armv7/am33xx/mem.c
View file @ a0a3718
1   -/*
2   - * (C) Copyright 2010
3   - * Texas Instruments, <www.ti.com>
4   - *
5   - * Author :
6   - * Mansoor Ahamed <mansoor.ahamed@ti.com>
7   - *
8   - * Initial Code from:
9   - * Manikandan Pillai <mani.pillai@ti.com>
10   - * Richard Woodruff <r-woodruff2@ti.com>
11   - * Syed Mohammed Khasim <khasim@ti.com>
12   - *
13   - * SPDX-License-Identifier: GPL-2.0+
14   - */
15   -
16   -#include <common.h>
17   -#include <asm/io.h>
18   -#include <asm/arch/cpu.h>
19   -#include <asm/arch/mem.h>
20   -#include <asm/arch/sys_proto.h>
21   -#include <command.h>
22   -
23   -struct gpmc *gpmc_cfg;
24   -
25   -
26   -void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
27   - u32 size)
28   -{
29   - writel(0, &cs->config7);
30   - sdelay(1000);
31   - /* Delay for settling */
32   - writel(gpmc_config[0], &cs->config1);
33   - writel(gpmc_config[1], &cs->config2);
34   - writel(gpmc_config[2], &cs->config3);
35   - writel(gpmc_config[3], &cs->config4);
36   - writel(gpmc_config[4], &cs->config5);
37   - writel(gpmc_config[5], &cs->config6);
38   - /* Enable the config */
39   - writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
40   - (1 << 6)), &cs->config7);
41   - sdelay(2000);
42   -}
43   -
44   -/*****************************************************
45   - * gpmc_init(): init gpmc bus
46   - * Init GPMC for x16, MuxMode (SDRAM in x32).
47   - * This code can only be executed from SRAM or SDRAM.
48   - *****************************************************/
49   -void gpmc_init(void)
50   -{
51   - /* putting a blanket check on GPMC based on ZeBu for now */
52   - gpmc_cfg = (struct gpmc *)GPMC_BASE;
53   -#if defined(CONFIG_NOR)
54   -/* configure GPMC for NOR */
55   - const u32 gpmc_regs[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1,
56   - STNOR_GPMC_CONFIG2,
57   - STNOR_GPMC_CONFIG3,
58   - STNOR_GPMC_CONFIG4,
59   - STNOR_GPMC_CONFIG5,
60   - STNOR_GPMC_CONFIG6,
61   - STNOR_GPMC_CONFIG7
62   - };
63   - u32 size = GPMC_SIZE_16M;
64   - u32 base = CONFIG_SYS_FLASH_BASE;
65   -#elif defined(CONFIG_NAND)
66   -/* configure GPMC for NAND */
67   - const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1,
68   - M_NAND_GPMC_CONFIG2,
69   - M_NAND_GPMC_CONFIG3,
70   - M_NAND_GPMC_CONFIG4,
71   - M_NAND_GPMC_CONFIG5,
72   - M_NAND_GPMC_CONFIG6,
73   - 0
74   - };
75   - u32 size = GPMC_SIZE_256M;
76   - u32 base = CONFIG_SYS_NAND_BASE;
77   -#else
78   - const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 };
79   - u32 size = 0;
80   - u32 base = 0;
81   -#endif
82   - /* global settings */
83   - writel(0x00000008, &gpmc_cfg->sysconfig);
84   - writel(0x00000000, &gpmc_cfg->irqstatus);
85   - writel(0x00000000, &gpmc_cfg->irqenable);
86   -#ifdef CONFIG_NOR
87   - writel(0x00000200, &gpmc_cfg->config);
88   -#else
89   - writel(0x00000012, &gpmc_cfg->config);
90   -#endif
91   - /*
92   - * Disable the GPMC0 config set by ROM code
93   - */
94   - writel(0, &gpmc_cfg->cs[0].config7);
95   - sdelay(1000);
96   - /* enable chip-select specific configurations */
97   - enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);
98   -}
arch/arm/cpu/armv7/omap-common/Makefile
Diff comments   View file @ a0a3718
... ... @@ -27,9 +27,5 @@
27 27 obj-y += lowlevel_init.o
28 28 endif
29 29  
30   -ifndef CONFIG_SPL_BUILD
31   -ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
32 30 obj-y += mem-common.o
33   -endif
34   -endif
arch/arm/cpu/armv7/omap-common/mem-common.c
Diff comments   View file @ a0a3718
... ... @@ -2,32 +2,137 @@
2 2 * (C) Copyright 2010
3 3 * Texas Instruments, <www.ti.com>
4 4 *
5   - * Steve Sakoman <steve@sakoman.com>
  5 + * Author :
  6 + * Mansoor Ahamed <mansoor.ahamed@ti.com>
6 7 *
  8 + * Initial Code from:
  9 + * Manikandan Pillai <mani.pillai@ti.com>
  10 + * Richard Woodruff <r-woodruff2@ti.com>
  11 + * Syed Mohammed Khasim <khasim@ti.com>
  12 + *
7 13 * SPDX-License-Identifier: GPL-2.0+
8 14 */
9 15  
  16 +#include <common.h>
  17 +#include <asm/io.h>
10 18 #include <asm/arch/cpu.h>
  19 +#include <asm/arch/mem.h>
11 20 #include <asm/arch/sys_proto.h>
  21 +#include <command.h>
  22 +#include <linux/mtd/omap_gpmc.h>
12 23  
13 24 struct gpmc *gpmc_cfg;
14 25  
  26 +#if defined(CONFIG_OMAP34XX)
  27 +/********************************************************
  28 + * mem_ok() - test used to see if timings are correct
  29 + * for a part. Helps in guessing which part
  30 + * we are currently using.
  31 + *******************************************************/
  32 +u32 mem_ok(u32 cs)
  33 +{
  34 + u32 val1, val2, addr;
  35 + u32 pattern = 0x12345678;
  36 +
  37 + addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
  38 +
  39 + writel(0x0, addr + 0x400); /* clear pos A */
  40 + writel(pattern, addr); /* pattern to pos B */
  41 + writel(0x0, addr + 4); /* remove pattern off the bus */
  42 + val1 = readl(addr + 0x400); /* get pos A value */
  43 + val2 = readl(addr); /* get val2 */
  44 + writel(0x0, addr + 0x400); /* clear pos A */
  45 +
  46 + if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */
  47 + return 0;
  48 + else
  49 + return 1;
  50 +}
  51 +#endif
  52 +
  53 +void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
  54 + u32 size)
  55 +{
  56 + writel(0, &cs->config7);
  57 + sdelay(1000);
  58 + /* Delay for settling */
  59 + writel(gpmc_config[0], &cs->config1);
  60 + writel(gpmc_config[1], &cs->config2);
  61 + writel(gpmc_config[2], &cs->config3);
  62 + writel(gpmc_config[3], &cs->config4);
  63 + writel(gpmc_config[4], &cs->config5);
  64 + writel(gpmc_config[5], &cs->config6);
  65 + /* Enable the config */
  66 + writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
  67 + (1 << 6)), &cs->config7);
  68 + sdelay(2000);
  69 +}
  70 +
15 71 /*****************************************************
16 72 * gpmc_init(): init gpmc bus
  73 + * Init GPMC for x16, MuxMode (SDRAM in x32).
17 74 * This code can only be executed from SRAM or SDRAM.
18 75 *****************************************************/
19 76 void gpmc_init(void)
20 77 {
  78 + /* putting a blanket check on GPMC based on ZeBu for now */
21 79 gpmc_cfg = (struct gpmc *)GPMC_BASE;
22   -
  80 +#if defined(CONFIG_NOR)
  81 +/* configure GPMC for NOR */
  82 + const u32 gpmc_regs[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1,
  83 + STNOR_GPMC_CONFIG2,
  84 + STNOR_GPMC_CONFIG3,
  85 + STNOR_GPMC_CONFIG4,
  86 + STNOR_GPMC_CONFIG5,
  87 + STNOR_GPMC_CONFIG6,
  88 + STNOR_GPMC_CONFIG7
  89 + };
  90 + u32 size = GPMC_SIZE_16M;
  91 + u32 base = CONFIG_SYS_FLASH_BASE;
  92 +#elif defined(CONFIG_NAND)
  93 +/* configure GPMC for NAND */
  94 + const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1,
  95 + M_NAND_GPMC_CONFIG2,
  96 + M_NAND_GPMC_CONFIG3,
  97 + M_NAND_GPMC_CONFIG4,
  98 + M_NAND_GPMC_CONFIG5,
  99 + M_NAND_GPMC_CONFIG6,
  100 + 0
  101 + };
  102 + u32 size = GPMC_SIZE_256M;
  103 + u32 base = CONFIG_SYS_NAND_BASE;
  104 +#elif defined(CONFIG_CMD_ONENAND)
  105 + const u32 gpmc_regs[GPMC_MAX_REG] = { ONENAND_GPMC_CONFIG1,
  106 + ONENAND_GPMC_CONFIG2,
  107 + ONENAND_GPMC_CONFIG3,
  108 + ONENAND_GPMC_CONFIG4,
  109 + ONENAND_GPMC_CONFIG5,
  110 + ONENAND_GPMC_CONFIG6,
  111 + 0
  112 + };
  113 + u32 base = PISMO1_ONEN_BASE;
  114 + u32 size = PISMO1_ONEN_SIZE;
  115 +#else
  116 + const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 };
  117 + u32 size = 0;
  118 + u32 base = 0;
  119 +#endif
23 120 /* global settings */
24   - writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */
25   - writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
26   -
  121 + writel(0x00000008, &gpmc_cfg->sysconfig);
  122 + writel(0x00000000, &gpmc_cfg->irqstatus);
  123 + writel(0x00000000, &gpmc_cfg->irqenable);
  124 + writel(0x00000000, &gpmc_cfg->timeout_control);
  125 +#ifdef CONFIG_NOR
  126 + writel(0x00000200, &gpmc_cfg->config);
  127 +#else
  128 + writel(0x00000012, &gpmc_cfg->config);
  129 +#endif
27 130 /*
28 131 * Disable the GPMC0 config set by ROM code
29   - * It conflicts with our MPDB (both at 0x08000000)
30 132 */
31 133 writel(0, &gpmc_cfg->cs[0].config7);
  134 + sdelay(1000);
  135 + /* enable chip-select specific configurations */
  136 + enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);
32 137 }
arch/arm/cpu/armv7/omap3/Makefile
Diff comments   View file @ a0a3718
... ... @@ -9,7 +9,6 @@
9 9  
10 10 obj-y += board.o
11 11 obj-y += clock.o
12   -obj-y += mem.o
13 12 obj-y += sys_info.o
14 13 ifdef CONFIG_SPL_BUILD
15 14 obj-$(CONFIG_SPL_OMAP3_ID_NAND) += spl_id_nand.o
arch/arm/include/asm/arch-omap3/mem.h
Diff comments   View file @ a0a3718
... ... @@ -344,6 +344,7 @@
344 344 * MAP - Map this CS to which address(GPMC address space)- Absolute address
345 345 * >>24 before being used.
346 346 */
  347 +#define GPMC_SIZE_256M 0x0
347 348 #define GPMC_SIZE_128M 0x8
348 349 #define GPMC_SIZE_64M 0xC
349 350 #define GPMC_SIZE_32M 0xE