Eric Lee / smarc-uboot

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Commit a1b341989b241be6e308ec9328d2fbb08049c8f9

Authored by Tom Rini
2 parents 6fa361903c 44ba7a373a
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

Merge git://git.denx.de/u-boot-pxa

Showing 16 changed files Side-by-side Diff

board/balloon3/balloon3.c
Diff comments   View file @ a1b3419
... ... @@ -29,7 +29,7 @@
29 29 dcache_disable();
30 30 icache_disable();
31 31  
32   - /* arch number of vpac270 */
  32 + /* arch number of balloon3 */
33 33 gd->bd->bi_arch_number = MACH_TYPE_BALLOON3;
34 34  
35 35 /* adress of boot parameters */
board/toradex/colibri_pxa270/colibri_pxa270.c
Diff comments   View file @ a1b3419
... ... @@ -23,7 +23,7 @@
23 23 dcache_disable();
24 24 icache_disable();
25 25  
26   - /* arch number of vpac270 */
  26 + /* arch number of Toradex Colibri PXA270 */
27 27 gd->bd->bi_arch_number = MACH_TYPE_COLIBRI;
28 28  
29 29 /* adress of boot parameters */
include/configs/balloon3.h
Diff comments   View file @ a1b3419
... ... @@ -13,7 +13,7 @@
13 13 * High Level Board Configuration Options
14 14 */
15 15 #define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
16   -#define CONFIG_BALLOON3 1 /* Balloon3 board */
  16 +#define CONFIG_BALLOON3 1 /* Balloon3 board */
17 17  
18 18 /*
19 19 * Environment settings
20 20  
21 21  
... ... @@ -84,18 +84,17 @@
84 84 /*
85 85 * Clock Configuration
86 86 */
87   -#undef CONFIG_SYS_CLKS_IN_HZ
88 87 #define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */
89 88  
90 89 /*
91 90 * DRAM Map
92 91 */
93   -#define CONFIG_NR_DRAM_BANKS 3 /* 2 banks of DRAM */
  92 +#define CONFIG_NR_DRAM_BANKS 3 /* 3 banks of DRAM */
94 93 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
95 94 #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
96 95 #define PHYS_SDRAM_2 0xb0000000 /* SDRAM Bank #2 */
97 96 #define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
98   -#define PHYS_SDRAM_3 0x80000000 /* SDRAM Bank #2 */
  97 +#define PHYS_SDRAM_3 0x80000000 /* SDRAM Bank #3 */
99 98 #define PHYS_SDRAM_3_SIZE 0x08000000 /* 128 MB */
100 99  
101 100 #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
... ... @@ -135,7 +134,7 @@
135 134 #define CONFIG_ENV_IS_IN_FLASH
136 135 #else
137 136 #define CONFIG_SYS_NO_FLASH
138   -#define CONFIG_SYS_ENV_IS_NOWHERE
  137 +#define CONFIG_ENV_IS_NOWHERE
139 138 #endif
140 139  
141 140 #define CONFIG_SYS_MONITOR_BASE 0x000000
... ... @@ -191,7 +190,6 @@
191 190 #define CONFIG_SYS_MDMRS_VAL 0x00220022
192 191 #define CONFIG_SYS_FLYCNFG_VAL 0x00000000
193 192 #define CONFIG_SYS_SXCNFG_VAL 0x00000000
194   -#define CONFIG_SYS_MEM_BUF_IMP 0x0f
195 193  
196 194 /*
197 195 * PCMCIA and CF Interfaces
include/configs/colibri_pxa270.h
Diff comments   View file @ a1b3419
... ... @@ -2,18 +2,22 @@
2 2 * Toradex Colibri PXA270 configuration file
3 3 *
4 4 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
  5 + * Copyright (C) 2015 Marcel Ziswiler <marcel@ziswiler.com>
5 6 *
6 7 * SPDX-License-Identifier: GPL-2.0+
7 8 */
8 9  
9   -#ifndef __CONFIG_H
10   -#define __CONFIG_H
  10 +#ifndef __CONFIG_H
  11 +#define __CONFIG_H
11 12  
12 13 /*
13 14 * High Level Board Configuration Options
14 15 */
15 16 #define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
  17 +#define CONFIG_SYS_GENERIC_BOARD
16 18 #define CONFIG_SYS_TEXT_BASE 0x0
  19 +/* Avoid overwriting factory configuration block */
  20 +#define CONFIG_BOARD_SIZE_LIMIT 0x40000
17 21  
18 22 /*
19 23 * Environment settings
20 24  
... ... @@ -22,13 +26,13 @@
22 26 #define CONFIG_SYS_MALLOC_LEN (128 * 1024)
23 27 #define CONFIG_ARCH_CPU_INIT
24 28 #define CONFIG_BOOTCOMMAND \
25   - "if mmc init && fatload mmc 0 0xa0000000 uImage; then " \
  29 + "if fatload mmc 0 0xa0000000 uImage; then " \
26 30 "bootm 0xa0000000; " \
27 31 "fi; " \
28 32 "if usb reset && fatload usb 0 0xa0000000 uImage; then " \
29 33 "bootm 0xa0000000; " \
30 34 "fi; " \
31   - "bootm 0x80000;"
  35 + "bootm 0xc0000;"
32 36 #define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200"
33 37 #define CONFIG_TIMESTAMP
34 38 #define CONFIG_BOOTDELAY 2 /* Autoboot delay */
... ... @@ -50,6 +54,8 @@
50 54 */
51 55 #include <config_cmd_default.h>
52 56  
  57 +#undef CONFIG_CMD_LOADB /* Both together */
  58 +#undef CONFIG_CMD_LOADS /* saves 10 KB */
53 59 #define CONFIG_CMD_NET
54 60 #define CONFIG_CMD_ENV
55 61 #undef CONFIG_CMD_IMLS
... ... @@ -59,7 +65,6 @@
59 65  
60 66 /*
61 67 * Networking Configuration
62   - * chip on the Voipac PXA270 board
63 68 */
64 69 #ifdef CONFIG_CMD_NET
65 70 #define CONFIG_CMD_PING
... ... @@ -82,7 +87,7 @@
82 87 */
83 88 #define CONFIG_SYS_HUSH_PARSER 1
84 89  
85   -#define CONFIG_SYS_LONGHELP
  90 +#undef CONFIG_SYS_LONGHELP /* Saves 10 KB */
86 91 #ifdef CONFIG_SYS_HUSH_PARSER
87 92 #define CONFIG_SYS_PROMPT "$ "
88 93 #else
... ... @@ -96,7 +101,6 @@
96 101 #define CONFIG_CMDLINE_EDITING 1
97 102 #define CONFIG_AUTO_COMPLETE 1
98 103  
99   -
100 104 /*
101 105 * Clock Configuration
102 106 */
103 107  
104 108  
105 109  
106 110  
107 111  
... ... @@ -142,25 +146,24 @@
142 146  
143 147 #else /* No flash */
144 148 #define CONFIG_SYS_NO_FLASH
145   -#define CONFIG_SYS_ENV_IS_NOWHERE
  149 +#define CONFIG_ENV_IS_NOWHERE
146 150 #endif
147 151  
148 152 #define CONFIG_SYS_MONITOR_BASE 0x0
149   -#define CONFIG_SYS_MONITOR_LEN 0x80000
  153 +#define CONFIG_SYS_MONITOR_LEN 0x40000
150 154  
  155 +/* Skip factory configuration block */
151 156 #define CONFIG_ENV_ADDR \
152   - (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
  157 + (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + 0x40000)
153 158 #define CONFIG_ENV_SIZE 0x40000
154 159 #define CONFIG_ENV_SECT_SIZE 0x40000
155   -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
156   -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
157 160  
158 161 /*
159 162 * GPIO settings
160 163 */
161 164 #define CONFIG_SYS_GPSR0_VAL 0x00000000
162 165 #define CONFIG_SYS_GPSR1_VAL 0x00020000
163   -#define CONFIG_SYS_GPSR2_VAL 0x0002C000
  166 +#define CONFIG_SYS_GPSR2_VAL 0x0002c000
164 167 #define CONFIG_SYS_GPSR3_VAL 0x00000000
165 168  
166 169 #define CONFIG_SYS_GPCR0_VAL 0x00000000
167 170  
... ... @@ -168,19 +171,19 @@
168 171 #define CONFIG_SYS_GPCR2_VAL 0x00000000
169 172 #define CONFIG_SYS_GPCR3_VAL 0x00000000
170 173  
171   -#define CONFIG_SYS_GPDR0_VAL 0x08000000
172   -#define CONFIG_SYS_GPDR1_VAL 0x0002A981
173   -#define CONFIG_SYS_GPDR2_VAL 0x0202FC00
174   -#define CONFIG_SYS_GPDR3_VAL 0x00000000
  174 +#define CONFIG_SYS_GPDR0_VAL 0xc8008000
  175 +#define CONFIG_SYS_GPDR1_VAL 0xfc02a981
  176 +#define CONFIG_SYS_GPDR2_VAL 0x92c3ffff
  177 +#define CONFIG_SYS_GPDR3_VAL 0x0061e804
175 178  
176   -#define CONFIG_SYS_GAFR0_L_VAL 0x00100000
177   -#define CONFIG_SYS_GAFR0_U_VAL 0x00C00010
178   -#define CONFIG_SYS_GAFR1_L_VAL 0x999A901A
179   -#define CONFIG_SYS_GAFR1_U_VAL 0xAAA00008
180   -#define CONFIG_SYS_GAFR2_L_VAL 0xAAAAAAAA
181   -#define CONFIG_SYS_GAFR2_U_VAL 0x0109A000
182   -#define CONFIG_SYS_GAFR3_L_VAL 0x54000300
183   -#define CONFIG_SYS_GAFR3_U_VAL 0x00024001
  179 +#define CONFIG_SYS_GAFR0_L_VAL 0x80100000
  180 +#define CONFIG_SYS_GAFR0_U_VAL 0xa5c00010
  181 +#define CONFIG_SYS_GAFR1_L_VAL 0x6992901a
  182 +#define CONFIG_SYS_GAFR1_U_VAL 0xaaa50008
  183 +#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
  184 +#define CONFIG_SYS_GAFR2_U_VAL 0x4109a002
  185 +#define CONFIG_SYS_GAFR3_L_VAL 0x54000310
  186 +#define CONFIG_SYS_GAFR3_U_VAL 0x00005401
184 187  
185 188 #define CONFIG_SYS_PSSR_VAL 0x30
186 189  
187 190  
188 191  
189 192  
190 193  
... ... @@ -193,27 +196,27 @@
193 196 /*
194 197 * Memory settings
195 198 */
196   -#define CONFIG_SYS_MSC0_VAL 0x000095f2
197   -#define CONFIG_SYS_MSC1_VAL 0x00007ff4
198   -#define CONFIG_SYS_MSC2_VAL 0x00000000
199   -#define CONFIG_SYS_MDCNFG_VAL 0x08000ac9
200   -#define CONFIG_SYS_MDREFR_VAL 0x2013e01e
201   -#define CONFIG_SYS_MDMRS_VAL 0x00320032
202   -#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
  199 +#define CONFIG_SYS_MSC0_VAL 0x9ee1c5f2
  200 +#define CONFIG_SYS_MSC1_VAL 0x9ee1f994
  201 +#define CONFIG_SYS_MSC2_VAL 0x9ee19ee1
  202 +#define CONFIG_SYS_MDCNFG_VAL 0x090009c9
  203 +#define CONFIG_SYS_MDREFR_VAL 0x2003a031
  204 +#define CONFIG_SYS_MDMRS_VAL 0x00220022
  205 +#define CONFIG_SYS_FLYCNFG_VAL 0x00010001
203 206 #define CONFIG_SYS_SXCNFG_VAL 0x40044004
204 207  
205 208 /*
206 209 * PCMCIA and CF Interfaces
207 210 */
208   -#define CONFIG_SYS_MECR_VAL 0x00000001
209   -#define CONFIG_SYS_MCMEM0_VAL 0x00014307
  211 +#define CONFIG_SYS_MECR_VAL 0x00000000
  212 +#define CONFIG_SYS_MCMEM0_VAL 0x00028307
210 213 #define CONFIG_SYS_MCMEM1_VAL 0x00014307
211   -#define CONFIG_SYS_MCATT0_VAL 0x0001c787
  214 +#define CONFIG_SYS_MCATT0_VAL 0x00038787
212 215 #define CONFIG_SYS_MCATT1_VAL 0x0001c787
213   -#define CONFIG_SYS_MCIO0_VAL 0x0001430f
  216 +#define CONFIG_SYS_MCIO0_VAL 0x0002830f
214 217 #define CONFIG_SYS_MCIO1_VAL 0x0001430f
215 218  
216 219 #include "pxa-common.h"
217 220  
218   -#endif /* __CONFIG_H */
  221 +#endif /* __CONFIG_H */
include/configs/flea3.h
Diff comments   View file @ a1b3419
... ... @@ -124,8 +124,6 @@
124 124 #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
125 125 #define CONFIG_SYS_MEMTEST_END 0x10000
126 126  
127   -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
128   -
129 127 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
130 128  
131 129 /*
include/configs/mx35pdk.h
Diff comments   View file @ a1b3419
... ... @@ -146,8 +146,6 @@
146 146 #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
147 147 #define CONFIG_SYS_MEMTEST_END 0x10000
148 148  
149   -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
150   -
151 149 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
152 150  
153 151 /*
include/configs/palmld.h
Diff comments   View file @ a1b3419
... ... @@ -114,7 +114,6 @@
114 114 /*
115 115 * Clock Configuration
116 116 */
117   -#undef CONFIG_SYS_CLKS_IN_HZ
118 117 #define CONFIG_SYS_CPUSPEED 0x210 /* 416MHz ; N=2,L=16 */
119 118  
120 119 /*
include/configs/palmtc.h
Diff comments   View file @ a1b3419
... ... @@ -116,7 +116,6 @@
116 116 /*
117 117 * Clock Configuration
118 118 */
119   -#undef CONFIG_SYS_CLKS_IN_HZ
120 119 #define CONFIG_SYS_CPUSPEED 0x161 /* 400MHz;L=1 M=3 T=1 */
121 120  
122 121 /*
include/configs/palmtreo680.h
Diff comments   View file @ a1b3419
... ... @@ -117,7 +117,6 @@
117 117 /*
118 118 * Clock Configuration
119 119 */
120   -#undef CONFIG_SYS_CLKS_IN_HZ
121 120 #define CONFIG_SYS_CPUSPEED 0x210 /* 416MHz ; N=2,L=16 */
122 121  
123 122 /*
include/configs/snowball.h
Diff comments   View file @ a1b3419
... ... @@ -175,7 +175,6 @@
175 175 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
176 176 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */
177 177  
178   -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
179 178 #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
180 179 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1
181 180  
include/configs/ti816x_evm.h
Diff comments   View file @ a1b3419
... ... @@ -58,7 +58,6 @@
58 58 + sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */
59 59 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot arg buffer size */
60 60  
61   -#undef CONFIG_SYS_CLKS_IN_HZ
62 61 #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */
63 62  
64 63 #define CONFIG_CMD_ASKEN
include/configs/u8500_href.h
Diff comments   View file @ a1b3419
... ... @@ -131,7 +131,6 @@
131 131 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
132 132 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */
133 133  
134   -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
135 134 #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
136 135 #define CONFIG_SYS_LOADS_BAUD_CHANGE
137 136  
include/configs/vexpress_common.h
Diff comments   View file @ a1b3419
... ... @@ -188,7 +188,6 @@
188 188 #define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
189 189  
190 190 /* Miscellaneous configurable options */
191   -#undef CONFIG_SYS_CLKS_IN_HZ
192 191 #define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x8000)
193 192 #define LINUX_BOOT_PARAM_ADDR (V2M_BASE + 0x2000)
194 193 #define CONFIG_BOOTDELAY 2
include/configs/vpac270.h
Diff comments   View file @ a1b3419
... ... @@ -221,7 +221,7 @@
221 221  
222 222 #else /* No flash */
223 223 #define CONFIG_SYS_NO_FLASH
224   -#define CONFIG_SYS_ENV_IS_NOWHERE
  224 +#define CONFIG_ENV_IS_NOWHERE
225 225 #endif
226 226  
227 227 /*
... ... @@ -297,7 +297,6 @@
297 297 #define CONFIG_SYS_MDMRS_VAL 0x00000000
298 298 #define CONFIG_SYS_FLYCNFG_VAL 0x00000000
299 299 #define CONFIG_SYS_SXCNFG_VAL 0x40044004
300   -#define CONFIG_SYS_MEM_BUF_IMP 0x0f
301 300  
302 301 /*
303 302 * PCMCIA and CF Interfaces
include/configs/woodburn_common.h
Diff comments   View file @ a1b3419
... ... @@ -146,8 +146,6 @@
146 146 #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
147 147 #define CONFIG_SYS_MEMTEST_END 0x10000
148 148  
149   -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
150   -
151 149 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
152 150  
153 151 /*
include/configs/zipitz2.h
Diff comments   View file @ a1b3419
... ... @@ -136,7 +136,6 @@
136 136 /*
137 137 * Clock Configuration
138 138 */
139   -#undef CONFIG_SYS_CLKS_IN_HZ
140 139 #define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
141 140  
142 141 /*