Eric Lee / smarc-uboot | Embedian Git Server

Commit a2a89b2e21dbb68c9302a174013a1fab3a8ef42b

Authored by Patrice Chotard 2019-05-01 00:08:28 +0800

Exists in smarc_8mq_lf_v2020.04 and in 9 other branches

spi: stm32: Add Serial Peripheral Interface driver for STM32MP

Add SPI driver support for STM32MP SoCs family.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

Showing 4 changed files with 625 additions and 0 deletions Inline Diff

MAINTAINERS
drivers/spi/Kconfig
drivers/spi/Makefile
drivers/spi/stm32_spi.c

MAINTAINERS

Diff comments View file @ a2a89b2

 Descriptions of section entries:
 	P: Person (obsolete)
 	M: Mail patches to: FullName <address@domain>
 	R: Designated reviewer: FullName <address@domain>
 	   These reviewers should be CCed on patches.
 	L: Mailing list that is relevant to this area
 	W: Web-page with status/info
 	Q: Patchwork web based patch tracking system site
 	T: SCM tree type and location.
 	   Type is one of: git, hg, quilt, stgit, topgit
 	S: Status, one of the following:
 	   Supported:	Someone is actually paid to look after this.
 	   Maintained:	Someone actually looks after it.
 	   Orphan:	No current maintainer [but maybe you could take the
 			role as you write your new code].
 	F: Files and directories with wildcard patterns.
 	   A trailing slash includes all files and subdirectory files.
 	   F:	drivers/net/	all files in and below drivers/net
 	   F:	drivers/net/*	all files in drivers/net, but not below
 	   F:	*/net/*		all files in "any top level directory"/net
 	   One pattern per line.  Multiple F: lines acceptable.
 	N: Files and directories with regex patterns.
 	   N:	[^a-z]tegra	all files whose path contains the word tegra
 	   One pattern per line.  Multiple N: lines acceptable.
 	   scripts/get_maintainer.pl has different behavior for files that
 	   match F: pattern and matches of N: patterns.  By default,
 	   get_maintainer will not look at git log history when an F: pattern
 	   match occurs.  When an N: match occurs, git log history is used
 	   to also notify the people that have git commit signatures.
 	X: Files and directories that are NOT maintained, same rules as F:
 	   Files exclusions are tested before file matches.
 	   Can be useful for excluding a specific subdirectory, for instance:
 	   F:	net/
 	   X:	net/ipv6/
 	   matches all files in and below net excluding net/ipv6/
 	K: Keyword perl extended regex pattern to match content in a
 	   patch or file.  For instance:
 	   K: of_get_profile
 	      matches patches or files that contain "of_get_profile"
 	   K: \b(printk|pr_(info|err))\b
 	      matches patches or files that contain one or more of the words
 	      printk, pr_info or pr_err
 	   One regex pattern per line.  Multiple K: lines acceptable.
 Note: For the hard of thinking, this list is meant to remain in alphabetical
 order. If you could add yourselves to it in alphabetical order that would be
 so much easier [Ed]
 Maintainers List (try to look for most precise areas first)
 		-----------------------------------
 ARC
 M:	Alexey Brodkin <alexey.brodkin@synopsys.com>
 M:	Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
 S:	Maintained
 L:	uboot-snps-arc@synopsys.com
 T:	git git://git.denx.de/u-boot-arc.git
 F:	arch/arc/
 F:	board/synopsys/
 ARC HSDK CGU CLOCK
 M:	Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
 S:	Maintained
 L:	uboot-snps-arc@synopsys.com
 F:	drivers/clk/clk-hsdk-cgu.c
 F:	include/dt-bindings/clock/snps,hsdk-cgu.h
 F:	doc/device-tree-bindings/clock/snps,hsdk-cgu.txt
 ARC HSDK CREG GPIO
 M:	Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
 S:	Maintained
 L:	uboot-snps-arc@synopsys.com
 F:	doc/device-tree-bindings/gpio/snps,creg-gpio.txt
 F:	drivers/gpio/hsdk-creg-gpio.c
 ARC SYNOPSYS DW MMC EXTENSIONS
 M:	Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
 S:	Maintained
 L:	uboot-snps-arc@synopsys.com
 F:	doc/device-tree-bindings/mmc/snps,dw-mmc.txt
 F:	drivers/mmc/snps_dw_mmc.c
 ARM
 M:	Albert Aribaud <albert.u.boot@aribaud.net>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-arm.git
 F:	arch/arm/
 F:	cmd/arm/
 ARM ALTERA SOCFPGA
 M:	Marek Vasut <marex@denx.de>
 M:	Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
 S:	Maintainted
 T:	git git://git.denx.de/u-boot-socfpga.git
 F:	arch/arm/mach-socfpga/
 ARM AMLOGIC SOC SUPPORT
 M:	Neil Armstrong <narmstrong@baylibre.com>
 S:	Maintained
 L:	u-boot-amlogic@groups.io
 T:	git git://git.denx.de/u-boot-amlogic.git
 F:	arch/arm/mach-meson/
 F:	arch/arm/include/asm/arch-meson/
 F:	drivers/clk/meson/
 F:	drivers/serial/serial_meson.c
 F:	drivers/reset/reset-meson.c
 F:	drivers/i2c/meson_i2c.c
 F:	drivers/net/phy/meson-gxl.c
 F:	drivers/adc/meson-saradc.c
 F:	drivers/phy/meson*
 F:	drivers/mmc/meson_gx_mmc.c
 F:	drivers/spi/meson_spifc.c
 F:	drivers/pinctrl/meson/
 F:	drivers/power/domain/meson-gx-pwrc-vpu.c
 F:	drivers/video/meson/
 F:	include/configs/meson64.h
 N:	meson
 ARM BROADCOM BCM283X
 M:	Matthias Brugger <mbrugger@suse.com>
 S:	Maintained
 F:	arch/arm/mach-bcm283x/
 F:	drivers/gpio/bcm2835_gpio.c
 F:	drivers/mmc/bcm2835_sdhci.c
 F:	drivers/mmc/bcm2835_sdhost.c
 F:	drivers/serial/serial_bcm283x_mu.c
 F:	drivers/serial/serial_bcm283x_pl011.c
 F:	drivers/video/bcm2835.c
 F:	include/dm/platform_data/serial_bcm283x_mu.h
 F:	drivers/pinctrl/broadcom/
 ARM BROADCOM BCMSTB
 M:	Thomas Fitzsimmons <fitzsim@fitzsim.org>
 S:	Maintained
 F:	arch/arm/mach-bcmstb/
 F:	board/broadcom/bcmstb/
 F:	configs/bcm7*_defconfig
 F:	doc/README.bcm7xxx
 F:	drivers/mmc/bcmstb_sdhci.c
 F:	drivers/spi/bcmstb_spi.c
 ARM/CZ.NIC TURRIS MOX SUPPORT
 M:	Marek Behun <marek.behun@nic.cz>
 S:	Maintained
 F:	arch/arm/dts/armada-3720-turris-mox.dts
 F:	board/CZ.NIC/
 F:	configs/turris_*_defconfig
 F:	include/configs/turris_*.h
 ARM FREESCALE IMX
 M:	Stefano Babic <sbabic@denx.de>
 M:	Fabio Estevam <festevam@gmail.com>
 R:	NXP i.MX U-Boot Team <uboot-imx@nxp.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-imx.git
 F:	arch/arm/cpu/arm1136/mx*/
 F:	arch/arm/cpu/arm926ejs/mx*/
 F:	arch/arm/cpu/armv7/vf610/
 F:	arch/arm/mach-imx/
 F:	arch/arm/include/asm/arch-imx/
 F:	arch/arm/include/asm/arch-mx*/
 F:	arch/arm/include/asm/arch-vf610/
 F:	arch/arm/include/asm/mach-imx/
 F:	board/freescale/*mx*/
 ARM HISILICON
 M:	Peter Griffin <peter.griffin@linaro.org>
 S:	Maintained
 F:	arch/arm/cpu/armv8/hisilicon
 F:	arch/arm/include/asm/arch-hi6220/
 ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K
 M:	Stefan Roese <sr@denx.de>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-marvell.git
 F:	arch/arm/mach-kirkwood/
 F:	arch/arm/mach-mvebu/
 F:	drivers/ata/ahci_mvebu.c
 F:	drivers/ddr/marvell/
 F:	drivers/gpio/mvebu_gpio.c
 F:	drivers/spi/kirkwood_spi.c
 F:	drivers/pci/pci_mvebu.c
 F:	drivers/pci/pcie_dw_mvebu.c
 F:	drivers/watchdog/orion_wdt.c
 ARM MARVELL PXA
 M:	Marek Vasut <marex@denx.de>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-pxa.git
 F:	arch/arm/cpu/pxa/
 F:	arch/arm/include/asm/arch-pxa/
 ARM MEDIATEK
 M:	Ryder Lee <ryder.lee@mediatek.com>
 M:	Weijie Gao <weijie.gao@mediatek.com>
 S:	Maintained
 F:	arch/arm/mach-mediatek/
 F:	arch/arm/include/asm/arch-mediatek/
 F:	board/mediatek/
 F:	doc/README.mediatek
 F:	drivers/clk/mediatek/
 F:	drivers/mmc/mtk-sd.c
 F:	drivers/pinctrl/mediatek/
 F:	drivers/power/domain/mtk-power-domain.c
 F:	drivers/ram/mediatek/
 F:	drivers/spi/mtk_qspi.c
 F:	drivers/timer/mtk_timer.c
 F:	drivers/watchdog/mtk_wdt.c
 F:	drivers/net/mtk_eth.c
 F:	drivers/reset/reset-mediatek.c
 F:	tools/mtk_image.c
 F:	tools/mtk_image.h
 N:	mediatek
 ARM MICROCHIP/ATMEL AT91
 M:	Eugen Hristev <eugen.hristev@microchip.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-atmel.git
 F:	arch/arm/mach-at91/
 F:	board/atmel/
 ARM OWL
 M:	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
 S:	Maintained
 F:	arch/arm/include/asm/arch-owl/
 F:	arch/arm/mach-owl/
 F:	board/ucRobotics/
 F:	drivers/clk/owl/
 F:	drivers/serial/serial_owl.c
 ARM RENESAS RMOBILE/R-CAR
 M:	Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 M:	Marek Vasut <marek.vasut+renesas@gmail.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-sh.git
 F:	arch/arm/mach-rmobile/
 ARM ROCKCHIP
 M:	Simon Glass <sjg@chromium.org>
 M:	Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
 M:	Kever Yang <kever.yang@rock-chips.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-rockchip.git
 F:	arch/arm/include/asm/arch-rockchip/
 F:	arch/arm/mach-rockchip/
 F:	board/rockchip/
 F:	drivers/clk/rockchip/
 F:	drivers/gpio/rk_gpio.c
 F:	drivers/misc/rockchip-efuse.c
 F:	drivers/mmc/rockchip_sdhci.c
 F:	drivers/mmc/rockchip_dw_mmc.c
 F:	drivers/pinctrl/rockchip/
 F:	drivers/ram/rockchip/
 F:	drivers/sysreset/sysreset_rockchip.c
 F:	drivers/video/rockchip/
 F:	tools/rkcommon.c
 F:	tools/rkcommon.h
 F:	tools/rkimage.c
 F:	tools/rksd.c
 F:	tools/rkspi.c
 ARM SAMSUNG
 M:	Minkyu Kang <mk7.kang@samsung.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-samsung.git
 F:	arch/arm/mach-exynos/
 F:	arch/arm/mach-s5pc1xx/
 F:	arch/arm/cpu/armv7/s5p-common/
 ARM SNAPDRAGON
 M:	Ramon Fried <ramon.fried@gmail.com>
 S:	Maintained
 F:	arch/arm/mach-snapdragon/
 F:	drivers/gpio/msm_gpio.c
 F:	drivers/mmc/msm_sdhci.c
 F:	drivers/phy/msm8916-usbh-phy.c
 F:	drivers/serial/serial_msm.c
 F:	drivers/smem/msm_smem.c
 F:	drivers/usb/host/ehci-msm.c
 ARM STI
 M:	Patrice Chotard <patrice.chotard@st.com>
 S:	Maintained
 F:	arch/arm/mach-sti/
 F:	arch/arm/include/asm/arch-sti*/
 ARM STM SPEAR
 #M:	Vipin Kumar <vipin.kumar@st.com>
 S:	Orphaned (Since 2016-02)
 T:	git git://git.denx.de/u-boot-stm.git
 F:	arch/arm/cpu/arm926ejs/spear/
 F:	arch/arm/include/asm/arch-spear/
 ARM STM STM32MP
 M:	Patrick Delaunay <patrick.delaunay@st.com>
 M:	Christophe Kerello <christophe.kerello@st.com>
 M:	Patrice Chotard <patrice.chotard@st.com>
 L:	uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers)
 S:	Maintained
 F:	arch/arm/mach-stm32mp/
 F:	drivers/clk/clk_stm32mp1.c
 F:	drivers/i2c/stm32f7_i2c.c
 F:	drivers/misc/stm32mp_fuse.c
 F:	drivers/mmc/stm32_sdmmc2.c
 F:	drivers/phy/phy-stm32-usbphyc.c
 F:	drivers/pinctrl/pinctrl_stm32.c
 F:	drivers/power/pmic/stpmic1.c
 F:	drivers/power/regulator/stm32-vrefbuf.c
 F:	drivers/power/regulator/stpmic1.c
 F:	drivers/ram/stm32mp1/
 F:	drivers/misc/stm32_rcc.c
 F:	drivers/reset/stm32-reset.c
 F:	drivers/spi/stm32_qspi.c
+F:	drivers/spi/stm32_spi.c
 F:	drivers/watchdog/stm32mp_wdt.c
 ARM STM STV0991
 M:	Vikas Manocha <vikas.manocha@st.com>
 S:	Maintained
 F:	arch/arm/cpu/armv7/stv0991/
 F:	arch/arm/include/asm/arch-stv0991/
 ARM SUNXI
 M:	Jagan Teki <jagan@amarulasolutions.com>
 M:	Maxime Ripard <maxime.ripard@bootlin.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-sunxi.git
 F:	arch/arm/cpu/armv7/sunxi/
 F:	arch/arm/include/asm/arch-sunxi/
 F:	arch/arm/mach-sunxi/
 F:	board/sunxi/
 ARM TEGRA
 M:	Tom Warren <twarren@nvidia.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-tegra.git
 F:	arch/arm/mach-tegra/
 F:	arch/arm/include/asm/arch-tegra*/
 ARM TI
 M:	Tom Rini <trini@konsulko.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-ti.git
 F:	arch/arm/mach-davinci/
 F:	arch/arm/mach-k3/
 F:	arch/arm/mach-keystone/
 F:	arch/arm/include/asm/arch-omap*/
 F:	arch/arm/include/asm/ti-common/
 ARM UNIPHIER
 M:	Masahiro Yamada <yamada.masahiro@socionext.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-uniphier.git
 F:	arch/arm/mach-uniphier/
 F:	configs/uniphier_*_defconfig
 N:	uniphier
 ARM VERSAL
 M:	Michal Simek <michal.simek@xilinx.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-microblaze.git
 F:	arch/arm/mach-versal/
 ARM VERSATILE EXPRESS DRIVERS
 M:	Liviu Dudau <liviu.dudau@foss.arm.com>
 S:	Maintained
 T:	git git://github.com/ARM-software/u-boot.git
 F:	drivers/misc/vexpress_config.c
 N:	vexpress
 ARM ZYNQ
 M:	Michal Simek <monstr@monstr.eu>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-microblaze.git
 F:	arch/arm/mach-zynq/
 F:	drivers/clk/clk_zynq.c
 F:	drivers/fpga/zynqpl.c
 F:	drivers/gpio/zynq_gpio.c
 F:	drivers/i2c/i2c-cdns.c
 F:	drivers/i2c/muxes/pca954x.c
 F:	drivers/i2c/zynq_i2c.c
 F:	drivers/mmc/zynq_sdhci.c
 F:	drivers/mtd/nand/raw/zynq_nand.c
 F:	drivers/net/phy/xilinx_phy.c
 F:	drivers/net/zynq_gem.c
 F:	drivers/serial/serial_zynq.c
 F:	drivers/spi/zynq_qspi.c
 F:	drivers/spi/zynq_spi.c
 F:	drivers/usb/host/ehci-zynq.c
 F:	drivers/watchdog/cdns_wdt.c
 F:	include/zynqpl.h
 F:	tools/zynqimage.c
 N:	zynq
 ARM ZYNQMP
 M:	Michal Simek <michal.simek@xilinx.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-microblaze.git
 F:	arch/arm/mach-zynqmp/
 F:	drivers/clk/clk_zynqmp.c
 F:	drivers/fpga/zynqpl.c
 F:	drivers/gpio/zynq_gpio.c
 F:	drivers/i2c/i2c-cdns.c
 F:	drivers/i2c/muxes/pca954x.c
 F:	drivers/i2c/zynq_i2c.c
 F:	drivers/mmc/zynq_sdhci.c
 F:	drivers/mtd/nand/raw/zynq_nand.c
 F:	drivers/net/phy/xilinx_phy.c
 F:	drivers/net/zynq_gem.c
 F:	drivers/serial/serial_zynq.c
 F:	drivers/spi/zynq_qspi.c
 F:	drivers/spi/zynq_spi.c
 F:	drivers/timer/cadence-ttc.c
 F:	drivers/usb/host/ehci-zynq.c
 F:	drivers/watchdog/cdns_wdt.c
 F:	include/zynqmppl.h
 F:	tools/zynqmp*
 N:	ultra96
 N:	zynqmp
 ARM ZYNQMP R5
 M:	Michal Simek <michal.simek@xilinx.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-microblaze.git
 F:	arch/arm/mach-zynqmp-r5/
 BINMAN
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
 F:	tools/binman/
 BUILDMAN
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
 F:	tools/buildman/
 CFI FLASH
 M:	Stefan Roese <sr@denx.de>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-cfi-flash.git
 F:	drivers/mtd/cfi_flash.c
 F:	drivers/mtd/jedec_flash.c
 COLDFIRE
 M:	Huan Wang <alison.wang@nxp.com>
 M:	Angelo Dureghello <angelo@sysam.it>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-coldfire.git
 F:	arch/m68k/
 DFU
 M:	Lukasz Majewski <lukma@denx.de>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-dfu.git
 F:	cmd/dfu.c
 F:	cmd/usb_*.c
 F:	common/dfu.c
 F:	common/update.c
 F:	common/usb_storage.c
 F:	drivers/dfu/
 F:	drivers/usb/gadget/
 DRIVER MODEL
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-dm.git
 F:	drivers/core/
 F:	include/dm/
 F:	test/dm/
 EFI PAYLOAD
 M:	Heinrich Schuchardt <xypron.glpk@gmx.de>
 R:	Alexander Graf <agraf@csgraf.de>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-efi.git
 F:	doc/README.uefi
 F:	doc/README.iscsi
 F:	Documentation/efi.rst
 F:	include/capitalization.h
 F:	include/charset.h
 F:	include/cp1250.h
 F:	include/cp437.h
 F:	include/efi*
 F:	include/pe.h
 F:	include/asm-generic/pe.h
 F:	lib/charset.c
 F:	lib/efi*/
 F:	test/py/tests/test_efi*
 F:	test/unicode_ut.c
 F:	cmd/bootefi.c
 F:	cmd/efidebug.c
 F:	cmd/nvedit_efi.c
 F:	tools/file2include.c
 FPGA
 M:	Michal Simek <michal.simek@xilinx.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-microblaze.git
 F:	drivers/fpga/
 F:	cmd/fpga.c
 F:	include/fpga.h
 FLATTENED DEVICE TREE
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-fdt.git
 F:	lib/fdtdec*
 F:	lib/libfdt/
 F:	include/fdt*
 F:	include/linux/libfdt*
 F:	cmd/fdt.c
 F:	common/fdt_support.c
 FREEBSD
 M:	Rafal Jaworowski <raj@semihalf.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-freebsd.git
 FREESCALE QORIQ
 M:	Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-fsl-qoriq.git
 F:	drivers/watchdog/sp805_wdt.c
 I2C
 M:	Heiko Schocher <hs@denx.de>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-i2c.git
 F:	drivers/i2c/
 LOGGING
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
 T:	git git://git.denx.de/u-boot.git
 F:	common/log.c
 F:	cmd/log.c
 F:	test/log/log_test.c
 F:	test/py/tests/test_log.py
 MALI DISPLAY PROCESSORS
 M:	Liviu Dudau <liviu.dudau@foss.arm.com>
 S:	Supported
 T:	git git://github.com/ARM-software/u-boot.git
 F:	drivers/video/mali_dp.c
 F:	drivers/i2c/i2c-versatile.c
 MICROBLAZE
 M:	Michal Simek <monstr@monstr.eu>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-microblaze.git
 F:	arch/microblaze/
 F:	cmd/mfsl.c
 F:	drivers/gpio/xilinx_gpio.c
 F:	drivers/net/xilinx_axi_emac.c
 F:	drivers/net/xilinx_emaclite.c
 F:	drivers/serial/serial_xuartlite.c
 F:	drivers/spi/xilinx_spi.c
 F:	drivers/sysreset/sysreset_gpio.c
 F:	drivers/watchdog/xilinx_tb_wdt.c
 N:	xilinx
 MIPS
 M:	Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-mips.git
 F:	arch/mips/
 MIPS MSCC
 M:	Gregory CLEMENT <gregory.clement@bootlin.com>
 M:	Lars Povlsen <lars.povlsen@microchip.com>
 M:	Horatiu Vultur <horatiu.vultur@microchip.com>
 S:	Maintained
 F:	arch/mips/mach-mscc/
 F:	arch/mips/dts/luton*
 F:	arch/mips/dts/mscc*
 F:	arch/mips/dts/ocelot*
 F:	arch/mips/dts/jr2*
 F:	arch/mips/dts/serval*
 F:	board/mscc/
 F:	configs/mscc*
 F:	drivers/gpio/mscc_sgpio.c
 F:	drivers/spi/mscc_bb_spi.c
 F:	include/configs/vcoreiii.h
 F:	include/dt-bindings/mscc/
 F:	drivers/pinctrl/mscc/
 F:	drivers/net/mscc_eswitch/
 MIPS JZ4780
 M:	Ezequiel Garcia <ezequiel@collabora.com>
 S:	Maintained
 F:	arch/mips/mach-jz47xx/
 MMC
 M:	Peng Fan <peng.fan@nxp.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-mmc.git
 F:	drivers/mmc/
 NAND FLASH
 #M:	Scott Wood <oss@buserror.net>
 S:	Orphaned (Since 2018-07)
 T:	git git://git.denx.de/u-boot-nand-flash.git
 F:	drivers/mtd/nand/raw/
 NDS32
 M:	Macpaul Lin <macpaul@andestech.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-nds32.git
 F:	arch/nds32/
 NETWORK
 M:	Joe Hershberger <joe.hershberger@ni.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-net.git
 F:	drivers/net/
 F:	net/
 NIOS
 M:	Thomas Chou <thomas@wytron.com.tw>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-nios.git
 F:	arch/nios2/
 ONENAND
 #M:	Lukasz Majewski <l.majewski@majess.pl>
 S:	Orphaned (Since 2017-01)
 T:	git git://git.denx.de/u-boot-onenand.git
 F:	drivers/mtd/onenand/
 PATMAN
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
 F:	tools/patman/
 POWER
 M:	Jaehoon Chung <jh80.chung@samsung.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-pmic.git
 F:	drivers/power/
 POWERPC
 M:	Wolfgang Denk <wd@denx.de>
 S:	Maintained
 F:	arch/powerpc/
 POWERPC MPC8XX
 M:	Christophe Leroy <christophe.leroy@c-s.fr>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-mpc8xx.git
 F:	arch/powerpc/cpu/mpc8xx/
 POWERPC MPC83XX
 M:	Mario Six <mario.six@gdsys.cc>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-mpc83xx.git
 F:	drivers/ram/mpc83xx_sdram.c
 F:	include/dt-bindings/memory/mpc83xx-sdram.h
 F:	drivers/sysreset/sysreset_mpc83xx.c
 F:	drivers/sysreset/sysreset_mpc83xx.h
 F:	drivers/clk/mpc83xx_clk.c
 F:	drivers/clk/mpc83xx_clk.h
 F:	include/dt-bindings/clk/mpc83xx-clk.h
 F:	drivers/timer/mpc83xx_timer.c
 F:	drivers/cpu/mpc83xx_cpu.c
 F:	drivers/cpu/mpc83xx_cpu.h
 F:	drivers/misc/mpc83xx_serdes.c
 F:	arch/powerpc/cpu/mpc83xx/
 F:	arch/powerpc/include/asm/arch-mpc83xx/
 POWERPC MPC85XX
 M:	Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-mpc85xx.git
 F:	arch/powerpc/cpu/mpc85xx/
 POWERPC MPC86XX
 M:	Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-mpc86xx.git
 F:	arch/powerpc/cpu/mpc86xx/
 RISC-V
 M:	Rick Chen <rick@andestech.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-riscv.git
 F:	arch/riscv/
 F:	cmd/riscv/
 F:	tools/prelink-riscv.c
 ROCKUSB
 M:	Eddie Cai <eddie.cai.linux@gmail.com>
 S:	Maintained
 F:	drivers/usb/gadget/f_rockusb.c
 F:	cmd/rockusb.c
 F:	doc/README.rockusb
 SANDBOX
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
 F:	arch/sandbox/
 SH
 M:	Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-sh.git
 F:	arch/sh/
 SPI
 M:	Jagan Teki <jagan@amarulasolutions.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-spi.git
 F:	drivers/spi/
 F:	include/spi*
 SPI-NOR
 M:	Jagan Teki <jagan@amarulasolutions.com>
 M:	Vignesh R <vigneshr@ti.com>
 S:	Maintained
 F:	drivers/mtd/spi/
 F:	include/spi_flash.h
 F:	include/linux/mtd/cfi.h
 F:	include/linux/mtd/spi-nor.h
 SPMI
 M:	Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
 S:	Maintained
 F:	drivers/spmi/
 F:	include/spmi/
 TDA19988 HDMI ENCODER
 M:	Liviu Dudau <liviu.dudau@foss.arm.com>
 S:	Maintained
 F:	drivers/video/tda19988.c
 TI SYSTEM SECURITY
 M:	Andrew F. Davis <afd@ti.com>
 S:	Supported
 F:	arch/arm/mach-omap2/omap5/sec_entry_cpu1.S
 F:	arch/arm/mach-omap2/sec-common.c
 F:	arch/arm/mach-omap2/config_secure.mk
 F:	arch/arm/mach-k3/security.c
 F:	arch/arm/mach-k3/config_secure.mk
 F:	configs/am335x_hs_evm_defconfig
 F:	configs/am335x_hs_evm_uart_defconfig
 F:	configs/am43xx_hs_evm_defconfig
 F:	configs/am57xx_hs_evm_defconfig
 F:	configs/am57xx_hs_evm_usb_defconfig
 F:	configs/dra7xx_hs_evm_defconfig
 F:	configs/dra7xx_hs_evm_usb_defconfig
 F:	configs/k2hk_hs_evm_defconfig
 F:	configs/k2e_hs_evm_defconfig
 F:	configs/k2g_hs_evm_defconfig
 F:	configs/k2l_hs_evm_defconfig
 F:	configs/am65x_hs_evm_r5_defconfig
 F:	configs/am65x_hs_evm_a53_defconfig
 TQ GROUP
 #M:	Martin Krause <martin.krause@tq-systems.de>
 S:	Orphaned (Since 2016-02)
 T:	git git://git.denx.de/u-boot-tq-group.git
 TEE
 M:	Jens Wiklander <jens.wiklander@linaro.org>
 S:	Maintained
 F:	drivers/tee/
 F:	include/tee.h
 F:	include/tee/
 UBI
 M:	Kyungmin Park <kmpark@infradead.org>
 M:	Heiko Schocher <hs@denx.de>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-ubi.git
 F:	drivers/mtd/ubi/
 USB
 M:	Marek Vasut <marex@denx.de>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-usb.git
 F:	drivers/usb/
 USB xHCI
 M:	Bin Meng <bmeng.cn@gmail.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-usb.git topic-xhci
 F:	drivers/usb/host/xhci*
 VIDEO
 M:	Anatolij Gustschin <agust@denx.de>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-video.git
 F:	drivers/video/
 F:	common/lcd*.c
 F:	include/lcd*.h
 F:	include/video*.h
 X86
 M:	Simon Glass <sjg@chromium.org>
 M:	Bin Meng <bmeng.cn@gmail.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-x86.git
 F:	arch/x86/
 F:	cmd/x86/
 XTENSA
 M:	Max Filippov <jcmvbkbc@gmail.com>
 S:	Maintained
 F:	arch/xtensa/
 THE REST
 M:	Tom Rini <trini@konsulko.com>
 L:	u-boot@lists.denx.de
 Q:	http://patchwork.ozlabs.org/project/uboot/list/
 S:	Maintained
 T:	git git://git.denx.de/u-boot.git
 F:	configs/tools-only_defconfig
 F:	*
 F:	*/

drivers/spi/Kconfig

Diff comments View file @ a2a89b2

 menuconfig SPI
 	bool "SPI Support"
 if SPI
 config DM_SPI
 	bool "Enable Driver Model for SPI drivers"
 	depends on DM
 	help
 	  Enable driver model for SPI. The SPI slave interface
 	  (spi_setup_slave(), spi_xfer(), etc.) is then implemented by
 	  the SPI uclass. Drivers provide methods to access the SPI
 	  buses that they control. The uclass interface is defined in
 	  include/spi.h. The existing spi_slave structure is attached
 	  as 'parent data' to every slave on each bus. Slaves
 	  typically use driver-private data instead of extending the
 	  spi_slave structure.
 config SPI_MEM
 	bool "SPI memory extension"
 	help
 	  Enable this option if you want to enable the SPI memory extension.
 	  This extension is meant to simplify interaction with SPI memories
 	  by providing an high-level interface to send memory-like commands.
 if DM_SPI
 config ALTERA_SPI
 	bool "Altera SPI driver"
 	help
 	  Enable the Altera SPI driver. This driver can be used to
 	  access the SPI NOR flash on platforms embedding this Altera
 	  IP core. Please find details on the "Embedded Peripherals IP
 	  User Guide" of Altera.
 config ATCSPI200_SPI
 	bool "Andestech ATCSPI200 SPI driver"
 	help
 	  Enable the Andestech ATCSPI200 SPI driver. This driver can be
 	  used to access the SPI flash on AE3XX and AE250 platforms embedding
 	  this Andestech IP core.
 config ATH79_SPI
 	bool "Atheros SPI driver"
 	depends on ARCH_ATH79
 	help
 	  Enable the Atheros ar7xxx/ar9xxx SoC SPI driver, it was used
 	  to access SPI NOR flash and other SPI peripherals. This driver
 	  uses driver model and requires a device tree binding to operate.
 	  please refer to doc/device-tree-bindings/spi/spi-ath79.txt.
 config ATMEL_SPI
 	bool "Atmel SPI driver"
 	default y if ARCH_AT91
 	help
 	  This enables driver for the Atmel SPI Controller, present on
 	  many AT91 (ARM) chips. This driver can be used to access
 	  the SPI Flash, such as AT25DF321.
 config BCM63XX_HSSPI
 	bool "BCM63XX HSSPI driver"
 	depends on ARCH_BMIPS
 	help
 	  Enable the BCM6328 HSSPI driver. This driver can be used to
 	  access the SPI NOR flash on platforms embedding this Broadcom
 	  SPI core.
 config BCM63XX_SPI
 	bool "BCM6348 SPI driver"
 	depends on ARCH_BMIPS
 	help
 	  Enable the BCM6348/BCM6358 SPI driver. This driver can be used to
 	  access the SPI NOR flash on platforms embedding these Broadcom
 	  SPI cores.
 config BCMSTB_SPI
 	bool "BCMSTB SPI driver"
 	help
 	  Enable the Broadcom set-top box SPI driver. This driver can
 	  be used to access the SPI flash on platforms embedding this
 	  Broadcom SPI core.
 config CADENCE_QSPI
 	bool "Cadence QSPI driver"
 	help
 	  Enable the Cadence Quad-SPI (QSPI) driver. This driver can be
 	  used to access the SPI NOR flash on platforms embedding this
 	  Cadence IP core.
 config CF_SPI
         bool "ColdFire SPI driver"
         help
           Enable the ColdFire SPI driver. This driver can be used on
           some m68k SoCs.
 config DESIGNWARE_SPI
 	bool "Designware SPI driver"
 	help
 	  Enable the Designware SPI driver. This driver can be used to
 	  access the SPI NOR flash on platforms embedding this Designware
 	  IP core.
 config EXYNOS_SPI
 	bool "Samsung Exynos SPI driver"
 	help
 	  Enable the Samsung Exynos SPI driver. This driver can be used to
 	  access the SPI NOR flash on platforms embedding this Samsung
 	  Exynos IP core.
 config FSL_DSPI
 	bool "Freescale DSPI driver"
 	help
 	  Enable the Freescale DSPI driver. This driver can be used to
 	  access the SPI NOR flash and SPI Data flash on platforms embedding
 	  this Freescale DSPI IP core. LS102xA and Colibri VF50/VF61 platforms
 	  use this driver.
 config ICH_SPI
 	bool "Intel ICH SPI driver"
 	imply SPI_FLASH_BAR
 	help
 	  Enable the Intel ICH SPI driver. This driver can be used to
 	  access the SPI NOR flash on platforms embedding this Intel
 	  ICH IP core.
 config MESON_SPIFC
 	bool "Amlogic Meson SPI Flash Controller driver"
 	depends on ARCH_MESON
 	help
 	  Enable the Amlogic Meson SPI Flash Controller SPIFC) driver.
 	  This driver can be used to access the SPI NOR flash chips on
 	  Amlogic Meson SoCs.
 config MPC8XX_SPI
 	bool "MPC8XX SPI Driver"
 	depends on MPC8xx
 	help
 	  Enable support for SPI on MPC8XX
 config MT7621_SPI
 	bool "MediaTek MT7621 SPI driver"
 	depends on SOC_MT7628
 	help
 	  Enable the MT7621 SPI driver. This driver can be used to access
 	  the SPI NOR flash on platforms embedding this Ralink / MediaTek
 	  SPI core, like MT7621/7628/7688.
 config MTK_QSPI
 	bool "Mediatek QSPI driver"
 	imply SPI_FLASH_BAR
 	help
 	  Enable the Mediatek QSPI driver. This driver can be
 	  used to access the SPI NOR flash on platforms embedding this
 	  Mediatek QSPI IP core.
 config MVEBU_A3700_SPI
 	bool "Marvell Armada 3700 SPI driver"
 	select CLK_ARMADA_3720
 	help
 	  Enable the Marvell Armada 3700 SPI driver. This driver can be
 	  used to access the SPI NOR flash on platforms embedding this
 	  Marvell IP core.
 config PIC32_SPI
 	bool "Microchip PIC32 SPI driver"
 	depends on MACH_PIC32
 	help
 	  Enable the Microchip PIC32 SPI driver. This driver can be used
 	  to access the SPI NOR flash, MMC-over-SPI on platforms based on
 	  Microchip PIC32 family devices.
 config PL022_SPI
 	bool "ARM AMBA PL022 SSP controller driver"
 	depends on ARM
 	help
 	  This selects the ARM(R) AMBA(R) PrimeCell PL022 SSP
 	  controller. If you have an embedded system with an AMBA(R)
 	  bus and a PL022 controller, say Y or M here.
 config RENESAS_RPC_SPI
 	bool "Renesas RPC SPI driver"
 	depends on RCAR_GEN3 || RZA1
 	imply SPI_FLASH_BAR
 	help
 	  Enable the Renesas RPC SPI driver, used to access SPI NOR flash
 	  on Renesas RCar Gen3 SoCs. This uses driver model and requires a
 	  device tree binding to operate.
 config ROCKCHIP_SPI
 	bool "Rockchip SPI driver"
 	help
 	  Enable the Rockchip SPI driver, used to access SPI NOR flash and
 	  other SPI peripherals (such as the Chrome OS EC) on Rockchip SoCs.
 	  This uses driver model and requires a device tree binding to
 	  operate.
 config SANDBOX_SPI
 	bool "Sandbox SPI driver"
 	depends on SANDBOX && DM
 	help
 	  Enable SPI support for sandbox. This is an emulation of a real SPI
 	  bus. Devices can be attached to the bus using the device tree
 	  which specifies the driver to use. As an example, see this device
 	  tree fragment from sandbox.dts. It shows that the SPI bus has a
 	  single flash device on chip select 0 which is emulated by the driver
 	  for "sandbox,spi-flash", which is in drivers/mtd/spi/sandbox.c.
 	  spi@0 {
 		#address-cells = <1>;
 		#size-cells = <0>;
 		reg = <0>;
 		compatible = "sandbox,spi";
 		cs-gpios = <0>, <&gpio_a 0>;
 		flash@0 {
 			reg = <0>;
 			compatible = "spansion,m25p16", "sandbox,spi-flash";
 			spi-max-frequency = <40000000>;
 			sandbox,filename = "spi.bin";
 		};
 	  };
 config SPI_SUNXI
 	bool "Allwinner SoC SPI controllers"
 	help
 	  Enable the Allwinner SoC SPi controller driver.
 	  Same controller driver can reuse in all Allwinner SoC variants.
 config STM32_QSPI
 	bool "STM32F7 QSPI driver"
 	depends on STM32F4 || STM32F7 || ARCH_STM32MP
 	help
 	  Enable the STM32F7 Quad-SPI (QSPI) driver. This driver can be
 	  used to access the SPI NOR flash chips on platforms embedding
 	  this ST IP core.
+config STM32_SPI
+	bool "STM32 SPI driver"
+	depends on ARCH_STM32MP
+	help
+	  Enable the STM32 Serial Peripheral Interface (SPI) driver for STM32MP
+	  SoCs. This uses driver model and requires a device tree binding to
+	  operate.
 config TEGRA114_SPI
 	bool "nVidia Tegra114 SPI driver"
 	help
 	  Enable the nVidia Tegra114 SPI driver. This driver can be used to
 	  access the SPI NOR flash on platforms embedding this nVidia Tegra114
 	  IP core.
 	  This controller is different than the older SoCs SPI controller and
 	  also register interface get changed with this controller.
 config TEGRA20_SFLASH
 	bool "nVidia Tegra20 Serial Flash controller driver"
 	help
 	  Enable the nVidia Tegra20 Serial Flash controller driver. This driver
 	  can be used to access the SPI NOR flash on platforms embedding this
 	  nVidia Tegra20 IP core.
 config TEGRA20_SLINK
 	bool "nVidia Tegra20/Tegra30 SLINK driver"
 	help
 	  Enable the nVidia Tegra20/Tegra30 SLINK driver. This driver can
 	  be used to access the SPI NOR flash on platforms embedding this
 	  nVidia Tegra20/Tegra30 IP cores.
 config TEGRA210_QSPI
 	bool "nVidia Tegra210 QSPI driver"
 	help
 	  Enable the Tegra Quad-SPI (QSPI) driver for T210. This driver
 	  be used to access SPI chips on platforms embedding this
 	  NVIDIA Tegra210 IP core.
 config TI_QSPI
 	bool "TI QSPI driver"
 	imply TI_EDMA3
 	help
 	  Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms.
 	  This driver support spi flash single, quad and memory reads.
 config XILINX_SPI
 	bool "Xilinx SPI driver"
 	help
 	  Enable the Xilinx SPI driver from the Xilinx EDK. This SPI
 	  controller support 8 bit SPI transfers only, with or w/o FIFO.
 	  For more info on Xilinx SPI Register Definitions and Overview
 	  see driver file - drivers/spi/xilinx_spi.c
 config ZYNQ_SPI
 	bool "Zynq SPI driver"
 	depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL
 	help
 	  Enable the Zynq SPI driver. This driver can be used to
 	  access the SPI NOR flash on platforms embedding this Zynq
 	  SPI IP core.
 config ZYNQ_QSPI
 	bool "Zynq QSPI driver"
 	depends on ARCH_ZYNQ
 	imply SPI_FLASH_BAR
 	help
 	  Enable the Zynq Quad-SPI (QSPI) driver. This driver can be
 	  used to access the SPI NOR flash on platforms embedding this
 	  Zynq QSPI IP core. This IP is used to connect the flash in
 	  4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel.
 config ZYNQMP_GQSPI
 	bool "Configure ZynqMP Generic QSPI"
 	depends on ARCH_ZYNQMP || ARCH_VERSAL
 	help
 	  This option is used to enable ZynqMP QSPI controller driver which
 	  is used to communicate with qspi flash devices.
 endif # if DM_SPI
 config SOFT_SPI
 	bool "Soft SPI driver"
 	help
 	 Enable Soft SPI driver. This driver is to use GPIO simulate
 	 the SPI protocol.
 config MSCC_BB_SPI
 	bool "MSCC bitbang SPI driver"
 	depends on SOC_VCOREIII
 	help
 	  Enable MSCC bitbang SPI driver. This driver can be used on
 	  MSCC SOCs.
 config CF_SPI
 	bool "ColdFire SPI driver"
 	help
 	  Enable the ColdFire SPI driver. This driver can be used on
 	  some m68k SoCs.
 config FSL_ESPI
 	bool "Freescale eSPI driver"
 	help
 	  Enable the Freescale eSPI driver. This driver can be used to
 	  access the SPI interface and SPI NOR flash on platforms embedding
 	  this Freescale eSPI IP core.
 config FSL_QSPI
 	bool "Freescale QSPI driver"
 	imply SPI_FLASH_BAR
 	help
 	  Enable the Freescale Quad-SPI (QSPI) driver. This driver can be
 	  used to access the SPI NOR flash on platforms embedding this
 	  Freescale IP core.
 config DAVINCI_SPI
 	bool "Davinci & Keystone SPI driver"
 	depends on ARCH_DAVINCI || ARCH_KEYSTONE
 	help
 	  Enable the Davinci SPI driver
 config SH_SPI
 	bool "SuperH SPI driver"
 	help
 	  Enable the SuperH SPI controller driver. This driver can be used
 	  on various SuperH SoCs, such as SH7757.
 config SH_QSPI
 	bool "Renesas Quad SPI driver"
 	help
 	  Enable the Renesas Quad SPI controller driver. This driver can be
 	  used on Renesas SoCs.
 config KIRKWOOD_SPI
 	bool "Marvell Kirkwood SPI Driver"
 	help
 	  Enable support for SPI on various Marvell SoCs, such as
 	  Kirkwood and Armada 375.
 config LPC32XX_SSP
 	bool "LPC32XX SPI Driver"
 	help
 	  Enable support for SPI on LPC32xx
 config MPC8XXX_SPI
 	bool "MPC8XXX SPI Driver"
 	help
 	  Enable support for SPI on the MPC8XXX PowerPC SoCs.
 config MXC_SPI
 	bool "MXC SPI Driver"
 	help
 	  Enable the MXC SPI controller driver. This driver can be used
 	  on various i.MX SoCs such as i.MX31/35/51/6/7.
 config MXS_SPI
 	bool "MXS SPI Driver"
 	help
 	  Enable the MXS SPI controller driver. This driver can be used
 	  on the i.MX23 and i.MX28 SoCs.
 config OMAP3_SPI
 	bool "McSPI driver for OMAP"
 	help
 	  SPI master controller for OMAP24XX and later Multichannel SPI
 	  (McSPI). This driver be used to access SPI chips on platforms
 	  embedding this OMAP3 McSPI IP core.
 endif # menu "SPI Support"

drivers/spi/Makefile

Diff comments View file @ a2a89b2

 # SPDX-License-Identifier: GPL-2.0+
 #
 # (C) Copyright 2000-2007
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 # There are many options which enable SPI, so make this library available
 ifdef CONFIG_DM_SPI
 obj-y += spi-uclass.o
 obj-$(CONFIG_SANDBOX) += spi-emul-uclass.o
 obj-$(CONFIG_SOFT_SPI) += soft_spi.o
 obj-$(CONFIG_SPI_MEM) += spi-mem.o
 obj-$(CONFIG_TI_QSPI) += ti_qspi.o
 else
 obj-y += spi.o
 obj-$(CONFIG_SPI_MEM) += spi-mem-nodm.o
 obj-$(CONFIG_SOFT_SPI) += soft_spi_legacy.o
 endif
 obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
 obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
 obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
 obj-$(CONFIG_BCM63XX_HSSPI) += bcm63xx_hsspi.o
 obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o
 obj-$(CONFIG_BCMSTB_SPI) += bcmstb_spi.o
 obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
 obj-$(CONFIG_CF_SPI) += cf_spi.o
 obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
 obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o
 obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
 obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o
 obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
 obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o
 obj-$(CONFIG_ICH_SPI) +=  ich.o
 obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
 obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o
 obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o
 obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o
 obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
 obj-$(CONFIG_MTK_QSPI) += mtk_qspi.o
 obj-$(CONFIG_MT7621_SPI) += mt7621_spi.o
 obj-$(CONFIG_MSCC_BB_SPI) += mscc_bb_spi.o
 obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
 obj-$(CONFIG_MXC_SPI) += mxc_spi.o
 obj-$(CONFIG_MXS_SPI) += mxs_spi.o
 obj-$(CONFIG_ATCSPI200_SPI) += atcspi200_spi.o
 obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
 obj-$(CONFIG_PIC32_SPI) += pic32_spi.o
 obj-$(CONFIG_PL022_SPI) += pl022_spi.o
 obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o
 obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o
 obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
 obj-$(CONFIG_SPI_SUNXI) += spi-sunxi.o
 obj-$(CONFIG_SH_SPI) += sh_spi.o
 obj-$(CONFIG_SH_QSPI) += sh_qspi.o
 obj-$(CONFIG_STM32_QSPI) += stm32_qspi.o
+obj-$(CONFIG_STM32_SPI) += stm32_spi.o
 obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
 obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
 obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
 obj-$(CONFIG_TEGRA210_QSPI) += tegra210_qspi.o
 obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
 obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
 obj-$(CONFIG_ZYNQ_QSPI) += zynq_qspi.o
 obj-$(CONFIG_ZYNQMP_GQSPI) += zynqmp_gqspi.o

drivers/spi/stm32_spi.c

Diff comments View file @ a2a89b2

File was created	1	// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
	2	/*
	3	* Copyright (C) 2019, STMicroelectronics - All Rights Reserved
	4	*
	5	* Driver for STMicroelectronics Serial peripheral interface (SPI)
	6	*/
	7	#include <common.h>
	8	#include <clk.h>
	9	#include <dm.h>
	10	#include <errno.h>
	11	#include <reset.h>
	12	#include <spi.h>
	13
	14	#include <asm/io.h>
	15	#include <asm/gpio.h>
	16	#include <linux/bitfield.h>
	17	#include <linux/iopoll.h>
	18
	19	/* STM32 SPI registers */
	20	#define STM32_SPI_CR1 0x00
	21	#define STM32_SPI_CR2 0x04
	22	#define STM32_SPI_CFG1 0x08
	23	#define STM32_SPI_CFG2 0x0C
	24	#define STM32_SPI_SR 0x14
	25	#define STM32_SPI_IFCR 0x18
	26	#define STM32_SPI_TXDR 0x20
	27	#define STM32_SPI_RXDR 0x30
	28	#define STM32_SPI_I2SCFGR 0x50
	29
	30	/* STM32_SPI_CR1 bit fields */
	31	#define SPI_CR1_SPE BIT(0)
	32	#define SPI_CR1_MASRX BIT(8)
	33	#define SPI_CR1_CSTART BIT(9)
	34	#define SPI_CR1_CSUSP BIT(10)
	35	#define SPI_CR1_HDDIR BIT(11)
	36	#define SPI_CR1_SSI BIT(12)
	37
	38	/* STM32_SPI_CR2 bit fields */
	39	#define SPI_CR2_TSIZE GENMASK(15, 0)
	40
	41	/* STM32_SPI_CFG1 bit fields */
	42	#define SPI_CFG1_DSIZE GENMASK(4, 0)
	43	#define SPI_CFG1_DSIZE_MIN 3
	44	#define SPI_CFG1_FTHLV_SHIFT 5
	45	#define SPI_CFG1_FTHLV GENMASK(8, 5)
	46	#define SPI_CFG1_MBR_SHIFT 28
	47	#define SPI_CFG1_MBR GENMASK(30, 28)
	48	#define SPI_CFG1_MBR_MIN 0
	49	#define SPI_CFG1_MBR_MAX FIELD_GET(SPI_CFG1_MBR, SPI_CFG1_MBR)
	50
	51	/* STM32_SPI_CFG2 bit fields */
	52	#define SPI_CFG2_COMM_SHIFT 17
	53	#define SPI_CFG2_COMM GENMASK(18, 17)
	54	#define SPI_CFG2_MASTER BIT(22)
	55	#define SPI_CFG2_LSBFRST BIT(23)
	56	#define SPI_CFG2_CPHA BIT(24)
	57	#define SPI_CFG2_CPOL BIT(25)
	58	#define SPI_CFG2_SSM BIT(26)
	59	#define SPI_CFG2_AFCNTR BIT(31)
	60
	61	/* STM32_SPI_SR bit fields */
	62	#define SPI_SR_RXP BIT(0)
	63	#define SPI_SR_TXP BIT(1)
	64	#define SPI_SR_EOT BIT(3)
	65	#define SPI_SR_TXTF BIT(4)
	66	#define SPI_SR_OVR BIT(6)
	67	#define SPI_SR_SUSP BIT(11)
	68	#define SPI_SR_RXPLVL_SHIFT 13
	69	#define SPI_SR_RXPLVL GENMASK(14, 13)
	70	#define SPI_SR_RXWNE BIT(15)
	71
	72	/* STM32_SPI_IFCR bit fields */
	73	#define SPI_IFCR_ALL GENMASK(11, 3)
	74
	75	/* STM32_SPI_I2SCFGR bit fields */
	76	#define SPI_I2SCFGR_I2SMOD BIT(0)
	77
	78	#define MAX_CS_COUNT 4
	79
	80	/* SPI Master Baud Rate min/max divisor */
	81	#define STM32_MBR_DIV_MIN (2 << SPI_CFG1_MBR_MIN)
	82	#define STM32_MBR_DIV_MAX (2 << SPI_CFG1_MBR_MAX)
	83
	84	#define STM32_SPI_TIMEOUT_US 100000
	85
	86	/* SPI Communication mode */
	87	#define SPI_FULL_DUPLEX 0
	88	#define SPI_SIMPLEX_TX 1
	89	#define SPI_SIMPLEX_RX 2
	90	#define SPI_HALF_DUPLEX 3
	91
	92	struct stm32_spi_priv {
	93	void __iomem *base;
	94	struct clk clk;
	95	struct reset_ctl rst_ctl;
	96	struct gpio_desc cs_gpios[MAX_CS_COUNT];
	97	ulong bus_clk_rate;
	98	unsigned int fifo_size;
	99	unsigned int cur_bpw;
	100	unsigned int cur_hz;
	101	unsigned int cur_xferlen; /* current transfer length in bytes */
	102	int tx_len; /* number of data to be written in bytes */
	103	int rx_len; /* number of data to be read in bytes */
	104	const void tx_buf; / data to be written, or NULL */
	105	void rx_buf; / data to be read, or NULL */
	106	u32 cur_mode;
	107	bool cs_high;
	108	};
	109
	110	static void stm32_spi_write_txfifo(struct stm32_spi_priv *priv)
	111	{
	112	while ((priv->tx_len > 0) &&
	113	(readl(priv->base + STM32_SPI_SR) & SPI_SR_TXP)) {
	114	u32 offs = priv->cur_xferlen - priv->tx_len;
	115
	116	if (priv->tx_len >= sizeof(u32) &&
	117	IS_ALIGNED((uintptr_t)(priv->tx_buf + offs), sizeof(u32))) {
	118	const u32 tx_buf32 = (const u32 )(priv->tx_buf + offs);
	119
	120	writel(*tx_buf32, priv->base + STM32_SPI_TXDR);
	121	priv->tx_len -= sizeof(u32);
	122	} else if (priv->tx_len >= sizeof(u16) &&
	123	IS_ALIGNED((uintptr_t)(priv->tx_buf + offs), sizeof(u16))) {
	124	const u16 tx_buf16 = (const u16 )(priv->tx_buf + offs);
	125
	126	writew(*tx_buf16, priv->base + STM32_SPI_TXDR);
	127	priv->tx_len -= sizeof(u16);
	128	} else {
	129	const u8 tx_buf8 = (const u8 )(priv->tx_buf + offs);
	130
	131	writeb(*tx_buf8, priv->base + STM32_SPI_TXDR);
	132	priv->tx_len -= sizeof(u8);
	133	}
	134	}
	135
	136	debug("%s: %d bytes left\n", __func__, priv->tx_len);
	137	}
	138
	139	static void stm32_spi_read_rxfifo(struct stm32_spi_priv *priv)
	140	{
	141	u32 sr = readl(priv->base + STM32_SPI_SR);
	142	u32 rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
	143
	144	while ((priv->rx_len > 0) &&
	145	((sr & SPI_SR_RXP) \|\|
	146	((sr & SPI_SR_EOT) && ((sr & SPI_SR_RXWNE) \|\| (rxplvl > 0))))) {
	147	u32 offs = priv->cur_xferlen - priv->rx_len;
	148
	149	if (IS_ALIGNED((uintptr_t)(priv->rx_buf + offs), sizeof(u32)) &&
	150	(priv->rx_len >= sizeof(u32) \|\| (sr & SPI_SR_RXWNE))) {
	151	u32 rx_buf32 = (u32 )(priv->rx_buf + offs);
	152
	153	*rx_buf32 = readl(priv->base + STM32_SPI_RXDR);
	154	priv->rx_len -= sizeof(u32);
	155	} else if (IS_ALIGNED((uintptr_t)(priv->rx_buf + offs), sizeof(u16)) &&
	156	(priv->rx_len >= sizeof(u16) \|\|
	157	(!(sr & SPI_SR_RXWNE) &&
	158	(rxplvl >= 2 \|\| priv->cur_bpw > 8)))) {
	159	u16 rx_buf16 = (u16 )(priv->rx_buf + offs);
	160
	161	*rx_buf16 = readw(priv->base + STM32_SPI_RXDR);
	162	priv->rx_len -= sizeof(u16);
	163	} else {
	164	u8 rx_buf8 = (u8 )(priv->rx_buf + offs);
	165
	166	*rx_buf8 = readb(priv->base + STM32_SPI_RXDR);
	167	priv->rx_len -= sizeof(u8);
	168	}
	169
	170	sr = readl(priv->base + STM32_SPI_SR);
	171	rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
	172	}
	173
	174	debug("%s: %d bytes left\n", __func__, priv->rx_len);
	175	}
	176
	177	static int stm32_spi_enable(struct stm32_spi_priv *priv)
	178	{
	179	debug("%s\n", __func__);
	180
	181	/* Enable the SPI hardware */
	182	setbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE);
	183
	184	return 0;
	185	}
	186
	187	static int stm32_spi_disable(struct stm32_spi_priv *priv)
	188	{
	189	debug("%s\n", __func__);
	190
	191	/* Disable the SPI hardware */
	192	clrbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE);
	193
	194	return 0;
	195	}
	196
	197	static int stm32_spi_claim_bus(struct udevice *slave)
	198	{
	199	struct udevice *bus = dev_get_parent(slave);
	200	struct stm32_spi_priv *priv = dev_get_priv(bus);
	201
	202	debug("%s\n", __func__);
	203
	204	/* Enable the SPI hardware */
	205	return stm32_spi_enable(priv);
	206	}
	207
	208	static int stm32_spi_release_bus(struct udevice *slave)
	209	{
	210	struct udevice *bus = dev_get_parent(slave);
	211	struct stm32_spi_priv *priv = dev_get_priv(bus);
	212
	213	debug("%s\n", __func__);
	214
	215	/* Disable the SPI hardware */
	216	return stm32_spi_disable(priv);
	217	}
	218
	219	static void stm32_spi_stopxfer(struct udevice *dev)
	220	{
	221	struct stm32_spi_priv *priv = dev_get_priv(dev);
	222	u32 cr1, sr;
	223	int ret;
	224
	225	debug("%s\n", __func__);
	226
	227	cr1 = readl(priv->base + STM32_SPI_CR1);
	228
	229	if (!(cr1 & SPI_CR1_SPE))
	230	return;
	231
	232	/* Wait on EOT or suspend the flow */
	233	ret = readl_poll_timeout(priv->base + STM32_SPI_SR, sr,
	234	!(sr & SPI_SR_EOT), 100000);
	235	if (ret < 0) {
	236	if (cr1 & SPI_CR1_CSTART) {
	237	writel(cr1 \| SPI_CR1_CSUSP, priv->base + STM32_SPI_CR1);
	238	if (readl_poll_timeout(priv->base + STM32_SPI_SR,
	239	sr, !(sr & SPI_SR_SUSP),
	240	100000) < 0)
	241	dev_err(dev, "Suspend request timeout\n");
	242	}
	243	}
	244
	245	/* clear status flags */
	246	setbits_le32(priv->base + STM32_SPI_IFCR, SPI_IFCR_ALL);
	247	}
	248
	249	static int stm32_spi_set_cs(struct udevice *dev, unsigned int cs, bool enable)
	250	{
	251	struct stm32_spi_priv *priv = dev_get_priv(dev);
	252
	253	debug("%s: cs=%d enable=%d\n", __func__, cs, enable);
	254
	255	if (cs >= MAX_CS_COUNT)
	256	return -ENODEV;
	257
	258	if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
	259	return -EINVAL;
	260
	261	if (priv->cs_high)
	262	enable = !enable;
	263
	264	return dm_gpio_set_value(&priv->cs_gpios[cs], enable ? 1 : 0);
	265	}
	266
	267	static int stm32_spi_set_mode(struct udevice *bus, uint mode)
	268	{
	269	struct stm32_spi_priv *priv = dev_get_priv(bus);
	270	u32 cfg2_clrb = 0, cfg2_setb = 0;
	271
	272	debug("%s: mode=%d\n", __func__, mode);
	273
	274	if (mode & SPI_CPOL)
	275	cfg2_setb \|= SPI_CFG2_CPOL;
	276	else
	277	cfg2_clrb \|= SPI_CFG2_CPOL;
	278
	279	if (mode & SPI_CPHA)
	280	cfg2_setb \|= SPI_CFG2_CPHA;
	281	else
	282	cfg2_clrb \|= SPI_CFG2_CPHA;
	283
	284	if (mode & SPI_LSB_FIRST)
	285	cfg2_setb \|= SPI_CFG2_LSBFRST;
	286	else
	287	cfg2_clrb \|= SPI_CFG2_LSBFRST;
	288
	289	if (cfg2_clrb \|\| cfg2_setb)
	290	clrsetbits_le32(priv->base + STM32_SPI_CFG2,
	291	cfg2_clrb, cfg2_setb);
	292
	293	if (mode & SPI_CS_HIGH)
	294	priv->cs_high = true;
	295	else
	296	priv->cs_high = false;
	297	return 0;
	298	}
	299
	300	static int stm32_spi_set_fthlv(struct udevice *dev, u32 xfer_len)
	301	{
	302	struct stm32_spi_priv *priv = dev_get_priv(dev);
	303	u32 fthlv, half_fifo;
	304
	305	/* data packet should not exceed 1/2 of fifo space */
	306	half_fifo = (priv->fifo_size / 2);
	307
	308	/* data_packet should not exceed transfer length */
	309	fthlv = (half_fifo > xfer_len) ? xfer_len : half_fifo;
	310
	311	/* align packet size with data registers access */
	312	fthlv -= (fthlv % 4);
	313
	314	if (!fthlv)
	315	fthlv = 1;
	316	clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_FTHLV,
	317	(fthlv - 1) << SPI_CFG1_FTHLV_SHIFT);
	318
	319	return 0;
	320	}
	321
	322	static int stm32_spi_set_speed(struct udevice *bus, uint hz)
	323	{
	324	struct stm32_spi_priv *priv = dev_get_priv(bus);
	325	u32 div, mbrdiv;
	326
	327	debug("%s: hz=%d\n", __func__, hz);
	328
	329	if (priv->cur_hz == hz)
	330	return 0;
	331
	332	div = DIV_ROUND_UP(priv->bus_clk_rate, hz);
	333
	334	if (div < STM32_MBR_DIV_MIN \|\|
	335	div > STM32_MBR_DIV_MAX)
	336	return -EINVAL;
	337
	338	/* Determine the first power of 2 greater than or equal to div */
	339	if (div & (div - 1))
	340	mbrdiv = fls(div);
	341	else
	342	mbrdiv = fls(div) - 1;
	343
	344	if ((mbrdiv - 1) < 0)
	345	return -EINVAL;
	346
	347	clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_MBR,
	348	(mbrdiv - 1) << SPI_CFG1_MBR_SHIFT);
	349
	350	priv->cur_hz = hz;
	351
	352	return 0;
	353	}
	354
	355	static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen,
	356	const void dout, void din, unsigned long flags)
	357	{
	358	struct udevice *bus = dev_get_parent(slave);
	359	struct dm_spi_slave_platdata *slave_plat;
	360	struct stm32_spi_priv *priv = dev_get_priv(bus);
	361	u32 sr;
	362	u32 ifcr = 0;
	363	u32 xferlen;
	364	u32 mode;
	365	int xfer_status = 0;
	366
	367	xferlen = bitlen / 8;
	368
	369	if (xferlen <= SPI_CR2_TSIZE)
	370	writel(xferlen, priv->base + STM32_SPI_CR2);
	371	else
	372	return -EMSGSIZE;
	373
	374	priv->tx_buf = dout;
	375	priv->rx_buf = din;
	376	priv->tx_len = priv->tx_buf ? bitlen / 8 : 0;
	377	priv->rx_len = priv->rx_buf ? bitlen / 8 : 0;
	378
	379	mode = SPI_FULL_DUPLEX;
	380	if (!priv->tx_buf)
	381	mode = SPI_SIMPLEX_RX;
	382	else if (!priv->rx_buf)
	383	mode = SPI_SIMPLEX_TX;
	384
	385	if (priv->cur_xferlen != xferlen \|\| priv->cur_mode != mode) {
	386	priv->cur_mode = mode;
	387	priv->cur_xferlen = xferlen;
	388
	389	/* Disable the SPI hardware to unlock CFG1/CFG2 registers */
	390	stm32_spi_disable(priv);
	391
	392	clrsetbits_le32(priv->base + STM32_SPI_CFG2, SPI_CFG2_COMM,
	393	mode << SPI_CFG2_COMM_SHIFT);
	394
	395	stm32_spi_set_fthlv(bus, xferlen);
	396
	397	/* Enable the SPI hardware */
	398	stm32_spi_enable(priv);
	399	}
	400
	401	debug("%s: priv->tx_len=%d priv->rx_len=%d\n", __func__,
	402	priv->tx_len, priv->rx_len);
	403
	404	slave_plat = dev_get_parent_platdata(slave);
	405	if (flags & SPI_XFER_BEGIN)
	406	stm32_spi_set_cs(bus, slave_plat->cs, false);
	407
	408	/* Be sure to have data in fifo before starting data transfer */
	409	if (priv->tx_buf)
	410	stm32_spi_write_txfifo(priv);
	411
	412	setbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_CSTART);
	413
	414	while (1) {
	415	sr = readl(priv->base + STM32_SPI_SR);
	416
	417	if (sr & SPI_SR_OVR) {
	418	dev_err(bus, "Overrun: RX data lost\n");
	419	xfer_status = -EIO;
	420	break;
	421	}
	422
	423	if (sr & SPI_SR_SUSP) {
	424	dev_warn(bus, "System too slow is limiting data throughput\n");
	425
	426	if (priv->rx_buf && priv->rx_len > 0)
	427	stm32_spi_read_rxfifo(priv);
	428
	429	ifcr \|= SPI_SR_SUSP;
	430	}
	431
	432	if (sr & SPI_SR_TXTF)
	433	ifcr \|= SPI_SR_TXTF;
	434
	435	if (sr & SPI_SR_TXP)
	436	if (priv->tx_buf && priv->tx_len > 0)
	437	stm32_spi_write_txfifo(priv);
	438
	439	if (sr & SPI_SR_RXP)
	440	if (priv->rx_buf && priv->rx_len > 0)
	441	stm32_spi_read_rxfifo(priv);
	442
	443	if (sr & SPI_SR_EOT) {
	444	if (priv->rx_buf && priv->rx_len > 0)
	445	stm32_spi_read_rxfifo(priv);
	446	break;
	447	}
	448
	449	writel(ifcr, priv->base + STM32_SPI_IFCR);
	450	}
	451
	452	/* clear status flags */
	453	setbits_le32(priv->base + STM32_SPI_IFCR, SPI_IFCR_ALL);
	454	stm32_spi_stopxfer(bus);
	455
	456	if (flags & SPI_XFER_END)
	457	stm32_spi_set_cs(bus, slave_plat->cs, true);
	458
	459	return xfer_status;
	460	}
	461
	462	static int stm32_spi_get_fifo_size(struct udevice *dev)
	463	{
	464	struct stm32_spi_priv *priv = dev_get_priv(dev);
	465	u32 count = 0;
	466
	467	stm32_spi_enable(priv);
	468
	469	while (readl(priv->base + STM32_SPI_SR) & SPI_SR_TXP)
	470	writeb(++count, priv->base + STM32_SPI_TXDR);
	471
	472	stm32_spi_disable(priv);
	473
	474	debug("%s %d x 8-bit fifo size\n", __func__, count);
	475
	476	return count;
	477	}
	478
	479	static int stm32_spi_probe(struct udevice *dev)
	480	{
	481	struct stm32_spi_priv *priv = dev_get_priv(dev);
	482	unsigned long clk_rate;
	483	int ret;
	484	int i;
	485
	486	priv->base = dev_remap_addr(dev);
	487	if (!priv->base)
	488	return -EINVAL;
	489
	490	/* enable clock */
	491	ret = clk_get_by_index(dev, 0, &priv->clk);
	492	if (ret < 0)
	493	return ret;
	494
	495	ret = clk_enable(&priv->clk);
	496	if (ret < 0)
	497	return ret;
	498
	499	clk_rate = clk_get_rate(&priv->clk);
	500	if (!clk_rate) {
	501	ret = -EINVAL;
	502	goto clk_err;
	503	}
	504
	505	priv->bus_clk_rate = clk_rate;
	506
	507	/* perform reset */
	508	ret = reset_get_by_index(dev, 0, &priv->rst_ctl);
	509	if (ret < 0)
	510	goto clk_err;
	511
	512	reset_assert(&priv->rst_ctl);
	513	udelay(2);
	514	reset_deassert(&priv->rst_ctl);
	515
	516	ret = gpio_request_list_by_name(dev, "cs-gpios", priv->cs_gpios,
	517	ARRAY_SIZE(priv->cs_gpios), 0);
	518	if (ret < 0) {
	519	pr_err("Can't get %s cs gpios: %d", dev->name, ret);
	520	goto reset_err;
	521	}
	522
	523	priv->fifo_size = stm32_spi_get_fifo_size(dev);
	524
	525	priv->cur_mode = SPI_FULL_DUPLEX;
	526	priv->cur_xferlen = 0;
	527	priv->cur_bpw = SPI_DEFAULT_WORDLEN;
	528	clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_DSIZE,
	529	priv->cur_bpw - 1);
	530
	531	for (i = 0; i < ARRAY_SIZE(priv->cs_gpios); i++) {
	532	if (!dm_gpio_is_valid(&priv->cs_gpios[i]))
	533	continue;
	534
	535	dm_gpio_set_dir_flags(&priv->cs_gpios[i],
	536	GPIOD_IS_OUT \| GPIOD_IS_OUT_ACTIVE);
	537	}
	538
	539	/* Ensure I2SMOD bit is kept cleared */
	540	clrbits_le32(priv->base + STM32_SPI_I2SCFGR, SPI_I2SCFGR_I2SMOD);
	541
	542	/*
	543	* - SS input value high
	544	* - transmitter half duplex direction
	545	* - automatic communication suspend when RX-Fifo is full
	546	*/
	547	setbits_le32(priv->base + STM32_SPI_CR1,
	548	SPI_CR1_SSI \| SPI_CR1_HDDIR \| SPI_CR1_MASRX);
	549
	550	/*
	551	* - Set the master mode (default Motorola mode)
	552	* - Consider 1 master/n slaves configuration and
	553	* SS input value is determined by the SSI bit
	554	* - keep control of all associated GPIOs
	555	*/
	556	setbits_le32(priv->base + STM32_SPI_CFG2,
	557	SPI_CFG2_MASTER \| SPI_CFG2_SSM \| SPI_CFG2_AFCNTR);
	558
	559	return 0;
	560
	561	reset_err:
	562	reset_free(&priv->rst_ctl);
	563
	564	clk_err:
	565	clk_disable(&priv->clk);
	566	clk_free(&priv->clk);
	567
	568	return ret;
	569	};
	570
	571	static int stm32_spi_remove(struct udevice *dev)
	572	{
	573	struct stm32_spi_priv *priv = dev_get_priv(dev);
	574	int ret;
	575
	576	stm32_spi_stopxfer(dev);
	577	stm32_spi_disable(priv);
	578
	579	ret = reset_assert(&priv->rst_ctl);
	580	if (ret < 0)
	581	return ret;
	582
	583	reset_free(&priv->rst_ctl);
	584
	585	ret = clk_disable(&priv->clk);
	586	if (ret < 0)
	587	return ret;
	588
	589	clk_free(&priv->clk);
	590
	591	return ret;
	592	};
	593
	594	static const struct dm_spi_ops stm32_spi_ops = {
	595	.claim_bus = stm32_spi_claim_bus,
	596	.release_bus = stm32_spi_release_bus,
	597	.set_mode = stm32_spi_set_mode,
	598	.set_speed = stm32_spi_set_speed,
	599	.xfer = stm32_spi_xfer,
	600	};
	601
	602	static const struct udevice_id stm32_spi_ids[] = {
	603	{ .compatible = "st,stm32h7-spi", },
	604	{ }
	605	};
	606
	607	U_BOOT_DRIVER(stm32_spi) = {
	608	.name = "stm32_spi",
	609	.id = UCLASS_SPI,
	610	.of_match = stm32_spi_ids,
	611	.ops = &stm32_spi_ops,
	612	.priv_auto_alloc_size = sizeof(struct stm32_spi_priv),
	613	.probe = stm32_spi_probe,
	614	.remove = stm32_spi_remove,
	615	};
	616