spi: stm32: Add Serial Peripheral Interface driver for STM32MP

Add SPI driver support for STM32MP SoCs family. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

spi: stm32: Add Serial Peripheral Interface driver for STM32MP
Add SPI driver support for STM32MP SoCs family. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrice Chotard
1 parent 248278d7f7
Showing 4 changed files with 625 additions and 0 deletions Side-by-side Diff
MAINTAINERS
drivers/spi/Kconfig
drivers/spi/Makefile
drivers/spi/stm32_spi.c
@@ -312,6 +312,7 @@
 F:	drivers/misc/stm32_rcc.c
 F:	drivers/reset/stm32-reset.c
 F:	drivers/spi/stm32_qspi.c
+F:	drivers/spi/stm32_spi.c
 F:	drivers/watchdog/stm32mp_wdt.c
  
 ARM STM STV0991
@@ -234,6 +234,14 @@
 	  used to access the SPI NOR flash chips on platforms embedding
 	  this ST IP core.
  
+config STM32_SPI
+	bool "STM32 SPI driver"
+	depends on ARCH_STM32MP
+	help
+	  Enable the STM32 Serial Peripheral Interface (SPI) driver for STM32MP
+	  SoCs. This uses driver model and requires a device tree binding to
+	  operate.
+
 config TEGRA114_SPI
 	bool "nVidia Tegra114 SPI driver"
 	help
@@ -53,6 +53,7 @@
 obj-$(CONFIG_SH_SPI) += sh_spi.o
 obj-$(CONFIG_SH_QSPI) += sh_qspi.o
 obj-$(CONFIG_STM32_QSPI) += stm32_qspi.o
+obj-$(CONFIG_STM32_SPI) += stm32_spi.o
 obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
 obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
 obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
+ *
+ * Driver for STMicroelectronics Serial peripheral interface (SPI)
+ */
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <errno.h>
+#include <reset.h>
+#include <spi.h>
+
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <linux/bitfield.h>
+#include <linux/iopoll.h>
+
+/* STM32 SPI registers */
+#define STM32_SPI_CR1		0x00
+#define STM32_SPI_CR2		0x04
+#define STM32_SPI_CFG1		0x08
+#define STM32_SPI_CFG2		0x0C
+#define STM32_SPI_SR		0x14
+#define STM32_SPI_IFCR		0x18
+#define STM32_SPI_TXDR		0x20
+#define STM32_SPI_RXDR		0x30
+#define STM32_SPI_I2SCFGR	0x50
+
+/* STM32_SPI_CR1 bit fields */
+#define SPI_CR1_SPE		BIT(0)
+#define SPI_CR1_MASRX		BIT(8)
+#define SPI_CR1_CSTART		BIT(9)
+#define SPI_CR1_CSUSP		BIT(10)
+#define SPI_CR1_HDDIR		BIT(11)
+#define SPI_CR1_SSI		BIT(12)
+
+/* STM32_SPI_CR2 bit fields */
+#define SPI_CR2_TSIZE		GENMASK(15, 0)
+
+/* STM32_SPI_CFG1 bit fields */
+#define SPI_CFG1_DSIZE		GENMASK(4, 0)
+#define SPI_CFG1_DSIZE_MIN	3
+#define SPI_CFG1_FTHLV_SHIFT	5
+#define SPI_CFG1_FTHLV		GENMASK(8, 5)
+#define SPI_CFG1_MBR_SHIFT	28
+#define SPI_CFG1_MBR		GENMASK(30, 28)
+#define SPI_CFG1_MBR_MIN	0
+#define SPI_CFG1_MBR_MAX	FIELD_GET(SPI_CFG1_MBR, SPI_CFG1_MBR)
+
+/* STM32_SPI_CFG2 bit fields */
+#define SPI_CFG2_COMM_SHIFT	17
+#define SPI_CFG2_COMM		GENMASK(18, 17)
+#define SPI_CFG2_MASTER		BIT(22)
+#define SPI_CFG2_LSBFRST	BIT(23)
+#define SPI_CFG2_CPHA		BIT(24)
+#define SPI_CFG2_CPOL		BIT(25)
+#define SPI_CFG2_SSM		BIT(26)
+#define SPI_CFG2_AFCNTR		BIT(31)
+
+/* STM32_SPI_SR bit fields */
+#define SPI_SR_RXP		BIT(0)
+#define SPI_SR_TXP		BIT(1)
+#define SPI_SR_EOT		BIT(3)
+#define SPI_SR_TXTF		BIT(4)
+#define SPI_SR_OVR		BIT(6)
+#define SPI_SR_SUSP		BIT(11)
+#define SPI_SR_RXPLVL_SHIFT	13
+#define SPI_SR_RXPLVL		GENMASK(14, 13)
+#define SPI_SR_RXWNE		BIT(15)
+
+/* STM32_SPI_IFCR bit fields */
+#define SPI_IFCR_ALL		GENMASK(11, 3)
+
+/* STM32_SPI_I2SCFGR bit fields */
+#define SPI_I2SCFGR_I2SMOD	BIT(0)
+
+#define MAX_CS_COUNT	4
+
+/* SPI Master Baud Rate min/max divisor */
+#define STM32_MBR_DIV_MIN	(2 << SPI_CFG1_MBR_MIN)
+#define STM32_MBR_DIV_MAX	(2 << SPI_CFG1_MBR_MAX)
+
+#define STM32_SPI_TIMEOUT_US	100000
+
+/* SPI Communication mode */
+#define SPI_FULL_DUPLEX		0
+#define SPI_SIMPLEX_TX		1
+#define SPI_SIMPLEX_RX		2
+#define SPI_HALF_DUPLEX		3
+
+struct stm32_spi_priv {
+	void __iomem *base;
+	struct clk clk;
+	struct reset_ctl rst_ctl;
+	struct gpio_desc cs_gpios[MAX_CS_COUNT];
+	ulong bus_clk_rate;
+	unsigned int fifo_size;
+	unsigned int cur_bpw;
+	unsigned int cur_hz;
+	unsigned int cur_xferlen; /* current transfer length in bytes */
+	int tx_len;		  /* number of data to be written in bytes */
+	int rx_len;		  /* number of data to be read in bytes */
+	const void *tx_buf;	  /* data to be written, or NULL */
+	void *rx_buf;		  /* data to be read, or NULL */
+	u32 cur_mode;
+	bool cs_high;
+};
+
+static void stm32_spi_write_txfifo(struct stm32_spi_priv *priv)
+{
+	while ((priv->tx_len > 0) &&
+	       (readl(priv->base + STM32_SPI_SR) & SPI_SR_TXP)) {
+		u32 offs = priv->cur_xferlen - priv->tx_len;
+
+		if (priv->tx_len >= sizeof(u32) &&
+		    IS_ALIGNED((uintptr_t)(priv->tx_buf + offs), sizeof(u32))) {
+			const u32 *tx_buf32 = (const u32 *)(priv->tx_buf + offs);
+
+			writel(*tx_buf32, priv->base + STM32_SPI_TXDR);
+			priv->tx_len -= sizeof(u32);
+		} else if (priv->tx_len >= sizeof(u16) &&
+			   IS_ALIGNED((uintptr_t)(priv->tx_buf + offs), sizeof(u16))) {
+			const u16 *tx_buf16 = (const u16 *)(priv->tx_buf + offs);
+
+			writew(*tx_buf16, priv->base + STM32_SPI_TXDR);
+			priv->tx_len -= sizeof(u16);
+		} else {
+			const u8 *tx_buf8 = (const u8 *)(priv->tx_buf + offs);
+
+			writeb(*tx_buf8, priv->base + STM32_SPI_TXDR);
+			priv->tx_len -= sizeof(u8);
+		}
+	}
+
+	debug("%s: %d bytes left\n", __func__, priv->tx_len);
+}
+
+static void stm32_spi_read_rxfifo(struct stm32_spi_priv *priv)
+{
+	u32 sr = readl(priv->base + STM32_SPI_SR);
+	u32 rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
+
+	while ((priv->rx_len > 0) &&
+	       ((sr & SPI_SR_RXP) ||
+	       ((sr & SPI_SR_EOT) && ((sr & SPI_SR_RXWNE) || (rxplvl > 0))))) {
+		u32 offs = priv->cur_xferlen - priv->rx_len;
+
+		if (IS_ALIGNED((uintptr_t)(priv->rx_buf + offs), sizeof(u32)) &&
+		    (priv->rx_len >= sizeof(u32) || (sr & SPI_SR_RXWNE))) {
+			u32 *rx_buf32 = (u32 *)(priv->rx_buf + offs);
+
+			*rx_buf32 = readl(priv->base + STM32_SPI_RXDR);
+			priv->rx_len -= sizeof(u32);
+		} else if (IS_ALIGNED((uintptr_t)(priv->rx_buf + offs), sizeof(u16)) &&
+			   (priv->rx_len >= sizeof(u16) ||
+			    (!(sr & SPI_SR_RXWNE) &&
+			    (rxplvl >= 2 || priv->cur_bpw > 8)))) {
+			u16 *rx_buf16 = (u16 *)(priv->rx_buf + offs);
+
+			*rx_buf16 = readw(priv->base + STM32_SPI_RXDR);
+			priv->rx_len -= sizeof(u16);
+		} else {
+			u8 *rx_buf8 = (u8 *)(priv->rx_buf + offs);
+
+			*rx_buf8 = readb(priv->base + STM32_SPI_RXDR);
+			priv->rx_len -= sizeof(u8);
+		}
+
+		sr = readl(priv->base + STM32_SPI_SR);
+		rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
+	}
+
+	debug("%s: %d bytes left\n", __func__, priv->rx_len);
+}
+
+static int stm32_spi_enable(struct stm32_spi_priv *priv)
+{
+	debug("%s\n", __func__);
+
+	/* Enable the SPI hardware */
+	setbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE);
+
+	return 0;
+}
+
+static int stm32_spi_disable(struct stm32_spi_priv *priv)
+{
+	debug("%s\n", __func__);
+
+	/* Disable the SPI hardware */
+	clrbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE);
+
+	return 0;
+}
+
+static int stm32_spi_claim_bus(struct udevice *slave)
+{
+	struct udevice *bus = dev_get_parent(slave);
+	struct stm32_spi_priv *priv = dev_get_priv(bus);
+
+	debug("%s\n", __func__);
+
+	/* Enable the SPI hardware */
+	return stm32_spi_enable(priv);
+}
+
+static int stm32_spi_release_bus(struct udevice *slave)
+{
+	struct udevice *bus = dev_get_parent(slave);
+	struct stm32_spi_priv *priv = dev_get_priv(bus);
+
+	debug("%s\n", __func__);
+
+	/* Disable the SPI hardware */
+	return stm32_spi_disable(priv);
+}
+
+static void stm32_spi_stopxfer(struct udevice *dev)
+{
+	struct stm32_spi_priv *priv = dev_get_priv(dev);
+	u32 cr1, sr;
+	int ret;
+
+	debug("%s\n", __func__);
+
+	cr1 = readl(priv->base + STM32_SPI_CR1);
+
+	if (!(cr1 & SPI_CR1_SPE))
+		return;
+
+	/* Wait on EOT or suspend the flow */
+	ret = readl_poll_timeout(priv->base + STM32_SPI_SR, sr,
+				 !(sr & SPI_SR_EOT), 100000);
+	if (ret < 0) {
+		if (cr1 & SPI_CR1_CSTART) {
+			writel(cr1 | SPI_CR1_CSUSP, priv->base + STM32_SPI_CR1);
+			if (readl_poll_timeout(priv->base + STM32_SPI_SR,
+					       sr, !(sr & SPI_SR_SUSP),
+					       100000) < 0)
+				dev_err(dev, "Suspend request timeout\n");
+		}
+	}
+
+	/* clear status flags */
+	setbits_le32(priv->base + STM32_SPI_IFCR, SPI_IFCR_ALL);
+}
+
+static int stm32_spi_set_cs(struct udevice *dev, unsigned int cs, bool enable)
+{
+	struct stm32_spi_priv *priv = dev_get_priv(dev);
+
+	debug("%s: cs=%d enable=%d\n", __func__, cs, enable);
+
+	if (cs >= MAX_CS_COUNT)
+		return -ENODEV;
+
+	if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
+		return -EINVAL;
+
+	if (priv->cs_high)
+		enable = !enable;
+
+	return dm_gpio_set_value(&priv->cs_gpios[cs], enable ? 1 : 0);
+}
+
+static int stm32_spi_set_mode(struct udevice *bus, uint mode)
+{
+	struct stm32_spi_priv *priv = dev_get_priv(bus);
+	u32 cfg2_clrb = 0, cfg2_setb = 0;
+
+	debug("%s: mode=%d\n", __func__, mode);
+
+	if (mode & SPI_CPOL)
+		cfg2_setb |= SPI_CFG2_CPOL;
+	else
+		cfg2_clrb |= SPI_CFG2_CPOL;
+
+	if (mode & SPI_CPHA)
+		cfg2_setb |= SPI_CFG2_CPHA;
+	else
+		cfg2_clrb |= SPI_CFG2_CPHA;
+
+	if (mode & SPI_LSB_FIRST)
+		cfg2_setb |= SPI_CFG2_LSBFRST;
+	else
+		cfg2_clrb |= SPI_CFG2_LSBFRST;
+
+	if (cfg2_clrb || cfg2_setb)
+		clrsetbits_le32(priv->base + STM32_SPI_CFG2,
+				cfg2_clrb, cfg2_setb);
+
+	if (mode & SPI_CS_HIGH)
+		priv->cs_high = true;
+	else
+		priv->cs_high = false;
+	return 0;
+}
+
+static int stm32_spi_set_fthlv(struct udevice *dev, u32 xfer_len)
+{
+	struct stm32_spi_priv *priv = dev_get_priv(dev);
+	u32 fthlv, half_fifo;
+
+	/* data packet should not exceed 1/2 of fifo space */
+	half_fifo = (priv->fifo_size / 2);
+
+	/* data_packet should not exceed transfer length */
+	fthlv = (half_fifo > xfer_len) ? xfer_len : half_fifo;
+
+	/* align packet size with data registers access */
+	fthlv -= (fthlv % 4);
+
+	if (!fthlv)
+		fthlv = 1;
+	clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_FTHLV,
+			(fthlv - 1) << SPI_CFG1_FTHLV_SHIFT);
+
+	return 0;
+}
+
+static int stm32_spi_set_speed(struct udevice *bus, uint hz)
+{
+	struct stm32_spi_priv *priv = dev_get_priv(bus);
+	u32 div, mbrdiv;
+
+	debug("%s: hz=%d\n", __func__, hz);
+
+	if (priv->cur_hz == hz)
+		return 0;
+
+	div = DIV_ROUND_UP(priv->bus_clk_rate, hz);
+
+	if (div < STM32_MBR_DIV_MIN ||
+	    div > STM32_MBR_DIV_MAX)
+		return -EINVAL;
+
+	/* Determine the first power of 2 greater than or equal to div */
+	if (div & (div - 1))
+		mbrdiv = fls(div);
+	else
+		mbrdiv = fls(div) - 1;
+
+	if ((mbrdiv - 1) < 0)
+		return -EINVAL;
+
+	clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_MBR,
+			(mbrdiv - 1) << SPI_CFG1_MBR_SHIFT);
+
+	priv->cur_hz = hz;
+
+	return 0;
+}
+
+static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen,
+			  const void *dout, void *din, unsigned long flags)
+{
+	struct udevice *bus = dev_get_parent(slave);
+	struct dm_spi_slave_platdata *slave_plat;
+	struct stm32_spi_priv *priv = dev_get_priv(bus);
+	u32 sr;
+	u32 ifcr = 0;
+	u32 xferlen;
+	u32 mode;
+	int xfer_status = 0;
+
+	xferlen = bitlen / 8;
+
+	if (xferlen <= SPI_CR2_TSIZE)
+		writel(xferlen, priv->base + STM32_SPI_CR2);
+	else
+		return -EMSGSIZE;
+
+	priv->tx_buf = dout;
+	priv->rx_buf = din;
+	priv->tx_len = priv->tx_buf ? bitlen / 8 : 0;
+	priv->rx_len = priv->rx_buf ? bitlen / 8 : 0;
+
+	mode = SPI_FULL_DUPLEX;
+	if (!priv->tx_buf)
+		mode = SPI_SIMPLEX_RX;
+	else if (!priv->rx_buf)
+		mode = SPI_SIMPLEX_TX;
+
+	if (priv->cur_xferlen != xferlen || priv->cur_mode != mode) {
+		priv->cur_mode = mode;
+		priv->cur_xferlen = xferlen;
+
+		/* Disable the SPI hardware to unlock CFG1/CFG2 registers */
+		stm32_spi_disable(priv);
+
+		clrsetbits_le32(priv->base + STM32_SPI_CFG2, SPI_CFG2_COMM,
+				mode << SPI_CFG2_COMM_SHIFT);
+
+		stm32_spi_set_fthlv(bus, xferlen);
+
+		/* Enable the SPI hardware */
+		stm32_spi_enable(priv);
+	}
+
+	debug("%s: priv->tx_len=%d priv->rx_len=%d\n", __func__,
+	      priv->tx_len, priv->rx_len);
+
+	slave_plat = dev_get_parent_platdata(slave);
+	if (flags & SPI_XFER_BEGIN)
+		stm32_spi_set_cs(bus, slave_plat->cs, false);
+
+	/* Be sure to have data in fifo before starting data transfer */
+	if (priv->tx_buf)
+		stm32_spi_write_txfifo(priv);
+
+	setbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_CSTART);
+
+	while (1) {
+		sr = readl(priv->base + STM32_SPI_SR);
+
+		if (sr & SPI_SR_OVR) {
+			dev_err(bus, "Overrun: RX data lost\n");
+			xfer_status = -EIO;
+			break;
+		}
+
+		if (sr & SPI_SR_SUSP) {
+			dev_warn(bus, "System too slow is limiting data throughput\n");
+
+			if (priv->rx_buf && priv->rx_len > 0)
+				stm32_spi_read_rxfifo(priv);
+
+			ifcr |= SPI_SR_SUSP;
+		}
+
+		if (sr & SPI_SR_TXTF)
+			ifcr |= SPI_SR_TXTF;
+
+		if (sr & SPI_SR_TXP)
+			if (priv->tx_buf && priv->tx_len > 0)
+				stm32_spi_write_txfifo(priv);
+
+		if (sr & SPI_SR_RXP)
+			if (priv->rx_buf && priv->rx_len > 0)
+				stm32_spi_read_rxfifo(priv);
+
+		if (sr & SPI_SR_EOT) {
+			if (priv->rx_buf && priv->rx_len > 0)
+				stm32_spi_read_rxfifo(priv);
+			break;
+		}
+
+		writel(ifcr, priv->base + STM32_SPI_IFCR);
+	}
+
+	/* clear status flags */
+	setbits_le32(priv->base + STM32_SPI_IFCR, SPI_IFCR_ALL);
+	stm32_spi_stopxfer(bus);
+
+	if (flags & SPI_XFER_END)
+		stm32_spi_set_cs(bus, slave_plat->cs, true);
+
+	return xfer_status;
+}
+
+static int stm32_spi_get_fifo_size(struct udevice *dev)
+{
+	struct stm32_spi_priv *priv = dev_get_priv(dev);
+	u32 count = 0;
+
+	stm32_spi_enable(priv);
+
+	while (readl(priv->base + STM32_SPI_SR) & SPI_SR_TXP)
+		writeb(++count, priv->base + STM32_SPI_TXDR);
+
+	stm32_spi_disable(priv);
+
+	debug("%s %d x 8-bit fifo size\n", __func__, count);
+
+	return count;
+}
+
+static int stm32_spi_probe(struct udevice *dev)
+{
+	struct stm32_spi_priv *priv = dev_get_priv(dev);
+	unsigned long clk_rate;
+	int ret;
+	int i;
+
+	priv->base = dev_remap_addr(dev);
+	if (!priv->base)
+		return -EINVAL;
+
+	/* enable clock */
+	ret = clk_get_by_index(dev, 0, &priv->clk);
+	if (ret < 0)
+		return ret;
+
+	ret = clk_enable(&priv->clk);
+	if (ret < 0)
+		return ret;
+
+	clk_rate = clk_get_rate(&priv->clk);
+	if (!clk_rate) {
+		ret = -EINVAL;
+		goto clk_err;
+	}
+
+	priv->bus_clk_rate = clk_rate;
+
+	/* perform reset */
+	ret = reset_get_by_index(dev, 0, &priv->rst_ctl);
+	if (ret < 0)
+		goto clk_err;
+
+	reset_assert(&priv->rst_ctl);
+	udelay(2);
+	reset_deassert(&priv->rst_ctl);
+
+	ret = gpio_request_list_by_name(dev, "cs-gpios", priv->cs_gpios,
+					ARRAY_SIZE(priv->cs_gpios), 0);
+	if (ret < 0) {
+		pr_err("Can't get %s cs gpios: %d", dev->name, ret);
+		goto reset_err;
+	}
+
+	priv->fifo_size = stm32_spi_get_fifo_size(dev);
+
+	priv->cur_mode = SPI_FULL_DUPLEX;
+	priv->cur_xferlen = 0;
+	priv->cur_bpw = SPI_DEFAULT_WORDLEN;
+	clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_DSIZE,
+			priv->cur_bpw - 1);
+
+	for (i = 0; i < ARRAY_SIZE(priv->cs_gpios); i++) {
+		if (!dm_gpio_is_valid(&priv->cs_gpios[i]))
+			continue;
+
+		dm_gpio_set_dir_flags(&priv->cs_gpios[i],
+				      GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+	}
+
+	/* Ensure I2SMOD bit is kept cleared */
+	clrbits_le32(priv->base + STM32_SPI_I2SCFGR, SPI_I2SCFGR_I2SMOD);
+
+	/*
+	 * - SS input value high
+	 * - transmitter half duplex direction
+	 * - automatic communication suspend when RX-Fifo is full
+	 */
+	setbits_le32(priv->base + STM32_SPI_CR1,
+		     SPI_CR1_SSI | SPI_CR1_HDDIR | SPI_CR1_MASRX);
+
+	/*
+	 * - Set the master mode (default Motorola mode)
+	 * - Consider 1 master/n slaves configuration and
+	 *   SS input value is determined by the SSI bit
+	 * - keep control of all associated GPIOs
+	 */
+	setbits_le32(priv->base + STM32_SPI_CFG2,
+		     SPI_CFG2_MASTER | SPI_CFG2_SSM | SPI_CFG2_AFCNTR);
+
+	return 0;
+
+reset_err:
+	reset_free(&priv->rst_ctl);
+
+clk_err:
+	clk_disable(&priv->clk);
+	clk_free(&priv->clk);
+
+	return ret;
+};
+
+static int stm32_spi_remove(struct udevice *dev)
+{
+	struct stm32_spi_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	stm32_spi_stopxfer(dev);
+	stm32_spi_disable(priv);
+
+	ret = reset_assert(&priv->rst_ctl);
+	if (ret < 0)
+		return ret;
+
+	reset_free(&priv->rst_ctl);
+
+	ret = clk_disable(&priv->clk);
+	if (ret < 0)
+		return ret;
+
+	clk_free(&priv->clk);
+
+	return ret;
+};
+
+static const struct dm_spi_ops stm32_spi_ops = {
+	.claim_bus	= stm32_spi_claim_bus,
+	.release_bus	= stm32_spi_release_bus,
+	.set_mode	= stm32_spi_set_mode,
+	.set_speed	= stm32_spi_set_speed,
+	.xfer		= stm32_spi_xfer,
+};
+
+static const struct udevice_id stm32_spi_ids[] = {
+	{ .compatible = "st,stm32h7-spi", },
+	{ }
+};
+
+U_BOOT_DRIVER(stm32_spi) = {
+	.name			= "stm32_spi",
+	.id			= UCLASS_SPI,
+	.of_match		= stm32_spi_ids,
+	.ops			= &stm32_spi_ops,
+	.priv_auto_alloc_size	= sizeof(struct stm32_spi_priv),
+	.probe			= stm32_spi_probe,
+	.remove			= stm32_spi_remove,
+};
...	...	@@ -312,6 +312,7 @@
312	312	F: drivers/misc/stm32_rcc.c
313	313	F: drivers/reset/stm32-reset.c
314	314	F: drivers/spi/stm32_qspi.c
	315	+F: drivers/spi/stm32_spi.c
315	316	F: drivers/watchdog/stm32mp_wdt.c
316	317
317	318	ARM STM STV0991
...	...	@@ -234,6 +234,14 @@
234	234	used to access the SPI NOR flash chips on platforms embedding
235	235	this ST IP core.
236	236
	237	+config STM32_SPI
	238	+ bool "STM32 SPI driver"
	239	+ depends on ARCH_STM32MP
	240	+ help
	241	+ Enable the STM32 Serial Peripheral Interface (SPI) driver for STM32MP
	242	+ SoCs. This uses driver model and requires a device tree binding to
	243	+ operate.
	244	+
237	245	config TEGRA114_SPI
238	246	bool "nVidia Tegra114 SPI driver"
239	247	help
...	...	@@ -53,6 +53,7 @@
53	53	obj-$(CONFIG_SH_SPI) += sh_spi.o
54	54	obj-$(CONFIG_SH_QSPI) += sh_qspi.o
55	55	obj-$(CONFIG_STM32_QSPI) += stm32_qspi.o
	56	+obj-$(CONFIG_STM32_SPI) += stm32_spi.o
56	57	obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
57	58	obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
58	59	obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
	1	+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
	2	+/*
	3	+ * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
	4	+ *
	5	+ * Driver for STMicroelectronics Serial peripheral interface (SPI)
	6	+ */
	7	+#include <common.h>
	8	+#include <clk.h>
	9	+#include <dm.h>
	10	+#include <errno.h>
	11	+#include <reset.h>
	12	+#include <spi.h>
	13	+
	14	+#include <asm/io.h>
	15	+#include <asm/gpio.h>
	16	+#include <linux/bitfield.h>
	17	+#include <linux/iopoll.h>
	18	+
	19	+/* STM32 SPI registers */
	20	+#define STM32_SPI_CR1 0x00
	21	+#define STM32_SPI_CR2 0x04
	22	+#define STM32_SPI_CFG1 0x08
	23	+#define STM32_SPI_CFG2 0x0C
	24	+#define STM32_SPI_SR 0x14
	25	+#define STM32_SPI_IFCR 0x18
	26	+#define STM32_SPI_TXDR 0x20
	27	+#define STM32_SPI_RXDR 0x30
	28	+#define STM32_SPI_I2SCFGR 0x50
	29	+
	30	+/* STM32_SPI_CR1 bit fields */
	31	+#define SPI_CR1_SPE BIT(0)
	32	+#define SPI_CR1_MASRX BIT(8)
	33	+#define SPI_CR1_CSTART BIT(9)
	34	+#define SPI_CR1_CSUSP BIT(10)
	35	+#define SPI_CR1_HDDIR BIT(11)
	36	+#define SPI_CR1_SSI BIT(12)
	37	+
	38	+/* STM32_SPI_CR2 bit fields */
	39	+#define SPI_CR2_TSIZE GENMASK(15, 0)
	40	+
	41	+/* STM32_SPI_CFG1 bit fields */
	42	+#define SPI_CFG1_DSIZE GENMASK(4, 0)
	43	+#define SPI_CFG1_DSIZE_MIN 3
	44	+#define SPI_CFG1_FTHLV_SHIFT 5
	45	+#define SPI_CFG1_FTHLV GENMASK(8, 5)
	46	+#define SPI_CFG1_MBR_SHIFT 28
	47	+#define SPI_CFG1_MBR GENMASK(30, 28)
	48	+#define SPI_CFG1_MBR_MIN 0
	49	+#define SPI_CFG1_MBR_MAX FIELD_GET(SPI_CFG1_MBR, SPI_CFG1_MBR)
	50	+
	51	+/* STM32_SPI_CFG2 bit fields */
	52	+#define SPI_CFG2_COMM_SHIFT 17
	53	+#define SPI_CFG2_COMM GENMASK(18, 17)
	54	+#define SPI_CFG2_MASTER BIT(22)
	55	+#define SPI_CFG2_LSBFRST BIT(23)
	56	+#define SPI_CFG2_CPHA BIT(24)
	57	+#define SPI_CFG2_CPOL BIT(25)
	58	+#define SPI_CFG2_SSM BIT(26)
	59	+#define SPI_CFG2_AFCNTR BIT(31)
	60	+
	61	+/* STM32_SPI_SR bit fields */
	62	+#define SPI_SR_RXP BIT(0)
	63	+#define SPI_SR_TXP BIT(1)
	64	+#define SPI_SR_EOT BIT(3)
	65	+#define SPI_SR_TXTF BIT(4)
	66	+#define SPI_SR_OVR BIT(6)
	67	+#define SPI_SR_SUSP BIT(11)
	68	+#define SPI_SR_RXPLVL_SHIFT 13
	69	+#define SPI_SR_RXPLVL GENMASK(14, 13)
	70	+#define SPI_SR_RXWNE BIT(15)
	71	+
	72	+/* STM32_SPI_IFCR bit fields */
	73	+#define SPI_IFCR_ALL GENMASK(11, 3)
	74	+
	75	+/* STM32_SPI_I2SCFGR bit fields */
	76	+#define SPI_I2SCFGR_I2SMOD BIT(0)
	77	+
	78	+#define MAX_CS_COUNT 4
	79	+
	80	+/* SPI Master Baud Rate min/max divisor */
	81	+#define STM32_MBR_DIV_MIN (2 << SPI_CFG1_MBR_MIN)
	82	+#define STM32_MBR_DIV_MAX (2 << SPI_CFG1_MBR_MAX)
	83	+
	84	+#define STM32_SPI_TIMEOUT_US 100000
	85	+
	86	+/* SPI Communication mode */
	87	+#define SPI_FULL_DUPLEX 0
	88	+#define SPI_SIMPLEX_TX 1
	89	+#define SPI_SIMPLEX_RX 2
	90	+#define SPI_HALF_DUPLEX 3
	91	+
	92	+struct stm32_spi_priv {
	93	+ void __iomem *base;
	94	+ struct clk clk;
	95	+ struct reset_ctl rst_ctl;
	96	+ struct gpio_desc cs_gpios[MAX_CS_COUNT];
	97	+ ulong bus_clk_rate;
	98	+ unsigned int fifo_size;
	99	+ unsigned int cur_bpw;
	100	+ unsigned int cur_hz;
	101	+ unsigned int cur_xferlen; /* current transfer length in bytes */
	102	+ int tx_len; /* number of data to be written in bytes */
	103	+ int rx_len; /* number of data to be read in bytes */
	104	+ const void tx_buf; / data to be written, or NULL */
	105	+ void rx_buf; / data to be read, or NULL */
	106	+ u32 cur_mode;
	107	+ bool cs_high;
	108	+};
	109	+
	110	+static void stm32_spi_write_txfifo(struct stm32_spi_priv *priv)
	111	+{
	112	+ while ((priv->tx_len > 0) &&
	113	+ (readl(priv->base + STM32_SPI_SR) & SPI_SR_TXP)) {
	114	+ u32 offs = priv->cur_xferlen - priv->tx_len;
	115	+
	116	+ if (priv->tx_len >= sizeof(u32) &&
	117	+ IS_ALIGNED((uintptr_t)(priv->tx_buf + offs), sizeof(u32))) {
	118	+ const u32 tx_buf32 = (const u32 )(priv->tx_buf + offs);
	119	+
	120	+ writel(*tx_buf32, priv->base + STM32_SPI_TXDR);
	121	+ priv->tx_len -= sizeof(u32);
	122	+ } else if (priv->tx_len >= sizeof(u16) &&
	123	+ IS_ALIGNED((uintptr_t)(priv->tx_buf + offs), sizeof(u16))) {
	124	+ const u16 tx_buf16 = (const u16 )(priv->tx_buf + offs);
	125	+
	126	+ writew(*tx_buf16, priv->base + STM32_SPI_TXDR);
	127	+ priv->tx_len -= sizeof(u16);
	128	+ } else {
	129	+ const u8 tx_buf8 = (const u8 )(priv->tx_buf + offs);
	130	+
	131	+ writeb(*tx_buf8, priv->base + STM32_SPI_TXDR);
	132	+ priv->tx_len -= sizeof(u8);
	133	+ }
	134	+ }
	135	+
	136	+ debug("%s: %d bytes left\n", __func__, priv->tx_len);
	137	+}
	138	+
	139	+static void stm32_spi_read_rxfifo(struct stm32_spi_priv *priv)
	140	+{
	141	+ u32 sr = readl(priv->base + STM32_SPI_SR);
	142	+ u32 rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
	143	+
	144	+ while ((priv->rx_len > 0) &&
	145	+ ((sr & SPI_SR_RXP) \|\|
	146	+ ((sr & SPI_SR_EOT) && ((sr & SPI_SR_RXWNE) \|\| (rxplvl > 0))))) {
	147	+ u32 offs = priv->cur_xferlen - priv->rx_len;
	148	+
	149	+ if (IS_ALIGNED((uintptr_t)(priv->rx_buf + offs), sizeof(u32)) &&
	150	+ (priv->rx_len >= sizeof(u32) \|\| (sr & SPI_SR_RXWNE))) {
	151	+ u32 rx_buf32 = (u32 )(priv->rx_buf + offs);
	152	+
	153	+ *rx_buf32 = readl(priv->base + STM32_SPI_RXDR);
	154	+ priv->rx_len -= sizeof(u32);
	155	+ } else if (IS_ALIGNED((uintptr_t)(priv->rx_buf + offs), sizeof(u16)) &&
	156	+ (priv->rx_len >= sizeof(u16) \|\|
	157	+ (!(sr & SPI_SR_RXWNE) &&
	158	+ (rxplvl >= 2 \|\| priv->cur_bpw > 8)))) {
	159	+ u16 rx_buf16 = (u16 )(priv->rx_buf + offs);
	160	+
	161	+ *rx_buf16 = readw(priv->base + STM32_SPI_RXDR);
	162	+ priv->rx_len -= sizeof(u16);
	163	+ } else {
	164	+ u8 rx_buf8 = (u8 )(priv->rx_buf + offs);
	165	+
	166	+ *rx_buf8 = readb(priv->base + STM32_SPI_RXDR);
	167	+ priv->rx_len -= sizeof(u8);
	168	+ }
	169	+
	170	+ sr = readl(priv->base + STM32_SPI_SR);
	171	+ rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
	172	+ }
	173	+
	174	+ debug("%s: %d bytes left\n", __func__, priv->rx_len);
	175	+}
	176	+
	177	+static int stm32_spi_enable(struct stm32_spi_priv *priv)
	178	+{
	179	+ debug("%s\n", __func__);
	180	+
	181	+ /* Enable the SPI hardware */
	182	+ setbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE);
	183	+
	184	+ return 0;
	185	+}
	186	+
	187	+static int stm32_spi_disable(struct stm32_spi_priv *priv)
	188	+{
	189	+ debug("%s\n", __func__);
	190	+
	191	+ /* Disable the SPI hardware */
	192	+ clrbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE);
	193	+
	194	+ return 0;
	195	+}
	196	+
	197	+static int stm32_spi_claim_bus(struct udevice *slave)
	198	+{
	199	+ struct udevice *bus = dev_get_parent(slave);
	200	+ struct stm32_spi_priv *priv = dev_get_priv(bus);
	201	+
	202	+ debug("%s\n", __func__);
	203	+
	204	+ /* Enable the SPI hardware */
	205	+ return stm32_spi_enable(priv);
	206	+}
	207	+
	208	+static int stm32_spi_release_bus(struct udevice *slave)
	209	+{
	210	+ struct udevice *bus = dev_get_parent(slave);
	211	+ struct stm32_spi_priv *priv = dev_get_priv(bus);
	212	+
	213	+ debug("%s\n", __func__);
	214	+
	215	+ /* Disable the SPI hardware */
	216	+ return stm32_spi_disable(priv);
	217	+}
	218	+
	219	+static void stm32_spi_stopxfer(struct udevice *dev)
	220	+{
	221	+ struct stm32_spi_priv *priv = dev_get_priv(dev);
	222	+ u32 cr1, sr;
	223	+ int ret;
	224	+
	225	+ debug("%s\n", __func__);
	226	+
	227	+ cr1 = readl(priv->base + STM32_SPI_CR1);
	228	+
	229	+ if (!(cr1 & SPI_CR1_SPE))
	230	+ return;
	231	+
	232	+ /* Wait on EOT or suspend the flow */
	233	+ ret = readl_poll_timeout(priv->base + STM32_SPI_SR, sr,
	234	+ !(sr & SPI_SR_EOT), 100000);
	235	+ if (ret < 0) {
	236	+ if (cr1 & SPI_CR1_CSTART) {
	237	+ writel(cr1 \| SPI_CR1_CSUSP, priv->base + STM32_SPI_CR1);
	238	+ if (readl_poll_timeout(priv->base + STM32_SPI_SR,
	239	+ sr, !(sr & SPI_SR_SUSP),
	240	+ 100000) < 0)
	241	+ dev_err(dev, "Suspend request timeout\n");
	242	+ }
	243	+ }
	244	+
	245	+ /* clear status flags */
	246	+ setbits_le32(priv->base + STM32_SPI_IFCR, SPI_IFCR_ALL);
	247	+}
	248	+
	249	+static int stm32_spi_set_cs(struct udevice *dev, unsigned int cs, bool enable)
	250	+{
	251	+ struct stm32_spi_priv *priv = dev_get_priv(dev);
	252	+
	253	+ debug("%s: cs=%d enable=%d\n", __func__, cs, enable);
	254	+
	255	+ if (cs >= MAX_CS_COUNT)
	256	+ return -ENODEV;
	257	+
	258	+ if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
	259	+ return -EINVAL;
	260	+
	261	+ if (priv->cs_high)
	262	+ enable = !enable;
	263	+
	264	+ return dm_gpio_set_value(&priv->cs_gpios[cs], enable ? 1 : 0);
	265	+}
	266	+
	267	+static int stm32_spi_set_mode(struct udevice *bus, uint mode)
	268	+{
	269	+ struct stm32_spi_priv *priv = dev_get_priv(bus);
	270	+ u32 cfg2_clrb = 0, cfg2_setb = 0;
	271	+
	272	+ debug("%s: mode=%d\n", __func__, mode);
	273	+
	274	+ if (mode & SPI_CPOL)
	275	+ cfg2_setb \|= SPI_CFG2_CPOL;
	276	+ else
	277	+ cfg2_clrb \|= SPI_CFG2_CPOL;
	278	+
	279	+ if (mode & SPI_CPHA)
	280	+ cfg2_setb \|= SPI_CFG2_CPHA;
	281	+ else
	282	+ cfg2_clrb \|= SPI_CFG2_CPHA;
	283	+
	284	+ if (mode & SPI_LSB_FIRST)
	285	+ cfg2_setb \|= SPI_CFG2_LSBFRST;
	286	+ else
	287	+ cfg2_clrb \|= SPI_CFG2_LSBFRST;
	288	+
	289	+ if (cfg2_clrb \|\| cfg2_setb)
	290	+ clrsetbits_le32(priv->base + STM32_SPI_CFG2,
	291	+ cfg2_clrb, cfg2_setb);
	292	+
	293	+ if (mode & SPI_CS_HIGH)
	294	+ priv->cs_high = true;
	295	+ else
	296	+ priv->cs_high = false;
	297	+ return 0;
	298	+}
	299	+
	300	+static int stm32_spi_set_fthlv(struct udevice *dev, u32 xfer_len)
	301	+{
	302	+ struct stm32_spi_priv *priv = dev_get_priv(dev);
	303	+ u32 fthlv, half_fifo;
	304	+
	305	+ /* data packet should not exceed 1/2 of fifo space */
	306	+ half_fifo = (priv->fifo_size / 2);
	307	+
	308	+ /* data_packet should not exceed transfer length */
	309	+ fthlv = (half_fifo > xfer_len) ? xfer_len : half_fifo;
	310	+
	311	+ /* align packet size with data registers access */
	312	+ fthlv -= (fthlv % 4);
	313	+
	314	+ if (!fthlv)
	315	+ fthlv = 1;
	316	+ clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_FTHLV,
	317	+ (fthlv - 1) << SPI_CFG1_FTHLV_SHIFT);
	318	+
	319	+ return 0;
	320	+}
	321	+
	322	+static int stm32_spi_set_speed(struct udevice *bus, uint hz)
	323	+{
	324	+ struct stm32_spi_priv *priv = dev_get_priv(bus);
	325	+ u32 div, mbrdiv;
	326	+
	327	+ debug("%s: hz=%d\n", __func__, hz);
	328	+
	329	+ if (priv->cur_hz == hz)
	330	+ return 0;
	331	+
	332	+ div = DIV_ROUND_UP(priv->bus_clk_rate, hz);
	333	+
	334	+ if (div < STM32_MBR_DIV_MIN \|\|
	335	+ div > STM32_MBR_DIV_MAX)
	336	+ return -EINVAL;
	337	+
	338	+ /* Determine the first power of 2 greater than or equal to div */
	339	+ if (div & (div - 1))
	340	+ mbrdiv = fls(div);
	341	+ else
	342	+ mbrdiv = fls(div) - 1;
	343	+
	344	+ if ((mbrdiv - 1) < 0)
	345	+ return -EINVAL;
	346	+
	347	+ clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_MBR,
	348	+ (mbrdiv - 1) << SPI_CFG1_MBR_SHIFT);
	349	+
	350	+ priv->cur_hz = hz;
	351	+
	352	+ return 0;
	353	+}
	354	+
	355	+static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen,
	356	+ const void dout, void din, unsigned long flags)
	357	+{
	358	+ struct udevice *bus = dev_get_parent(slave);
	359	+ struct dm_spi_slave_platdata *slave_plat;
	360	+ struct stm32_spi_priv *priv = dev_get_priv(bus);
	361	+ u32 sr;
	362	+ u32 ifcr = 0;
	363	+ u32 xferlen;
	364	+ u32 mode;
	365	+ int xfer_status = 0;
	366	+
	367	+ xferlen = bitlen / 8;
	368	+
	369	+ if (xferlen <= SPI_CR2_TSIZE)
	370	+ writel(xferlen, priv->base + STM32_SPI_CR2);
	371	+ else
	372	+ return -EMSGSIZE;
	373	+
	374	+ priv->tx_buf = dout;
	375	+ priv->rx_buf = din;
	376	+ priv->tx_len = priv->tx_buf ? bitlen / 8 : 0;
	377	+ priv->rx_len = priv->rx_buf ? bitlen / 8 : 0;
	378	+
	379	+ mode = SPI_FULL_DUPLEX;
	380	+ if (!priv->tx_buf)
	381	+ mode = SPI_SIMPLEX_RX;
	382	+ else if (!priv->rx_buf)
	383	+ mode = SPI_SIMPLEX_TX;
	384	+
	385	+ if (priv->cur_xferlen != xferlen \|\| priv->cur_mode != mode) {
	386	+ priv->cur_mode = mode;
	387	+ priv->cur_xferlen = xferlen;
	388	+
	389	+ /* Disable the SPI hardware to unlock CFG1/CFG2 registers */
	390	+ stm32_spi_disable(priv);
	391	+
	392	+ clrsetbits_le32(priv->base + STM32_SPI_CFG2, SPI_CFG2_COMM,
	393	+ mode << SPI_CFG2_COMM_SHIFT);
	394	+
	395	+ stm32_spi_set_fthlv(bus, xferlen);
	396	+
	397	+ /* Enable the SPI hardware */
	398	+ stm32_spi_enable(priv);
	399	+ }
	400	+
	401	+ debug("%s: priv->tx_len=%d priv->rx_len=%d\n", __func__,
	402	+ priv->tx_len, priv->rx_len);
	403	+
	404	+ slave_plat = dev_get_parent_platdata(slave);
	405	+ if (flags & SPI_XFER_BEGIN)
	406	+ stm32_spi_set_cs(bus, slave_plat->cs, false);
	407	+
	408	+ /* Be sure to have data in fifo before starting data transfer */
	409	+ if (priv->tx_buf)
	410	+ stm32_spi_write_txfifo(priv);
	411	+
	412	+ setbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_CSTART);
	413	+
	414	+ while (1) {
	415	+ sr = readl(priv->base + STM32_SPI_SR);
	416	+
	417	+ if (sr & SPI_SR_OVR) {
	418	+ dev_err(bus, "Overrun: RX data lost\n");
	419	+ xfer_status = -EIO;
	420	+ break;
	421	+ }
	422	+
	423	+ if (sr & SPI_SR_SUSP) {
	424	+ dev_warn(bus, "System too slow is limiting data throughput\n");
	425	+
	426	+ if (priv->rx_buf && priv->rx_len > 0)
	427	+ stm32_spi_read_rxfifo(priv);
	428	+
	429	+ ifcr \|= SPI_SR_SUSP;
	430	+ }
	431	+
	432	+ if (sr & SPI_SR_TXTF)
	433	+ ifcr \|= SPI_SR_TXTF;
	434	+
	435	+ if (sr & SPI_SR_TXP)
	436	+ if (priv->tx_buf && priv->tx_len > 0)
	437	+ stm32_spi_write_txfifo(priv);
	438	+
	439	+ if (sr & SPI_SR_RXP)
	440	+ if (priv->rx_buf && priv->rx_len > 0)
	441	+ stm32_spi_read_rxfifo(priv);
	442	+
	443	+ if (sr & SPI_SR_EOT) {
	444	+ if (priv->rx_buf && priv->rx_len > 0)
	445	+ stm32_spi_read_rxfifo(priv);
	446	+ break;
	447	+ }
	448	+
	449	+ writel(ifcr, priv->base + STM32_SPI_IFCR);
	450	+ }
	451	+
	452	+ /* clear status flags */
	453	+ setbits_le32(priv->base + STM32_SPI_IFCR, SPI_IFCR_ALL);
	454	+ stm32_spi_stopxfer(bus);
	455	+
	456	+ if (flags & SPI_XFER_END)
	457	+ stm32_spi_set_cs(bus, slave_plat->cs, true);
	458	+
	459	+ return xfer_status;
	460	+}
	461	+
	462	+static int stm32_spi_get_fifo_size(struct udevice *dev)
	463	+{
	464	+ struct stm32_spi_priv *priv = dev_get_priv(dev);
	465	+ u32 count = 0;
	466	+
	467	+ stm32_spi_enable(priv);
	468	+
	469	+ while (readl(priv->base + STM32_SPI_SR) & SPI_SR_TXP)
	470	+ writeb(++count, priv->base + STM32_SPI_TXDR);
	471	+
	472	+ stm32_spi_disable(priv);
	473	+
	474	+ debug("%s %d x 8-bit fifo size\n", __func__, count);
	475	+
	476	+ return count;
	477	+}
	478	+
	479	+static int stm32_spi_probe(struct udevice *dev)
	480	+{
	481	+ struct stm32_spi_priv *priv = dev_get_priv(dev);
	482	+ unsigned long clk_rate;
	483	+ int ret;
	484	+ int i;
	485	+
	486	+ priv->base = dev_remap_addr(dev);
	487	+ if (!priv->base)
	488	+ return -EINVAL;
	489	+
	490	+ /* enable clock */
	491	+ ret = clk_get_by_index(dev, 0, &priv->clk);
	492	+ if (ret < 0)
	493	+ return ret;
	494	+
	495	+ ret = clk_enable(&priv->clk);
	496	+ if (ret < 0)
	497	+ return ret;
	498	+
	499	+ clk_rate = clk_get_rate(&priv->clk);
	500	+ if (!clk_rate) {
	501	+ ret = -EINVAL;
	502	+ goto clk_err;
	503	+ }
	504	+
	505	+ priv->bus_clk_rate = clk_rate;
	506	+
	507	+ /* perform reset */
	508	+ ret = reset_get_by_index(dev, 0, &priv->rst_ctl);
	509	+ if (ret < 0)
	510	+ goto clk_err;
	511	+
	512	+ reset_assert(&priv->rst_ctl);
	513	+ udelay(2);
	514	+ reset_deassert(&priv->rst_ctl);
	515	+
	516	+ ret = gpio_request_list_by_name(dev, "cs-gpios", priv->cs_gpios,
	517	+ ARRAY_SIZE(priv->cs_gpios), 0);
	518	+ if (ret < 0) {
	519	+ pr_err("Can't get %s cs gpios: %d", dev->name, ret);
	520	+ goto reset_err;
	521	+ }
	522	+
	523	+ priv->fifo_size = stm32_spi_get_fifo_size(dev);
	524	+
	525	+ priv->cur_mode = SPI_FULL_DUPLEX;
	526	+ priv->cur_xferlen = 0;
	527	+ priv->cur_bpw = SPI_DEFAULT_WORDLEN;
	528	+ clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_DSIZE,
	529	+ priv->cur_bpw - 1);
	530	+
	531	+ for (i = 0; i < ARRAY_SIZE(priv->cs_gpios); i++) {
	532	+ if (!dm_gpio_is_valid(&priv->cs_gpios[i]))
	533	+ continue;
	534	+
	535	+ dm_gpio_set_dir_flags(&priv->cs_gpios[i],
	536	+ GPIOD_IS_OUT \| GPIOD_IS_OUT_ACTIVE);
	537	+ }
	538	+
	539	+ /* Ensure I2SMOD bit is kept cleared */
	540	+ clrbits_le32(priv->base + STM32_SPI_I2SCFGR, SPI_I2SCFGR_I2SMOD);
	541	+
	542	+ /*
	543	+ * - SS input value high
	544	+ * - transmitter half duplex direction
	545	+ * - automatic communication suspend when RX-Fifo is full
	546	+ */
	547	+ setbits_le32(priv->base + STM32_SPI_CR1,
	548	+ SPI_CR1_SSI \| SPI_CR1_HDDIR \| SPI_CR1_MASRX);
	549	+
	550	+ /*
	551	+ * - Set the master mode (default Motorola mode)
	552	+ * - Consider 1 master/n slaves configuration and
	553	+ * SS input value is determined by the SSI bit
	554	+ * - keep control of all associated GPIOs
	555	+ */
	556	+ setbits_le32(priv->base + STM32_SPI_CFG2,
	557	+ SPI_CFG2_MASTER \| SPI_CFG2_SSM \| SPI_CFG2_AFCNTR);
	558	+
	559	+ return 0;
	560	+
	561	+reset_err:
	562	+ reset_free(&priv->rst_ctl);
	563	+
	564	+clk_err:
	565	+ clk_disable(&priv->clk);
	566	+ clk_free(&priv->clk);
	567	+
	568	+ return ret;
	569	+};
	570	+
	571	+static int stm32_spi_remove(struct udevice *dev)
	572	+{
	573	+ struct stm32_spi_priv *priv = dev_get_priv(dev);
	574	+ int ret;
	575	+
	576	+ stm32_spi_stopxfer(dev);
	577	+ stm32_spi_disable(priv);
	578	+
	579	+ ret = reset_assert(&priv->rst_ctl);
	580	+ if (ret < 0)
	581	+ return ret;
	582	+
	583	+ reset_free(&priv->rst_ctl);
	584	+
	585	+ ret = clk_disable(&priv->clk);
	586	+ if (ret < 0)
	587	+ return ret;
	588	+
	589	+ clk_free(&priv->clk);
	590	+
	591	+ return ret;
	592	+};
	593	+
	594	+static const struct dm_spi_ops stm32_spi_ops = {
	595	+ .claim_bus = stm32_spi_claim_bus,
	596	+ .release_bus = stm32_spi_release_bus,
	597	+ .set_mode = stm32_spi_set_mode,
	598	+ .set_speed = stm32_spi_set_speed,
	599	+ .xfer = stm32_spi_xfer,
	600	+};
	601	+
	602	+static const struct udevice_id stm32_spi_ids[] = {
	603	+ { .compatible = "st,stm32h7-spi", },
	604	+ { }
	605	+};
	606	+
	607	+U_BOOT_DRIVER(stm32_spi) = {
	608	+ .name = "stm32_spi",
	609	+ .id = UCLASS_SPI,
	610	+ .of_match = stm32_spi_ids,
	611	+ .ops = &stm32_spi_ops,
	612	+ .priv_auto_alloc_size = sizeof(struct stm32_spi_priv),
	613	+ .probe = stm32_spi_probe,
	614	+ .remove = stm32_spi_remove,
	615	+};