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Commit c6d88630158af79f5700c8bbc37972f511e84500

Authored by Alison Wang
Committed by Jason
1 parent aa0d99fc28
Exists in master and in 57 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf-6.6.52-2.2.0, emb_lf_v2022.04, emb_lf_v2023.04, emb_lf_v2024.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

ColdFire: Clean up checkpatch warnings for MCF523x 

Signed-off-by: Alison Wang <b18965@freescale.com>

Showing 5 changed files with 120 additions and 103 deletions Side-by-side Diff

arch/m68k/cpu/mcf523x/cpu.c
Diff comments   View file @ c6d8863
... ... @@ -3,7 +3,7 @@
3 3 * (C) Copyright 2000-2003
4 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 5 *
6   - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  6 + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
7 7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 8 *
9 9 * See file CREDITS for list of people who contributed to this
10 10  
11 11  
12 12  
13 13  
14 14  
... ... @@ -31,28 +31,29 @@
31 31 #include <netdev.h>
32 32  
33 33 #include <asm/immap.h>
  34 +#include <asm/io.h>
34 35  
35 36 DECLARE_GLOBAL_DATA_PTR;
36 37  
37 38 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
38 39 {
39   - volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
  40 + ccm_t *ccm = (ccm_t *) MMAP_CCM;
40 41  
41   - ccm->rcr = CCM_RCR_SOFTRST;
  42 + out_8(&ccm->rcr, CCM_RCR_SOFTRST);
42 43 /* we don't return! */
43 44 return 0;
44   -};
  45 +}
45 46  
46 47 int checkcpu(void)
47 48 {
48   - volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
  49 + ccm_t *ccm = (ccm_t *) MMAP_CCM;
49 50 u16 msk;
50 51 u16 id = 0;
51 52 u8 ver;
52 53  
53 54 puts("CPU: ");
54   - msk = (ccm->cir >> 6);
55   - ver = (ccm->cir & 0x003f);
  55 + msk = (in_be16(&ccm->cir) >> 6);
  56 + ver = (in_be16(&ccm->cir) & 0x003f);
56 57 switch (msk) {
57 58 case 0x31:
58 59 id = 5235;
59 60  
60 61  
61 62  
62 63  
... ... @@ -76,19 +77,21 @@
76 77 /* Called by macro WATCHDOG_RESET */
77 78 void watchdog_reset(void)
78 79 {
79   - volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
  80 + wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
80 81  
81   - wdp->sr = 0x5555; /* Count register */
  82 + /* Count register */
  83 + out_be16(&wdp->sr, 0x5555);
82 84 asm("nop");
83   - wdp->sr = 0xAAAA; /* Count register */
  85 + out_be16(&wdp->sr, 0xaaaa);
84 86 }
85 87  
86 88 int watchdog_disable(void)
87 89 {
88   - volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
  90 + wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
89 91  
90 92 /* UserManual, once the wdog is disabled, wdog cannot be re-enabled */
91   - wdp->cr |= WTM_WCR_HALTED; /* halted watchdog timer */
  93 + /* halted watchdog timer */
  94 + setbits_be16(&wdp->cr, WTM_WCR_HALTED);
92 95  
93 96 puts("WATCHDOG:disabled\n");
94 97 return (0);
95 98  
96 99  
... ... @@ -96,15 +99,15 @@
96 99  
97 100 int watchdog_init(void)
98 101 {
99   - volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
  102 + wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
100 103 u32 wdog_module = 0;
101 104  
102 105 /* set timeout and enable watchdog */
103 106 wdog_module = ((CONFIG_SYS_CLK / CONFIG_SYS_HZ) * CONFIG_WATCHDOG_TIMEOUT);
104 107 wdog_module |= (wdog_module / 8192);
105   - wdp->mr = wdog_module;
  108 + out_be16(&wdp->mr, wdog_module);
106 109  
107   - wdp->cr = WTM_WCR_EN;
  110 + out_be16(&wdp->cr, WTM_WCR_EN);
108 111 puts("WATCHDOG:enabled\n");
109 112  
110 113 return (0);
arch/m68k/cpu/mcf523x/cpu_init.c
Diff comments   View file @ c6d8863
... ... @@ -3,7 +3,7 @@
3 3 * (C) Copyright 2000-2003
4 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 5 *
6   - * (C) Copyright 2007 Freescale Semiconductor, Inc.
  6 + * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
7 7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 8 *
9 9 * See file CREDITS for list of people who contributed to this
... ... @@ -28,6 +28,7 @@
28 28 #include <common.h>
29 29 #include <watchdog.h>
30 30 #include <asm/immap.h>
  31 +#include <asm/io.h>
31 32  
32 33 #if defined(CONFIG_CMD_NET)
33 34 #include <config.h>
34 35  
35 36  
36 37  
37 38  
38 39  
39 40  
40 41  
41 42  
42 43  
43 44  
44 45  
... ... @@ -44,74 +45,74 @@
44 45 */
45 46 void cpu_init_f(void)
46 47 {
47   - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
48   - volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
49   - volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG;
50   - volatile scm_t *scm = (scm_t *) MMAP_SCM;
  48 + gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  49 + fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
  50 + wdog_t *wdog = (wdog_t *) MMAP_WDOG;
  51 + scm_t *scm = (scm_t *) MMAP_SCM;
51 52  
52 53 /* watchdog is enabled by default - disable the watchdog */
53 54 #ifndef CONFIG_WATCHDOG
54   - wdog->cr = 0;
  55 + out_be16(&wdog->cr, 0);
55 56 #endif
56 57  
57   - scm->rambar = (CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
  58 + out_be32(&scm->rambar, CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
58 59  
59 60 /* Port configuration */
60   - gpio->par_cs = 0;
  61 + out_8(&gpio->par_cs, 0);
61 62  
62 63 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
63   - fbcs->csar0 = CONFIG_SYS_CS0_BASE;
64   - fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
65   - fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
  64 + out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
  65 + out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
  66 + out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
66 67 #endif
67 68  
68 69 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
69   - gpio->par_cs |= GPIO_PAR_CS_CS1;
70   - fbcs->csar1 = CONFIG_SYS_CS1_BASE;
71   - fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
72   - fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
  70 + setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS1);
  71 + out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
  72 + out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
  73 + out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
73 74 #endif
74 75  
75 76 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
76   - gpio->par_cs |= GPIO_PAR_CS_CS2;
77   - fbcs->csar2 = CONFIG_SYS_CS2_BASE;
78   - fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
79   - fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
  77 + setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS2);
  78 + out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
  79 + out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
  80 + out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
80 81 #endif
81 82  
82 83 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
83   - gpio->par_cs |= GPIO_PAR_CS_CS3;
84   - fbcs->csar3 = CONFIG_SYS_CS3_BASE;
85   - fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
86   - fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
  84 + setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS3);
  85 + out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
  86 + out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
  87 + out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
87 88 #endif
88 89  
89 90 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
90   - gpio->par_cs |= GPIO_PAR_CS_CS4;
91   - fbcs->csar4 = CONFIG_SYS_CS4_BASE;
92   - fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
93   - fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
  91 + setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS4);
  92 + out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
  93 + out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
  94 + out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
94 95 #endif
95 96  
96 97 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
97   - gpio->par_cs |= GPIO_PAR_CS_CS5;
98   - fbcs->csar5 = CONFIG_SYS_CS5_BASE;
99   - fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
100   - fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
  98 + setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS5);
  99 + out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
  100 + out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
  101 + out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
101 102 #endif
102 103  
103 104 #if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && defined(CONFIG_SYS_CS6_CTRL))
104   - gpio->par_cs |= GPIO_PAR_CS_CS6;
105   - fbcs->csar6 = CONFIG_SYS_CS6_BASE;
106   - fbcs->cscr6 = CONFIG_SYS_CS6_CTRL;
107   - fbcs->csmr6 = CONFIG_SYS_CS6_MASK;
  105 + setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS6);
  106 + out_be32(&fbcs->csar6, CONFIG_SYS_CS6_BASE);
  107 + out_be32(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL);
  108 + out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK);
108 109 #endif
109 110  
110 111 #if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && defined(CONFIG_SYS_CS7_CTRL))
111   - gpio->par_cs |= GPIO_PAR_CS_CS7;
112   - fbcs->csar7 = CONFIG_SYS_CS7_BASE;
113   - fbcs->cscr7 = CONFIG_SYS_CS7_CTRL;
114   - fbcs->csmr7 = CONFIG_SYS_CS7_MASK;
  112 + setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS7);
  113 + out_be32(&fbcs->csar7, CONFIG_SYS_CS7_BASE);
  114 + out_be32(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL);
  115 + out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK);
115 116 #endif
116 117  
117 118 #ifdef CONFIG_FSL_I2C
118 119  
119 120  
120 121  
121 122  
... ... @@ -132,29 +133,33 @@
132 133  
133 134 void uart_port_conf(int port)
134 135 {
135   - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  136 + gpio_t *gpio = (gpio_t *) MMAP_GPIO;
136 137  
137 138 /* Setup Ports: */
138 139 switch (port) {
139 140 case 0:
140   - gpio->par_uart &= ~(GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
141   - gpio->par_uart |= (GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
  141 + clrbits_be16(&gpio->par_uart,
  142 + GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
  143 + setbits_be16(&gpio->par_uart,
  144 + GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
142 145 break;
143 146 case 1:
144   - gpio->par_uart &=
145   - ~(GPIO_PAR_UART_U1RXD_MASK | GPIO_PAR_UART_U1TXD_MASK);
146   - gpio->par_uart |=
147   - (GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD);
  147 + clrbits_be16(&gpio->par_uart,
  148 + GPIO_PAR_UART_U1RXD_MASK | GPIO_PAR_UART_U1TXD_MASK);
  149 + setbits_be16(&gpio->par_uart,
  150 + GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD);
148 151 break;
149 152 case 2:
150 153 #ifdef CONFIG_SYS_UART2_PRI_GPIO
151   - gpio->par_uart &= ~(GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
152   - gpio->par_uart |= (GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
  154 + clrbits_be16(&gpio->par_uart,
  155 + GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
  156 + setbits_be16(&gpio->par_uart,
  157 + GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
153 158 #elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
154   - gpio->feci2c &=
155   - ~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
156   - gpio->feci2c |=
157   - (GPIO_PAR_FECI2C_EMDC_U2TXD | GPIO_PAR_FECI2C_EMDIO_U2RXD);
  159 + clrbits_8(&gpio->par_feci2c,
  160 + GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
  161 + setbits_8(&gpio->par_feci2c,
  162 + GPIO_PAR_FECI2C_EMDC_U2TXD | GPIO_PAR_FECI2C_EMDIO_U2RXD);
158 163 #endif
159 164 break;
160 165 }
161 166  
162 167  
... ... @@ -163,15 +168,16 @@
163 168 #if defined(CONFIG_CMD_NET)
164 169 int fecpin_setclear(struct eth_device *dev, int setclear)
165 170 {
166   - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  171 + gpio_t *gpio = (gpio_t *) MMAP_GPIO;
167 172  
168 173 if (setclear) {
169   - gpio->par_feci2c |=
170   - (GPIO_PAR_FECI2C_EMDC_FECEMDC |
171   - GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
  174 + setbits_8(&gpio->par_feci2c,
  175 + GPIO_PAR_FECI2C_EMDC_FECEMDC |
  176 + GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
172 177 } else {
173   - gpio->par_feci2c &=
174   - ~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
  178 + clrbits_8(&gpio->par_feci2c,
  179 + GPIO_PAR_FECI2C_EMDC_MASK |
  180 + GPIO_PAR_FECI2C_EMDIO_MASK);
175 181 }
176 182  
177 183 return 0;
arch/m68k/cpu/mcf523x/interrupts.c
Diff comments   View file @ c6d8863
1 1 /*
2 2 *
3   - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  3 + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
4 4 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
5 5 *
6 6 * See file CREDITS for list of people who contributed to this
7 7  
8 8  
... ... @@ -25,13 +25,14 @@
25 25 /* CPU specific interrupt routine */
26 26 #include <common.h>
27 27 #include <asm/immap.h>
  28 +#include <asm/io.h>
28 29  
29 30 int interrupt_init(void)
30 31 {
31   - volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
  32 + int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
32 33  
33 34 /* Make sure all interrupts are disabled */
34   - intp->imrl0 |= 0x1;
  35 + setbits_be32(&intp->imrl0, 0x1);
35 36  
36 37 enable_interrupts();
37 38 return 0;
38 39  
... ... @@ -40,11 +41,11 @@
40 41 #if defined(CONFIG_MCFTMR)
41 42 void dtimer_intr_setup(void)
42 43 {
43   - volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
  44 + int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
44 45  
45   - intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
46   - intp->imrl0 &= ~INTC_IPRL_INT0;
47   - intp->imrl0 &= ~CONFIG_SYS_TMRINTR_MASK;
  46 + out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
  47 + clrbits_be32(&intp->imrl0, INTC_IPRL_INT0);
  48 + clrbits_be32(&intp->imrl0, CONFIG_SYS_TMRINTR_MASK);
48 49 }
49 50 #endif
arch/m68k/cpu/mcf523x/speed.c
Diff comments   View file @ c6d8863
... ... @@ -3,7 +3,7 @@
3 3 * (C) Copyright 2000-2003
4 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 5 *
6   - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  6 + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
7 7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 8 *
9 9 * See file CREDITS for list of people who contributed to this
... ... @@ -29,6 +29,7 @@
29 29 #include <asm/processor.h>
30 30  
31 31 #include <asm/immap.h>
  32 +#include <asm/io.h>
32 33  
33 34 DECLARE_GLOBAL_DATA_PTR;
34 35 /*
35 36  
36 37  
... ... @@ -36,11 +37,12 @@
36 37 */
37 38 int get_clocks(void)
38 39 {
39   - volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
  40 + pll_t *pll = (pll_t *)(MMAP_PLL);
40 41  
41   - pll->syncr = PLL_SYNCR_MFD(1);
  42 + out_be32(&pll->syncr, PLL_SYNCR_MFD(1));
42 43  
43   - while (!(pll->synsr & PLL_SYNSR_LOCK));
  44 + while (!(in_be32(&pll->synsr) & PLL_SYNSR_LOCK))
  45 + ;
44 46  
45 47 gd->bus_clk = CONFIG_SYS_CLK;
46 48 gd->cpu_clk = (gd->bus_clk * 2);
board/freescale/m5235evb/m5235evb.c
Diff comments   View file @ c6d8863
... ... @@ -2,7 +2,7 @@
2 2 * (C) Copyright 2000-2003
3 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 4 *
5   - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  5 + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
6 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 7 *
8 8 * See file CREDITS for list of people who contributed to this
... ... @@ -27,6 +27,7 @@
27 27 #include <config.h>
28 28 #include <common.h>
29 29 #include <asm/immap.h>
  30 +#include <asm/io.h>
30 31  
31 32 DECLARE_GLOBAL_DATA_PTR;
32 33  
... ... @@ -39,8 +40,8 @@
39 40  
40 41 phys_size_t initdram(int board_type)
41 42 {
42   - volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
43   - volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
  43 + sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
  44 + gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
44 45 u32 dramsize, i, dramclk;
45 46  
46 47 /*
47 48  
... ... @@ -48,14 +49,15 @@
48 49 * the port-size of SDRAM. In this case it is necessary to enable
49 50 * Data[15:0] on Port Address/Data.
50 51 */
51   - gpio->par_ad =
52   - GPIO_PAR_AD_ADDR23 | GPIO_PAR_AD_ADDR22 | GPIO_PAR_AD_ADDR21 |
53   - GPIO_PAR_AD_DATAL;
  52 + out_8(&gpio->par_ad,
  53 + GPIO_PAR_AD_ADDR23 | GPIO_PAR_AD_ADDR22 | GPIO_PAR_AD_ADDR21 |
  54 + GPIO_PAR_AD_DATAL);
54 55  
55 56 /* Initialize PAR to enable SDRAM signals */
56   - gpio->par_sdram =
57   - GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS | GPIO_PAR_SDRAM_SRAS |
58   - GPIO_PAR_SDRAM_SCKE | GPIO_PAR_SDRAM_SDCS(3);
  57 + out_8(&gpio->par_sdram,
  58 + GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS |
  59 + GPIO_PAR_SDRAM_SRAS | GPIO_PAR_SDRAM_SCKE |
  60 + GPIO_PAR_SDRAM_SDCS(3));
59 61  
60 62 dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
61 63 for (i = 0x13; i < 0x20; i++) {
62 64  
63 65  
64 66  
65 67  
... ... @@ -64,25 +66,28 @@
64 66 }
65 67 i--;
66 68  
67   - if (!(sdram->dacr0 & SDRAMC_DARCn_RE)) {
  69 + if (!(in_be32(&sdram->dacr0) & SDRAMC_DARCn_RE)) {
68 70 dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ);
69 71  
70 72 /* Initialize DRAM Control Register: DCR */
71   - sdram->dcr = SDRAMC_DCR_RTIM_9CLKS |
72   - SDRAMC_DCR_RTIM_6CLKS | SDRAMC_DCR_RC((15 * dramclk) >> 4);
  73 + out_be16(&sdram->dcr, SDRAMC_DCR_RTIM_9CLKS |
  74 + SDRAMC_DCR_RTIM_6CLKS |
  75 + SDRAMC_DCR_RC((15 * dramclk) >> 4));
73 76  
74 77 /* Initialize DACR0 */
75   - sdram->dacr0 =
76   - SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 |
77   - SDRAMC_DARCn_CBM_CMD20 | SDRAMC_DARCn_PS_32;
  78 + out_be32(&sdram->dacr0,
  79 + SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE) |
  80 + SDRAMC_DARCn_CASL_C1 | SDRAMC_DARCn_CBM_CMD20 |
  81 + SDRAMC_DARCn_PS_32);
78 82 asm("nop");
79 83  
80 84 /* Initialize DMR0 */
81   - sdram->dmr0 = ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V;
  85 + out_be32(&sdram->dmr0,
  86 + ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V);
82 87 asm("nop");
83 88  
84 89 /* Set IP (bit 3) in DACR */
85   - sdram->dacr0 |= SDRAMC_DARCn_IP;
  90 + setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IP);
86 91  
87 92 /* Wait 30ns to allow banks to precharge */
88 93 for (i = 0; i < 5; i++) {
... ... @@ -93,7 +98,7 @@
93 98 *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
94 99  
95 100 /* Set RE (bit 15) in DACR */
96   - sdram->dacr0 |= SDRAMC_DARCn_RE;
  101 + setbits_be32(&sdram->dacr0, SDRAMC_DARCn_RE);
97 102  
98 103 /* Wait for at least 8 auto refresh cycles to occur */
99 104 for (i = 0; i < 0x2000; i++) {
... ... @@ -101,7 +106,7 @@
101 106 }
102 107  
103 108 /* Finish the configuration by issuing the MRS. */
104   - sdram->dacr0 |= SDRAMC_DARCn_IMRS;
  109 + setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IMRS);
105 110 asm("nop");
106 111  
107 112 /* Write to the SDRAM Mode Register */