Eric Lee / smarc-uboot

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Commit a42789ade30eaf3595fafb61ade326dc24e6825a

Authored by BJ DevOps Team
2 parents 8f5a1be80b ebae18a52c
Exists in smarc_8mq_lf_v2020.04 and in 4 other branches pitx_8mp_lf_v2020.04, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mp_lf_v2020.04

Merge remote-tracking branch 'origin/imx_v2020.04' into lf_v2020.04 

* origin/imx_v2020.04:
  LF-3161-2 mx6ul: bee: Remove XN bit for bee enabled region
  LF-3161-1 arm: imx: Fix speculative instruction prefetch issue

Showing 2 changed files Inline Diff

arch/arm/mach-imx/cache.c
Diff comments   View file @ a42789a
1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright 2015 Freescale Semiconductor, Inc. 3 * Copyright 2015 Freescale Semiconductor, Inc.
4 */ 4 */
5 5
6 #include <common.h> 6 #include <common.h>
7 #include <cpu_func.h> 7 #include <cpu_func.h>
8 #include <asm/armv7.h> 8 #include <asm/armv7.h>
9 #include <asm/pl310.h> 9 #include <asm/pl310.h>
10 #include <asm/io.h> 10 #include <asm/io.h>
11 #include <asm/mach-imx/sys_proto.h> 11 #include <asm/mach-imx/sys_proto.h>
12 12
13 DECLARE_GLOBAL_DATA_PTR;
14
13 static void enable_ca7_smp(void) 15 static void enable_ca7_smp(void)
14 { 16 {
15 u32 val; 17 u32 val;
16 18
17 /* Read MIDR */ 19 /* Read MIDR */
18 asm volatile ("mrc p15, 0, %0, c0, c0, 0\n\t" : "=r"(val)); 20 asm volatile ("mrc p15, 0, %0, c0, c0, 0\n\t" : "=r"(val));
19 val = (val >> 4); 21 val = (val >> 4);
20 val &= 0xf; 22 val &= 0xf;
21 23
22 /* Only set the SMP for Cortex A7 */ 24 /* Only set the SMP for Cortex A7 */
23 if (val == 0x7) { 25 if (val == 0x7) {
24 /* Read auxiliary control register */ 26 /* Read auxiliary control register */
25 asm volatile ("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(val)); 27 asm volatile ("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(val));
26 28
27 if (val & (1 << 6)) 29 if (val & (1 << 6))
28 return; 30 return;
29 31
30 /* Enable SMP */ 32 /* Enable SMP */
31 val |= (1 << 6); 33 val |= (1 << 6);
32 34
33 /* Write auxiliary control register */ 35 /* Write auxiliary control register */
34 asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(val)); 36 asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(val));
35 37
36 DSB; 38 DSB;
37 ISB; 39 ISB;
38 } 40 }
39 } 41 }
40 42
41 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) 43 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
44
45 #define ARMV7_DOMAIN_CLIENT 1
46 #define ARMV7_DOMAIN_MASK (0x3 << 0)
47
42 void enable_caches(void) 48 void enable_caches(void)
43 { 49 {
44 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) 50 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
45 enum dcache_option option = DCACHE_WRITETHROUGH; 51 enum dcache_option option = DCACHE_WRITETHROUGH & ~TTB_SECT_XN_MASK;
46 #else 52 #else
47 enum dcache_option option = DCACHE_WRITEBACK; 53 enum dcache_option option = DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK;
48 #endif 54 #endif
49 /* Avoid random hang when download by usb */ 55 /* Avoid random hang when download by usb */
50 invalidate_dcache_all(); 56 invalidate_dcache_all();
51 57
52 /* Set ACTLR.SMP bit for Cortex-A7 */ 58 /* Set ACTLR.SMP bit for Cortex-A7 */
53 enable_ca7_smp(); 59 enable_ca7_smp();
54 60
55 /* Enable D-cache. I-cache is already enabled in start.S */ 61 /* Enable D-cache. I-cache is already enabled in start.S */
56 dcache_enable(); 62 dcache_enable();
57 63
58 /* Enable caching on OCRAM and ROM */ 64 /* Enable caching on OCRAM and ROM */
59 mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR, 65 mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
60 ROMCP_ARB_END_ADDR, 66 ROMCP_ARB_END_ADDR,
61 option); 67 option);
62 mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR, 68 mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
63 IRAM_SIZE, 69 IRAM_SIZE,
64 option); 70 option);
65 } 71 }
72
73 void dram_bank_mmu_setup(int bank)
74 {
75 bd_t *bd = gd->bd;
76 int i;
77
78 debug("%s: bank: %d\n", __func__, bank);
79 for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
80 i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) +
81 (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT);
82 i++) {
83 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
84 set_section_dcache(i, DCACHE_WRITETHROUGH & ~TTB_SECT_XN_MASK);
85 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
86 set_section_dcache(i, DCACHE_WRITEALLOC & ~TTB_SECT_XN_MASK);
87 #else
88 set_section_dcache(i, DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK);
89 #endif
90 }
91 }
92
93 void arm_init_domains(void)
94 {
95 u32 reg;
96
97 reg = get_dacr();
98 /*
99 * Set domain to client to do access and XN check
100 */
101 reg &= ~ARMV7_DOMAIN_MASK;
102 reg |= ARMV7_DOMAIN_CLIENT;
103 set_dacr(reg);
104 }
105
66 #else 106 #else
67 void enable_caches(void) 107 void enable_caches(void)
68 { 108 {
69 /* 109 /*
70 * Set ACTLR.SMP bit for Cortex-A7, even if the caches are 110 * Set ACTLR.SMP bit for Cortex-A7, even if the caches are
71 * disabled by u-boot 111 * disabled by u-boot
72 */ 112 */
73 enable_ca7_smp(); 113 enable_ca7_smp();
74 114
75 puts("WARNING: Caches not enabled\n"); 115 puts("WARNING: Caches not enabled\n");
76 } 116 }
77 #endif 117 #endif
78 118
79 #ifndef CONFIG_SYS_L2CACHE_OFF 119 #ifndef CONFIG_SYS_L2CACHE_OFF
80 #ifdef CONFIG_SYS_L2_PL310 120 #ifdef CONFIG_SYS_L2_PL310
81 #define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002 121 #define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
82 void v7_outer_cache_enable(void) 122 void v7_outer_cache_enable(void)
83 { 123 {
84 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE; 124 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
85 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 125 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
86 unsigned int val, cache_id; 126 unsigned int val, cache_id;
87 127
88 128
89 /* 129 /*
90 * Must disable the L2 before changing the latency parameters 130 * Must disable the L2 before changing the latency parameters
91 * and auxiliary control register. 131 * and auxiliary control register.
92 */ 132 */
93 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); 133 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
94 134
95 /* 135 /*
96 * Set bit 22 in the auxiliary control register. If this bit 136 * Set bit 22 in the auxiliary control register. If this bit
97 * is cleared, PL310 treats Normal Shared Non-cacheable 137 * is cleared, PL310 treats Normal Shared Non-cacheable
98 * accesses as Cacheable no-allocate. 138 * accesses as Cacheable no-allocate.
99 */ 139 */
100 setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE); 140 setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
101 141
102 if (is_mx6sl() || is_mx6sll()) { 142 if (is_mx6sl() || is_mx6sll()) {
103 val = readl(&iomux->gpr[11]); 143 val = readl(&iomux->gpr[11]);
104 if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) { 144 if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
105 /* L2 cache configured as OCRAM, reset it */ 145 /* L2 cache configured as OCRAM, reset it */
106 val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM; 146 val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
107 writel(val, &iomux->gpr[11]); 147 writel(val, &iomux->gpr[11]);
108 } 148 }
109 } 149 }
110 150
111 writel(0x132, &pl310->pl310_tag_latency_ctrl); 151 writel(0x132, &pl310->pl310_tag_latency_ctrl);
112 writel(0x132, &pl310->pl310_data_latency_ctrl); 152 writel(0x132, &pl310->pl310_data_latency_ctrl);
113 153
114 val = readl(&pl310->pl310_prefetch_ctrl); 154 val = readl(&pl310->pl310_prefetch_ctrl);
115 155
116 /* Turn on the L2 I/D prefetch, double linefill */ 156 /* Turn on the L2 I/D prefetch, double linefill */
117 /* Set prefetch offset with any value except 23 as per errata 765569 */ 157 /* Set prefetch offset with any value except 23 as per errata 765569 */
118 val |= 0x7000000f; 158 val |= 0x7000000f;
119 159
120 /* 160 /*
121 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 161 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
122 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL/SX/DQP 162 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL/SX/DQP
123 * is r3p2. 163 * is r3p2.
124 * But according to ARM PL310 errata: 752271 164 * But according to ARM PL310 errata: 752271
125 * ID: 752271: Double linefill feature can cause data corruption 165 * ID: 752271: Double linefill feature can cause data corruption
126 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2 166 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
127 * Workaround: The only workaround to this erratum is to disable the 167 * Workaround: The only workaround to this erratum is to disable the
128 * double linefill feature. This is the default behavior. 168 * double linefill feature. This is the default behavior.
129 */ 169 */
130 cache_id = readl(&pl310->pl310_cache_id); 170 cache_id = readl(&pl310->pl310_cache_id);
131 if (((cache_id & L2X0_CACHE_ID_PART_MASK) == L2X0_CACHE_ID_PART_L310) 171 if (((cache_id & L2X0_CACHE_ID_PART_MASK) == L2X0_CACHE_ID_PART_L310)
132 && ((cache_id & L2X0_CACHE_ID_RTL_MASK) < L2X0_CACHE_ID_RTL_R3P2)) 172 && ((cache_id & L2X0_CACHE_ID_RTL_MASK) < L2X0_CACHE_ID_RTL_R3P2))
133 val &= ~(1 << 30); 173 val &= ~(1 << 30);
134 writel(val, &pl310->pl310_prefetch_ctrl); 174 writel(val, &pl310->pl310_prefetch_ctrl);
135 175
136 val = readl(&pl310->pl310_power_ctrl); 176 val = readl(&pl310->pl310_power_ctrl);
137 val |= L2X0_DYNAMIC_CLK_GATING_EN; 177 val |= L2X0_DYNAMIC_CLK_GATING_EN;
138 val |= L2X0_STNDBY_MODE_EN; 178 val |= L2X0_STNDBY_MODE_EN;
139 writel(val, &pl310->pl310_power_ctrl); 179 writel(val, &pl310->pl310_power_ctrl);
140 180
141 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); 181 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
142 } 182 }
143 183
144 void v7_outer_cache_disable(void) 184 void v7_outer_cache_disable(void)
145 { 185 {
146 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE; 186 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
147 187
148 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); 188 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
149 } 189 }
150 #endif /* !CONFIG_SYS_L2_PL310 */ 190 #endif /* !CONFIG_SYS_L2_PL310 */
151 #endif /* !CONFIG_SYS_L2CACHE_OFF */ 191 #endif /* !CONFIG_SYS_L2CACHE_OFF */
152 192
arch/arm/mach-imx/mx6/bee.c
Diff comments   View file @ a42789a
1 /* 1 /*
2 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. 2 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
3 * Copyright 2018 NXP 3 * Copyright 2018 NXP
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 #include <asm/io.h> 8 #include <asm/io.h>
9 #include <asm/arch/mx6_bee.h> 9 #include <asm/arch/mx6_bee.h>
10 #include <linux/errno.h> 10 #include <linux/errno.h>
11 #include <asm/system.h> 11 #include <asm/system.h>
12 #include <common.h> 12 #include <common.h>
13 #include <command.h> 13 #include <command.h>
14 #include <fuse.h> 14 #include <fuse.h>
15 #include <asm/arch/sys_proto.h> 15 #include <asm/arch/sys_proto.h>
16 #include <cpu_func.h> 16 #include <cpu_func.h>
17 17
18 DECLARE_GLOBAL_DATA_PTR; 18 DECLARE_GLOBAL_DATA_PTR;
19 19
20 #if (defined(CONFIG_SYS_DCACHE_OFF) || defined(CONFIG_SYS_ICACHE_OFF)) 20 #if (defined(CONFIG_SYS_DCACHE_OFF) || defined(CONFIG_SYS_ICACHE_OFF))
21 #error "Bee needs Cache Open" 21 #error "Bee needs Cache Open"
22 #endif 22 #endif
23 23
24 struct bee_parameters { 24 struct bee_parameters {
25 int key_method; 25 int key_method;
26 int mode; 26 int mode;
27 u32 start1; 27 u32 start1;
28 u32 size1; 28 u32 size1;
29 u32 start2; 29 u32 start2;
30 u32 size2; 30 u32 size2;
31 }; 31 };
32 32
33 #define SOFT_KEY 0 33 #define SOFT_KEY 0
34 #define SNVS_KEY 1 34 #define SNVS_KEY 1
35 35
36 #define ECB_MODE 0 36 #define ECB_MODE 0
37 #define CTR_MODE 1 37 #define CTR_MODE 1
38 38
39 #define AES_REGION0_ADDR 0x10000000 39 #define AES_REGION0_ADDR 0x10000000
40 #define AES_REGION1_ADDR 0x30000000 40 #define AES_REGION1_ADDR 0x30000000
41 41
42 static struct bee_parameters para; 42 static struct bee_parameters para;
43 static int bee_inited; 43 static int bee_inited;
44 44
45 union key_soft { 45 union key_soft {
46 u8 s_key[16]; 46 u8 s_key[16];
47 u32 b_key[4]; 47 u32 b_key[4];
48 }; 48 };
49 49
50 union key_soft key_bad; 50 union key_soft key_bad;
51 51
52 /* software version */ 52 /* software version */
53 u8 hw_get_random_byte(void) 53 u8 hw_get_random_byte(void)
54 { 54 {
55 static u32 lcg_state; 55 static u32 lcg_state;
56 static u32 nb_soft = 9876543; 56 static u32 nb_soft = 9876543;
57 #define MAX_SOFT_RNG 1024 57 #define MAX_SOFT_RNG 1024
58 static const u32 a = 1664525; 58 static const u32 a = 1664525;
59 static const u32 c = 1013904223; 59 static const u32 c = 1013904223;
60 nb_soft = (nb_soft + 1) % MAX_SOFT_RNG; 60 nb_soft = (nb_soft + 1) % MAX_SOFT_RNG;
61 lcg_state = (a * lcg_state + c); 61 lcg_state = (a * lcg_state + c);
62 return (u8) (lcg_state >> 24); 62 return (u8) (lcg_state >> 24);
63 } 63 }
64 64
65 /* 65 /*
66 * Lock bee GPR0 bits 66 * Lock bee GPR0 bits
67 * Only reset can release these bits. 67 * Only reset can release these bits.
68 */ 68 */
69 static int bee_lock(void) 69 static int bee_lock(void)
70 { 70 {
71 int val; 71 int val;
72 72
73 val = readl(BEE_BASE_ADDR + GPR0); 73 val = readl(BEE_BASE_ADDR + GPR0);
74 val |= (GPR0_CTRL_CLK_EN_LOCK | GPR0_CTRL_SFTRST_N_LOCK | 74 val |= (GPR0_CTRL_CLK_EN_LOCK | GPR0_CTRL_SFTRST_N_LOCK |
75 GPR0_CTRL_AES_MODE_LOCK | GPR0_SEC_LEVEL_LOCK | 75 GPR0_CTRL_AES_MODE_LOCK | GPR0_SEC_LEVEL_LOCK |
76 GPR0_AES_KEY_SEL_LOCK | GPR0_BEE_ENABLE_LOCK); 76 GPR0_AES_KEY_SEL_LOCK | GPR0_BEE_ENABLE_LOCK);
77 writel(val, BEE_BASE_ADDR + GPR0); 77 writel(val, BEE_BASE_ADDR + GPR0);
78 78
79 return 0; 79 return 0;
80 } 80 }
81 81
82 /* Only check bee enable lock is enough */ 82 /* Only check bee enable lock is enough */
83 static int bee_locked(void) 83 static int bee_locked(void)
84 { 84 {
85 int val; 85 int val;
86 86
87 val = readl(BEE_BASE_ADDR + GPR0); 87 val = readl(BEE_BASE_ADDR + GPR0);
88 88
89 return val & GPR0_BEE_ENABLE_LOCK ? 1 : 0; 89 return val & GPR0_BEE_ENABLE_LOCK ? 1 : 0;
90 } 90 }
91 91
92 int bee_init(struct bee_parameters *p) 92 int bee_init(struct bee_parameters *p)
93 { 93 {
94 int i; 94 int i;
95 union key_soft *key = &key_bad; 95 union key_soft *key = &key_bad;
96 u32 value; 96 u32 value;
97 97
98 if (bee_locked()) { 98 if (bee_locked()) {
99 printf("BEE already enabled and locked.\n"); 99 printf("BEE already enabled and locked.\n");
100 return CMD_RET_FAILURE; 100 return CMD_RET_FAILURE;
101 } 101 }
102 102
103 /* CLKGATE, SFTRST */ 103 /* CLKGATE, SFTRST */
104 writel(GPR0_CTRL_CLK_EN | GPR0_CTRL_SFTRST_N, BEE_BASE_ADDR + GPR0); 104 writel(GPR0_CTRL_CLK_EN | GPR0_CTRL_SFTRST_N, BEE_BASE_ADDR + GPR0);
105 /* OFFSET_ADDR0 */ 105 /* OFFSET_ADDR0 */
106 writel(p->start1 >> 16, BEE_BASE_ADDR + GPR1); 106 writel(p->start1 >> 16, BEE_BASE_ADDR + GPR1);
107 /* 107 /*
108 * OFFSET_ADDR1 108 * OFFSET_ADDR1
109 * Default protect IRAM region, if what you want to protect 109 * Default protect IRAM region, if what you want to protect
110 * bigger that 512M which is the max size that one AES region 110 * bigger that 512M which is the max size that one AES region
111 * can protect, we need AES region 1 to cover. 111 * can protect, we need AES region 1 to cover.
112 */ 112 */
113 writel(p->start2 >> 16, BEE_BASE_ADDR + GPR2); 113 writel(p->start2 >> 16, BEE_BASE_ADDR + GPR2);
114 114
115 if (p->key_method == SOFT_KEY) { 115 if (p->key_method == SOFT_KEY) {
116 for (i = 0; i < 16; i++) 116 for (i = 0; i < 16; i++)
117 key->s_key[i] = hw_get_random_byte(); 117 key->s_key[i] = hw_get_random_byte();
118 /* AES 128 key from software */ 118 /* AES 128 key from software */
119 /* aes0_key0_w0 */ 119 /* aes0_key0_w0 */
120 writel(key->b_key[0], BEE_BASE_ADDR + GPR3); 120 writel(key->b_key[0], BEE_BASE_ADDR + GPR3);
121 /* aes0_key0_w1 */ 121 /* aes0_key0_w1 */
122 writel(key->b_key[1], BEE_BASE_ADDR + GPR4); 122 writel(key->b_key[1], BEE_BASE_ADDR + GPR4);
123 /* aes0_key0_w2 */ 123 /* aes0_key0_w2 */
124 writel(key->b_key[2], BEE_BASE_ADDR + GPR5); 124 writel(key->b_key[2], BEE_BASE_ADDR + GPR5);
125 /* aes0_key0_w3 */ 125 /* aes0_key0_w3 */
126 writel(key->b_key[3], BEE_BASE_ADDR + GPR6); 126 writel(key->b_key[3], BEE_BASE_ADDR + GPR6);
127 } 127 }
128 128
129 if (p->mode == ECB_MODE) { 129 if (p->mode == ECB_MODE) {
130 value = GPR0_CTRL_CLK_EN | GPR0_CTRL_SFTRST_N | 130 value = GPR0_CTRL_CLK_EN | GPR0_CTRL_SFTRST_N |
131 GPR0_SEC_LEVEL_3 | GPR0_AES_KEY_SEL_SNVS | 131 GPR0_SEC_LEVEL_3 | GPR0_AES_KEY_SEL_SNVS |
132 GPR0_BEE_ENABLE | GPR0_CTRL_AES_MODE_ECB; 132 GPR0_BEE_ENABLE | GPR0_CTRL_AES_MODE_ECB;
133 if (p->key_method == SOFT_KEY) 133 if (p->key_method == SOFT_KEY)
134 value = GPR0_CTRL_CLK_EN | GPR0_CTRL_SFTRST_N | 134 value = GPR0_CTRL_CLK_EN | GPR0_CTRL_SFTRST_N |
135 GPR0_SEC_LEVEL_3 | GPR0_AES_KEY_SEL_SOFT | 135 GPR0_SEC_LEVEL_3 | GPR0_AES_KEY_SEL_SOFT |
136 GPR0_BEE_ENABLE | GPR0_CTRL_AES_MODE_ECB; 136 GPR0_BEE_ENABLE | GPR0_CTRL_AES_MODE_ECB;
137 writel(value, BEE_BASE_ADDR + GPR0); 137 writel(value, BEE_BASE_ADDR + GPR0);
138 } else { 138 } else {
139 for (i = 0; i < 16; i++) 139 for (i = 0; i < 16; i++)
140 key->s_key[i] = hw_get_random_byte(); 140 key->s_key[i] = hw_get_random_byte();
141 /* aes_key1_w0 */ 141 /* aes_key1_w0 */
142 writel(key->b_key[0], BEE_BASE_ADDR + GPR8); 142 writel(key->b_key[0], BEE_BASE_ADDR + GPR8);
143 /* aes_key1_w1 */ 143 /* aes_key1_w1 */
144 writel(key->b_key[1], BEE_BASE_ADDR + GPR9); 144 writel(key->b_key[1], BEE_BASE_ADDR + GPR9);
145 /* aes_key1_w2 */ 145 /* aes_key1_w2 */
146 writel(key->b_key[2], BEE_BASE_ADDR + GPR10); 146 writel(key->b_key[2], BEE_BASE_ADDR + GPR10);
147 /* aes_key1_w3 */ 147 /* aes_key1_w3 */
148 writel(key->b_key[3], BEE_BASE_ADDR + GPR11); 148 writel(key->b_key[3], BEE_BASE_ADDR + GPR11);
149 149
150 value = GPR0_CTRL_CLK_EN | GPR0_CTRL_SFTRST_N | 150 value = GPR0_CTRL_CLK_EN | GPR0_CTRL_SFTRST_N |
151 GPR0_SEC_LEVEL_3 | GPR0_AES_KEY_SEL_SNVS | 151 GPR0_SEC_LEVEL_3 | GPR0_AES_KEY_SEL_SNVS |
152 GPR0_BEE_ENABLE | GPR0_CTRL_AES_MODE_CTR; 152 GPR0_BEE_ENABLE | GPR0_CTRL_AES_MODE_CTR;
153 if (p->key_method == SOFT_KEY) 153 if (p->key_method == SOFT_KEY)
154 value = GPR0_CTRL_CLK_EN | GPR0_CTRL_SFTRST_N | 154 value = GPR0_CTRL_CLK_EN | GPR0_CTRL_SFTRST_N |
155 GPR0_SEC_LEVEL_3 | GPR0_AES_KEY_SEL_SOFT | 155 GPR0_SEC_LEVEL_3 | GPR0_AES_KEY_SEL_SOFT |
156 GPR0_BEE_ENABLE | GPR0_CTRL_AES_MODE_CTR; 156 GPR0_BEE_ENABLE | GPR0_CTRL_AES_MODE_CTR;
157 writel(value, BEE_BASE_ADDR + GPR0); 157 writel(value, BEE_BASE_ADDR + GPR0);
158 } 158 }
159 159
160 bee_lock(); 160 bee_lock();
161 161
162 printf("BEE is settings as: %s mode, %s %d key\n", 162 printf("BEE is settings as: %s mode, %s %d key\n",
163 (p->mode == ECB_MODE) ? "ECB" : "CTR", 163 (p->mode == ECB_MODE) ? "ECB" : "CTR",
164 (p->key_method == SOFT_KEY) ? "SOFT" : "SNVS HW", 164 (p->key_method == SOFT_KEY) ? "SOFT" : "SNVS HW",
165 (p->mode == ECB_MODE) ? 128 : 256); 165 (p->mode == ECB_MODE) ? 128 : 256);
166 166
167 return CMD_RET_SUCCESS; 167 return CMD_RET_SUCCESS;
168 } 168 }
169 169
170 int bee_test(struct bee_parameters *p, int region) 170 int bee_test(struct bee_parameters *p, int region)
171 { 171 {
172 u32 result = 0, range, address; 172 u32 result = 0, range, address;
173 int i, val; 173 int i, val;
174 /* 174 /*
175 * Test instruction running in AES Region: 175 * Test instruction running in AES Region:
176 * int test(void) 176 * int test(void)
177 * { 177 * {
178 * return 0x55aa55aa; 178 * return 0x55aa55aa;
179 * } 179 * }
180 * Assemble: 180 * Assemble:
181 * 0xe59f0000: ldr r0, [pc] 181 * 0xe59f0000: ldr r0, [pc]
182 * 0xe12fff1e: bx lr 182 * 0xe12fff1e: bx lr
183 * 0x55aa55aa: 0x55aa55aa 183 * 0x55aa55aa: 0x55aa55aa
184 */ 184 */
185 u32 inst[3] = {0xe59f0000, 0xe12fff1e, 0x55aa55aa}; 185 u32 inst[3] = {0xe59f0000, 0xe12fff1e, 0x55aa55aa};
186 186
187 /* Cache enabled? */ 187 /* Cache enabled? */
188 if ((get_cr() & (CR_I | CR_C)) != (CR_I | CR_C)) { 188 if ((get_cr() & (CR_I | CR_C)) != (CR_I | CR_C)) {
189 printf("Enable dcache and icache first!\n"); 189 printf("Enable dcache and icache first!\n");
190 return CMD_RET_FAILURE; 190 return CMD_RET_FAILURE;
191 } 191 }
192 192
193 printf("Test Region %d\nBegin Data test: Writing... ", region); 193 printf("Test Region %d\nBegin Data test: Writing... ", region);
194 194
195 range = (region == 0) ? p->size1 : p->size2; 195 range = (region == 0) ? p->size1 : p->size2;
196 address = (region == 0) ? AES_REGION0_ADDR : AES_REGION1_ADDR; 196 address = (region == 0) ? AES_REGION0_ADDR : AES_REGION1_ADDR;
197 for (i = 0; i < range; i = i + 4) 197 for (i = 0; i < range; i = i + 4)
198 writel(i, address + i); 198 writel(i, address + i);
199 199
200 printf("Finshed Write!\n"); 200 printf("Finshed Write!\n");
201 201
202 flush_dcache_range(address, address + range); 202 flush_dcache_range(address, address + range);
203 203
204 printf("Reading... "); 204 printf("Reading... ");
205 for (i = 0; i < range; i = i + 4) { 205 for (i = 0; i < range; i = i + 4) {
206 val = readl(address + i); 206 val = readl(address + i);
207 if (val != i) 207 if (val != i)
208 result++; 208 result++;
209 } 209 }
210 printf("Finshed Read!\n"); 210 printf("Finshed Read!\n");
211 211
212 if (result > 0) 212 if (result > 0)
213 printf("BEE Data Test check Failed!\n"); 213 printf("BEE Data Test check Failed!\n");
214 else 214 else
215 printf("BEE Data Test Check Passed!\n"); 215 printf("BEE Data Test Check Passed!\n");
216 216
217 for (i = 0; i < ARRAY_SIZE(inst); i++) 217 for (i = 0; i < ARRAY_SIZE(inst); i++)
218 writel(inst[i], address + (i * 4)); 218 writel(inst[i], address + (i * 4));
219 219
220 flush_dcache_range(address, address + sizeof(inst)); 220 flush_dcache_range(address, address + sizeof(inst));
221 221
222 val = ((int (*)(void))address)(); 222 val = ((int (*)(void))address)();
223 223
224 printf("\nBee Instruction test, Program:\n" 224 printf("\nBee Instruction test, Program:\n"
225 "int test(void)\n" 225 "int test(void)\n"
226 "{\n" 226 "{\n"
227 " return 0x55aa55aa;\n" 227 " return 0x55aa55aa;\n"
228 "}\n" 228 "}\n"
229 "Assemble:\n" 229 "Assemble:\n"
230 "0xe59f0000: ldr r0, [pc]\n" 230 "0xe59f0000: ldr r0, [pc]\n"
231 "0xe12fff1e: bx lr\n" 231 "0xe12fff1e: bx lr\n"
232 "0x55aa55aa: 0x55aa55aa\n" 232 "0x55aa55aa: 0x55aa55aa\n"
233 "Runnint at 0x%x\n", address); 233 "Runnint at 0x%x\n", address);
234 if (val == 0x55aa55aa) 234 if (val == 0x55aa55aa)
235 printf("Bee Instruction Test Passed!\n"); 235 printf("Bee Instruction Test Passed!\n");
236 else 236 else
237 printf("Bee Instruction Test Failed!\n"); 237 printf("Bee Instruction Test Failed!\n");
238 238
239 return CMD_RET_SUCCESS; 239 return CMD_RET_SUCCESS;
240 } 240 }
241 241
242 static int region_valid(u32 start, u32 size) 242 static int region_valid(u32 start, u32 size)
243 { 243 {
244 if ((start < PHYS_SDRAM) || (start >= (start + size - 1)) || 244 if ((start < PHYS_SDRAM) || (start >= (start + size - 1)) ||
245 (start >= (PHYS_SDRAM + PHYS_SDRAM_SIZE - 1))) { 245 (start >= (PHYS_SDRAM + PHYS_SDRAM_SIZE - 1))) {
246 printf("Invalid start 0x%x, size 0x%x\n", start, size); 246 printf("Invalid start 0x%x, size 0x%x\n", start, size);
247 return -EINVAL; 247 return -EINVAL;
248 } 248 }
249 249
250 if (size > SZ_512M) { 250 if (size > SZ_512M) {
251 printf("The region size exceeds SZ_512M\n"); 251 printf("The region size exceeds SZ_512M\n");
252 return -EINVAL; 252 return -EINVAL;
253 } 253 }
254 254
255 if ((start & 0xFFFF) && (size & 0xFFFF)) { 255 if ((start & 0xFFFF) && (size & 0xFFFF)) {
256 printf("start or size not 64KB aligned!\n"); 256 printf("start or size not 64KB aligned!\n");
257 return -EINVAL; 257 return -EINVAL;
258 } 258 }
259 259
260 /* 128K for U-Boot Stack */ 260 /* 128K for U-Boot Stack */
261 if ((start + size - 1) >= (gd->start_addr_sp - SZ_128K)) { 261 if ((start + size - 1) >= (gd->start_addr_sp - SZ_128K)) {
262 printf("Overlap with uboot execution environment!\n" 262 printf("Overlap with uboot execution environment!\n"
263 "Decrease size or start\n"); 263 "Decrease size or start\n");
264 return -EINVAL; 264 return -EINVAL;
265 } 265 }
266 266
267 return 0; 267 return 0;
268 } 268 }
269 269
270 static int do_bee_init(cmd_tbl_t *cmdtp, int flag, int argc, 270 static int do_bee_init(cmd_tbl_t *cmdtp, int flag, int argc,
271 char * const argv[]) 271 char * const argv[])
272 { 272 {
273 u32 start, size; 273 u32 start, size;
274 int ret; 274 int ret;
275 struct bee_parameters *p = &para; 275 struct bee_parameters *p = &para;
276 276
277 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) 277 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
278 enum dcache_option option = DCACHE_WRITETHROUGH; 278 enum dcache_option option = DCACHE_WRITETHROUGH & ~TTB_SECT_XN_MASK;
279 #else 279 #else
280 enum dcache_option option = DCACHE_WRITEBACK; 280 enum dcache_option option = DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK;
281 #endif 281 #endif
282 282
283 if (argc > 5) 283 if (argc > 5)
284 return CMD_RET_USAGE; 284 return CMD_RET_USAGE;
285 285
286 #ifdef CONFIG_MX6 286 #ifdef CONFIG_MX6
287 if (check_module_fused(MX6_MODULE_BEE)) { 287 if (check_module_fused(MX6_MODULE_BEE)) {
288 printf("BEE is fused, disable it!\n"); 288 printf("BEE is fused, disable it!\n");
289 return CMD_RET_FAILURE; 289 return CMD_RET_FAILURE;
290 } 290 }
291 #endif 291 #endif
292 292
293 /* Cache enabled? */ 293 /* Cache enabled? */
294 if ((get_cr() & (CR_I | CR_C)) != (CR_I | CR_C)) { 294 if ((get_cr() & (CR_I | CR_C)) != (CR_I | CR_C)) {
295 /* 295 /*
296 * Here we need icache and dcache both enabled, because 296 * Here we need icache and dcache both enabled, because
297 * we may take the protected region for instruction and 297 * we may take the protected region for instruction and
298 * data usage. And icache and dcache both enabled are 298 * data usage. And icache and dcache both enabled are
299 * better for performance. 299 * better for performance.
300 */ 300 */
301 printf("Please enable dcache and icache first!\n"); 301 printf("Please enable dcache and icache first!\n");
302 return CMD_RET_FAILURE; 302 return CMD_RET_FAILURE;
303 } 303 }
304 304
305 p->key_method = SOFT_KEY; 305 p->key_method = SOFT_KEY;
306 p->mode = ECB_MODE; 306 p->mode = ECB_MODE;
307 p->start1 = PHYS_SDRAM; 307 p->start1 = PHYS_SDRAM;
308 p->size1 = SZ_512M; 308 p->size1 = SZ_512M;
309 p->start2 = IRAM_BASE_ADDR; 309 p->start2 = IRAM_BASE_ADDR;
310 p->size2 = IRAM_SIZE; 310 p->size2 = IRAM_SIZE;
311 311
312 if (argc == 2) { 312 if (argc == 2) {
313 p->key_method = (int)simple_strtoul(argv[1], NULL, 16); 313 p->key_method = (int)simple_strtoul(argv[1], NULL, 16);
314 p->mode = ECB_MODE; 314 p->mode = ECB_MODE;
315 p->start1 = PHYS_SDRAM; 315 p->start1 = PHYS_SDRAM;
316 p->size1 = SZ_512M; 316 p->size1 = SZ_512M;
317 } else if (argc == 3) { 317 } else if (argc == 3) {
318 p->key_method = (int)simple_strtoul(argv[1], NULL, 16); 318 p->key_method = (int)simple_strtoul(argv[1], NULL, 16);
319 p->mode = (int)simple_strtoul(argv[2], NULL, 10); 319 p->mode = (int)simple_strtoul(argv[2], NULL, 10);
320 p->start1 = PHYS_SDRAM; 320 p->start1 = PHYS_SDRAM;
321 p->size1 = SZ_512M; 321 p->size1 = SZ_512M;
322 } else if ((argc == 4) || (argc == 5)) { 322 } else if ((argc == 4) || (argc == 5)) {
323 p->key_method = (int)simple_strtoul(argv[1], NULL, 16); 323 p->key_method = (int)simple_strtoul(argv[1], NULL, 16);
324 p->mode = (int)simple_strtoul(argv[2], NULL, 10); 324 p->mode = (int)simple_strtoul(argv[2], NULL, 10);
325 start = (u32)simple_strtoul(argv[3], NULL, 16); 325 start = (u32)simple_strtoul(argv[3], NULL, 16);
326 /* Default size that AES Region0 can protected */ 326 /* Default size that AES Region0 can protected */
327 size = SZ_512M; 327 size = SZ_512M;
328 if (argc == 5) 328 if (argc == 5)
329 size = (u32)simple_strtoul(argv[4], NULL, 16); 329 size = (u32)simple_strtoul(argv[4], NULL, 16);
330 p->start1 = start; 330 p->start1 = start;
331 p->size1 = size; 331 p->size1 = size;
332 } 332 }
333 333
334 if ((p->key_method != SOFT_KEY) && (p->key_method != SNVS_KEY)) 334 if ((p->key_method != SOFT_KEY) && (p->key_method != SNVS_KEY))
335 return CMD_RET_USAGE; 335 return CMD_RET_USAGE;
336 336
337 if ((p->mode != ECB_MODE) && (p->mode != CTR_MODE)) 337 if ((p->mode != ECB_MODE) && (p->mode != CTR_MODE))
338 return CMD_RET_USAGE; 338 return CMD_RET_USAGE;
339 339
340 /* 340 /*
341 * No need to check region valid for IRAM, since it is fixed. 341 * No need to check region valid for IRAM, since it is fixed.
342 * Only check DRAM region here. 342 * Only check DRAM region here.
343 */ 343 */
344 if (region_valid(p->start1, p->size1)) 344 if (region_valid(p->start1, p->size1))
345 return CMD_RET_FAILURE; 345 return CMD_RET_FAILURE;
346 346
347 ret = bee_init(p); 347 ret = bee_init(p);
348 if (ret) 348 if (ret)
349 return CMD_RET_FAILURE; 349 return CMD_RET_FAILURE;
350 350
351 /* 351 /*
352 * Set DCACHE OFF to AES REGION0 and AES REGION1 first 352 * Set DCACHE OFF to AES REGION0 and AES REGION1 first
353 * to avoid possible unexcepted cache settings. 353 * to avoid possible unexcepted cache settings.
354 */ 354 */
355 mmu_set_region_dcache_behaviour(AES_REGION0_ADDR, SZ_1G, DCACHE_OFF); 355 mmu_set_region_dcache_behaviour(AES_REGION0_ADDR, SZ_1G, DCACHE_OFF);
356 356
357 mmu_set_region_dcache_behaviour(AES_REGION0_ADDR, p->size1, option); 357 mmu_set_region_dcache_behaviour(AES_REGION0_ADDR, p->size1, option);
358 358
359 mmu_set_region_dcache_behaviour(AES_REGION1_ADDR, p->size2, option); 359 mmu_set_region_dcache_behaviour(AES_REGION1_ADDR, p->size2, option);
360 360
361 printf("Access Region 0x%x - 0x%x to protect 0x%x - 0x%x\n" 361 printf("Access Region 0x%x - 0x%x to protect 0x%x - 0x%x\n"
362 "Do not directly access 0x%x - 0x%x\n" 362 "Do not directly access 0x%x - 0x%x\n"
363 "Access Region 0x%x - 0x%x to protect 0x%x - 0x%x\n" 363 "Access Region 0x%x - 0x%x to protect 0x%x - 0x%x\n"
364 "Do not directly access 0x%x - 0x%x\n", 364 "Do not directly access 0x%x - 0x%x\n",
365 AES_REGION0_ADDR, AES_REGION0_ADDR + p->size1 - 1, 365 AES_REGION0_ADDR, AES_REGION0_ADDR + p->size1 - 1,
366 p->start1, p->start1 + p->size1 - 1, 366 p->start1, p->start1 + p->size1 - 1,
367 p->start1, p->start1 + p->size1 - 1, 367 p->start1, p->start1 + p->size1 - 1,
368 AES_REGION1_ADDR, AES_REGION1_ADDR + p->size2 - 1, 368 AES_REGION1_ADDR, AES_REGION1_ADDR + p->size2 - 1,
369 p->start2, p->start2 + p->size2 - 1, 369 p->start2, p->start2 + p->size2 - 1,
370 p->start2, p->start2 + p->size2 - 1); 370 p->start2, p->start2 + p->size2 - 1);
371 371
372 bee_inited = 1; 372 bee_inited = 1;
373 373
374 return CMD_RET_SUCCESS; 374 return CMD_RET_SUCCESS;
375 } 375 }
376 376
377 static int do_bee_test(cmd_tbl_t *cmdtp, int flag, int argc, 377 static int do_bee_test(cmd_tbl_t *cmdtp, int flag, int argc,
378 char * const argv[]) 378 char * const argv[])
379 { 379 {
380 int ret; 380 int ret;
381 int region; 381 int region;
382 382
383 if (bee_inited == 0) { 383 if (bee_inited == 0) {
384 printf("Bee not initialized, run bee init first!\n"); 384 printf("Bee not initialized, run bee init first!\n");
385 return CMD_RET_FAILURE; 385 return CMD_RET_FAILURE;
386 } 386 }
387 if (argc > 2) 387 if (argc > 2)
388 return CMD_RET_USAGE; 388 return CMD_RET_USAGE;
389 389
390 region = 0; 390 region = 0;
391 if (argc == 2) 391 if (argc == 2)
392 region = (int)simple_strtoul(argv[1], NULL, 16); 392 region = (int)simple_strtoul(argv[1], NULL, 16);
393 /* Only two regions are supported, 0 and 1 */ 393 /* Only two regions are supported, 0 and 1 */
394 if (region >= 2) 394 if (region >= 2)
395 return CMD_RET_USAGE; 395 return CMD_RET_USAGE;
396 396
397 ret = bee_test(&para, region); 397 ret = bee_test(&para, region);
398 if (ret) 398 if (ret)
399 return CMD_RET_FAILURE; 399 return CMD_RET_FAILURE;
400 400
401 return CMD_RET_SUCCESS; 401 return CMD_RET_SUCCESS;
402 } 402 }
403 403
404 static cmd_tbl_t cmd_bmp_sub[] = { 404 static cmd_tbl_t cmd_bmp_sub[] = {
405 U_BOOT_CMD_MKENT(init, 5, 0, do_bee_init, "", ""), 405 U_BOOT_CMD_MKENT(init, 5, 0, do_bee_init, "", ""),
406 U_BOOT_CMD_MKENT(test, 2, 0, do_bee_test, "", ""), 406 U_BOOT_CMD_MKENT(test, 2, 0, do_bee_test, "", ""),
407 }; 407 };
408 408
409 static int do_bee_ops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 409 static int do_bee_ops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
410 { 410 {
411 cmd_tbl_t *c; 411 cmd_tbl_t *c;
412 412
413 c = find_cmd_tbl(argv[1], &cmd_bmp_sub[0], ARRAY_SIZE(cmd_bmp_sub)); 413 c = find_cmd_tbl(argv[1], &cmd_bmp_sub[0], ARRAY_SIZE(cmd_bmp_sub));
414 414
415 /* Drop off the 'bee' command argument */ 415 /* Drop off the 'bee' command argument */
416 argc--; 416 argc--;
417 argv++; 417 argv++;
418 418
419 if (c) 419 if (c)
420 return c->cmd(cmdtp, flag, argc, argv); 420 return c->cmd(cmdtp, flag, argc, argv);
421 else 421 else
422 return CMD_RET_USAGE; 422 return CMD_RET_USAGE;
423 } 423 }
424 424
425 U_BOOT_CMD( 425 U_BOOT_CMD(
426 bee, CONFIG_SYS_MAXARGS, 1, do_bee_ops, 426 bee, CONFIG_SYS_MAXARGS, 1, do_bee_ops,
427 "BEE function test", 427 "BEE function test",
428 "init [key] [mode] [start] [size] - BEE block initial\n" 428 "init [key] [mode] [start] [size] - BEE block initial\n"
429 " key: 0 | 1, 0 means software key, 1 means SNVS random key\n" 429 " key: 0 | 1, 0 means software key, 1 means SNVS random key\n"
430 " mode: 0 | 1, 0 means ECB mode, 1 means CTR mode\n" 430 " mode: 0 | 1, 0 means ECB mode, 1 means CTR mode\n"
431 " start: start address that you want to protect\n" 431 " start: start address that you want to protect\n"
432 " size: The size of the area that you want to protect\n" 432 " size: The size of the area that you want to protect\n"
433 " start and end(start + size) addr both should be 64KB aligned.\n" 433 " start and end(start + size) addr both should be 64KB aligned.\n"
434 "\n" 434 "\n"
435 " After initialization, the mapping:\n" 435 " After initialization, the mapping:\n"
436 " 1. [0x10000000 - (0x10000000 + size - 1)] <--->\n" 436 " 1. [0x10000000 - (0x10000000 + size - 1)] <--->\n"
437 " [start - (start + size - 1)]\n" 437 " [start - (start + size - 1)]\n"
438 " Here [start - (start + size -1)] is fixed mapping to\n" 438 " Here [start - (start + size -1)] is fixed mapping to\n"
439 " [0x10000000 - (0x10000000 + size - 1)], whatever start is.\n" 439 " [0x10000000 - (0x10000000 + size - 1)], whatever start is.\n"
440 " 2. [0x30000000 - (0x30000000 + IRAM_SIZE - 1)] <--->\n" 440 " 2. [0x30000000 - (0x30000000 + IRAM_SIZE - 1)] <--->\n"
441 " [IRAM_BASE_ADDR - (IRAM_BASE_ADDR + IRAM_SIZE - 1)]\n" 441 " [IRAM_BASE_ADDR - (IRAM_BASE_ADDR + IRAM_SIZE - 1)]\n"
442 "\n" 442 "\n"
443 " Note: Here we only use AES region 0 to protect the DRAM\n" 443 " Note: Here we only use AES region 0 to protect the DRAM\n"
444 " area that you specified, max size SZ_512M.\n" 444 " area that you specified, max size SZ_512M.\n"
445 " AES region 1 is used to protect IRAM area.\n" 445 " AES region 1 is used to protect IRAM area.\n"
446 " Example:\n" 446 " Example:\n"
447 " 1. bee init 1 1 0xa0000000 0x10000\n" 447 " 1. bee init 1 1 0xa0000000 0x10000\n"
448 " Access 0x10000000 - 0x10010000 to protect 0xa0000000 - 0xa0010000\n" 448 " Access 0x10000000 - 0x10010000 to protect 0xa0000000 - 0xa0010000\n"
449 " 2. bee init 1 1 0x80000000 0x20000\n" 449 " 2. bee init 1 1 0x80000000 0x20000\n"
450 " Access 0x10000000 - 0x10020000 to protect 0x80000000 - 0x80020000\n" 450 " Access 0x10000000 - 0x10020000 to protect 0x80000000 - 0x80020000\n"
451 "\n" 451 "\n"
452 " Default configuration if only `bee init` without any args:\n" 452 " Default configuration if only `bee init` without any args:\n"
453 " 1. software key\n" 453 " 1. software key\n"
454 " 2. ECB mode\n" 454 " 2. ECB mode\n"
455 " 3. Address protected:\n" 455 " 3. Address protected:\n"
456 " Remapped Region0: PHYS_SDRAM - PHYS_SDRAM + SZ_512M\n" 456 " Remapped Region0: PHYS_SDRAM - PHYS_SDRAM + SZ_512M\n"
457 " Remapped Region1: IRAM_BASE_ADDR - IRAM_BASE_ADDR + IRAM_SIZE\n" 457 " Remapped Region1: IRAM_BASE_ADDR - IRAM_BASE_ADDR + IRAM_SIZE\n"
458 " 4. Default Mapping for 6UL:\n" 458 " 4. Default Mapping for 6UL:\n"
459 " [0x10000000 - 0x2FFFFFFF] <-> [0x80000000 - 0x9FFFFFFF]\n" 459 " [0x10000000 - 0x2FFFFFFF] <-> [0x80000000 - 0x9FFFFFFF]\n"
460 " [0x30000000 - 0x3001FFFF] <-> [0x00900000 - 0x0091FFFF]\n" 460 " [0x30000000 - 0x3001FFFF] <-> [0x00900000 - 0x0091FFFF]\n"
461 "\n" 461 "\n"
462 "bee test [region] - BEE function test\n" 462 "bee test [region] - BEE function test\n"
463 " region: 0 | 1, 0 means region0, 1 means regions1\n" 463 " region: 0 | 1, 0 means region0, 1 means regions1\n"
464 ); 464 );
465 465
466 466