Eric Lee / smarc-uboot

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Commit a6c7ad2f65afaa717ba19cbf9d8d138b5f10ccf9

Authored by wdenk
1 parent ea909b7604
Exists in master and in 55 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

* Fix startup problems with VFD display on TRAB 

* Patch by Pierre Aubert, 20 Nov 2002
  Add driver for Epson SED13806 graphic controller.
  Add support for BMP logos in cfb_console driver.

Showing 21 changed files with 1000 additions and 104 deletions Side-by-side Diff

... ... @@ -2,6 +2,12 @@
2 2 Changes since for U-Boot 0.1.0:
3 3 ======================================================================
4 4  
  5 +* Fix startup problems with VFD display on TRAB
  6 +
  7 +* Patch by Pierre Aubert, 20 Nov 2002
  8 + Add driver for Epson SED13806 graphic controller.
  9 + Add support for BMP logos in cfb_console driver.
  10 +
5 11 * Added support for both PCMCIA slots (at the same time!) on MPC8xx
6 12  
7 13 * Patch by Rod Boyce, 21 Nov 2002:
... ... @@ -423,6 +423,9 @@
423 423 (requires CFG_CMD_DATE)
424 424 CONFIG_VIDEO_LOGO display Linux logo in
425 425 upper left corner
  426 + CONFIG_VIDEO_BMP_LOGO use bmp_logo.h instead of
  427 + linux_logo.h for logo.
  428 + Requires CONFIG_VIDEO_LOGO
426 429 CONFIG_CONSOLE_EXTRA_INFO
427 430 addional board info beside
428 431 the logo
... ... @@ -709,6 +712,12 @@
709 712 65536 (16bit) 314 317 31a
710 713 16,7 Mill (24bit) 315 318 31b
711 714 (i.e. setenv videomode 317; saveenv; reset;)
  715 +
  716 + CONFIG_VIDEO_SED13806
  717 + Enable Epson SED13806 driver. This driver supports 8bpp
  718 + and 16bpp modes defined by CONFIG_VIDEO_SED13806_8BPP
  719 + or CONFIG_VIDEO_SED13806_16BPP
  720 +
712 721  
713 722 - LCD Support: CONFIG_LCD
714 723  
board/MAI/bios_emulator/scitech/src/x86emu/makefile.cross
Diff comments   View file @ a6c7ad2
... ... @@ -30,6 +30,9 @@
30 30 #
31 31 #############################################################################
32 32  
  33 +CC = $(CROSS_COMPILE)gcc
  34 +AR = $(CROSS_COMPILE)ar
  35 +
33 36 TARGETLIB = libx86emu.a
34 37 TARGETDEBUGLIB =libx86emud.a
35 38  
36 39  
37 40  
38 41  
39 42  
40 43  
... ... @@ -54,27 +57,27 @@
54 57 all: $(TARGETLIB) $(TARGETDEBUGLIB)
55 58  
56 59 $(TARGETLIB): $(OBJS)
57   - ppc-elf32-ar rv $(TARGETLIB) $(OBJS)
  60 + $(AR) rv $(TARGETLIB) $(OBJS)
58 61  
59 62 $(TARGETDEBUGLIB): $(DEBUGOBJS)
60   - ppc-elf32-ar rv $(TARGETDEBUGLIB) $(DEBUGOBJS)
  63 + $(AR) rv $(TARGETDEBUGLIB) $(DEBUGOBJS)
61 64  
62 65 INCS = -I. -Ix86emu -I../../include
63 66 CFLAGS = -D__DRIVER__ -DFORCE_POST -D_CEXPORT= -DNO_LONG_LONG -Dprintk=printf -fsigned-char -fomit-frame-pointer -mrelocatable -ffixed-r14 -meabi -mrelocatable -ffixed-r14 -meabi
64 67 CDEBUGFLAGS = -DDEBUG
65 68  
66 69 .c.o:
67   - ppc-elf32-gcc -g -O2 -Wall -c $(CFLAGS) $(INCS) $*.c
  70 + $(CC) -g -O2 -Wall -c $(CFLAGS) $(INCS) $*.c
68 71  
69 72 .c.d:
70   - ppc-elf32-gcc -g -O2 -Wall -c -o$*.d $(CFLAGS) $(CDEBUGFLAGS) $(INCS) $*.c
  73 + $(CC) -g -O2 -Wall -c -o$*.d $(CFLAGS) $(CDEBUGFLAGS) $(INCS) $*.c
71 74  
72 75 .cpp.o:
73   - ppc-elf32-gcc -c $(CFLAGS) $(INCS) $*.cpp
  76 + $(CC) -c $(CFLAGS) $(INCS) $*.cpp
74 77  
75 78 clean:
76 79 rm -f *.a *.o *.d
77 80  
78 81 validate: validate.o libx86emu.a
79   - ppc-elf32-gcc -o validate validate.o -lx86emu -L.
  82 + $(CC) -o validate validate.o -lx86emu -L.
board/RPXClassic/Makefile
Diff comments   View file @ a6c7ad2
... ... @@ -25,7 +25,7 @@
25 25  
26 26 LIB = lib$(BOARD).a
27 27  
28   -OBJS = $(BOARD).o flash.o
  28 +OBJS = $(BOARD).o flash.o eccx.o
29 29  
30 30 $(LIB): .depend $(OBJS)
31 31 $(AR) crv $@ $^
board/RPXClassic/eccx.c
Diff comments   View file @ a6c7ad2
  1 +/*
  2 + * (C) Copyright 2002
  3 + * Stรคubli Faverges - <www.staubli.com>
  4 + * Pierre AUBERT p.aubert@staubli.com
  5 + *
  6 + * See file CREDITS for list of people who contributed to this
  7 + * project.
  8 + *
  9 + * This program is free software; you can redistribute it and/or
  10 + * modify it under the terms of the GNU General Public License as
  11 + * published by the Free Software Foundation; either version 2 of
  12 + * the License, or (at your option) any later version.
  13 + *
  14 + * This program is distributed in the hope that it will be useful,
  15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17 + * GNU General Public License for more details.
  18 + *
  19 + * You should have received a copy of the GNU General Public License
  20 + * along with this program; if not, write to the Free Software
  21 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 + * MA 02111-1307 USA
  23 + */
  24 +/* Video support for the ECCX daughter board */
  25 +
  26 +
  27 +#include <common.h>
  28 +#include <config.h>
  29 +
  30 +#ifdef CONFIG_VIDEO_SED13806
  31 +#include <sed13806.h>
  32 +
  33 +
  34 +
  35 +/* Screen configurations: the initialization of the SD13806 depends on
  36 + screen and on display mode. We handle only 8bpp and 16 bpp modes */
  37 +
  38 +/* ECCX board is supplied with a NEC NL6448BC20 screen */
  39 +#ifdef CONFIG_NEC_NL6448BC20
  40 +#define DISPLAY_WIDTH 640
  41 +#define DISPLAY_HEIGHT 480
  42 +
  43 +#ifdef CONFIG_VIDEO_SED13806_8BPP
  44 +static const S1D_REGS init_regs [] =
  45 +{
  46 + {0x0001,0x00}, // Miscellaneous Register
  47 + {0x01FC,0x00}, // Display Mode Register
  48 + {0x0004,0x1b}, // General IO Pins Configuration Register 0
  49 + {0x0005,0x00}, // General IO Pins Configuration Register 1
  50 + {0x0008,0xe5}, // General IO Pins Control Register 0
  51 + {0x0009,0x1f}, // General IO Pins Control Register 1
  52 + {0x0010,0x02}, // Memory Clock Configuration Register
  53 + {0x0014,0x10}, // LCD Pixel Clock Configuration Register
  54 + {0x0018,0x02}, // CRT/TV Pixel Clock Configuration Register
  55 + {0x001C,0x02}, // MediaPlug Clock Configuration Register
  56 + {0x001E,0x01}, // CPU To Memory Wait State Select Register
  57 + {0x0021,0x04}, // DRAM Refresh Rate Register
  58 + {0x002A,0x00}, // DRAM Timings Control Register 0
  59 + {0x002B,0x01}, // DRAM Timings Control Register 1
  60 + {0x0020,0x80}, // Memory Configuration Register
  61 + {0x0030,0x25}, // Panel Type Register
  62 + {0x0031,0x00}, // MOD Rate Register
  63 + {0x0032,0x4F}, // LCD Horizontal Display Width Register
  64 + {0x0034,0x13}, // LCD Horizontal Non-Display Period Register
  65 + {0x0035,0x01}, // TFT FPLINE Start Position Register
  66 + {0x0036,0x0B}, // TFT FPLINE Pulse Width Register
  67 + {0x0038,0xDF}, // LCD Vertical Display Height Register 0
  68 + {0x0039,0x01}, // LCD Vertical Display Height Register 1
  69 + {0x003A,0x2C}, // LCD Vertical Non-Display Period Register
  70 + {0x003B,0x00}, // TFT FPFRAME Start Position Register
  71 + {0x003C,0x01}, // TFT FPFRAME Pulse Width Register
  72 + {0x0040,0x03}, // LCD Display Mode Register
  73 + {0x0041,0x02}, // LCD Miscellaneous Register
  74 + {0x0042,0x00}, // LCD Display Start Address Register 0
  75 + {0x0043,0x00}, // LCD Display Start Address Register 1
  76 + {0x0044,0x00}, // LCD Display Start Address Register 2
  77 + {0x0046,0x40}, // LCD Memory Address Offset Register 0
  78 + {0x0047,0x01}, // LCD Memory Address Offset Register 1
  79 + {0x0048,0x00}, // LCD Pixel Panning Register
  80 + {0x004A,0x00}, // LCD Display FIFO High Threshold Control Register
  81 + {0x004B,0x00}, // LCD Display FIFO Low Threshold Control Register
  82 + {0x0050,0x4F}, // CRT/TV Horizontal Display Width Register
  83 + {0x0052,0x13}, // CRT/TV Horizontal Non-Display Period Register
  84 + {0x0053,0x01}, // CRT/TV HRTC Start Position Register
  85 + {0x0054,0x0B}, // CRT/TV HRTC Pulse Width Register
  86 + {0x0056,0xDF}, // CRT/TV Vertical Display Height Register 0
  87 + {0x0057,0x01}, // CRT/TV Vertical Display Height Register 1
  88 + {0x0058,0x2B}, // CRT/TV Vertical Non-Display Period Register
  89 + {0x0059,0x09}, // CRT/TV VRTC Start Position Register
  90 + {0x005A,0x01}, // CRT/TV VRTC Pulse Width Register
  91 + {0x005B,0x00}, // TV Output Control Register
  92 + {0x0060,0x03}, // CRT/TV Display Mode Register
  93 + {0x0062,0x00}, // CRT/TV Display Start Address Register 0
  94 + {0x0063,0x00}, // CRT/TV Display Start Address Register 1
  95 + {0x0064,0x00}, // CRT/TV Display Start Address Register 2
  96 + {0x0066,0x40}, // CRT/TV Memory Address Offset Register 0
  97 + {0x0067,0x01}, // CRT/TV Memory Address Offset Register 1
  98 + {0x0068,0x00}, // CRT/TV Pixel Panning Register
  99 + {0x006A,0x00}, // CRT/TV Display FIFO High Threshold Control Register
  100 + {0x006B,0x00}, // CRT/TV Display FIFO Low Threshold Control Register
  101 + {0x0070,0x00}, // LCD Ink/Cursor Control Register
  102 + {0x0071,0x00}, // LCD Ink/Cursor Start Address Register
  103 + {0x0072,0x00}, // LCD Cursor X Position Register 0
  104 + {0x0073,0x00}, // LCD Cursor X Position Register 1
  105 + {0x0074,0x00}, // LCD Cursor Y Position Register 0
  106 + {0x0075,0x00}, // LCD Cursor Y Position Register 1
  107 + {0x0076,0x00}, // LCD Ink/Cursor Blue Color 0 Register
  108 + {0x0077,0x00}, // LCD Ink/Cursor Green Color 0 Register
  109 + {0x0078,0x00}, // LCD Ink/Cursor Red Color 0 Register
  110 + {0x007A,0x1F}, // LCD Ink/Cursor Blue Color 1 Register
  111 + {0x007B,0x3F}, // LCD Ink/Cursor Green Color 1 Register
  112 + {0x007C,0x1F}, // LCD Ink/Cursor Red Color 1 Register
  113 + {0x007E,0x00}, // LCD Ink/Cursor FIFO Threshold Register
  114 + {0x0080,0x00}, // CRT/TV Ink/Cursor Control Register
  115 + {0x0081,0x00}, // CRT/TV Ink/Cursor Start Address Register
  116 + {0x0082,0x00}, // CRT/TV Cursor X Position Register 0
  117 + {0x0083,0x00}, // CRT/TV Cursor X Position Register 1
  118 + {0x0084,0x00}, // CRT/TV Cursor Y Position Register 0
  119 + {0x0085,0x00}, // CRT/TV Cursor Y Position Register 1
  120 + {0x0086,0x00}, // CRT/TV Ink/Cursor Blue Color 0 Register
  121 + {0x0087,0x00}, // CRT/TV Ink/Cursor Green Color 0 Register
  122 + {0x0088,0x00}, // CRT/TV Ink/Cursor Red Color 0 Register
  123 + {0x008A,0x1F}, // CRT/TV Ink/Cursor Blue Color 1 Register
  124 + {0x008B,0x3F}, // CRT/TV Ink/Cursor Green Color 1 Register
  125 + {0x008C,0x1F}, // CRT/TV Ink/Cursor Red Color 1 Register
  126 + {0x008E,0x00}, // CRT/TV Ink/Cursor FIFO Threshold Register
  127 + {0x0100,0x00}, // BitBlt Control Register 0
  128 + {0x0101,0x00}, // BitBlt Control Register 1
  129 + {0x0102,0x00}, // BitBlt ROP Code/Color Expansion Register
  130 + {0x0103,0x00}, // BitBlt Operation Register
  131 + {0x0104,0x00}, // BitBlt Source Start Address Register 0
  132 + {0x0105,0x00}, // BitBlt Source Start Address Register 1
  133 + {0x0106,0x00}, // BitBlt Source Start Address Register 2
  134 + {0x0108,0x00}, // BitBlt Destination Start Address Register 0
  135 + {0x0109,0x00}, // BitBlt Destination Start Address Register 1
  136 + {0x010A,0x00}, // BitBlt Destination Start Address Register 2
  137 + {0x010C,0x00}, // BitBlt Memory Address Offset Register 0
  138 + {0x010D,0x00}, // BitBlt Memory Address Offset Register 1
  139 + {0x0110,0x00}, // BitBlt Width Register 0
  140 + {0x0111,0x00}, // BitBlt Width Register 1
  141 + {0x0112,0x00}, // BitBlt Height Register 0
  142 + {0x0113,0x00}, // BitBlt Height Register 1
  143 + {0x0114,0x00}, // BitBlt Background Color Register 0
  144 + {0x0115,0x00}, // BitBlt Background Color Register 1
  145 + {0x0118,0x00}, // BitBlt Foreground Color Register 0
  146 + {0x0119,0x00}, // BitBlt Foreground Color Register 1
  147 + {0x01E0,0x00}, // Look-Up Table Mode Register
  148 + {0x01E2,0x00}, // Look-Up Table Address Register
  149 + {0x01E4,0x00}, // Look-Up Table Data Register
  150 + {0x01F0,0x10}, // Power Save Configuration Register
  151 + {0x01F1,0x00}, // Power Save Status Register
  152 + {0x01F4,0x00}, // CPU-to-Memory Access Watchdog Timer Register
  153 + {0x01FC,0x01}, // Display Mode Register
  154 + {0, 0}
  155 +};
  156 +#endif /* CONFIG_VIDEO_SED13806_8BPP */
  157 +
  158 +#ifdef CONFIG_VIDEO_SED13806_16BPP
  159 +
  160 +static const S1D_REGS init_regs [] =
  161 +{
  162 + {0x0001,0x00}, // Miscellaneous Register
  163 + {0x01FC,0x00}, // Display Mode Register
  164 + {0x0004,0x1b}, // General IO Pins Configuration Register 0
  165 + {0x0005,0x00}, // General IO Pins Configuration Register 1
  166 + {0x0008,0xe5}, // General IO Pins Control Register 0
  167 + {0x0009,0x1f}, // General IO Pins Control Register 1
  168 + {0x0010,0x02}, // Memory Clock Configuration Register
  169 + {0x0014,0x10}, // LCD Pixel Clock Configuration Register
  170 + {0x0018,0x02}, // CRT/TV Pixel Clock Configuration Register
  171 + {0x001C,0x02}, // MediaPlug Clock Configuration Register
  172 + {0x001E,0x01}, // CPU To Memory Wait State Select Register
  173 + {0x0021,0x04}, // DRAM Refresh Rate Register
  174 + {0x002A,0x00}, // DRAM Timings Control Register 0
  175 + {0x002B,0x01}, // DRAM Timings Control Register 1
  176 + {0x0020,0x80}, // Memory Configuration Register
  177 + {0x0030,0x25}, // Panel Type Register
  178 + {0x0031,0x00}, // MOD Rate Register
  179 + {0x0032,0x4F}, // LCD Horizontal Display Width Register
  180 + {0x0034,0x13}, // LCD Horizontal Non-Display Period Register
  181 + {0x0035,0x01}, // TFT FPLINE Start Position Register
  182 + {0x0036,0x0B}, // TFT FPLINE Pulse Width Register
  183 + {0x0038,0xDF}, // LCD Vertical Display Height Register 0
  184 + {0x0039,0x01}, // LCD Vertical Display Height Register 1
  185 + {0x003A,0x2C}, // LCD Vertical Non-Display Period Register
  186 + {0x003B,0x00}, // TFT FPFRAME Start Position Register
  187 + {0x003C,0x01}, // TFT FPFRAME Pulse Width Register
  188 + {0x0040,0x05}, // LCD Display Mode Register
  189 + {0x0041,0x02}, // LCD Miscellaneous Register
  190 + {0x0042,0x00}, // LCD Display Start Address Register 0
  191 + {0x0043,0x00}, // LCD Display Start Address Register 1
  192 + {0x0044,0x00}, // LCD Display Start Address Register 2
  193 + {0x0046,0x80}, // LCD Memory Address Offset Register 0
  194 + {0x0047,0x02}, // LCD Memory Address Offset Register 1
  195 + {0x0048,0x00}, // LCD Pixel Panning Register
  196 + {0x004A,0x00}, // LCD Display FIFO High Threshold Control Register
  197 + {0x004B,0x00}, // LCD Display FIFO Low Threshold Control Register
  198 + {0x0050,0x4F}, // CRT/TV Horizontal Display Width Register
  199 + {0x0052,0x13}, // CRT/TV Horizontal Non-Display Period Register
  200 + {0x0053,0x01}, // CRT/TV HRTC Start Position Register
  201 + {0x0054,0x0B}, // CRT/TV HRTC Pulse Width Register
  202 + {0x0056,0xDF}, // CRT/TV Vertical Display Height Register 0
  203 + {0x0057,0x01}, // CRT/TV Vertical Display Height Register 1
  204 + {0x0058,0x2B}, // CRT/TV Vertical Non-Display Period Register
  205 + {0x0059,0x09}, // CRT/TV VRTC Start Position Register
  206 + {0x005A,0x01}, // CRT/TV VRTC Pulse Width Register
  207 + {0x005B,0x00}, // TV Output Control Register
  208 + {0x0060,0x05}, // CRT/TV Display Mode Register
  209 + {0x0062,0x00}, // CRT/TV Display Start Address Register 0
  210 + {0x0063,0x00}, // CRT/TV Display Start Address Register 1
  211 + {0x0064,0x00}, // CRT/TV Display Start Address Register 2
  212 + {0x0066,0x80}, // CRT/TV Memory Address Offset Register 0
  213 + {0x0067,0x02}, // CRT/TV Memory Address Offset Register 1
  214 + {0x0068,0x00}, // CRT/TV Pixel Panning Register
  215 + {0x006A,0x00}, // CRT/TV Display FIFO High Threshold Control Register
  216 + {0x006B,0x00}, // CRT/TV Display FIFO Low Threshold Control Register
  217 + {0x0070,0x00}, // LCD Ink/Cursor Control Register
  218 + {0x0071,0x00}, // LCD Ink/Cursor Start Address Register
  219 + {0x0072,0x00}, // LCD Cursor X Position Register 0
  220 + {0x0073,0x00}, // LCD Cursor X Position Register 1
  221 + {0x0074,0x00}, // LCD Cursor Y Position Register 0
  222 + {0x0075,0x00}, // LCD Cursor Y Position Register 1
  223 + {0x0076,0x00}, // LCD Ink/Cursor Blue Color 0 Register
  224 + {0x0077,0x00}, // LCD Ink/Cursor Green Color 0 Register
  225 + {0x0078,0x00}, // LCD Ink/Cursor Red Color 0 Register
  226 + {0x007A,0x1F}, // LCD Ink/Cursor Blue Color 1 Register
  227 + {0x007B,0x3F}, // LCD Ink/Cursor Green Color 1 Register
  228 + {0x007C,0x1F}, // LCD Ink/Cursor Red Color 1 Register
  229 + {0x007E,0x00}, // LCD Ink/Cursor FIFO Threshold Register
  230 + {0x0080,0x00}, // CRT/TV Ink/Cursor Control Register
  231 + {0x0081,0x00}, // CRT/TV Ink/Cursor Start Address Register
  232 + {0x0082,0x00}, // CRT/TV Cursor X Position Register 0
  233 + {0x0083,0x00}, // CRT/TV Cursor X Position Register 1
  234 + {0x0084,0x00}, // CRT/TV Cursor Y Position Register 0
  235 + {0x0085,0x00}, // CRT/TV Cursor Y Position Register 1
  236 + {0x0086,0x00}, // CRT/TV Ink/Cursor Blue Color 0 Register
  237 + {0x0087,0x00}, // CRT/TV Ink/Cursor Green Color 0 Register
  238 + {0x0088,0x00}, // CRT/TV Ink/Cursor Red Color 0 Register
  239 + {0x008A,0x1F}, // CRT/TV Ink/Cursor Blue Color 1 Register
  240 + {0x008B,0x3F}, // CRT/TV Ink/Cursor Green Color 1 Register
  241 + {0x008C,0x1F}, // CRT/TV Ink/Cursor Red Color 1 Register
  242 + {0x008E,0x00}, // CRT/TV Ink/Cursor FIFO Threshold Register
  243 + {0x0100,0x00}, // BitBlt Control Register 0
  244 + {0x0101,0x00}, // BitBlt Control Register 1
  245 + {0x0102,0x00}, // BitBlt ROP Code/Color Expansion Register
  246 + {0x0103,0x00}, // BitBlt Operation Register
  247 + {0x0104,0x00}, // BitBlt Source Start Address Register 0
  248 + {0x0105,0x00}, // BitBlt Source Start Address Register 1
  249 + {0x0106,0x00}, // BitBlt Source Start Address Register 2
  250 + {0x0108,0x00}, // BitBlt Destination Start Address Register 0
  251 + {0x0109,0x00}, // BitBlt Destination Start Address Register 1
  252 + {0x010A,0x00}, // BitBlt Destination Start Address Register 2
  253 + {0x010C,0x00}, // BitBlt Memory Address Offset Register 0
  254 + {0x010D,0x00}, // BitBlt Memory Address Offset Register 1
  255 + {0x0110,0x00}, // BitBlt Width Register 0
  256 + {0x0111,0x00}, // BitBlt Width Register 1
  257 + {0x0112,0x00}, // BitBlt Height Register 0
  258 + {0x0113,0x00}, // BitBlt Height Register 1
  259 + {0x0114,0x00}, // BitBlt Background Color Register 0
  260 + {0x0115,0x00}, // BitBlt Background Color Register 1
  261 + {0x0118,0x00}, // BitBlt Foreground Color Register 0
  262 + {0x0119,0x00}, // BitBlt Foreground Color Register 1
  263 + {0x01E0,0x01}, // Look-Up Table Mode Register
  264 + {0x01E2,0x00}, // Look-Up Table Address Register
  265 + {0x01E4,0x00}, // Look-Up Table Data Register
  266 + {0x01F0,0x10}, // Power Save Configuration Register
  267 + {0x01F1,0x00}, // Power Save Status Register
  268 + {0x01F4,0x00}, // CPU-to-Memory Access Watchdog Timer Register
  269 + {0x01FC,0x01}, // Display Mode Register
  270 + {0, 0}
  271 +};
  272 +
  273 +#endif /* CONFIG_VIDEO_SED13806_16BPP */
  274 +#endif /* CONFIG_NEC_NL6448BC20 */
  275 +
  276 +
  277 +
  278 +#ifdef CONFIG_CONSOLE_EXTRA_INFO
  279 +
  280 +/*-----------------------------------------------------------------------------
  281 + * video_get_info_str -- setup a board string: type, speed, etc.
  282 + * line_number= location to place info string beside logo
  283 + * info= buffer for info string
  284 + *-----------------------------------------------------------------------------
  285 + */
  286 +void video_get_info_str (int line_number, char *info)
  287 +{
  288 + if (line_number == 1) {
  289 + strcpy (info, " RPXClassic board");
  290 + }
  291 + else {
  292 + info [0] = '\0';
  293 + }
  294 +
  295 +}
  296 +#endif
  297 +
  298 +/*-----------------------------------------------------------------------------
  299 + * board_video_init -- init de l'EPSON, config du CS
  300 + *-----------------------------------------------------------------------------
  301 + */
  302 +unsigned int board_video_init (void)
  303 +{
  304 + volatile immap_t *immap = (immap_t *)CFG_IMMR;
  305 + volatile memctl8xx_t *memctl = &immap->im_memctl;
  306 +
  307 + /* Program ECCX registers */
  308 + *(ECCX_CSR12) |= ECCX_860;
  309 + *(ECCX_CSR8) |= ECCX_BE | ECCX_CS2;
  310 + *(ECCX_CSR8) |= ECCX_ENEPSON;
  311 +
  312 + memctl->memc_or2 = SED13806_OR;
  313 + memctl->memc_br2 = SED13806_REG_ADDR | SED13806_ACCES;
  314 +
  315 + return (SED13806_REG_ADDR);
  316 +}
  317 +
  318 +/*-----------------------------------------------------------------------------
  319 + * board_validate_screen --
  320 + *-----------------------------------------------------------------------------
  321 + */
  322 +void board_validate_screen (unsigned int base)
  323 +{
  324 + /* Activate the panel bias power */
  325 + *(volatile unsigned char *)(base + REG_GPIO_CTRL) = 0x80;
  326 +}
  327 +/*-----------------------------------------------------------------------------
  328 + * board_get_regs --
  329 + *-----------------------------------------------------------------------------
  330 + */
  331 +const S1D_REGS *board_get_regs (void)
  332 +{
  333 + return (init_regs);
  334 +}
  335 +/*-----------------------------------------------------------------------------
  336 + * board_get_width --
  337 + *-----------------------------------------------------------------------------
  338 + */
  339 +int board_get_width (void)
  340 +{
  341 + return (DISPLAY_WIDTH);
  342 +}
  343 +
  344 +/*-----------------------------------------------------------------------------
  345 + * board_get_height --
  346 + *-----------------------------------------------------------------------------
  347 + */
  348 +int board_get_height (void)
  349 +{
  350 + return (DISPLAY_HEIGHT);
  351 +}
  352 +
  353 +#endif /* CONFIG_VIDEO_SED13806 */
board/eltec/bab7xx/asm_init.S
Diff comments   View file @ a6c7ad2
... ... @@ -24,7 +24,7 @@
24 24 */
25 25  
26 26 #include <config.h>
27   -#include <mpc75x.h>
  27 +#include <74xx_7xx.h>
28 28 #include <mpc106.h>
29 29 #include <version.h>
30 30  
... ... @@ -60,6 +60,12 @@
60 60  
61 61 int board_init ()
62 62 {
  63 +#if defined(CONFIG_MODEM_SUPPORT) && defined(CONFIG_VFD)
  64 + ulong size;
  65 + unsigned long addr;
  66 + extern void mem_malloc_init (ulong);
  67 + extern int drv_vfd_init(void);
  68 +#endif
63 69 DECLARE_GLOBAL_DATA_PTR;
64 70  
65 71 /* memory and cpu-speed are setup before relocation */
66 72  
... ... @@ -102,25 +108,24 @@
102 108 gd->bd->bi_boot_params = 0x0c000100;
103 109  
104 110 #ifdef CONFIG_MODEM_SUPPORT
105   - /* This stuff is needed by the CPLD to read keyboard data.
106   - * (Copied from the LCD initialization routine.)
107   - */
108   - if (rLCDCON1 == 0) {
109   - extern void init_grid_ctrl(void);
110   -
111   - rPCCON = (rPCCON & 0xFFFFFF00)| 0x000000AA;
112   - rPDCON = (rPDCON & 0xFFFFFF03)| 0x000000A8;
113   -#if 0
114   - rPDCON = (rPDCON & 0xFFFFFF00)| 0x000000AA;
  111 +#ifdef CONFIG_VFD
  112 +#ifndef PAGE_SIZE
  113 +#define PAGE_SIZE 4096
115 114 #endif
116   - rLCDCON2 = 0x000DC000;
117   - rLCDCON3 = 0x0051000A;
118   - rLCDCON4 = 0x00000001;
119   - rLCDCON5 = 0x00000440;
120   - rLCDCON1 = 0x00000B75;
121   -
122   - init_grid_ctrl();
123   - }
  115 + /*
  116 + * reserve memory for VFD display (always full pages)
  117 + */
  118 + /* armboot_real_end is defined in the board-specific linker script */
  119 + addr = (_armboot_real_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
  120 + size = vfd_setmem (addr);
  121 + gd->fb_base = addr;
  122 + /* round to the next page boundary */
  123 + addr += size;
  124 + addr = (addr + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
  125 + mem_malloc_init (addr);
  126 + /* must do this after the framebuffer is allocated */
  127 + drv_vfd_init();
  128 +#endif /* CONFIG_VFD */
124 129  
125 130 udelay_no_timer (KBD_MDELAY);
126 131  
... ... @@ -339,8 +339,13 @@
339 339 int drv_vfd_init(void)
340 340 {
341 341 ulong palette;
  342 + static int vfd_init_done = 0;
342 343  
343 344 DECLARE_GLOBAL_DATA_PTR;
  345 +
  346 + if (vfd_init_done != 0)
  347 + return;
  348 + vfd_init_done = 1;
344 349  
345 350 vfdbase = gd->fb_base;
346 351 create_vfd_table();
... ... @@ -2062,7 +2062,7 @@
2062 2062 /*
2063 2063 * Power On.
2064 2064 */
2065   - printf("\n Slot %c:", 'A' + slot);
  2065 + printf("%s Slot %c:", slot ? "" : "\n", 'A' + slot);
2066 2066 mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
2067 2067 reg = pcmp->pcmc_pipr;
2068 2068 debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
... ... @@ -177,7 +177,7 @@
177 177 #ifdef CONFIG_LCD
178 178 drv_lcd_init ();
179 179 #endif
180   -#ifdef CONFIG_VIDEO
  180 +#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
181 181 drv_video_init ();
182 182 #endif
183 183 #ifdef CONFIG_WL_4PPM_KEYBOARD
... ... @@ -21,6 +21,8 @@
21 21 * MA 02111-1307 USA
22 22 */
23 23  
  24 +/* #define DEBUG */
  25 +
24 26 #include <common.h>
25 27 #include <watchdog.h>
26 28 #include <command.h>
... ... @@ -304,9 +306,7 @@
304 306 s = getenv ("bootdelay");
305 307 bootdelay = s ? (int)simple_strtol(s, NULL, 10) : CONFIG_BOOTDELAY;
306 308  
307   -#if 0
308   - printf ("### main_loop entered:\n\n");
309   -#endif
  309 + debug ("### main_loop entered: bootdelay=%d\n\n", bootdelay);
310 310  
311 311 # ifdef CONFIG_BOOT_RETRY_TIME
312 312 s = getenv ("bootretry");
... ... @@ -319,6 +319,9 @@
319 319 # endif /* CONFIG_BOOT_RETRY_TIME */
320 320  
321 321 s = getenv ("bootcmd");
  322 +
  323 + debug ("### main_loop: bootcmd=\"%s\"\n", s ? s : "<UNDEFINED>");
  324 +
322 325 if (bootdelay >= 0 && s && !abortboot (bootdelay)) {
323 326 # ifdef CONFIG_AUTOBOOT_KEYED
324 327 int prev = disable_ctrlc(1); /* disable Control C checking */
325 328  
... ... @@ -337,11 +340,9 @@
337 340 }
338 341  
339 342 # ifdef CONFIG_MENUKEY
340   - if (menukey == CONFIG_MENUKEY)
341   - {
  343 + if (menukey == CONFIG_MENUKEY) {
342 344 s = getenv("menucmd");
343   - if (s)
344   - {
  345 + if (s) {
345 346 # ifndef CFG_HUSH_PARSER
346 347 run_command (s, bd, 0);
347 348 # else
... ... @@ -31,7 +31,7 @@
31 31 cfb_console.o cs8900.o dc2114x.o eepro100.o \
32 32 i8042.o natsemi.o ns16550.o ns8382x.o ns87308.o \
33 33 pci.o pci_auto.o pci_indirect.o \
34   - pcnet.o serial.o \
  34 + pcnet.o sed13806.o serial.o \
35 35 smc91111.o smiLynxEM.o sym53c8xx.o \
36 36 tigon3.o w83c553f.o ct69000.o
37 37  
drivers/cfb_console.c
Diff comments   View file @ a6c7ad2
... ... @@ -65,6 +65,7 @@
65 65 CONFIG_CONSOLE_TIME - display time/date in upper right corner,
66 66 needs CFG_CMD_DATE and CONFIG_CONSOLE_CURSOR
67 67 CONFIG_VIDEO_LOGO - display Linux Logo in upper left corner
  68 + CONFIG_VIDEO_BMP_LOGO - use bmp_logo instead of linux_logo
68 69 CONFIG_CONSOLE_EXTRA_INFO - display additional board information strings
69 70 that normaly goes to serial port. This define
70 71 requires a board specific function:
... ... @@ -93,6 +94,8 @@
93 94  
94 95 #ifdef CONFIG_CFB_CONSOLE
95 96  
  97 +#include <malloc.h>
  98 +
96 99 /*****************************************************************************/
97 100 /* Console device defines with SMI graphic */
98 101 /* Any other graphic must change this section */
... ... @@ -116,6 +119,16 @@
116 119 #endif
117 120  
118 121 /*****************************************************************************/
  122 +/* Defines for the SED13806 driver */
  123 +/*****************************************************************************/
  124 +#ifdef CONFIG_VIDEO_SED13806
  125 +
  126 +#define VIDEO_FB_LITTLE_ENDIAN
  127 +#define VIDEO_HW_RECTFILL
  128 +#define VIDEO_HW_BITBLT
  129 +#endif
  130 +
  131 +/*****************************************************************************/
119 132 /* Include video_fb.h after definitions of VIDEO_HW_RECTFILL etc */
120 133 /*****************************************************************************/
121 134 #include <video_fb.h>
... ... @@ -217,6 +230,14 @@
217 230 #endif /* CONFIG_VIDEO_HW_CURSOR */
218 231  
219 232 #ifdef CONFIG_VIDEO_LOGO
  233 +#ifdef CONFIG_VIDEO_BMP_LOGO
  234 +#include <bmp_logo.h>
  235 +#define VIDEO_LOGO_WIDTH BMP_LOGO_WIDTH
  236 +#define VIDEO_LOGO_HEIGHT BMP_LOGO_HEIGHT
  237 +#define VIDEO_LOGO_LUT_OFFSET BMP_LOGO_OFFSET
  238 +#define VIDEO_LOGO_COLORS BMP_LOGO_COLORS
  239 +
  240 +#else /* CONFIG_VIDEO_BMP_LOGO */
220 241 #define LINUX_LOGO_WIDTH 80
221 242 #define LINUX_LOGO_HEIGHT 80
222 243 #define LINUX_LOGO_COLORS 214
223 244  
224 245  
... ... @@ -225,13 +246,15 @@
225 246 #include <linux_logo.h>
226 247 #define VIDEO_LOGO_WIDTH LINUX_LOGO_WIDTH
227 248 #define VIDEO_LOGO_HEIGHT LINUX_LOGO_HEIGHT
228   -
  249 +#define VIDEO_LOGO_LUT_OFFSET LINUX_LOGO_LUT_OFFSET
  250 +#define VIDEO_LOGO_COLORS LINUX_LOGO_COLORS
  251 +#endif /* CONFIG_VIDEO_BMP_LOGO */
229 252 #define VIDEO_INFO_X (VIDEO_LOGO_WIDTH)
230 253 #define VIDEO_INFO_Y (VIDEO_FONT_HEIGHT/2)
231   -#else
  254 +#else /* CONFIG_VIDEO_LOGO */
232 255 #define VIDEO_LOGO_WIDTH 0
233 256 #define VIDEO_LOGO_HEIGHT 0
234   -#endif
  257 +#endif /* CONFIG_VIDEO_LOGO */
235 258  
236 259 #define VIDEO_COLS VIDEO_VISIBLE_COLS
237 260 #define VIDEO_ROWS VIDEO_VISIBLE_ROWS
238 261  
... ... @@ -463,11 +486,7 @@
463 486  
464 487 static void video_putchar(int xx, int yy, unsigned char c)
465 488 {
466   -#ifdef CONFIG_VIDEO_LOGO
467 489 video_drawchars (xx, yy + VIDEO_LOGO_HEIGHT, &c, 1);
468   -#else
469   - video_drawchars (xx, yy, &c, 1);
470   -#endif
471 490 }
472 491  
473 492 /*****************************************************************************/
474 493  
475 494  
476 495  
477 496  
478 497  
479 498  
480 499  
481 500  
482 501  
483 502  
484 503  
485 504  
486 505  
487 506  
488 507  
489 508  
... ... @@ -676,83 +695,107 @@
676 695 #ifdef CONFIG_VIDEO_LOGO
677 696 void logo_plot (void *screen, int width, int x, int y)
678 697 {
679   - int skip = (width - LINUX_LOGO_WIDTH) * VIDEO_PIXEL_SIZE,
  698 +
  699 + int skip = (width - VIDEO_LOGO_WIDTH) * VIDEO_PIXEL_SIZE,
680 700 xcount, i,
681   - ycount = LINUX_LOGO_HEIGHT;
  701 + ycount = VIDEO_LOGO_HEIGHT;
682 702 unsigned char
683   - *source = linux_logo,
  703 + *source,
684 704 *dest = (unsigned char *) screen + ((y * width * VIDEO_PIXEL_SIZE) + x),
685   - r, g, b;
  705 + r, g, b, *logo_red, *logo_blue, *logo_green;
686 706  
  707 +#ifdef CONFIG_VIDEO_BMP_LOGO
  708 + source = bmp_logo_bitmap;
  709 +
  710 + /* Allocate temporary space for computing colormap */
  711 + logo_red = malloc (BMP_LOGO_COLORS);
  712 + logo_green = malloc (BMP_LOGO_COLORS);
  713 + logo_blue = malloc (BMP_LOGO_COLORS);
  714 + /* Compute color map */
  715 + for (i = 0; i < VIDEO_LOGO_COLORS; i++) {
  716 + logo_red [i] = (bmp_logo_palette [i] & 0x0f00) >> 4;
  717 + logo_green [i] = (bmp_logo_palette [i] & 0x00f0);
  718 + logo_blue [i] = (bmp_logo_palette [i] & 0x000f) << 4;
  719 + }
  720 +#else
  721 + source = linux_logo;
  722 + logo_red = linux_logo_red;
  723 + logo_green = linux_logo_green;
  724 + logo_blue = linux_logo_blue;
  725 +#endif
  726 +
687 727 if (VIDEO_DATA_FORMAT == GDF__8BIT_INDEX)
688 728 {
689   - for (i = 0; i < LINUX_LOGO_COLORS; i++)
  729 + for (i = 0; i < VIDEO_LOGO_COLORS; i++)
690 730 {
691   - r = (unsigned char)linux_logo_red [i];
692   - g = (unsigned char)linux_logo_green[i];
693   - b = (unsigned char)linux_logo_blue [i];
694   - video_set_lut (LINUX_LOGO_LUT_OFFSET + i, r, g, b);
  731 + video_set_lut (i + VIDEO_LOGO_LUT_OFFSET,
  732 + logo_red [i], logo_green [i], logo_blue [i]);
695 733 }
696 734 }
697 735  
698 736 while (ycount--)
699 737 {
700   - xcount = LINUX_LOGO_WIDTH;
701   - while (xcount--)
702   - {
703   - r = (unsigned char)linux_logo_red [*source - LINUX_LOGO_LUT_OFFSET];
704   - g = (unsigned char)linux_logo_green[*source - LINUX_LOGO_LUT_OFFSET];
705   - b = (unsigned char)linux_logo_blue [*source - LINUX_LOGO_LUT_OFFSET];
706   -
707   - switch (VIDEO_DATA_FORMAT)
  738 + xcount = VIDEO_LOGO_WIDTH;
  739 + while (xcount--)
708 740 {
709   - case GDF__8BIT_INDEX:
710   - *dest = *source;
711   - break;
712   - case GDF__8BIT_332RGB:
713   - *dest = ((r>>5)<<5) | ((g>>5)<<2) | (b>>6);
714   - break;
715   - case GDF_15BIT_555RGB:
716   - *(unsigned short *)dest =
717   - SWAP16((unsigned short)(((r>>3)<<10) | ((g>>3)<<5) | (b>>3)));
718   - break;
719   - case GDF_16BIT_565RGB:
720   - *(unsigned short *)dest =
721   - SWAP16((unsigned short)(((r>>3)<<11) | ((g>>2)<<5) | (b>>3)));
722   - break;
723   - case GDF_32BIT_X888RGB:
724   - *(unsigned long *)dest =
725   - SWAP32((unsigned long)((r<<16) | (g<<8) | b));
726   - break;
727   - case GDF_24BIT_888RGB:
  741 + r = logo_red [*source - VIDEO_LOGO_LUT_OFFSET];
  742 + g = logo_green [*source - VIDEO_LOGO_LUT_OFFSET];
  743 + b = logo_blue [*source - VIDEO_LOGO_LUT_OFFSET];
  744 +
  745 + switch (VIDEO_DATA_FORMAT)
  746 + {
  747 + case GDF__8BIT_INDEX:
  748 + *dest = *source;
  749 + break;
  750 + case GDF__8BIT_332RGB:
  751 + *dest = ((r>>5)<<5) | ((g>>5)<<2) | (b>>6);
  752 + break;
  753 + case GDF_15BIT_555RGB:
  754 + *(unsigned short *)dest =
  755 + SWAP16((unsigned short)(((r>>3)<<10) | ((g>>3)<<5) | (b>>3)));
  756 + break;
  757 + case GDF_16BIT_565RGB:
  758 + *(unsigned short *)dest =
  759 + SWAP16((unsigned short)(((r>>3)<<11) | ((g>>2)<<5) | (b>>3)));
  760 + break;
  761 + case GDF_32BIT_X888RGB:
  762 + *(unsigned long *)dest =
  763 + SWAP32((unsigned long)((r<<16) | (g<<8) | b));
  764 + break;
  765 + case GDF_24BIT_888RGB:
728 766 #ifdef VIDEO_FB_LITTLE_ENDIAN
729   - dest[0] = b;
730   - dest[1] = g;
731   - dest[2] = r;
  767 + dest[0] = b;
  768 + dest[1] = g;
  769 + dest[2] = r;
732 770 #else
733   - dest[0] = r;
734   - dest[1] = g;
735   - dest[2] = b;
  771 + dest[0] = r;
  772 + dest[1] = g;
  773 + dest[2] = b;
736 774 #endif
737   - break;
  775 + break;
  776 + }
  777 + source++;
  778 + dest += VIDEO_PIXEL_SIZE;
738 779 }
739   - source++;
740   - dest += VIDEO_PIXEL_SIZE;
  780 + dest += skip;
741 781 }
742   - dest += skip;
743   - }
  782 +#ifdef CONFIG_VIDEO_BMP_LOGO
  783 + free (logo_red);
  784 + free (logo_green);
  785 + free (logo_blue);
  786 +#endif
744 787 }
745 788  
746   -
747 789 /*****************************************************************************/
748 790  
749 791 static void *video_logo (void)
750 792 {
751 793 char info[128];
  794 + extern char version_string;
752 795  
753 796 logo_plot (video_fb_address, VIDEO_COLS, 0, 0);
754 797  
755   - sprintf(info, " %s (%s - %s)", U_BOOT_VERSION, __DATE__, __TIME__);
  798 + sprintf(info, " %s", &version_string);
756 799 video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y, info);
757 800  
758 801 #ifdef CONFIG_CONSOLE_EXTRA_INFO
  1 +/*
  2 + * (C) Copyright 2002
  3 + * Stรคubli Faverges - <www.staubli.com>
  4 + * Pierre AUBERT p.aubert@staubli.com
  5 + *
  6 + * See file CREDITS for list of people who contributed to this
  7 + * project.
  8 + *
  9 + * This program is free software; you can redistribute it and/or
  10 + * modify it under the terms of the GNU General Public License as
  11 + * published by the Free Software Foundation; either version 2 of
  12 + * the License, or (at your option) any later version.
  13 + *
  14 + * This program is distributed in the hope that it will be useful,
  15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17 + * GNU General Public License for more details.
  18 + *
  19 + * You should have received a copy of the GNU General Public License
  20 + * along with this program; if not, write to the Free Software
  21 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 + * MA 02111-1307 USA
  23 + */
  24 +/* Video support for Epson SED13806 chipset */
  25 +
  26 +#include <common.h>
  27 +
  28 +#ifdef CONFIG_VIDEO_SED13806
  29 +
  30 +#include <video_fb.h>
  31 +#include <sed13806.h>
  32 +
  33 +#define readByte(ptrReg) \
  34 + *(volatile unsigned char *)(sed13806.isaBase + ptrReg)
  35 +
  36 +#define writeByte(ptrReg,value) \
  37 + *(volatile unsigned char *)(sed13806.isaBase + ptrReg) = value
  38 +
  39 +#define writeWord(ptrReg,value) \
  40 + (*(volatile unsigned short *)(sed13806.isaBase + ptrReg) = ((value >> 8 ) & 0xff) | ((value << 8) & 0xff00))
  41 +
  42 +
  43 +GraphicDevice sed13806;
  44 +
  45 +/*-----------------------------------------------------------------------------
  46 + * EpsonSetRegs --
  47 + *-----------------------------------------------------------------------------
  48 + */
  49 +static void EpsonSetRegs (void)
  50 +{
  51 + /* the content of the chipset register depends on the board (clocks, ...)*/
  52 + const S1D_REGS *preg = board_get_regs ();
  53 + while (preg -> Index) {
  54 + writeByte (preg -> Index, preg -> Value);
  55 + preg ++;
  56 + }
  57 +}
  58 +
  59 +/*-----------------------------------------------------------------------------
  60 + * video_hw_init --
  61 + *-----------------------------------------------------------------------------
  62 + */
  63 +void *video_hw_init (void)
  64 +{
  65 + unsigned int *vm, i;
  66 +
  67 + memset (&sed13806, 0, sizeof (GraphicDevice));
  68 +
  69 + /* Initialization of the access to the graphic chipset
  70 + Retreive base address of the chipset
  71 + (see board/RPXClassic/eccx.c) */
  72 + if ((sed13806.isaBase = board_video_init ()) == 0) {
  73 + return (NULL);
  74 + }
  75 +
  76 + sed13806.frameAdrs = sed13806.isaBase + FRAME_BUFFER_OFFSET;
  77 + sed13806.winSizeX = board_get_width ();
  78 + sed13806.winSizeY = board_get_height ();
  79 +
  80 +#if defined(CONFIG_VIDEO_SED13806_8BPP)
  81 + sed13806.gdfIndex = GDF__8BIT_INDEX;
  82 + sed13806.gdfBytesPP = 1;
  83 +
  84 +#elif defined(CONFIG_VIDEO_SED13806_16BPP)
  85 + sed13806.gdfIndex = GDF_16BIT_565RGB;
  86 + sed13806.gdfBytesPP = 2;
  87 +
  88 +#else
  89 +#error Unsupported SED13806 BPP
  90 +#endif
  91 +
  92 + sed13806.memSize = sed13806.winSizeX * sed13806.winSizeY * sed13806.gdfBytesPP;
  93 +
  94 + /* Load SED registers */
  95 + EpsonSetRegs ();
  96 +
  97 + /* (see board/RPXClassic/RPXClassic.c) */
  98 + board_validate_screen (sed13806.isaBase);
  99 +
  100 + /* Clear video memory */
  101 + i = sed13806.memSize/4;
  102 + vm = (unsigned int *)sed13806.frameAdrs;
  103 + while(i--)
  104 + *vm++ = 0;
  105 +
  106 +
  107 + return (&sed13806);
  108 +}
  109 +/*-----------------------------------------------------------------------------
  110 + * Epson_wait_idle -- Wait for hardware to become idle
  111 + *-----------------------------------------------------------------------------
  112 + */
  113 +static void Epson_wait_idle (void)
  114 +{
  115 + while (readByte (BLT_CTRL0) & 0x80);
  116 +
  117 + /* Read a word in the BitBLT memory area to shutdown the BitBLT engine */
  118 + *(volatile unsigned short *)(sed13806.isaBase + BLT_REG);
  119 +}
  120 +
  121 +/*-----------------------------------------------------------------------------
  122 + * video_hw_bitblt --
  123 + *-----------------------------------------------------------------------------
  124 + */
  125 +void video_hw_bitblt (
  126 + unsigned int bpp, /* bytes per pixel */
  127 + unsigned int src_x, /* source pos x */
  128 + unsigned int src_y, /* source pos y */
  129 + unsigned int dst_x, /* dest pos x */
  130 + unsigned int dst_y, /* dest pos y */
  131 + unsigned int dim_x, /* frame width */
  132 + unsigned int dim_y /* frame height */
  133 + )
  134 +{
  135 + register GraphicDevice *pGD = (GraphicDevice *)&sed13806;
  136 + unsigned long srcAddr, dstAddr;
  137 + unsigned int stride = bpp * pGD -> winSizeX;
  138 +
  139 + srcAddr = (src_y * stride) + (src_x * bpp);
  140 + dstAddr = (dst_y * stride) + (dst_x * bpp);
  141 +
  142 + Epson_wait_idle ();
  143 +
  144 + writeByte(BLT_ROP,0x0C); // source
  145 + writeByte(BLT_OP,0x02);// move blit in positive direction with ROP
  146 + writeWord(BLT_MEM_OFF0, stride / 2);
  147 + if (pGD -> gdfIndex == GDF__8BIT_INDEX) {
  148 + writeByte(BLT_CTRL1,0x00);
  149 + }
  150 + else {
  151 + writeByte(BLT_CTRL1,0x01);
  152 + }
  153 +
  154 + writeWord(BLT_WIDTH0,(dim_x - 1));
  155 + writeWord(BLT_HEIGHT0,(dim_y - 1));
  156 +
  157 + /* set up blit registers */
  158 + writeByte(BLT_SRC_ADDR0,srcAddr);
  159 + writeByte(BLT_SRC_ADDR1,srcAddr>>8);
  160 + writeByte(BLT_SRC_ADDR2,srcAddr>>16);
  161 +
  162 + writeByte(BLT_DST_ADDR0,dstAddr);
  163 + writeByte(BLT_DST_ADDR1,dstAddr>>8);
  164 + writeByte(BLT_DST_ADDR2,dstAddr>>16);
  165 +
  166 + /* Engage the blt engine */
  167 + /* rectangular region for src and dst */
  168 + writeByte(BLT_CTRL0,0x80);
  169 +
  170 + /* wait untill current blits finished */
  171 + Epson_wait_idle ();
  172 +}
  173 +/*-----------------------------------------------------------------------------
  174 + * video_hw_rectfill --
  175 + *-----------------------------------------------------------------------------
  176 + */
  177 +void video_hw_rectfill (
  178 + unsigned int bpp, /* bytes per pixel */
  179 + unsigned int dst_x, /* dest pos x */
  180 + unsigned int dst_y, /* dest pos y */
  181 + unsigned int dim_x, /* frame width */
  182 + unsigned int dim_y, /* frame height */
  183 + unsigned int color /* fill color */
  184 + )
  185 +{
  186 + register GraphicDevice *pGD = (GraphicDevice *)&sed13806;
  187 + unsigned long dstAddr;
  188 + unsigned int stride = bpp * pGD -> winSizeX;
  189 +
  190 + dstAddr = (dst_y * stride) + (dst_x * bpp);
  191 +
  192 + Epson_wait_idle ();
  193 +
  194 + /* set up blit registers */
  195 + writeByte(BLT_DST_ADDR0,dstAddr);
  196 + writeByte(BLT_DST_ADDR1,dstAddr>>8);
  197 + writeByte(BLT_DST_ADDR2,dstAddr>>16);
  198 +
  199 + writeWord(BLT_WIDTH0,(dim_x - 1));
  200 + writeWord(BLT_HEIGHT0,(dim_y - 1));
  201 + writeWord(BLT_FGCOLOR0,color);
  202 +
  203 + writeByte(BLT_OP,0x0C); /* solid fill */
  204 + writeWord(BLT_MEM_OFF0,stride / 2);
  205 +
  206 + if (pGD -> gdfIndex == GDF__8BIT_INDEX) {
  207 + writeByte(BLT_CTRL1,0x00);
  208 + }
  209 + else {
  210 + writeByte(BLT_CTRL1,0x01);
  211 + }
  212 +
  213 + /* Engage the blt engine */
  214 + /* rectangular region for src and dst */
  215 + writeByte(BLT_CTRL0,0x80);
  216 +
  217 + /* wait untill current blits finished */
  218 + Epson_wait_idle ();
  219 +}
  220 +
  221 +/*-----------------------------------------------------------------------------
  222 + * video_set_lut --
  223 + *-----------------------------------------------------------------------------
  224 + */
  225 +void video_set_lut (
  226 + unsigned int index, /* color number */
  227 + unsigned char r, /* red */
  228 + unsigned char g, /* green */
  229 + unsigned char b /* blue */
  230 + )
  231 +{
  232 + writeByte(REG_LUT_ADDR, index );
  233 + writeByte(REG_LUT_DATA, r);
  234 + writeByte(REG_LUT_DATA, g);
  235 + writeByte(REG_LUT_DATA, b);
  236 +}
  237 +#ifdef CONFIG_VIDEO_HW_CURSOR
  238 +/*-----------------------------------------------------------------------------
  239 + * video_set_hw_cursor --
  240 + *-----------------------------------------------------------------------------
  241 + */
  242 +void video_set_hw_cursor (int x, int y)
  243 +{
  244 + writeByte (LCD_CURSOR_XL, (x & 0xff));
  245 + writeByte (LCD_CURSOR_XM, (x >> 8));
  246 + writeByte (LCD_CURSOR_YL, (y & 0xff));
  247 + writeByte (LCD_CURSOR_YM, (y >> 8));
  248 +}
  249 +
  250 +/*-----------------------------------------------------------------------------
  251 + * video_init_hw_cursor --
  252 + *-----------------------------------------------------------------------------
  253 + */
  254 +void video_init_hw_cursor (int font_width, int font_height)
  255 +{
  256 + volatile unsigned char *ptr;
  257 + unsigned char pattern;
  258 + int i;
  259 +
  260 +
  261 + /* Init cursor content
  262 + Cursor size is 64x64 pixels
  263 + Start of the cursor memory depends on panel type (dual panel ...) */
  264 + if ((i = readByte (LCD_CURSOR_START)) == 0) {
  265 + ptr = (unsigned char *)(sed13806.frameAdrs + DEFAULT_VIDEO_MEMORY_SIZE - HWCURSORSIZE);
  266 + }
  267 + else {
  268 + ptr = (unsigned char *)(sed13806.frameAdrs + DEFAULT_VIDEO_MEMORY_SIZE - (i * 8192));
  269 + }
  270 +
  271 + /* Fill the first line and the first empty line after cursor */
  272 + for (i = 0, pattern = 0; i < 64; i++) {
  273 + if (i < font_width) {
  274 + /* Invert background */
  275 + pattern |= 0x3;
  276 +
  277 + }
  278 + else {
  279 + /* Background */
  280 + pattern |= 0x2;
  281 + }
  282 + if ((i & 3) == 3) {
  283 + *ptr = pattern;
  284 + *(ptr + font_height * 16) = 0xaa;
  285 + ptr ++;
  286 + pattern = 0;
  287 + }
  288 + pattern <<= 2;
  289 + }
  290 +
  291 + /* Duplicate this line */
  292 + for (i = 1; i < font_height; i++) {
  293 + memcpy ((void *)ptr, (void *)(ptr - 16), 16);
  294 + ptr += 16;
  295 + }
  296 +
  297 + for (; i < 64; i++) {
  298 + memcpy ((void *)(ptr + 16), (void *)ptr, 16);
  299 + ptr += 16;
  300 + }
  301 +
  302 + /* Select cursor mode */
  303 + writeByte (LCD_CURSOR_CNTL, 1);
  304 +}
  305 +#endif
  306 +#endif
include/configs/KUP4K.h
Diff comments   View file @ a6c7ad2
... ... @@ -45,7 +45,7 @@
45 45 #if 0
46 46 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
47 47 #else
48   -#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
  48 +#define CONFIG_BOOTDELAY 5 /* autoboot after 1 second */
49 49 #endif
50 50  
51 51 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
52 52  
... ... @@ -429,11 +429,13 @@
429 429 #define BOOTFLAG_WARM 0x02 /* Software reboot */
430 430  
431 431  
  432 +#if NOT_USED_FOR_NOW
432 433 #define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
433 434 #if 0
434 435 #define CONFIG_AUTOBOOT_PROMPT "Boote in %d Sekunden - stop mit \"2\"\n"
435 436 #endif
436 437 #define CONFIG_AUTOBOOT_STOP_STR "2" /* easy to stop for now */
  438 +#endif /* NOT_USED_FOR_NOW */
437 439  
438 440 #endif /* __CONFIG_H */
include/configs/RPXClassic.h
Diff comments   View file @ a6c7ad2
... ... @@ -47,13 +47,27 @@
47 47 #undef CONFIG_8xx_CONS_NONE
48 48 #define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
49 49  
50   -
51 50 /* Define CONFIG_FEC_ENET to use Fast ethernet instead of ethernet on SCC1 */
52   -#undef CONFIG_FEC_ENET
  51 +#define CONFIG_FEC_ENET
53 52 #ifdef CONFIG_FEC_ENET
54 53 #define CFG_DISCOVER_PHY 1
  54 +#define CONFIG_MII 1
55 55 #endif /* CONFIG_FEC_ENET */
56 56  
  57 +/* Video console (graphic: Epson SED13806 on ECCX board, no keyboard */
  58 +#if 1
  59 +#define CONFIG_VIDEO_SED13806
  60 +#define CONFIG_NEC_NL6448BC20
  61 +#define CONFIG_VIDEO_SED13806_16BPP
  62 +
  63 +#define CONFIG_CFB_CONSOLE
  64 +#define CONFIG_VIDEO_LOGO
  65 +#define CONFIG_VIDEO_BMP_LOGO
  66 +#define CONFIG_CONSOLE_EXTRA_INFO
  67 +#define CONFIG_VGA_AS_SINGLE_DEVICE
  68 +#define CONFIG_VIDEO_SW_CURSOR
  69 +#endif
  70 +
57 71 #if 0
58 72 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
59 73 #else
... ... @@ -168,7 +182,7 @@
168 182 #define CFG_SDRAM_BASE 0x00000000
169 183 #define CFG_FLASH_BASE 0xFF000000
170 184  
171   -#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
  185 +#if defined(DEBUG) || defined (CONFIG_VIDEO_SED13806) || (CONFIG_COMMANDS & CFG_CMD_IDE)
172 186 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
173 187 #else
174 188 #define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
... ... @@ -196,7 +210,8 @@
196 210 #if 0
197 211 #define CFG_ENV_IS_IN_FLASH 1
198 212 #define CFG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */
199   -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
  213 +#define CFG_ENV_SECT_SIZE 0x8000
  214 +#define CFG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */
200 215 #else
201 216 #define CFG_ENV_IS_IN_NVRAM 1
202 217 #define CFG_ENV_ADDR 0xfa000100
... ... @@ -352,6 +367,48 @@
352 367 #define CFG_OR3_PRELIM 0xff7f8970
353 368 #define CFG_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */
354 369 #define CFG_OR4_PRELIM 0xFFF80970
  370 +
  371 +/* ECCX CS settings */
  372 +#define SED13806_OR 0xFFC00108 /* - 4 Mo
  373 + - Burst inhibit
  374 + - external TA */
  375 +#define SED13806_REG_ADDR 0xa0000000
  376 +#define SED13806_ACCES 0x801 /* 16 bit access */
  377 +
  378 +
  379 +/* Global definitions for the ECCX board */
  380 +#define ECCX_CSR_ADDR (0xfac00000)
  381 +#define ECCX_CSR8_OFFSET (0x8)
  382 +#define ECCX_CSR11_OFFSET (0xB)
  383 +#define ECCX_CSR12_OFFSET (0xC)
  384 +
  385 +#define ECCX_CSR8 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR8_OFFSET)
  386 +#define ECCX_CSR11 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR11_OFFSET)
  387 +#define ECCX_CSR12 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR12_OFFSET)
  388 +
  389 +
  390 +#define REG_GPIO_CTRL 0x008
  391 +
  392 +/* Definitions for CSR8 */
  393 +#define ECCX_ENEPSON 0x80 /* Bit 0:
  394 + 0= disable and reset SED1386
  395 + 1= enable SED1386 */
  396 +/* Bit 1: 0= SED1386 in Big Endian mode */
  397 +/* 1= SED1386 in little endian mode */
  398 +#define ECCX_LE 0x40
  399 +#define ECCX_BE 0x00
  400 +
  401 +/* Bit 2,3: Selection */
  402 +/* 00 = Disabled */
  403 +/* 01 = CS2 is used for the SED1386 */
  404 +/* 10 = CS5 is used for the SED1386 */
  405 +/* 11 = reserved */
  406 +#define ECCX_CS2 0x10
  407 +#define ECCX_CS5 0x20
  408 +
  409 +/* Definitions for CSR12 */
  410 +#define ECCX_ID 0x02
  411 +#define ECCX_860 0x01
355 412  
356 413 /*
357 414 * Memory Periodic Timer Prescaler
... ... @@ -99,7 +99,7 @@
99 99 #ifdef CONFIG_VFD
100 100 int drv_vfd_init (void);
101 101 #endif
102   -#ifdef CONFIG_VIDEO
  102 +#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
103 103 int drv_video_init (void);
104 104 #endif
105 105 #ifdef CONFIG_WL_4PPM_KEYBOARD
  1 +/*
  2 + * (C) Copyright 2002
  3 + * Stรคubli Faverges - <www.staubli.com>
  4 + * Pierre AUBERT p.aubert@staubli.com
  5 + *
  6 + * See file CREDITS for list of people who contributed to this
  7 + * project.
  8 + *
  9 + * This program is free software; you can redistribute it and/or
  10 + * modify it under the terms of the GNU General Public License as
  11 + * published by the Free Software Foundation; either version 2 of
  12 + * the License, or (at your option) any later version.
  13 + *
  14 + * This program is distributed in the hope that it will be useful,
  15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17 + * GNU General Public License for more details.
  18 + *
  19 + * You should have received a copy of the GNU General Public License
  20 + * along with this program; if not, write to the Free Software
  21 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 + * MA 02111-1307 USA
  23 + */
  24 +/* Video support for Epson SED13806 chipset */
  25 +
  26 +
  27 +#ifndef _SED13806_H_
  28 +#define _SED13806_H_
  29 +
  30 +
  31 +/* General definitions */
  32 +#define FRAME_BUFFER_OFFSET 0x200000 /* Frame buffer offset */
  33 +#define TOTAL_SPACE_SIZE 0x400000
  34 +
  35 +#define DEFAULT_VIDEO_MEMORY_SIZE 0x140000 /* Video Memory Size */
  36 +
  37 +#define HWCURSORSIZE 1024 /* Size of memory reserved
  38 + for HW cursor*/
  39 +
  40 +/* Offset of chipset registers */
  41 +#define BLT_CTRL0 (0x0100)
  42 +#define BLT_CTRL1 (0x0101)
  43 +#define BLT_ROP (0x0102)
  44 +#define BLT_OP (0x0103)
  45 +#define BLT_SRC_ADDR0 (0x0104)
  46 +#define BLT_SRC_ADDR1 (0x0105)
  47 +#define BLT_SRC_ADDR2 (0x0106)
  48 +#define BLT_DST_ADDR0 (0x0108)
  49 +#define BLT_DST_ADDR1 (0x0109)
  50 +#define BLT_DST_ADDR2 (0x010A)
  51 +#define BLT_MEM_OFF0 (0x010C)
  52 +#define BLT_MEM_OFF1 (0x010D)
  53 +#define BLT_WIDTH0 (0x0110)
  54 +#define BLT_WIDTH1 (0x0111)
  55 +#define BLT_HEIGHT0 (0x0112)
  56 +#define BLT_HEIGHT1 (0x0113)
  57 +#define BLT_BGCOLOR0 (0x0114)
  58 +#define BLT_BGCOLOR1 (0x0115)
  59 +#define BLT_FGCOLOR0 (0x0118)
  60 +#define BLT_FGCOLOR1 (0x0119)
  61 +
  62 +#define BLT_REG (0x100000)
  63 +
  64 +/* Lookup table registers */
  65 +#define REG_LUT_ADDR 0x1e2
  66 +#define REG_LUT_DATA 0x1e4
  67 +
  68 +/* Cursor/Ink registers */
  69 +#define LCD_CURSOR_CNTL (0x0070)
  70 +#define LCD_CURSOR_START (0x0071)
  71 +#define LCD_CURSOR_XL (0x0072)
  72 +#define LCD_CURSOR_XM (0x0073)
  73 +#define LCD_CURSOR_YL (0x0074)
  74 +#define LCD_CURSOR_YM (0x0075)
  75 +#define LCD_CURSOR_COL0_B (0x0076)
  76 +#define LCD_CURSOR_COL0_G (0x0077)
  77 +#define LCD_CURSOR_COL0_R (0x0078)
  78 +#define LCD_CURSOR_COL1_B (0x007A)
  79 +#define LCD_CURSOR_COL1_G (0x007B)
  80 +#define LCD_CURSOR_COL1_R (0x007C)
  81 +#define LCD_CURSOR_FIFO (0x007E)
  82 +
  83 +typedef struct
  84 +{
  85 + unsigned short Index;
  86 + unsigned char Value;
  87 +} S1D_REGS;
  88 +
  89 +
  90 +
  91 +/* Board specific functions */
  92 +unsigned int board_video_init (void);
  93 +void board_validate_screen (unsigned int base);
  94 +const S1D_REGS *board_get_regs (void);
  95 +int board_get_width (void);
  96 +int board_get_height (void);
  97 +
  98 +#endif /* _SED13806_H_ */
... ... @@ -46,7 +46,10 @@
46 46 static ulong mem_malloc_end = 0;
47 47 static ulong mem_malloc_brk = 0;
48 48  
49   -static void mem_malloc_init (ulong dest_addr)
  49 +#if !defined(CONFIG_MODEM_SUPPORT)
  50 +static
  51 +#endif
  52 +void mem_malloc_init (ulong dest_addr)
50 53 {
51 54 mem_malloc_start = dest_addr;
52 55 mem_malloc_end = dest_addr + CFG_MALLOC_LEN;
... ... @@ -184,7 +187,7 @@
184 187 gd_t gd_data;
185 188 bd_t bd_data;
186 189 init_fnc_t **init_fnc_ptr;
187   -#ifdef CONFIG_VFD
  190 +#if defined(CONFIG_VFD) && !defined(CONFIG_MODEM_SUPPORT)
188 191 unsigned long addr;
189 192 #endif
190 193  
... ... @@ -205,6 +208,7 @@
205 208 display_flash_config (size);
206 209  
207 210 #ifdef CONFIG_VFD
  211 +#ifndef CONFIG_MODEM_SUPPORT
208 212 #ifndef PAGE_SIZE
209 213 #define PAGE_SIZE 4096
210 214 #endif
211 215  
212 216  
... ... @@ -219,14 +223,17 @@
219 223 addr += size;
220 224 addr = (addr + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
221 225 mem_malloc_init (addr);
  226 +#endif /* CONFIG_MODEM_SUPPORT */
222 227 #else
223 228 /* armboot_real_end is defined in the board-specific linker script */
224 229 mem_malloc_init (_armboot_real_end);
225 230 #endif /* CONFIG_VFD */
226 231  
227 232 #ifdef CONFIG_VFD
  233 +#ifndef CONFIG_MODEM_SUPPORT
228 234 /* must do this after the framebuffer is allocated */
229 235 drv_vfd_init();
  236 +#endif /* CONFIG_MODEM_SUPPORT */
230 237 #endif
231 238 /* initialize environment */
232 239 env_relocate ();
... ... @@ -266,7 +266,7 @@
266 266 ulong xor;
267 267 int ret = 0;
268 268  
269   - end = base + size;
  269 + end = (ulong *)((ulong)base + size); /* pointer arith! */
270 270 xor = 0;
271 271 for(xor = sizeof(ulong); xor > 0; xor <<= 1) {
272 272 target = (ulong *)((ulong)testaddr ^ xor);
... ... @@ -250,8 +250,9 @@
250 250 */
251 251 if (xflag) {
252 252 if (ep != addr + sizeof(image_header_t)) {
253   - fprintf (stderr, "%s: For XIP, the entry point must be the load addr + %d\n",
254   - cmdname, sizeof(image_header_t));
  253 + fprintf (stderr, "%s: For XIP, the entry point must be the load addr + %lu\n",
  254 + cmdname,
  255 + (unsigned long)sizeof(image_header_t));
255 256 exit (EXIT_FAILURE);
256 257 }
257 258 }