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Commit a99a06cbbd89d7c116b0ed61325ac359f26ed64e

Authored by Michal Simek
1 parent 4e9acc16fc
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

fpga: xilinx: spartan3: Setup NULL fpga_op without driver 

Set fpga operations to NULL for cases where
FPGA is setup in board file but driver is not added.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Showing 1 changed file with 31 additions and 14 deletions Side-by-side Diff

... ... @@ -40,7 +40,12 @@
40 40 xilinx_abort_fn abort;
41 41 } xilinx_spartan3_slave_serial_fns;
42 42  
  43 +#if defined(CONFIG_FPGA_SPARTAN3)
43 44 extern struct xilinx_fpga_op spartan3_op;
  45 +# define FPGA_SPARTAN3_OPS &spartan3_op
  46 +#else
  47 +# define FPGA_SPARTAN3_OPS NULL
  48 +#endif
44 49  
45 50 /* Device Image Sizes
46 51 *********************************************************************/
47 52  
48 53  
49 54  
50 55  
51 56  
52 57  
53 58  
54 59  
55 60  
56 61  
57 62  
58 63  
59 64  
... ... @@ -71,49 +76,61 @@
71 76 *********************************************************************/
72 77 /* Spartan-III devices */
73 78 #define XILINX_XC3S50_DESC(iface, fn_table, cookie) \
74   -{ xilinx_spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie, &spartan3_op }
  79 +{ xilinx_spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie, \
  80 + FPGA_SPARTAN3_OPS }
75 81  
76 82 #define XILINX_XC3S200_DESC(iface, fn_table, cookie) \
77   -{ xilinx_spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie, &spartan3_op }
  83 +{ xilinx_spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie, \
  84 + FPGA_SPARTAN3_OPS }
78 85  
79 86 #define XILINX_XC3S400_DESC(iface, fn_table, cookie) \
80   -{ xilinx_spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie, &spartan3_op }
  87 +{ xilinx_spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie, \
  88 + FPGA_SPARTAN3_OPS }
81 89  
82 90 #define XILINX_XC3S1000_DESC(iface, fn_table, cookie) \
83   -{ xilinx_spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie, &spartan3_op }
  91 +{ xilinx_spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie, \
  92 + FPGA_SPARTAN3_OPS }
84 93  
85 94 #define XILINX_XC3S1500_DESC(iface, fn_table, cookie) \
86   -{ xilinx_spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie, &spartan3_op }
  95 +{ xilinx_spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie, \
  96 + FPGA_SPARTAN3_OPS }
87 97  
88 98 #define XILINX_XC3S2000_DESC(iface, fn_table, cookie) \
89   -{ xilinx_spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie, &spartan3_op }
  99 +{ xilinx_spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie, \
  100 + FPGA_SPARTAN3_OPS }
90 101  
91 102 #define XILINX_XC3S4000_DESC(iface, fn_table, cookie) \
92   -{ xilinx_spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie, &spartan3_op }
  103 +{ xilinx_spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie, \
  104 + FPGA_SPARTAN3_OPS }
93 105  
94 106 #define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \
95   -{ xilinx_spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie, &spartan3_op }
  107 +{ xilinx_spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie, \
  108 + FPGA_SPARTAN3_OPS }
96 109  
97 110 /* Spartan-3E devices */
98 111 #define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \
99   -{ xilinx_spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie, &spartan3_op }
  112 +{ xilinx_spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie, \
  113 + FPGA_SPARTAN3_OPS }
100 114  
101 115 #define XILINX_XC3S250E_DESC(iface, fn_table, cookie) \
102   -{ xilinx_spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie, &spartan3_op }
  116 +{ xilinx_spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie, \
  117 + FPGA_SPARTAN3_OPS }
103 118  
104 119 #define XILINX_XC3S500E_DESC(iface, fn_table, cookie) \
105   -{ xilinx_spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie, &spartan3_op }
  120 +{ xilinx_spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie, \
  121 + FPGA_SPARTAN3_OPS }
106 122  
107 123 #define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \
108 124 { xilinx_spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie, \
109   - &spartan3_op }
  125 + FPGA_SPARTAN3_OPS }
110 126  
111 127 #define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \
112 128 { xilinx_spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie, \
113   - &spartan3_op }
  129 + FPGA_SPARTAN3_OPS }
114 130  
115 131 #define XILINX_XC6SLX4_DESC(iface, fn_table, cookie) \
116   -{ xilinx_spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie, &spartan3_op }
  132 +{ xilinx_spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie, \
  133 + FPGA_SPARTAN3_OPS }
117 134  
118 135 #endif /* _SPARTAN3_H_ */