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Commit aa0d99fc285a0b4ca71245c0c3ba8c00f8b51983

Authored by Alison Wang
Committed by Jason
1 parent 32dbaafa5a
Exists in master and in 57 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf-6.6.52-2.2.0, emb_lf_v2022.04, emb_lf_v2023.04, emb_lf_v2024.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

ColdFire: Clean up checkpatch warnings for MCF532x/MCF537x/MCF5301x 

Signed-off-by: Alison Wang <b18965@freescale.com>

Showing 9 changed files with 287 additions and 258 deletions Side-by-side Diff

arch/m68k/cpu/mcf532x/cpu.c
Diff comments   View file @ aa0d99f
... ... @@ -3,7 +3,7 @@
3 3 * (C) Copyright 2000-2003
4 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 5 *
6   - * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
  6 + * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
7 7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 8 *
9 9 * See file CREDITS for list of people who contributed to this
10 10  
11 11  
... ... @@ -31,15 +31,16 @@
31 31 #include <netdev.h>
32 32  
33 33 #include <asm/immap.h>
  34 +#include <asm/io.h>
34 35  
35 36 DECLARE_GLOBAL_DATA_PTR;
36 37  
37 38 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
38 39 {
39   - volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);
  40 + rcm_t *rcm = (rcm_t *) (MMAP_RCM);
40 41  
41 42 udelay(1000);
42   - rcm->rcr |= RCM_RCR_SOFTRST;
  43 + setbits_8(&rcm->rcr, RCM_RCR_SOFTRST);
43 44  
44 45 /* we don't return! */
45 46 return 0;
46 47  
... ... @@ -47,14 +48,14 @@
47 48  
48 49 int checkcpu(void)
49 50 {
50   - volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
  51 + ccm_t *ccm = (ccm_t *) MMAP_CCM;
51 52 u16 msk;
52 53 u16 id = 0;
53 54 u8 ver;
54 55  
55 56 puts("CPU: ");
56   - msk = (ccm->cir >> 6);
57   - ver = (ccm->cir & 0x003f);
  57 + msk = (in_be16(&ccm->cir) >> 6);
  58 + ver = (in_be16(&ccm->cir) & 0x003f);
58 59 switch (msk) {
59 60 #ifdef CONFIG_MCF5301x
60 61 case 0x78:
61 62  
62 63  
63 64  
... ... @@ -115,18 +116,20 @@
115 116 /* Called by macro WATCHDOG_RESET */
116 117 void watchdog_reset(void)
117 118 {
118   - volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
  119 + wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
119 120  
120   - wdp->sr = 0x5555; /* Count register */
121   - wdp->sr = 0xAAAA; /* Count register */
  121 + /* Count register */
  122 + out_be16(&wdp->sr, 0x5555);
  123 + out_be16(&wdp->sr, 0xaaaa);
122 124 }
123 125  
124 126 int watchdog_disable(void)
125 127 {
126   - volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
  128 + wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
127 129  
128 130 /* UserManual, once the wdog is disabled, wdog cannot be re-enabled */
129   - wdp->cr |= WTM_WCR_HALTED; /* halted watchdog timer */
  131 + /* halted watchdog timer */
  132 + setbits_be16(&wdp->cr, WTM_WCR_HALTED);
130 133  
131 134 puts("WATCHDOG:disabled\n");
132 135 return (0);
133 136  
134 137  
135 138  
... ... @@ -134,18 +137,18 @@
134 137  
135 138 int watchdog_init(void)
136 139 {
137   - volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
  140 + wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
138 141 u32 wdog_module = 0;
139 142  
140 143 /* set timeout and enable watchdog */
141 144 wdog_module = ((CONFIG_SYS_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT);
142 145 #ifdef CONFIG_M5329
143   - wdp->mr = (wdog_module / 8192);
  146 + out_be16(&wdp->mr, wdog_module / 8192);
144 147 #else
145   - wdp->mr = (wdog_module / 4096);
  148 + out_be16(&wdp->mr, wdog_module / 4096);
146 149 #endif
147 150  
148   - wdp->cr = WTM_WCR_EN;
  151 + out_be16(&wdp->cr, WTM_WCR_EN);
149 152 puts("WATCHDOG:enabled\n");
150 153  
151 154 return (0);
arch/m68k/cpu/mcf532x/cpu_init.c
Diff comments   View file @ aa0d99f
... ... @@ -3,7 +3,7 @@
3 3 * (C) Copyright 2000-2003
4 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 5 *
6   - * (C) Copyright 2004-2008 Freescale Semiconductor, Inc.
  6 + * (C) Copyright 2004-2008, 2012 Freescale Semiconductor, Inc.
7 7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 8 *
9 9 * See file CREDITS for list of people who contributed to this
... ... @@ -28,6 +28,7 @@
28 28 #include <common.h>
29 29 #include <watchdog.h>
30 30 #include <asm/immap.h>
  31 +#include <asm/io.h>
31 32  
32 33 #if defined(CONFIG_CMD_NET)
33 34 #include <config.h>
34 35  
35 36  
36 37  
37 38  
38 39  
39 40  
40 41  
41 42  
42 43  
... ... @@ -38,72 +39,68 @@
38 39 #ifdef CONFIG_MCF5301x
39 40 void cpu_init_f(void)
40 41 {
41   - volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
42   - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
43   - volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
  42 + scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
  43 + gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  44 + fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
44 45  
45   - /* watchdog is enabled by default - disable the watchdog */
46   -#ifndef CONFIG_WATCHDOG
47   - /*wdog->cr = 0; */
48   -#endif
  46 + out_be32(&scm1->mpr, 0x77777777);
  47 + out_be32(&scm1->pacra, 0);
  48 + out_be32(&scm1->pacrb, 0);
  49 + out_be32(&scm1->pacrc, 0);
  50 + out_be32(&scm1->pacrd, 0);
  51 + out_be32(&scm1->pacre, 0);
  52 + out_be32(&scm1->pacrf, 0);
  53 + out_be32(&scm1->pacrg, 0);
49 54  
50   - scm1->mpr = 0x77777777;
51   - scm1->pacra = 0;
52   - scm1->pacrb = 0;
53   - scm1->pacrc = 0;
54   - scm1->pacrd = 0;
55   - scm1->pacre = 0;
56   - scm1->pacrf = 0;
57   - scm1->pacrg = 0;
58   -
59 55 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
60 56 && defined(CONFIG_SYS_CS0_CTRL))
61   - gpio->par_cs |= GPIO_PAR_CS0_CS0;
62   - fbcs->csar0 = CONFIG_SYS_CS0_BASE;
63   - fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
64   - fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
  57 + setbits_8(&gpio->par_cs, GPIO_PAR_CS0_CS0);
  58 + out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
  59 + out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
  60 + out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
65 61 #endif
66 62  
67 63 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
68 64 && defined(CONFIG_SYS_CS1_CTRL))
69   - gpio->par_cs |= GPIO_PAR_CS1_CS1;
70   - fbcs->csar1 = CONFIG_SYS_CS1_BASE;
71   - fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
72   - fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
  65 + setbits_8(&gpio->par_cs, GPIO_PAR_CS1_CS1);
  66 + out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
  67 + out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
  68 + out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
73 69 #endif
74 70  
75 71 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
76 72 && defined(CONFIG_SYS_CS2_CTRL))
77   - fbcs->csar2 = CONFIG_SYS_CS2_BASE;
78   - fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
79   - fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
  73 + out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
  74 + out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
  75 + out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
80 76 #endif
81 77  
82 78 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
83 79 && defined(CONFIG_SYS_CS3_CTRL))
84   - fbcs->csar3 = CONFIG_SYS_CS3_BASE;
85   - fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
86   - fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
  80 + out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
  81 + out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
  82 + out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
87 83 #endif
88 84  
89 85 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
90 86 && defined(CONFIG_SYS_CS4_CTRL))
91   - gpio->par_cs |= GPIO_PAR_CS4;
92   - fbcs->csar4 = CONFIG_SYS_CS4_BASE;
93   - fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
94   - fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
  87 + setbits_8(&gpio->par_cs, GPIO_PAR_CS4);
  88 + out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
  89 + out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
  90 + out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
95 91 #endif
96 92  
97 93 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
98 94 && defined(CONFIG_SYS_CS5_CTRL))
99   - gpio->par_cs |= GPIO_PAR_CS5;
100   - fbcs->csar5 = CONFIG_SYS_CS5_BASE;
101   - fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
102   - fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
  95 + setbits_8(&gpio->par_cs, GPIO_PAR_CS5);
  96 + out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
  97 + out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
  98 + out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
103 99 #endif
104 100  
105 101 #ifdef CONFIG_FSL_I2C
106   - gpio->par_feci2c = GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL;
  102 + out_8(&gpio->par_feci2c,
  103 + GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL);
107 104 #endif
108 105  
109 106 icache_enable();
110 107  
111 108  
112 109  
113 110  
... ... @@ -113,21 +110,21 @@
113 110 int cpu_init_r(void)
114 111 {
115 112 #ifdef CONFIG_MCFFEC
116   - volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
  113 + ccm_t *ccm = (ccm_t *) MMAP_CCM;
117 114 #endif
118 115 #ifdef CONFIG_MCFRTC
119   - volatile rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE);
120   - volatile rtcex_t *rtcex = (rtcex_t *) & rtc->extended;
  116 + rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE);
  117 + rtcex_t *rtcex = (rtcex_t *) &rtc->extended;
121 118  
122   - rtcex->gocu = CONFIG_SYS_RTC_CNT;
123   - rtcex->gocl = CONFIG_SYS_RTC_SETUP;
  119 + out_be32(&rtcex->gocu, CONFIG_SYS_RTC_CNT);
  120 + out_be32(&rtcex->gocl, CONFIG_SYS_RTC_SETUP);
124 121  
125 122 #endif
126 123 #ifdef CONFIG_MCFFEC
127 124 if (CONFIG_SYS_FEC0_MIIBASE != CONFIG_SYS_FEC1_MIIBASE)
128   - ccm->misccr |= CCM_MISCCR_FECM;
  125 + setbits_be16(&ccm->misccr, CCM_MISCCR_FECM);
129 126 else
130   - ccm->misccr &= ~CCM_MISCCR_FECM;
  127 + clrbits_be16(&ccm->misccr, CCM_MISCCR_FECM);
131 128 #endif
132 129  
133 130 return (0);
134 131  
135 132  
136 133  
137 134  
138 135  
139 136  
... ... @@ -135,41 +132,52 @@
135 132  
136 133 void uart_port_conf(int port)
137 134 {
138   - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  135 + gpio_t *gpio = (gpio_t *) MMAP_GPIO;
139 136  
140 137 /* Setup Ports: */
141 138 switch (port) {
142 139 case 0:
143   - gpio->par_uart &= ~(GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
144   - gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
  140 + clrbits_8(&gpio->par_uart,
  141 + GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
  142 + setbits_8(&gpio->par_uart,
  143 + GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
145 144 break;
146 145 case 1:
147 146 #ifdef CONFIG_SYS_UART1_ALT1_GPIO
148   - gpio->par_simp1h &=
149   - ~(GPIO_PAR_SIMP1H_DATA1_UNMASK |
150   - GPIO_PAR_SIMP1H_VEN1_UNMASK);
151   - gpio->par_simp1h |=
152   - (GPIO_PAR_SIMP1H_DATA1_U1TXD | GPIO_PAR_SIMP1H_VEN1_U1RXD);
  147 + clrbits_8(&gpio->par_simp1h,
  148 + GPIO_PAR_SIMP1H_DATA1_UNMASK |
  149 + GPIO_PAR_SIMP1H_VEN1_UNMASK);
  150 + setbits_8(&gpio->par_simp1h,
  151 + GPIO_PAR_SIMP1H_DATA1_U1TXD |
  152 + GPIO_PAR_SIMP1H_VEN1_U1RXD);
153 153 #elif defined(CONFIG_SYS_UART1_ALT2_GPIO)
154   - gpio->par_ssih &=
155   - ~(GPIO_PAR_SSIH_RXD_UNMASK | GPIO_PAR_SSIH_TXD_UNMASK);
156   - gpio->par_ssih |=
157   - (GPIO_PAR_SSIH_RXD_U1RXD | GPIO_PAR_SSIH_TXD_U1TXD);
  154 + clrbits_8(&gpio->par_ssih,
  155 + GPIO_PAR_SSIH_RXD_UNMASK |
  156 + GPIO_PAR_SSIH_TXD_UNMASK);
  157 + setbits_8(&gpio->par_ssih,
  158 + GPIO_PAR_SSIH_RXD_U1RXD |
  159 + GPIO_PAR_SSIH_TXD_U1TXD);
158 160 #endif
159 161 break;
160 162 case 2:
161 163 #ifdef CONFIG_SYS_UART2_PRI_GPIO
162   - gpio->par_uart |= (GPIO_PAR_UART_U2TXD | GPIO_PAR_UART_U2RXD);
  164 + setbits_8(&gpio->par_uart,
  165 + GPIO_PAR_UART_U2TXD |
  166 + GPIO_PAR_UART_U2RXD);
163 167 #elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
164   - gpio->par_dspih &=
165   - ~(GPIO_PAR_DSPIH_SIN_UNMASK | GPIO_PAR_DSPIH_SOUT_UNMASK);
166   - gpio->par_dspih |=
167   - (GPIO_PAR_DSPIH_SIN_U2RXD | GPIO_PAR_DSPIH_SOUT_U2TXD);
  168 + clrbits_8(&gpio->par_dspih,
  169 + GPIO_PAR_DSPIH_SIN_UNMASK |
  170 + GPIO_PAR_DSPIH_SOUT_UNMASK);
  171 + setbits_8(&gpio->par_dspih,
  172 + GPIO_PAR_DSPIH_SIN_U2RXD |
  173 + GPIO_PAR_DSPIH_SOUT_U2TXD);
168 174 #elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
169   - gpio->par_feci2c &=
170   - ~(GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK);
171   - gpio->par_feci2c |=
172   - (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
  175 + clrbits_8(&gpio->par_feci2c,
  176 + GPIO_PAR_FECI2C_SDA_UNMASK |
  177 + GPIO_PAR_FECI2C_SCL_UNMASK);
  178 + setbits_8(&gpio->par_feci2c,
  179 + GPIO_PAR_FECI2C_SDA_U2TXD |
  180 + GPIO_PAR_FECI2C_SCL_U2RXD);
173 181 #endif
174 182 break;
175 183 }
176 184  
177 185  
178 186  
179 187  
... ... @@ -178,30 +186,30 @@
178 186 #if defined(CONFIG_CMD_NET)
179 187 int fecpin_setclear(struct eth_device *dev, int setclear)
180 188 {
181   - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  189 + gpio_t *gpio = (gpio_t *) MMAP_GPIO;
182 190 struct fec_info_s *info = (struct fec_info_s *)dev->priv;
183 191  
184 192 if (setclear) {
185 193 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
186   - gpio->par_fec |=
187   - GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC;
188   - gpio->par_feci2c |=
189   - GPIO_PAR_FECI2C_MDC0 | GPIO_PAR_FECI2C_MDIO0;
  194 + setbits_8(&gpio->par_fec,
  195 + GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
  196 + setbits_8(&gpio->par_feci2c,
  197 + GPIO_PAR_FECI2C_MDC0 | GPIO_PAR_FECI2C_MDIO0);
190 198 } else {
191   - gpio->par_fec |=
192   - GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC;
193   - gpio->par_feci2c |=
194   - GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1;
  199 + setbits_8(&gpio->par_fec,
  200 + GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC);
  201 + setbits_8(&gpio->par_feci2c,
  202 + GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1);
195 203 }
196 204 } else {
197 205 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
198   - gpio->par_fec &=
199   - ~(GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
200   - gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII0_UNMASK;
  206 + clrbits_8(&gpio->par_fec,
  207 + GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
  208 + clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII0_UNMASK);
201 209 } else {
202   - gpio->par_fec &=
203   - ~(GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC);
204   - gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII1_UNMASK;
  210 + clrbits_8(&gpio->par_fec,
  211 + GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC);
  212 + clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII1_UNMASK);
205 213 }
206 214 }
207 215 return 0;
208 216  
209 217  
210 218  
211 219  
212 220  
213 221  
214 222  
215 223  
216 224  
217 225  
... ... @@ -212,80 +220,81 @@
212 220 #ifdef CONFIG_MCF532x
213 221 void cpu_init_f(void)
214 222 {
215   - volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
216   - volatile scm2_t *scm2 = (scm2_t *) MMAP_SCM2;
217   - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
218   - volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
219   - volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG;
  223 + scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
  224 + scm2_t *scm2 = (scm2_t *) MMAP_SCM2;
  225 + gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  226 + fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
  227 + wdog_t *wdog = (wdog_t *) MMAP_WDOG;
220 228  
221 229 /* watchdog is enabled by default - disable the watchdog */
222 230 #ifndef CONFIG_WATCHDOG
223   - wdog->cr = 0;
  231 + out_be16(&wdog->cr, 0);
224 232 #endif
225 233  
226   - scm1->mpr0 = 0x77777777;
227   - scm2->pacra = 0;
228   - scm2->pacrb = 0;
229   - scm2->pacrc = 0;
230   - scm2->pacrd = 0;
231   - scm2->pacre = 0;
232   - scm2->pacrf = 0;
233   - scm2->pacrg = 0;
234   - scm1->pacrh = 0;
  234 + out_be32(&scm1->mpr0, 0x77777777);
  235 + out_be32(&scm2->pacra, 0);
  236 + out_be32(&scm2->pacrb, 0);
  237 + out_be32(&scm2->pacrc, 0);
  238 + out_be32(&scm2->pacrd, 0);
  239 + out_be32(&scm2->pacre, 0);
  240 + out_be32(&scm2->pacrf, 0);
  241 + out_be32(&scm2->pacrg, 0);
  242 + out_be32(&scm1->pacrh, 0);
235 243  
236 244 /* Port configuration */
237   - gpio->par_cs = 0;
  245 + out_8(&gpio->par_cs, 0);
238 246  
239 247 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
240 248 && defined(CONFIG_SYS_CS0_CTRL))
241   - fbcs->csar0 = CONFIG_SYS_CS0_BASE;
242   - fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
243   - fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
  249 + out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
  250 + out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
  251 + out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
244 252 #endif
245 253  
246 254 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
247 255 && defined(CONFIG_SYS_CS1_CTRL))
248 256 /* Latch chipselect */
249   - gpio->par_cs |= GPIO_PAR_CS1;
250   - fbcs->csar1 = CONFIG_SYS_CS1_BASE;
251   - fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
252   - fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
  257 + setbits_8(&gpio->par_cs, GPIO_PAR_CS1);
  258 + out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
  259 + out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
  260 + out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
253 261 #endif
254 262  
255 263 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
256 264 && defined(CONFIG_SYS_CS2_CTRL))
257   - gpio->par_cs |= GPIO_PAR_CS2;
258   - fbcs->csar2 = CONFIG_SYS_CS2_BASE;
259   - fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
260   - fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
  265 + setbits_8(&gpio->par_cs, GPIO_PAR_CS2);
  266 + out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
  267 + out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
  268 + out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
261 269 #endif
262 270  
263 271 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
264 272 && defined(CONFIG_SYS_CS3_CTRL))
265   - gpio->par_cs |= GPIO_PAR_CS3;
266   - fbcs->csar3 = CONFIG_SYS_CS3_BASE;
267   - fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
268   - fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
  273 + setbits_8(&gpio->par_cs, GPIO_PAR_CS3);
  274 + out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
  275 + out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
  276 + out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
269 277 #endif
270 278  
271 279 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
272 280 && defined(CONFIG_SYS_CS4_CTRL))
273   - gpio->par_cs |= GPIO_PAR_CS4;
274   - fbcs->csar4 = CONFIG_SYS_CS4_BASE;
275   - fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
276   - fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
  281 + setbits_8(&gpio->par_cs, GPIO_PAR_CS4);
  282 + out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
  283 + out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
  284 + out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
277 285 #endif
278 286  
279 287 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
280 288 && defined(CONFIG_SYS_CS5_CTRL))
281   - gpio->par_cs |= GPIO_PAR_CS5;
282   - fbcs->csar5 = CONFIG_SYS_CS5_BASE;
283   - fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
284   - fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
  289 + setbits_8(&gpio->par_cs, GPIO_PAR_CS5);
  290 + out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
  291 + out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
  292 + out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
285 293 #endif
286 294  
287 295 #ifdef CONFIG_FSL_I2C
288   - gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA;
  296 + out_8(&gpio->par_feci2c,
  297 + GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
289 298 #endif
290 299  
291 300 icache_enable();
292 301  
293 302  
294 303  
295 304  
296 305  
... ... @@ -301,30 +310,35 @@
301 310  
302 311 void uart_port_conf(int port)
303 312 {
304   - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  313 + gpio_t *gpio = (gpio_t *) MMAP_GPIO;
305 314  
306 315 /* Setup Ports: */
307 316 switch (port) {
308 317 case 0:
309   - gpio->par_uart &= ~(GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
310   - gpio->par_uart |= (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
  318 + clrbits_be16(&gpio->par_uart,
  319 + GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
  320 + setbits_be16(&gpio->par_uart,
  321 + GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
311 322 break;
312 323 case 1:
313   - gpio->par_uart &=
314   - ~(GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
315   - gpio->par_uart |=
316   - (GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
  324 + clrbits_be16(&gpio->par_uart,
  325 + GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
  326 + setbits_be16(&gpio->par_uart,
  327 + GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
317 328 break;
318 329 case 2:
319 330 #ifdef CONFIG_SYS_UART2_ALT1_GPIO
320   - gpio->par_timer &= 0x0F;
321   - gpio->par_timer |= (GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2);
  331 + clrbits_8(&gpio->par_timer, 0xf0);
  332 + setbits_8(&gpio->par_timer,
  333 + GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2);
322 334 #elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
323   - gpio->par_feci2c &= 0xFF00;
324   - gpio->par_feci2c |= (GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2);
  335 + clrbits_8(&gpio->par_feci2c, 0x00ff);
  336 + setbits_8(&gpio->par_feci2c,
  337 + GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2);
325 338 #elif defined(CONFIG_SYS_UART2_ALT3_GPIO)
326   - gpio->par_ssi &= 0xF0FF;
327   - gpio->par_ssi |= (GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2));
  339 + clrbits_be16(&gpio->par_ssi, 0x0f00);
  340 + setbits_be16(&gpio->par_ssi,
  341 + GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2));
328 342 #endif
329 343 break;
330 344 }
331 345  
332 346  
... ... @@ -333,16 +347,18 @@
333 347 #if defined(CONFIG_CMD_NET)
334 348 int fecpin_setclear(struct eth_device *dev, int setclear)
335 349 {
336   - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  350 + gpio_t *gpio = (gpio_t *) MMAP_GPIO;
337 351  
338 352 if (setclear) {
339   - gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
340   - gpio->par_feci2c |=
341   - GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO;
  353 + setbits_8(&gpio->par_fec,
  354 + GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
  355 + setbits_8(&gpio->par_feci2c,
  356 + GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
342 357 } else {
343   - gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
344   - gpio->par_feci2c &=
345   - ~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
  358 + clrbits_8(&gpio->par_fec,
  359 + GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
  360 + clrbits_8(&gpio->par_feci2c,
  361 + GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
346 362 }
347 363 return 0;
348 364 }
arch/m68k/cpu/mcf532x/interrupts.c
Diff comments   View file @ aa0d99f
1 1 /*
2 2 *
3   - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  3 + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
4 4 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
5 5 *
6 6 * See file CREDITS for list of people who contributed to this
7 7  
8 8  
... ... @@ -25,14 +25,15 @@
25 25 /* CPU specific interrupt routine */
26 26 #include <common.h>
27 27 #include <asm/immap.h>
  28 +#include <asm/io.h>
28 29  
29 30 int interrupt_init(void)
30 31 {
31   - volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
  32 + int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
32 33  
33 34 /* Make sure all interrupts are disabled */
34   - intp->imrh0 |= 0xFFFFFFFF;
35   - intp->imrl0 |= 0xFFFFFFFF;
  35 + setbits_be32(&intp->imrh0, 0xffffffff);
  36 + setbits_be32(&intp->imrl0, 0xffffffff);
36 37  
37 38 enable_interrupts();
38 39 return 0;
39 40  
... ... @@ -41,10 +42,10 @@
41 42 #if defined(CONFIG_MCFTMR)
42 43 void dtimer_intr_setup(void)
43 44 {
44   - volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
  45 + int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
45 46  
46   - intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
47   - intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK;
  47 + out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
  48 + clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK);
48 49 }
49 50 #endif
arch/m68k/cpu/mcf532x/speed.c
Diff comments   View file @ aa0d99f
... ... @@ -3,7 +3,7 @@
3 3 * (C) Copyright 2000-2003
4 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 5 *
6   - * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
  6 + * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
7 7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 8 *
9 9 * See file CREDITS for list of people who contributed to this
... ... @@ -29,6 +29,7 @@
29 29 #include <asm/processor.h>
30 30  
31 31 #include <asm/immap.h>
  32 +#include <asm/io.h>
32 33  
33 34 DECLARE_GLOBAL_DATA_PTR;
34 35  
35 36  
... ... @@ -65,13 +66,13 @@
65 66 /* Get the value of the current system clock */
66 67 int get_sys_clock(void)
67 68 {
68   - volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
69   - volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
  69 + ccm_t *ccm = (ccm_t *)(MMAP_CCM);
  70 + pll_t *pll = (pll_t *)(MMAP_PLL);
70 71 int divider;
71 72  
72 73 /* Test to see if device is in LIMP mode */
73   - if (ccm->misccr & CCM_MISCCR_LIMP) {
74   - divider = ccm->cdr & CCM_CDR_LPDIV(0xF);
  74 + if (in_be16(&ccm->misccr) & CCM_MISCCR_LIMP) {
  75 + divider = in_be16(&ccm->cdr) & CCM_CDR_LPDIV(0xF);
75 76 #ifdef CONFIG_MCF5301x
76 77 return (FREF / (3 * (1 << divider)));
77 78 #endif
78 79  
... ... @@ -80,14 +81,14 @@
80 81 #endif
81 82 } else {
82 83 #ifdef CONFIG_MCF5301x
83   - u32 pfdr = (pll->pcr & 0x3F) + 1;
84   - u32 refdiv = (1 << ((pll->pcr & PLL_PCR_REFDIV(7)) >> 8));
85   - u32 busdiv = ((pll->pdr & 0x00F0) >> 4) + 1;
  84 + u32 pfdr = (in_be32(&pll->pcr) & 0x3F) + 1;
  85 + u32 refdiv = (1 << ((in_be32(&pll->pcr) & PLL_PCR_REFDIV(7)) >> 8));
  86 + u32 busdiv = ((in_be32(&pll->pdr) & 0x00F0) >> 4) + 1;
86 87  
87 88 return (((FREF * pfdr) / refdiv) / busdiv);
88 89 #endif
89 90 #ifdef CONFIG_MCF532x
90   - return ((FREF * pll->pfdr) / (BUSDIV * 4));
  91 + return (FREF * in_8(&pll->pfdr)) / (BUSDIV * 4);
91 92 #endif
92 93 }
93 94 }
... ... @@ -103,7 +104,7 @@
103 104 */
104 105 int clock_limp(int div)
105 106 {
106   - volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
  107 + ccm_t *ccm = (ccm_t *)(MMAP_CCM);
107 108 u32 temp;
108 109  
109 110 /* Check bounds of divider */
110 111  
111 112  
... ... @@ -113,12 +114,12 @@
113 114 div = MAX_LPD;
114 115  
115 116 /* Save of the current value of the SSIDIV so we don't overwrite the value */
116   - temp = (ccm->cdr & CCM_CDR_SSIDIV(0xFF));
  117 + temp = (in_be16(&ccm->cdr) & CCM_CDR_SSIDIV(0xFF));
117 118  
118 119 /* Apply the divider to the system clock */
119   - ccm->cdr = (CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp));
  120 + out_be16(&ccm->cdr, CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp));
120 121  
121   - ccm->misccr |= CCM_MISCCR_LIMP;
  122 + setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
122 123  
123 124 return (FREF / (3 * (1 << div)));
124 125 }
125 126  
126 127  
... ... @@ -126,14 +127,15 @@
126 127 /* Exit low power LIMP mode */
127 128 int clock_exit_limp(void)
128 129 {
129   - volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
  130 + ccm_t *ccm = (ccm_t *)(MMAP_CCM);
130 131 int fout;
131 132  
132 133 /* Exit LIMP mode */
133   - ccm->misccr &= (~CCM_MISCCR_LIMP);
  134 + clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
134 135  
135 136 /* Wait for PLL to lock */
136   - while (!(ccm->misccr & CCM_MISCCR_PLL_LOCK)) ;
  137 + while (!(in_be16(&ccm->misccr) & CCM_MISCCR_PLL_LOCK))
  138 + ;
137 139  
138 140 fout = get_sys_clock();
139 141  
140 142  
... ... @@ -153,10 +155,10 @@
153 155 int clock_pll(int fsys, int flags)
154 156 {
155 157 #ifdef CONFIG_MCF532x
156   - volatile u32 *sdram_workaround = (volatile u32 *)(MMAP_SDRAM + 0x80);
  158 + u32 *sdram_workaround = (u32 *)(MMAP_SDRAM + 0x80);
157 159 #endif
158   - volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
159   - volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
  160 + sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
  161 + pll_t *pll = (pll_t *)(MMAP_PLL);
160 162 int fref, temp, fout, mfd;
161 163 u32 i;
162 164  
163 165  
... ... @@ -165,13 +167,13 @@
165 167 if (fsys == 0) {
166 168 /* Return current PLL output */
167 169 #ifdef CONFIG_MCF5301x
168   - u32 busdiv = ((pll->pdr >> 4) & 0x0F) + 1;
169   - mfd = (pll->pcr & 0x3F) + 1;
  170 + u32 busdiv = ((in_be32(&pll->pdr) >> 4) & 0x0F) + 1;
  171 + mfd = (in_be32(&pll->pcr) & 0x3F) + 1;
170 172  
171 173 return (fref * mfd) / busdiv;
172 174 #endif
173 175 #ifdef CONFIG_MCF532x
174   - mfd = pll->pfdr;
  176 + mfd = in_8(&pll->pfdr);
175 177  
176 178 return (fref * mfd / (BUSDIV * 4));
177 179 #endif
... ... @@ -211,8 +213,8 @@
211 213 * If it has then the SDRAM needs to be put into self refresh
212 214 * mode before reprogramming the PLL.
213 215 */
214   - if (sdram->ctrl & SDRAMC_SDCR_REF)
215   - sdram->ctrl &= ~SDRAMC_SDCR_CKE;
  216 + if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF)
  217 + clrbits_be32(&sdram->ctrl, SDRAMC_SDCR_CKE);
216 218  
217 219 /*
218 220 * Initialize the PLL to generate the new system clock frequency.
219 221  
220 222  
221 223  
222 224  
223 225  
... ... @@ -223,35 +225,36 @@
223 225 clock_limp(DEFAULT_LPD);
224 226  
225 227 #ifdef CONFIG_MCF5301x
226   - pll->pdr =
227   - PLL_PDR_OUTDIV1((BUSDIV / 3) - 1) |
228   - PLL_PDR_OUTDIV2(BUSDIV - 1) |
229   - PLL_PDR_OUTDIV3((BUSDIV / 2) - 1) |
230   - PLL_PDR_OUTDIV4(USBDIV - 1);
  228 + out_be32(&pll->pdr,
  229 + PLL_PDR_OUTDIV1((BUSDIV / 3) - 1) |
  230 + PLL_PDR_OUTDIV2(BUSDIV - 1) |
  231 + PLL_PDR_OUTDIV3((BUSDIV / 2) - 1) |
  232 + PLL_PDR_OUTDIV4(USBDIV - 1));
231 233  
232   - pll->pcr &= PLL_PCR_FBDIV_UNMASK;
233   - pll->pcr |= PLL_PCR_FBDIV(mfd - 1);
  234 + clrbits_be32(&pll->pcr, ~PLL_PCR_FBDIV_UNMASK);
  235 + setbits_be32(&pll->pcr, PLL_PCR_FBDIV(mfd - 1));
234 236 #endif
235 237 #ifdef CONFIG_MCF532x
236 238 /* Reprogram PLL for desired fsys */
237   - pll->podr = (PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV));
  239 + out_8(&pll->podr,
  240 + PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV));
238 241  
239   - pll->pfdr = mfd;
  242 + out_8(&pll->pfdr, mfd);
240 243 #endif
241 244  
242 245 /* Exit LIMP mode */
243 246 clock_exit_limp();
244 247  
245 248 /* Return the SDRAM to normal operation if it is in use. */
246   - if (sdram->ctrl & SDRAMC_SDCR_REF)
247   - sdram->ctrl |= SDRAMC_SDCR_CKE;
  249 + if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF)
  250 + setbits_be32(&sdram->ctrl, SDRAMC_SDCR_CKE);
248 251  
249 252 #ifdef CONFIG_MCF532x
250 253 /*
251 254 * software workaround for SDRAM opeartion after exiting LIMP
252 255 * mode errata
253 256 */
254   - *sdram_workaround = CONFIG_SYS_SDRAM_BASE;
  257 + out_be32(sdram_workaround, CONFIG_SYS_SDRAM_BASE);
255 258 #endif
256 259  
257 260 /* wait for DQS logic to relock */
board/freescale/m53017evb/m53017evb.c
Diff comments   View file @ aa0d99f
... ... @@ -2,7 +2,7 @@
2 2 * (C) Copyright 2000-2003
3 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 4 *
5   - * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
  5 + * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
6 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 7 *
8 8 * See file CREDITS for list of people who contributed to this
... ... @@ -27,6 +27,7 @@
27 27 #include <config.h>
28 28 #include <common.h>
29 29 #include <asm/immap.h>
  30 +#include <asm/io.h>
30 31  
31 32 DECLARE_GLOBAL_DATA_PTR;
32 33  
... ... @@ -39,7 +40,7 @@
39 40  
40 41 phys_size_t initdram(int board_type)
41 42 {
42   - volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
  43 + sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
43 44 u32 dramsize, i;
44 45  
45 46 dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
46 47  
47 48  
48 49  
49 50  
50 51  
51 52  
52 53  
53 54  
... ... @@ -50,34 +51,35 @@
50 51 }
51 52 i--;
52 53  
53   - sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
  54 + out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
54 55 #ifdef CONFIG_SYS_SDRAM_BASE1
55   - sdram->cs1 = (CONFIG_SYS_SDRAM_BASE | i);
  56 + out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i);
56 57 #endif
57   - sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
58   - sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
  58 + out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
  59 + out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
59 60  
60 61 udelay(500);
61 62  
62 63 /* Issue PALL */
63   - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
  64 + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
64 65 asm("nop");
65 66  
66 67 /* Perform two refresh cycles */
67   - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
68   - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
  68 + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
  69 + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
69 70 asm("nop");
70 71  
71 72 /* Issue LEMR */
72   - sdram->mode = CONFIG_SYS_SDRAM_MODE;
  73 + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
73 74 asm("nop");
74   - sdram->mode = CONFIG_SYS_SDRAM_EMOD;
  75 + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
75 76 asm("nop");
76 77  
77   - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
  78 + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
78 79 asm("nop");
79 80  
80   - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
  81 + out_be32(&sdram->ctrl,
  82 + (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
81 83 asm("nop");
82 84  
83 85 udelay(100);
board/freescale/m5329evb/m5329evb.c
Diff comments   View file @ aa0d99f
... ... @@ -2,7 +2,7 @@
2 2 * (C) Copyright 2000-2003
3 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 4 *
5   - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  5 + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
6 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 7 *
8 8 * See file CREDITS for list of people who contributed to this
... ... @@ -27,6 +27,7 @@
27 27 #include <config.h>
28 28 #include <common.h>
29 29 #include <asm/immap.h>
  30 +#include <asm/io.h>
30 31  
31 32 DECLARE_GLOBAL_DATA_PTR;
32 33  
... ... @@ -39,7 +40,7 @@
39 40  
40 41 phys_size_t initdram(int board_type)
41 42 {
42   - volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
  43 + sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
43 44 u32 dramsize, i;
44 45  
45 46 dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
46 47  
47 48  
48 49  
49 50  
50 51  
51 52  
... ... @@ -50,29 +51,30 @@
50 51 }
51 52 i--;
52 53  
53   - sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
54   - sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
55   - sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
  54 + out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
  55 + out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
  56 + out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
56 57  
57 58 /* Issue PALL */
58   - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
  59 + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
59 60  
60 61 /* Issue LEMR */
61   - sdram->mode = CONFIG_SYS_SDRAM_EMOD;
62   - sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
  62 + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
  63 + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
63 64  
64 65 udelay(500);
65 66  
66 67 /* Issue PALL */
67   - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
  68 + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
68 69  
69 70 /* Perform two refresh cycles */
70   - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
71   - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
  71 + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
  72 + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
72 73  
73   - sdram->mode = CONFIG_SYS_SDRAM_MODE;
  74 + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
74 75  
75   - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
  76 + out_be32(&sdram->ctrl,
  77 + (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
76 78  
77 79 udelay(100);
78 80  
board/freescale/m5329evb/nand.c
Diff comments   View file @ aa0d99f
... ... @@ -2,7 +2,7 @@
2 2 * (C) Copyright 2000-2003
3 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 4 *
5   - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  5 + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
6 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 7 *
8 8 * See file CREDITS for list of people who contributed to this
9 9  
... ... @@ -67,18 +67,18 @@
67 67  
68 68 int board_nand_init(struct nand_chip *nand)
69 69 {
70   - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  70 + gpio_t *gpio = (gpio_t *) MMAP_GPIO;
71 71  
72 72 /*
73 73 * set up pin configuration - enabled 2nd output buffer's signals
74 74 * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
75 75 * to use nCE signal
76 76 */
77   - gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
78   - gpio->pddr_timer |= 0x08;
79   - gpio->ppd_timer |= 0x08;
80   - gpio->pclrr_timer = 0;
81   - gpio->podr_timer = 0;
  77 + clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3);
  78 + setbits_8(&gpio->pddr_timer, 0x08);
  79 + setbits_8(&gpio->ppd_timer, 0x08);
  80 + out_8(&gpio->pclrr_timer, 0);
  81 + out_8(&gpio->podr_timer, 0);
82 82  
83 83 nand->chip_delay = 60;
84 84 nand->ecc.mode = NAND_ECC_SOFT;
board/freescale/m5373evb/m5373evb.c
Diff comments   View file @ aa0d99f
... ... @@ -2,7 +2,7 @@
2 2 * (C) Copyright 2000-2003
3 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 4 *
5   - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  5 + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
6 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 7 *
8 8 * See file CREDITS for list of people who contributed to this
... ... @@ -27,6 +27,7 @@
27 27 #include <config.h>
28 28 #include <common.h>
29 29 #include <asm/immap.h>
  30 +#include <asm/io.h>
30 31  
31 32 DECLARE_GLOBAL_DATA_PTR;
32 33  
... ... @@ -39,7 +40,7 @@
39 40  
40 41 phys_size_t initdram(int board_type)
41 42 {
42   - volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
  43 + sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
43 44 u32 dramsize, i;
44 45  
45 46 dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
46 47  
47 48  
48 49  
49 50  
50 51  
51 52  
... ... @@ -50,29 +51,30 @@
50 51 }
51 52 i--;
52 53  
53   - sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
54   - sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
55   - sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
  54 + out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
  55 + out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
  56 + out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
56 57  
57 58 /* Issue PALL */
58   - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
  59 + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
59 60  
60 61 /* Issue LEMR */
61   - sdram->mode = CONFIG_SYS_SDRAM_EMOD;
62   - sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
  62 + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
  63 + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
63 64  
64 65 udelay(500);
65 66  
66 67 /* Issue PALL */
67   - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
  68 + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
68 69  
69 70 /* Perform two refresh cycles */
70   - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
71   - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
  71 + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
  72 + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
72 73  
73   - sdram->mode = CONFIG_SYS_SDRAM_MODE;
  74 + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
74 75  
75   - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
  76 + out_be32(&sdram->ctrl,
  77 + (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
76 78  
77 79 udelay(100);
78 80  
board/freescale/m5373evb/nand.c
Diff comments   View file @ aa0d99f
... ... @@ -2,7 +2,7 @@
2 2 * (C) Copyright 2000-2003
3 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 4 *
5   - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  5 + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
6 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 7 *
8 8 * See file CREDITS for list of people who contributed to this
9 9  
10 10  
... ... @@ -68,21 +68,21 @@
68 68  
69 69 int board_nand_init(struct nand_chip *nand)
70 70 {
71   - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
72   - volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
  71 + gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  72 + fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
73 73  
74   - fbcs->csmr2 &= ~FBCS_CSMR_WP;
  74 + clrbits_be32(&fbcs->csmr2, FBCS_CSMR_WP);
75 75  
76 76 /*
77 77 * set up pin configuration - enabled 2nd output buffer's signals
78 78 * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
79 79 * to use nCE signal
80 80 */
81   - gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
82   - gpio->pddr_timer |= 0x08;
83   - gpio->ppd_timer |= 0x08;
84   - gpio->pclrr_timer = 0;
85   - gpio->podr_timer = 0;
  81 + clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3);
  82 + setbits_8(&gpio->pddr_timer, 0x08);
  83 + setbits_8(&gpio->ppd_timer, 0x08);
  84 + out_8(&gpio->pclrr_timer, 0);
  85 + out_8(&gpio->podr_timer, 0);
86 86  
87 87 nand->chip_delay = 60;
88 88 nand->ecc.mode = NAND_ECC_SOFT;