ColdFire: Clean up checkpatch warnings for MCF52x2

Signed-off-by: Alison Wang <b18965@freescale.com>

ColdFire: Clean up checkpatch warnings for MCF52x2
Signed-off-by: Alison Wang <b18965@freescale.com>
Alison Wang · Jason
1 parent 849fc42471
Showing 9 changed files with 310 additions and 262 deletions Side-by-side Diff
arch/m68k/cpu/mcf52x2/cpu.c
arch/m68k/cpu/mcf52x2/cpu_init.c
arch/m68k/cpu/mcf52x2/interrupts.c
arch/m68k/cpu/mcf52x2/speed.c
board/freescale/m5208evbe/m5208evbe.c
board/freescale/m5253demo/m5253demo.c
board/freescale/m5253evbe/m5253evbe.c
board/freescale/m5272c3/m5272c3.c
board/freescale/m5275evb/m5275evb.c
@@ -9,6 +9,8 @@
  * MCF5275 additions
  * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
  *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -32,6 +34,7 @@
 #include <watchdog.h>
 #include <command.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 #include <netdev.h>
 #include "cpu.h"
  
  
@@ -40,11 +43,11 @@
 #ifdef	CONFIG_M5208
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
+	rcm_t *rcm = (rcm_t *)(MMAP_RCM);
  
 	udelay(1000);
  
-	rcm->rcr = RCM_RCR_SOFTRST;
+	out_8(&rcm->rcr, RCM_RCR_SOFTRST);
  
 	/* we don't return! */
 	return 0;
  
  
@@ -65,18 +68,21 @@
 /* Called by macro WATCHDOG_RESET */
 void watchdog_reset(void)
 {
-	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
-	wdt->sr = 0x5555;
-	wdt->sr = 0xAAAA;
+	wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
+
+	out_be16(&wdt->sr, 0x5555);
+	out_be16(&wdt->sr, 0xaaaa);
 }
  
 int watchdog_disable(void)
 {
-	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+	wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  
-	wdt->sr = 0x5555; /* reset watchdog counter */
-	wdt->sr = 0xAAAA;
-	wdt->cr = 0;	/* disable watchdog timer */
+	/* reset watchdog counter */
+	out_be16(&wdt->sr, 0x5555);
+	out_be16(&wdt->sr, 0xaaaa);
+	/* disable watchdog timer */
+	out_be16(&wdt->cr, 0);
  
 	puts("WATCHDOG:disabled\n");
 	return (0);
  
  
  
@@ -84,16 +90,19 @@
  
 int watchdog_init(void)
 {
-	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+	wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  
-	wdt->cr = 0;	/* disable watchdog */
+	/* disable watchdog */
+	out_be16(&wdt->cr, 0);
  
 	/* set timeout and enable watchdog */
-	wdt->mr =
-		((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
-	wdt->sr = 0x5555; /* reset watchdog counter */
-	wdt->sr = 0xAAAA;
+	out_be16(&wdt->mr,
+		(CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
  
+	/* reset watchdog counter */
+	out_be16(&wdt->sr, 0x5555);
+	out_be16(&wdt->sr, 0xaaaa);
+
 	puts("WATCHDOG:enabled\n");
 	return (0);
 }
  
  
@@ -178,13 +187,13 @@
 #ifdef	CONFIG_M5272
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+	wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
  
-	wdp->wdog_wrrr = 0;
+	out_be16(&wdp->wdog_wrrr, 0);
 	udelay(1000);
  
 	/* enable watchdog, set timeout to 0 and wait */
-	wdp->wdog_wrrr = 1;
+	out_be16(&wdp->wdog_wrrr, 1);
 	while (1) ;
  
 	/* we don't return! */
  
@@ -193,12 +202,12 @@
  
 int checkcpu(void)
 {
-	volatile sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
+	sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
 	uchar msk;
 	char *suf;
  
 	puts("CPU:   ");
-	msk = (sysctrl->sc_dir > 28) & 0xf;
+	msk = (in_be32(&sysctrl->sc_dir) > 28) & 0xf;
 	switch (msk) {
 	case 0x2:
 		suf = "1K75N";
  
  
@@ -221,17 +230,21 @@
 /* Called by macro WATCHDOG_RESET */
 void watchdog_reset(void)
 {
-	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
-	wdt->wdog_wcr = 0;
+	wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
+
+	out_be16(&wdt->wdog_wcr, 0);
 }
  
 int watchdog_disable(void)
 {
-	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+	wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  
-	wdt->wdog_wcr = 0;	/* reset watchdog counter */
-	wdt->wdog_wirr = 0;	/* disable watchdog interrupt */
-	wdt->wdog_wrrr = 0;	/* disable watchdog timer */
+	/* reset watchdog counter */
+	out_be16(&wdt->wdog_wcr, 0);
+	/* disable watchdog interrupt */
+	out_be16(&wdt->wdog_wirr, 0);
+	/* disable watchdog timer */
+	out_be16(&wdt->wdog_wrrr, 0);
  
 	puts("WATCHDOG:disabled\n");
 	return (0);
  
  
  
@@ -239,15 +252,18 @@
  
 int watchdog_init(void)
 {
-	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+	wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  
-	wdt->wdog_wirr = 0;	/* disable watchdog interrupt */
+	/* disable watchdog interrupt */
+	out_be16(&wdt->wdog_wirr, 0);
  
 	/* set timeout and enable watchdog */
-	wdt->wdog_wrrr =
-	    ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
-	wdt->wdog_wcr = 0;	/* reset watchdog counter */
+	out_be16(&wdt->wdog_wrrr,
+		(CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
  
+	/* reset watchdog counter */
+	out_be16(&wdt->wdog_wcr, 0);
+
 	puts("WATCHDOG:enabled\n");
 	return (0);
 }
  
@@ -258,11 +274,11 @@
 #ifdef	CONFIG_M5275
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
+	rcm_t *rcm = (rcm_t *)(MMAP_RCM);
  
 	udelay(1000);
  
-	rcm->rcr = RCM_RCR_SOFTRST;
+	out_8(&rcm->rcr, RCM_RCR_SOFTRST);
  
 	/* we don't return! */
 	return 0;
  
  
  
  
  
  
@@ -282,34 +298,41 @@
 /* Called by macro WATCHDOG_RESET */
 void watchdog_reset(void)
 {
-	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
-	wdt->wsr = 0x5555;
-	wdt->wsr = 0xAAAA;
+	wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
+
+	out_be16(&wdt->wsr, 0x5555);
+	out_be16(&wdt->wsr, 0xaaaa);
 }
  
 int watchdog_disable(void)
 {
-	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+	wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  
-	wdt->wsr = 0x5555; /* reset watchdog counter */
-	wdt->wsr = 0xAAAA;
-	wdt->wcr = 0;	/* disable watchdog timer */
+	/* reset watchdog counter */
+	out_be16(&wdt->wsr, 0x5555);
+	out_be16(&wdt->wsr, 0xaaaa);
  
+	/* disable watchdog timer */
+	out_be16(&wdt->wcr, 0);
+
 	puts("WATCHDOG:disabled\n");
 	return (0);
 }
  
 int watchdog_init(void)
 {
-	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+	wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  
-	wdt->wcr = 0;	/* disable watchdog */
+	/* disable watchdog */
+	out_be16(&wdt->wcr, 0);
  
 	/* set timeout and enable watchdog */
-	wdt->wmr =
-		((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
-	wdt->wsr = 0x5555; /* reset watchdog counter */
-	wdt->wsr = 0xAAAA;
+	out_be16(&wdt->wmr,
+		(CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
+
+	/* reset watchdog counter */
+	out_be16(&wdt->wsr, 0x5555);
+	out_be16(&wdt->wsr, 0xaaaa);
  
 	puts("WATCHDOG:enabled\n");
 	return (0);
@@ -8,7 +8,7 @@
  * (c) Copyright 2010
  * Arcturus Networks Inc. <www.arcturusnetworks.com>
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  * Hayden Fraser (Hayden.Fraser@freescale.com)
  *
@@ -37,6 +37,7 @@
 #include <common.h>
 #include <watchdog.h>
 #include <asm/immap.h>
+#include <asm/io.h>
  
 #if defined(CONFIG_CMD_NET)
 #include <config.h>
  
  
  
  
  
  
  
  
@@ -48,57 +49,57 @@
 /* Only 5272 Flexbus chipselect is different from the rest */
 void init_fbcs(void)
 {
-	volatile fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
+	fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
  
 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
      && defined(CONFIG_SYS_CS0_CTRL))
-	fbcs->csar0 = CONFIG_SYS_CS0_BASE;
-	fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
-	fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
+	out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
+	out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
+	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
 #else
 #warning "Chip Select 0 are not initialized/used"
 #endif
 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
      && defined(CONFIG_SYS_CS1_CTRL))
-	fbcs->csar1 = CONFIG_SYS_CS1_BASE;
-	fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
-	fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
+	out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
+	out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
+	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
 #endif
 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
      && defined(CONFIG_SYS_CS2_CTRL))
-	fbcs->csar2 = CONFIG_SYS_CS2_BASE;
-	fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
-	fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
+	out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
+	out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
+	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
 #endif
 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
      && defined(CONFIG_SYS_CS3_CTRL))
-	fbcs->csar3 = CONFIG_SYS_CS3_BASE;
-	fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
-	fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
+	out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
+	out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
+	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
 #endif
 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
      && defined(CONFIG_SYS_CS4_CTRL))
-	fbcs->csar4 = CONFIG_SYS_CS4_BASE;
-	fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
-	fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
+	out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
+	out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
+	out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
 #endif
 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
      && defined(CONFIG_SYS_CS5_CTRL))
-	fbcs->csar5 = CONFIG_SYS_CS5_BASE;
-	fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
-	fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
+	out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
+	out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
+	out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
 #endif
 #if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \
      && defined(CONFIG_SYS_CS6_CTRL))
-	fbcs->csar6 = CONFIG_SYS_CS6_BASE;
-	fbcs->cscr6 = CONFIG_SYS_CS6_CTRL;
-	fbcs->csmr6 = CONFIG_SYS_CS6_MASK;
+	out_be32(&fbcs->csar6, CONFIG_SYS_CS6_BASE);
+	out_be32(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL);
+	out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK);
 #endif
 #if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \
      && defined(CONFIG_SYS_CS7_CTRL))
-	fbcs->csar7 = CONFIG_SYS_CS7_BASE;
-	fbcs->cscr7 = CONFIG_SYS_CS7_CTRL;
-	fbcs->csmr7 = CONFIG_SYS_CS7_MASK;
+	out_be32(&fbcs->csar7, CONFIG_SYS_CS7_BASE);
+	out_be32(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL);
+	out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK);
 #endif
 }
 #endif
  
  
  
@@ -106,22 +107,22 @@
 #if defined(CONFIG_M5208)
 void cpu_init_f(void)
 {
-	volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+	scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
  
 #ifndef CONFIG_WATCHDOG
-	volatile wdog_t *wdg = (wdog_t *) MMAP_WDOG;
+	wdog_t *wdg = (wdog_t *) MMAP_WDOG;
  
 	/* Disable the watchdog if we aren't using it */
-	wdg->cr = 0;
+	out_be16(&wdg->cr, 0);
 #endif
  
-	scm1->mpr = 0x77777777;
-	scm1->pacra = 0;
-	scm1->pacrb = 0;
-	scm1->pacrc = 0;
-	scm1->pacrd = 0;
-	scm1->pacre = 0;
-	scm1->pacrf = 0;
+	out_be32(&scm1->mpr, 0x77777777);
+	out_be32(&scm1->pacra, 0);
+	out_be32(&scm1->pacrb, 0);
+	out_be32(&scm1->pacrc, 0);
+	out_be32(&scm1->pacrd, 0);
+	out_be32(&scm1->pacre, 0);
+	out_be32(&scm1->pacrf, 0);
  
 	/* FlexBus Chipselect */
 	init_fbcs();
  
  
  
  
  
@@ -137,36 +138,36 @@
  
 void uart_port_conf(int port)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  
 	/* Setup Ports: */
 	switch (port) {
 	case 0:
-		gpio->par_uart &= GPIO_PAR_UART0_UNMASK;
-		gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
+		clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK);
+		setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
 		break;
 	case 1:
-		gpio->par_uart &= GPIO_PAR_UART0_UNMASK;
-		gpio->par_uart |= (GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD);
+		clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK);
+		setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD);
 		break;
 	case 2:
 #ifdef CONFIG_SYS_UART2_PRI_GPIO
-		gpio->par_timer &=
-		    (GPIO_PAR_TMR_TIN0_UNMASK | GPIO_PAR_TMR_TIN1_UNMASK);
-		gpio->par_timer |=
-		    (GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD);
+		clrbits_8(&gpio->par_timer,
+			~(GPIO_PAR_TMR_TIN0_UNMASK | GPIO_PAR_TMR_TIN1_UNMASK));
+		setbits_8(&gpio->par_timer,
+			GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD);
 #endif
 #ifdef CONFIG_SYS_UART2_ALT1_GPIO
-		gpio->par_feci2c &=
-		    (GPIO_PAR_FECI2C_MDC_UNMASK | GPIO_PAR_FECI2C_MDIO_UNMASK);
-		gpio->par_feci2c |=
-		    (GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD);
+		clrbits_8(&gpio->par_feci2c,
+			~(GPIO_PAR_FECI2C_MDC_UNMASK | GPIO_PAR_FECI2C_MDIO_UNMASK));
+		setbits_8(&gpio->par_feci2c,
+			GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD);
 #endif
 #ifdef CONFIG_SYS_UART2_ALT1_GPIO
-		gpio->par_feci2c &=
-		    (GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK);
-		gpio->par_feci2c |=
-		    (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
+		clrbits_8(&gpio->par_feci2c,
+			~(GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK));
+		setbits_8(&gpio->par_feci2c,
+			GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
 #endif
 		break;
 	}
  
  
@@ -175,17 +176,17 @@
 #if defined(CONFIG_CMD_NET)
 int fecpin_setclear(struct eth_device *dev, int setclear)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  
 	if (setclear) {
-		gpio->par_fec |=
-		    GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
-		gpio->par_feci2c |=
-		    GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO;
+		setbits_8(&gpio->par_fec,
+			GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
+		setbits_8(&gpio->par_feci2c,
+			GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO);
 	} else {
-		gpio->par_fec &=
-		    (GPIO_PAR_FEC_7W_UNMASK & GPIO_PAR_FEC_MII_UNMASK);
-		gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII_UNMASK;
+		clrbits_8(&gpio->par_fec,
+			~(GPIO_PAR_FEC_7W_UNMASK & GPIO_PAR_FEC_MII_UNMASK));
+		clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII_UNMASK);
 	}
 	return 0;
 }
  
  
@@ -249,17 +250,17 @@
  
 void uart_port_conf(int port)
 {
-	volatile u32 *par = (u32 *) MMAP_PAR;
+	u32 *par = (u32 *) MMAP_PAR;
  
 	/* Setup Ports: */
 	switch (port) {
 	case 1:
-		*par &= 0xFFE7FFFF;
-		*par |= 0x00180000;
+		clrbits_be32(par, 0x00180000);
+		setbits_be32(par, 0x00180000);
 		break;
 	case 2:
-		*par &= 0xFFFFFFFC;
-		*par &= 0x00000003;
+		clrbits_be32(par, 0x00000003);
+		clrbits_be32(par, 0xFFFFFFFC);
 		break;
 	}
 }
  
  
  
  
  
  
  
  
  
  
@@ -348,59 +349,59 @@
 	 * already initialized.
 	 */
 #ifndef CONFIG_MONITOR_IS_IN_RAM
-	volatile sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR);
-	volatile gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
-	volatile csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
+	sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR);
+	gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
+	csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
  
-	sysctrl->sc_scr = CONFIG_SYS_SCR;
-	sysctrl->sc_spr = CONFIG_SYS_SPR;
+	out_be16(&sysctrl->sc_scr, CONFIG_SYS_SCR);
+	out_be16(&sysctrl->sc_spr, CONFIG_SYS_SPR);
  
 	/* Setup Ports: */
-	gpio->gpio_pacnt = CONFIG_SYS_PACNT;
-	gpio->gpio_paddr = CONFIG_SYS_PADDR;
-	gpio->gpio_padat = CONFIG_SYS_PADAT;
-	gpio->gpio_pbcnt = CONFIG_SYS_PBCNT;
-	gpio->gpio_pbddr = CONFIG_SYS_PBDDR;
-	gpio->gpio_pbdat = CONFIG_SYS_PBDAT;
-	gpio->gpio_pdcnt = CONFIG_SYS_PDCNT;
+	out_be32(&gpio->gpio_pacnt, CONFIG_SYS_PACNT);
+	out_be16(&gpio->gpio_paddr, CONFIG_SYS_PADDR);
+	out_be16(&gpio->gpio_padat, CONFIG_SYS_PADAT);
+	out_be32(&gpio->gpio_pbcnt, CONFIG_SYS_PBCNT);
+	out_be16(&gpio->gpio_pbddr, CONFIG_SYS_PBDDR);
+	out_be16(&gpio->gpio_pbdat, CONFIG_SYS_PBDAT);
+	out_be32(&gpio->gpio_pdcnt, CONFIG_SYS_PDCNT);
  
 	/* Memory Controller: */
-	csctrl->cs_br0 = CONFIG_SYS_BR0_PRELIM;
-	csctrl->cs_or0 = CONFIG_SYS_OR0_PRELIM;
+	out_be32(&csctrl->cs_br0, CONFIG_SYS_BR0_PRELIM);
+	out_be32(&csctrl->cs_or0, CONFIG_SYS_OR0_PRELIM);
  
 #if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
-	csctrl->cs_br1 = CONFIG_SYS_BR1_PRELIM;
-	csctrl->cs_or1 = CONFIG_SYS_OR1_PRELIM;
+	out_be32(&csctrl->cs_br1, CONFIG_SYS_BR1_PRELIM);
+	out_be32(&csctrl->cs_or1, CONFIG_SYS_OR1_PRELIM);
 #endif
  
 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
-	csctrl->cs_br2 = CONFIG_SYS_BR2_PRELIM;
-	csctrl->cs_or2 = CONFIG_SYS_OR2_PRELIM;
+	out_be32(&csctrl->cs_br2, CONFIG_SYS_BR2_PRELIM);
+	out_be32(&csctrl->cs_or2, CONFIG_SYS_OR2_PRELIM);
 #endif
  
 #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
-	csctrl->cs_br3 = CONFIG_SYS_BR3_PRELIM;
-	csctrl->cs_or3 = CONFIG_SYS_OR3_PRELIM;
+	out_be32(&csctrl->cs_br3, CONFIG_SYS_BR3_PRELIM);
+	out_be32(&csctrl->cs_or3, CONFIG_SYS_OR3_PRELIM);
 #endif
  
 #if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
-	csctrl->cs_br4 = CONFIG_SYS_BR4_PRELIM;
-	csctrl->cs_or4 = CONFIG_SYS_OR4_PRELIM;
+	out_be32(&csctrl->cs_br4, CONFIG_SYS_BR4_PRELIM);
+	out_be32(&csctrl->cs_or4, CONFIG_SYS_OR4_PRELIM);
 #endif
  
 #if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
-	csctrl->cs_br5 = CONFIG_SYS_BR5_PRELIM;
-	csctrl->cs_or5 = CONFIG_SYS_OR5_PRELIM;
+	out_be32(&csctrl->cs_br5, CONFIG_SYS_BR5_PRELIM);
+	out_be32(&csctrl->cs_or5, CONFIG_SYS_OR5_PRELIM);
 #endif
  
 #if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
-	csctrl->cs_br6 = CONFIG_SYS_BR6_PRELIM;
-	csctrl->cs_or6 = CONFIG_SYS_OR6_PRELIM;
+	out_be32(&csctrl->cs_br6, CONFIG_SYS_BR6_PRELIM);
+	out_be32(&csctrl->cs_or6, CONFIG_SYS_OR6_PRELIM);
 #endif
  
 #if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
-	csctrl->cs_br7 = CONFIG_SYS_BR7_PRELIM;
-	csctrl->cs_or7 = CONFIG_SYS_OR7_PRELIM;
+	out_be32(&csctrl->cs_br7, CONFIG_SYS_BR7_PRELIM);
+	out_be32(&csctrl->cs_or7, CONFIG_SYS_OR7_PRELIM);
 #endif
  
 #endif				/* #ifndef CONFIG_MONITOR_IS_IN_RAM */
  
  
@@ -420,17 +421,21 @@
  
 void uart_port_conf(int port)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  
 	/* Setup Ports: */
 	switch (port) {
 	case 0:
-		gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
-		gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
+		clrbits_be32(&gpio->gpio_pbcnt,
+			GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
+		setbits_be32(&gpio->gpio_pbcnt,
+			GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
 		break;
 	case 1:
-		gpio->gpio_pdcnt &= ~(GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK);
-		gpio->gpio_pdcnt |= (GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD);
+		clrbits_be32(&gpio->gpio_pdcnt,
+			GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK);
+		setbits_be32(&gpio->gpio_pdcnt,
+			GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD);
 		break;
 	}
 }
  
@@ -438,13 +443,14 @@
 #if defined(CONFIG_CMD_NET)
 int fecpin_setclear(struct eth_device *dev, int setclear)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  
 	if (setclear) {
-		gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER |
-				    GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 |
-				    GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 |
-				    GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3;
+		setbits_be32(&gpio->gpio_pbcnt,
+			GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER |
+			GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 |
+			GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 |
+			GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3);
 	} else {
 	}
 	return 0;
  
@@ -469,11 +475,11 @@
 	 */
  
 #ifndef CONFIG_MONITOR_IS_IN_RAM
-	volatile wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG);
-	volatile gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO);
+	wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG);
+	gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO);
  
 	/* Kill watchdog so we can initialize the PLL */
-	wdog_reg->wcr = 0;
+	out_be16(&wdog_reg->wcr, 0);
  
 	/* FlexBus Chipselect */
 	init_fbcs();
  
  
  
@@ -498,21 +504,21 @@
  
 void uart_port_conf(int port)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  
 	/* Setup Ports: */
 	switch (port) {
 	case 0:
-		gpio->par_uart &= ~UART0_ENABLE_MASK;
-		gpio->par_uart |= UART0_ENABLE_MASK;
+		clrbits_be16(&gpio->par_uart, UART0_ENABLE_MASK);
+		setbits_be16(&gpio->par_uart, UART0_ENABLE_MASK);
 		break;
 	case 1:
-		gpio->par_uart &= ~UART1_ENABLE_MASK;
-		gpio->par_uart |= UART1_ENABLE_MASK;
+		clrbits_be16(&gpio->par_uart, UART1_ENABLE_MASK);
+		setbits_be16(&gpio->par_uart, UART1_ENABLE_MASK);
 		break;
 	case 2:
-		gpio->par_uart &= ~UART2_ENABLE_MASK;
-		gpio->par_uart |= UART2_ENABLE_MASK;
+		clrbits_be16(&gpio->par_uart, UART2_ENABLE_MASK);
+		setbits_be16(&gpio->par_uart, UART2_ENABLE_MASK);
 		break;
 	}
 }
  
  
  
  
@@ -521,24 +527,24 @@
 int fecpin_setclear(struct eth_device *dev, int setclear)
 {
 	struct fec_info_s *info = (struct fec_info_s *) dev->priv;
-	volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *)MMAP_GPIO;
  
 	if (setclear) {
 		/* Enable Ethernet pins */
 		if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
-			gpio->par_feci2c |= 0x0F00;
-			gpio->par_fec0hl |= 0xC0;
+			setbits_be16(&gpio->par_feci2c, 0x0f00);
+			setbits_8(&gpio->par_fec0hl, 0xc0);
 		} else {
-			gpio->par_feci2c |= 0x00A0;
-			gpio->par_fec1hl |= 0xC0;
+			setbits_be16(&gpio->par_feci2c, 0x00a0);
+			setbits_8(&gpio->par_fec1hl, 0xc0);
 		}
 	} else {
 		if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
-			gpio->par_feci2c &= ~0x0F00;
-			gpio->par_fec0hl &= ~0xC0;
+			clrbits_be16(&gpio->par_feci2c, 0x0f00);
+			clrbits_8(&gpio->par_fec0hl, 0xc0);
 		} else {
-			gpio->par_feci2c &= ~0x00A0;
-			gpio->par_fec1hl &= ~0xC0;
+			clrbits_be16(&gpio->par_feci2c, 0x00a0);
+			clrbits_8(&gpio->par_fec1hl, 0xc0);
 		}
 	}
  
@@ -2,7 +2,7 @@
  * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
  
  
  
@@ -28,20 +28,22 @@
 #include <watchdog.h>
 #include <asm/processor.h>
 #include <asm/immap.h>
+#include <asm/io.h>
  
 #ifdef	CONFIG_M5272
 int interrupt_init(void)
 {
-	volatile intctrl_t *intp = (intctrl_t *) (MMAP_INTC);
+	intctrl_t *intp = (intctrl_t *) (MMAP_INTC);
  
 	/* disable all external interrupts */
-	intp->int_icr1 = 0x88888888;
-	intp->int_icr2 = 0x88888888;
-	intp->int_icr3 = 0x88888888;
-	intp->int_icr4 = 0x88888888;
-	intp->int_pitr = 0x00000000;
+	out_be32(&intp->int_icr1, 0x88888888);
+	out_be32(&intp->int_icr2, 0x88888888);
+	out_be32(&intp->int_icr3, 0x88888888);
+	out_be32(&intp->int_icr4, 0x88888888);
+	out_be32(&intp->int_pitr, 0x00000000);
+
 	/* initialize vector register */
-	intp->int_pivr = 0x40;
+	out_8(&intp->int_pivr, 0x40);
  
 	enable_interrupts();
  
  
@@ -51,10 +53,10 @@
 #if defined(CONFIG_MCFTMR)
 void dtimer_intr_setup(void)
 {
-	volatile intctrl_t *intp = (intctrl_t *) (CONFIG_SYS_INTR_BASE);
+	intctrl_t *intp = (intctrl_t *) (CONFIG_SYS_INTR_BASE);
  
-	intp->int_icr1 &= ~INT_ICR1_TMR3MASK;
-	intp->int_icr1 |= CONFIG_SYS_TMRINTR_PRI;
+	clrbits_be32(&intp->int_icr1, INT_ICR1_TMR3MASK);
+	setbits_be32(&intp->int_icr1, CONFIG_SYS_TMRINTR_PRI);
 }
 #endif				/* CONFIG_MCFTMR */
 #endif				/* CONFIG_M5272 */
  
  
@@ -63,14 +65,14 @@
     defined(CONFIG_M5271) || defined(CONFIG_M5275)
 int interrupt_init(void)
 {
-	volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
  
 	/* Make sure all interrupts are disabled */
 #if defined(CONFIG_M5208)
-	intp->imrl0 = 0xFFFFFFFF;
-	intp->imrh0 = 0xFFFFFFFF;
+	out_be32(&intp->imrl0, 0xffffffff);
+	out_be32(&intp->imrh0, 0xffffffff);
 #else
-	intp->imrl0 |= 0x1;
+	setbits_be32(&intp->imrl0, 0x1);
 #endif
  
 	enable_interrupts();
  
@@ -80,11 +82,11 @@
 #if defined(CONFIG_MCFTMR)
 void dtimer_intr_setup(void)
 {
-	volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
  
-	intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
-	intp->imrl0 &= 0xFFFFFFFE;
-	intp->imrl0 &= ~CONFIG_SYS_TMRINTR_MASK;
+	out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
+	clrbits_be32(&intp->imrl0, 0x00000001);
+	clrbits_be32(&intp->imrl0, CONFIG_SYS_TMRINTR_MASK);
 }
 #endif				/* CONFIG_MCFTMR */
 #endif				/* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */
@@ -2,7 +2,7 @@
  * (C) Copyright 2003
  * Josef Baumgartner <josef.baumgartner@telex.de>
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * Hayden Fraser (Hayden.Fraser@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -27,6 +27,7 @@
 #include <common.h>
 #include <asm/processor.h>
 #include <asm/immap.h>
+#include <asm/io.h>
  
 DECLARE_GLOBAL_DATA_PTR;
  
  
@@ -34,10 +35,10 @@
 int get_clocks (void)
 {
 #if defined(CONFIG_M5208)
-	volatile pll_t *pll = (pll_t *) MMAP_PLL;
+	pll_t *pll = (pll_t *) MMAP_PLL;
  
-	pll->odr = CONFIG_SYS_PLL_ODR;
-	pll->fdr = CONFIG_SYS_PLL_FDR;
+	out_8(&pll->odr, CONFIG_SYS_PLL_ODR);
+	out_8(&pll->fdr, CONFIG_SYS_PLL_FDR);
 #endif
  
 #if defined(CONFIG_M5249) || defined(CONFIG_M5253)
  
  
@@ -70,14 +71,14 @@
 #endif				/* CONFIG_M5249 || CONFIG_M5253 */
  
 #if defined(CONFIG_M5275)
-	volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
+	pll_t *pll = (pll_t *)(MMAP_PLL);
  
 	/* Setup PLL */
-	pll->syncr = 0x01080000;
-	while (!(pll->synsr & FMPLL_SYNSR_LOCK))
+	out_be32(&pll->syncr, 0x01080000);
+	while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK))
 		;
-	pll->syncr = 0x01000000;
-	while (!(pll->synsr & FMPLL_SYNSR_LOCK))
+	out_be32(&pll->syncr, 0x01000000);
+	while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK))
 		;
 #endif
  
@@ -2,7 +2,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -27,6 +27,7 @@
 #include <config.h>
 #include <common.h>
 #include <asm/immap.h>
+#include <asm/io.h>
  
 DECLARE_GLOBAL_DATA_PTR;
  
@@ -39,7 +40,7 @@
  
 phys_size_t initdram(int board_type)
 {
-	volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
 	u32 dramsize, i;
  
 	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
  
  
  
  
  
  
  
  
@@ -50,34 +51,35 @@
 	}
 	i--;
  
-	sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
+	out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
 #ifdef CONFIG_SYS_SDRAM_BASE1
-	sdram->cs1 = (CONFIG_SYS_SDRAM_BASE | i);
+	out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i);
 #endif
-	sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
-	sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+	out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+	out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
  
 	udelay(500);
  
 	/* Issue PALL */
-	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
 	asm("nop");
  
 	/* Perform two refresh cycles */
-	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
-	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
 	asm("nop");
  
 	/* Issue LEMR */
-	sdram->mode = CONFIG_SYS_SDRAM_MODE;
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
 	asm("nop");
-	sdram->mode = CONFIG_SYS_SDRAM_EMOD;
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
 	asm("nop");
  
-	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
 	asm("nop");
  
-	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
+	out_be32(&sdram->ctrl,
+		(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
 	asm("nop");
  
 	udelay(100);
@@ -2,7 +2,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * Hayden Fraser (Hayden.Fraser@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -109,7 +109,7 @@
  
 void ide_set_reset(int idereset)
 {
-	volatile atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
+	atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
 	long period;
 	/*  t1,  t2,  t3,  t4,  t5,  t6,  t9, tRD,  tA */
 	int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35},	/* PIO 0 */
@@ -120,7 +120,8 @@
 	};
  
 	if (idereset) {
-		ata->cr = 0;	/* control reset */
+		/* control reset */
+		out_8(&ata->cr, 0);
 		udelay(100);
 	} else {
 		mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
  
  
@@ -129,17 +130,19 @@
 		period = 1000000000 / (CONFIG_SYS_CLK / 2);	/* period in ns */
  
 		/*ata->ton = CALC_TIMING (180); */
-		ata->t1 = CALC_TIMING(piotms[2][0]);
-		ata->t2w = CALC_TIMING(piotms[2][1]);
-		ata->t2r = CALC_TIMING(piotms[2][1]);
-		ata->ta = CALC_TIMING(piotms[2][8]);
-		ata->trd = CALC_TIMING(piotms[2][7]);
-		ata->t4 = CALC_TIMING(piotms[2][3]);
-		ata->t9 = CALC_TIMING(piotms[2][6]);
+		out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
+		out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
+		out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
+		out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
+		out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
+		out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
+		out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
  
-		ata->cr = 0x40;	/* IORDY enable */
+		/* IORDY enable */
+		out_8(&ata->cr, 0x40);
 		udelay(2000);
-		ata->cr |= 0x01;	/* IORDY enable */
+		/* IORDY enable */
+		setbits_8(&ata->cr, 0x01);
 	}
 }
 #endif				/* CONFIG_CMD_IDE */
@@ -2,7 +2,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * Hayden Fraser (Hayden.Fraser@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -26,6 +26,7 @@
  
 #include <common.h>
 #include <asm/immap.h>
+#include <asm/io.h>
  
 int checkboard(void)
 {
@@ -101,7 +102,7 @@
  
 void ide_set_reset(int idereset)
 {
-	volatile atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
+	atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
 	long period;
 	/*  t1,  t2,  t3,  t4,  t5,  t6,  t9, tRD,  tA */
 	int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35},	/* PIO 0 */
@@ -112,7 +113,8 @@
 	};
  
 	if (idereset) {
-		ata->cr = 0;	/* control reset */
+		/* control reset */
+		out_8(&ata->cr, 0);
 		udelay(100);
 	} else {
 		mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
  
  
@@ -121,17 +123,19 @@
 		period = 1000000000 / (CONFIG_SYS_CLK / 2);	/* period in ns */
  
 		/*ata->ton = CALC_TIMING (180); */
-		ata->t1 = CALC_TIMING(piotms[2][0]);
-		ata->t2w = CALC_TIMING(piotms[2][1]);
-		ata->t2r = CALC_TIMING(piotms[2][1]);
-		ata->ta = CALC_TIMING(piotms[2][8]);
-		ata->trd = CALC_TIMING(piotms[2][7]);
-		ata->t4 = CALC_TIMING(piotms[2][3]);
-		ata->t9 = CALC_TIMING(piotms[2][6]);
+		out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
+		out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
+		out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
+		out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
+		out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
+		out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
+		out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
  
-		ata->cr = 0x40;	/* IORDY enable */
+		/* IORDY enable */
+		out_8(&ata->cr, 0x40);
 		udelay(2000);
-		ata->cr |= 0x01;	/* IORDY enable */
+		/* IORDY enable */
+		setbits_8(&ata->cr, 0x01);
 	}
 }
 #endif				/* CONFIG_CMD_IDE */
@@ -2,6 +2,8 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -23,6 +25,7 @@
  
 #include <common.h>
 #include <asm/immap.h>
+#include <asm/io.h>
  
  
 int checkboard (void) {
  
@@ -32,10 +35,10 @@
 	};
  
 phys_size_t initdram (int board_type) {
-	volatile sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM);
+	sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM);
  
-	sdp->sdram_sdtr = 0xf539;
-	sdp->sdram_sdcr = 0x4211;
+	out_be16(&sdp->sdram_sdtr, 0xf539);
+	out_be16(&sdp->sdram_sdcr, 0x4211);
  
 	/* Dummy write to start SDRAM */
 	*((volatile unsigned long *)0) = 0;
@@ -4,6 +4,8 @@
  *
  * Copyright (C) 2005-2008 Arthur Shipkowski (art@videon-central.com)
  *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -25,6 +27,7 @@
  
 #include <common.h>
 #include <asm/immap.h>
+#include <asm/io.h>
  
 #define PERIOD		13	/* system bus period in ns */
 #define SDRAM_TREFI	7800	/* in ns */
  
  
  
  
  
  
  
  
  
  
  
  
  
  
@@ -38,67 +41,68 @@
  
 phys_size_t initdram(int board_type)
 {
-	volatile sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM);
-	volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
+	sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM);
+	gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
  
-	gpio_reg->par_sdram = 0x3FF; /* Enable SDRAM */
+	/* Enable SDRAM */
+	out_be16(&gpio_reg->par_sdram, 0x3FF);
  
 	/* Set up chip select */
-	sdp->sdbar0 = CONFIG_SYS_SDRAM_BASE;
-	sdp->sdbmr0 = MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V;
+	out_be32(&sdp->sdbar0, CONFIG_SYS_SDRAM_BASE);
+	out_be32(&sdp->sdbmr0, MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V);
  
 	/* Set up timing */
-	sdp->sdcfg1 = 0x83711630;
-	sdp->sdcfg2 = 0x46770000;
+	out_be32(&sdp->sdcfg1, 0x83711630);
+	out_be32(&sdp->sdcfg2, 0x46770000);
  
 	/* Enable clock */
-	sdp->sdcr = MCF_SDRAMC_SDCR_MODE_EN | MCF_SDRAMC_SDCR_CKE;
+	out_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN | MCF_SDRAMC_SDCR_CKE);
  
 	/* Set precharge */
-	sdp->sdcr |= MCF_SDRAMC_SDCR_IPALL;
+	setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
  
 	/* Dummy write to start SDRAM */
 	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
  
 	/* Send LEMR */
-	sdp->sdmr = MCF_SDRAMC_SDMR_BNKAD_LEMR
-			| MCF_SDRAMC_SDMR_AD(0x0)
-			| MCF_SDRAMC_SDMR_CMD;
+	setbits_be32(&sdp->sdmr,
+		MCF_SDRAMC_SDMR_BNKAD_LEMR | MCF_SDRAMC_SDMR_AD(0x0) |
+		MCF_SDRAMC_SDMR_CMD);
 	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
  
 	/* Send LMR */
-	sdp->sdmr = 0x058d0000;
+	out_be32(&sdp->sdmr, 0x058d0000);
 	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
  
 	/* Stop sending commands */
-	sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD);
+	clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
  
 	/* Set precharge */
-	sdp->sdcr |= MCF_SDRAMC_SDCR_IPALL;
+	setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
 	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
  
 	/* Stop manual precharge, send 2 IREF */
-	sdp->sdcr &= ~(MCF_SDRAMC_SDCR_IPALL);
-	sdp->sdcr |= MCF_SDRAMC_SDCR_IREF;
+	clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
+	setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IREF);
 	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
 	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
  
-	/* Write mode register, clear reset DLL */
-	sdp->sdmr = 0x018d0000;
+
+	out_be32(&sdp->sdmr, 0x018d0000);
 	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
  
 	/* Stop sending commands */
-	sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD);
-	sdp->sdcr &= ~(MCF_SDRAMC_SDCR_MODE_EN);
+	clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
+	clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN);
  
 	/* Turn on auto refresh, lock SDMR */
-	sdp->sdcr =
+	out_be32(&sdp->sdcr,
 		MCF_SDRAMC_SDCR_CKE
 		| MCF_SDRAMC_SDCR_REF
 		| MCF_SDRAMC_SDCR_MUX(1)
 		/* 1 added to round up */
 		| MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1)
-		| MCF_SDRAMC_SDCR_DQS_OE(0x3);
+		| MCF_SDRAMC_SDCR_DQS_OE(0x3));
  
 	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 };
...	...	@@ -9,6 +9,8 @@
9	9	* MCF5275 additions
10	10	* Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
11	11	*
	12	+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
	13	+ *
12	14	* See file CREDITS for list of people who contributed to this
13	15	* project.
14	16	*
...	...	@@ -32,6 +34,7 @@
32	34	#include <watchdog.h>
33	35	#include <command.h>
34	36	#include <asm/immap.h>
	37	+#include <asm/io.h>
35	38	#include <netdev.h>
36	39	#include "cpu.h"
37	40
38	41
...	...	@@ -40,11 +43,11 @@
40	43	#ifdef CONFIG_M5208
41	44	int do_reset(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
42	45	{
43		- volatile rcm_t rcm = (rcm_t )(MMAP_RCM);
	46	+ rcm_t rcm = (rcm_t )(MMAP_RCM);
44	47
45	48	udelay(1000);
46	49
47		- rcm->rcr = RCM_RCR_SOFTRST;
	50	+ out_8(&rcm->rcr, RCM_RCR_SOFTRST);
48	51
49	52	/* we don't return! */
50	53	return 0;
51	54
52	55
...	...	@@ -65,18 +68,21 @@
65	68	/* Called by macro WATCHDOG_RESET */
66	69	void watchdog_reset(void)
67	70	{
68		- volatile wdog_t wdt = (volatile wdog_t )(MMAP_WDOG);
69		- wdt->sr = 0x5555;
70		- wdt->sr = 0xAAAA;
	71	+ wdog_t wdt = (wdog_t )(MMAP_WDOG);
	72	+
	73	+ out_be16(&wdt->sr, 0x5555);
	74	+ out_be16(&wdt->sr, 0xaaaa);
71	75	}
72	76
73	77	int watchdog_disable(void)
74	78	{
75		- volatile wdog_t wdt = (volatile wdog_t )(MMAP_WDOG);
	79	+ wdog_t wdt = (wdog_t )(MMAP_WDOG);
76	80
77		- wdt->sr = 0x5555; /* reset watchdog counter */
78		- wdt->sr = 0xAAAA;
79		- wdt->cr = 0; /* disable watchdog timer */
	81	+ /* reset watchdog counter */
	82	+ out_be16(&wdt->sr, 0x5555);
	83	+ out_be16(&wdt->sr, 0xaaaa);
	84	+ /* disable watchdog timer */
	85	+ out_be16(&wdt->cr, 0);
80	86
81	87	puts("WATCHDOG:disabled\n");
82	88	return (0);
83	89
84	90
85	91
...	...	@@ -84,16 +90,19 @@
84	90
85	91	int watchdog_init(void)
86	92	{
87		- volatile wdog_t wdt = (volatile wdog_t )(MMAP_WDOG);
	93	+ wdog_t wdt = (wdog_t )(MMAP_WDOG);
88	94
89		- wdt->cr = 0; /* disable watchdog */
	95	+ /* disable watchdog */
	96	+ out_be16(&wdt->cr, 0);
90	97
91	98	/* set timeout and enable watchdog */
92		- wdt->mr =
93		- ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
94		- wdt->sr = 0x5555; /* reset watchdog counter */
95		- wdt->sr = 0xAAAA;
	99	+ out_be16(&wdt->mr,
	100	+ (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
96	101
	102	+ /* reset watchdog counter */
	103	+ out_be16(&wdt->sr, 0x5555);
	104	+ out_be16(&wdt->sr, 0xaaaa);
	105	+
97	106	puts("WATCHDOG:enabled\n");
98	107	return (0);
99	108	}
100	109
101	110
...	...	@@ -178,13 +187,13 @@
178	187	#ifdef CONFIG_M5272
179	188	int do_reset(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
180	189	{
181		- volatile wdog_t wdp = (wdog_t ) (MMAP_WDOG);
	190	+ wdog_t wdp = (wdog_t ) (MMAP_WDOG);
182	191
183		- wdp->wdog_wrrr = 0;
	192	+ out_be16(&wdp->wdog_wrrr, 0);
184	193	udelay(1000);
185	194
186	195	/* enable watchdog, set timeout to 0 and wait */
187		- wdp->wdog_wrrr = 1;
	196	+ out_be16(&wdp->wdog_wrrr, 1);
188	197	while (1) ;
189	198
190	199	/* we don't return! */
191	200
...	...	@@ -193,12 +202,12 @@
193	202
194	203	int checkcpu(void)
195	204	{
196		- volatile sysctrl_t sysctrl = (sysctrl_t ) (MMAP_CFG);
	205	+ sysctrl_t sysctrl = (sysctrl_t ) (MMAP_CFG);
197	206	uchar msk;
198	207	char *suf;
199	208
200	209	puts("CPU: ");
201		- msk = (sysctrl->sc_dir > 28) & 0xf;
	210	+ msk = (in_be32(&sysctrl->sc_dir) > 28) & 0xf;
202	211	switch (msk) {
203	212	case 0x2:
204	213	suf = "1K75N";
205	214
206	215
...	...	@@ -221,17 +230,21 @@
221	230	/* Called by macro WATCHDOG_RESET */
222	231	void watchdog_reset(void)
223	232	{
224		- volatile wdog_t wdt = (volatile wdog_t )(MMAP_WDOG);
225		- wdt->wdog_wcr = 0;
	233	+ wdog_t wdt = (wdog_t )(MMAP_WDOG);
	234	+
	235	+ out_be16(&wdt->wdog_wcr, 0);
226	236	}
227	237
228	238	int watchdog_disable(void)
229	239	{
230		- volatile wdog_t wdt = (volatile wdog_t )(MMAP_WDOG);
	240	+ wdog_t wdt = (wdog_t )(MMAP_WDOG);
231	241
232		- wdt->wdog_wcr = 0; /* reset watchdog counter */
233		- wdt->wdog_wirr = 0; /* disable watchdog interrupt */
234		- wdt->wdog_wrrr = 0; /* disable watchdog timer */
	242	+ /* reset watchdog counter */
	243	+ out_be16(&wdt->wdog_wcr, 0);
	244	+ /* disable watchdog interrupt */
	245	+ out_be16(&wdt->wdog_wirr, 0);
	246	+ /* disable watchdog timer */
	247	+ out_be16(&wdt->wdog_wrrr, 0);
235	248
236	249	puts("WATCHDOG:disabled\n");
237	250	return (0);
238	251
239	252
240	253
...	...	@@ -239,15 +252,18 @@
239	252
240	253	int watchdog_init(void)
241	254	{
242		- volatile wdog_t wdt = (volatile wdog_t )(MMAP_WDOG);
	255	+ wdog_t wdt = (wdog_t )(MMAP_WDOG);
243	256
244		- wdt->wdog_wirr = 0; /* disable watchdog interrupt */
	257	+ /* disable watchdog interrupt */
	258	+ out_be16(&wdt->wdog_wirr, 0);
245	259
246	260	/* set timeout and enable watchdog */
247		- wdt->wdog_wrrr =
248		- ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
249		- wdt->wdog_wcr = 0; /* reset watchdog counter */
	261	+ out_be16(&wdt->wdog_wrrr,
	262	+ (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
250	263
	264	+ /* reset watchdog counter */
	265	+ out_be16(&wdt->wdog_wcr, 0);
	266	+
251	267	puts("WATCHDOG:enabled\n");
252	268	return (0);
253	269	}
254	270
...	...	@@ -258,11 +274,11 @@
258	274	#ifdef CONFIG_M5275
259	275	int do_reset(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
260	276	{
261		- volatile rcm_t rcm = (rcm_t )(MMAP_RCM);
	277	+ rcm_t rcm = (rcm_t )(MMAP_RCM);
262	278
263	279	udelay(1000);
264	280
265		- rcm->rcr = RCM_RCR_SOFTRST;
	281	+ out_8(&rcm->rcr, RCM_RCR_SOFTRST);
266	282
267	283	/* we don't return! */
268	284	return 0;
269	285
270	286
271	287
272	288
273	289
274	290
...	...	@@ -282,34 +298,41 @@
282	298	/* Called by macro WATCHDOG_RESET */
283	299	void watchdog_reset(void)
284	300	{
285		- volatile wdog_t wdt = (volatile wdog_t )(MMAP_WDOG);
286		- wdt->wsr = 0x5555;
287		- wdt->wsr = 0xAAAA;
	301	+ wdog_t wdt = (wdog_t )(MMAP_WDOG);
	302	+
	303	+ out_be16(&wdt->wsr, 0x5555);
	304	+ out_be16(&wdt->wsr, 0xaaaa);
288	305	}
289	306
290	307	int watchdog_disable(void)
291	308	{
292		- volatile wdog_t wdt = (volatile wdog_t )(MMAP_WDOG);
	309	+ wdog_t wdt = (wdog_t )(MMAP_WDOG);
293	310
294		- wdt->wsr = 0x5555; /* reset watchdog counter */
295		- wdt->wsr = 0xAAAA;
296		- wdt->wcr = 0; /* disable watchdog timer */
	311	+ /* reset watchdog counter */
	312	+ out_be16(&wdt->wsr, 0x5555);
	313	+ out_be16(&wdt->wsr, 0xaaaa);
297	314
	315	+ /* disable watchdog timer */
	316	+ out_be16(&wdt->wcr, 0);
	317	+
298	318	puts("WATCHDOG:disabled\n");
299	319	return (0);
300	320	}
301	321
302	322	int watchdog_init(void)
303	323	{
304		- volatile wdog_t wdt = (volatile wdog_t )(MMAP_WDOG);
	324	+ wdog_t wdt = (wdog_t )(MMAP_WDOG);
305	325
306		- wdt->wcr = 0; /* disable watchdog */
	326	+ /* disable watchdog */
	327	+ out_be16(&wdt->wcr, 0);
307	328
308	329	/* set timeout and enable watchdog */
309		- wdt->wmr =
310		- ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
311		- wdt->wsr = 0x5555; /* reset watchdog counter */
312		- wdt->wsr = 0xAAAA;
	330	+ out_be16(&wdt->wmr,
	331	+ (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
	332	+
	333	+ /* reset watchdog counter */
	334	+ out_be16(&wdt->wsr, 0x5555);
	335	+ out_be16(&wdt->wsr, 0xaaaa);
313	336
314	337	puts("WATCHDOG:enabled\n");
315	338	return (0);
...	...	@@ -8,7 +8,7 @@
8	8	* (c) Copyright 2010
9	9	* Arcturus Networks Inc. <www.arcturusnetworks.com>
10	10	*
11		- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
	11	+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
12	12	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
13	13	* Hayden Fraser (Hayden.Fraser@freescale.com)
14	14	*
...	...	@@ -37,6 +37,7 @@
37	37	#include <common.h>
38	38	#include <watchdog.h>
39	39	#include <asm/immap.h>
	40	+#include <asm/io.h>
40	41
41	42	#if defined(CONFIG_CMD_NET)
42	43	#include <config.h>
43	44
44	45
45	46
46	47
47	48
48	49
49	50
50	51
...	...	@@ -48,57 +49,57 @@
48	49	/* Only 5272 Flexbus chipselect is different from the rest */
49	50	void init_fbcs(void)
50	51	{
51		- volatile fbcs_t fbcs = (fbcs_t ) (MMAP_FBCS);
	52	+ fbcs_t fbcs = (fbcs_t ) (MMAP_FBCS);
52	53
53	54	#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
54	55	&& defined(CONFIG_SYS_CS0_CTRL))
55		- fbcs->csar0 = CONFIG_SYS_CS0_BASE;
56		- fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
57		- fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
	56	+ out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
	57	+ out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
	58	+ out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
58	59	#else
59	60	#warning "Chip Select 0 are not initialized/used"
60	61	#endif
61	62	#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
62	63	&& defined(CONFIG_SYS_CS1_CTRL))
63		- fbcs->csar1 = CONFIG_SYS_CS1_BASE;
64		- fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
65		- fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
	64	+ out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
	65	+ out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
	66	+ out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
66	67	#endif
67	68	#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
68	69	&& defined(CONFIG_SYS_CS2_CTRL))
69		- fbcs->csar2 = CONFIG_SYS_CS2_BASE;
70		- fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
71		- fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
	70	+ out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
	71	+ out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
	72	+ out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
72	73	#endif
73	74	#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
74	75	&& defined(CONFIG_SYS_CS3_CTRL))
75		- fbcs->csar3 = CONFIG_SYS_CS3_BASE;
76		- fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
77		- fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
	76	+ out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
	77	+ out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
	78	+ out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
78	79	#endif
79	80	#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
80	81	&& defined(CONFIG_SYS_CS4_CTRL))
81		- fbcs->csar4 = CONFIG_SYS_CS4_BASE;
82		- fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
83		- fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
	82	+ out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
	83	+ out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
	84	+ out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
84	85	#endif
85	86	#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
86	87	&& defined(CONFIG_SYS_CS5_CTRL))
87		- fbcs->csar5 = CONFIG_SYS_CS5_BASE;
88		- fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
89		- fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
	88	+ out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
	89	+ out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
	90	+ out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
90	91	#endif
91	92	#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \
92	93	&& defined(CONFIG_SYS_CS6_CTRL))
93		- fbcs->csar6 = CONFIG_SYS_CS6_BASE;
94		- fbcs->cscr6 = CONFIG_SYS_CS6_CTRL;
95		- fbcs->csmr6 = CONFIG_SYS_CS6_MASK;
	94	+ out_be32(&fbcs->csar6, CONFIG_SYS_CS6_BASE);
	95	+ out_be32(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL);
	96	+ out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK);
96	97	#endif
97	98	#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \
98	99	&& defined(CONFIG_SYS_CS7_CTRL))
99		- fbcs->csar7 = CONFIG_SYS_CS7_BASE;
100		- fbcs->cscr7 = CONFIG_SYS_CS7_CTRL;
101		- fbcs->csmr7 = CONFIG_SYS_CS7_MASK;
	100	+ out_be32(&fbcs->csar7, CONFIG_SYS_CS7_BASE);
	101	+ out_be32(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL);
	102	+ out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK);
102	103	#endif
103	104	}
104	105	#endif
105	106
106	107
107	108
...	...	@@ -106,22 +107,22 @@
106	107	#if defined(CONFIG_M5208)
107	108	void cpu_init_f(void)
108	109	{
109		- volatile scm1_t scm1 = (scm1_t ) MMAP_SCM1;
	110	+ scm1_t scm1 = (scm1_t ) MMAP_SCM1;
110	111
111	112	#ifndef CONFIG_WATCHDOG
112		- volatile wdog_t wdg = (wdog_t ) MMAP_WDOG;
	113	+ wdog_t wdg = (wdog_t ) MMAP_WDOG;
113	114
114	115	/* Disable the watchdog if we aren't using it */
115		- wdg->cr = 0;
	116	+ out_be16(&wdg->cr, 0);
116	117	#endif
117	118
118		- scm1->mpr = 0x77777777;
119		- scm1->pacra = 0;
120		- scm1->pacrb = 0;
121		- scm1->pacrc = 0;
122		- scm1->pacrd = 0;
123		- scm1->pacre = 0;
124		- scm1->pacrf = 0;
	119	+ out_be32(&scm1->mpr, 0x77777777);
	120	+ out_be32(&scm1->pacra, 0);
	121	+ out_be32(&scm1->pacrb, 0);
	122	+ out_be32(&scm1->pacrc, 0);
	123	+ out_be32(&scm1->pacrd, 0);
	124	+ out_be32(&scm1->pacre, 0);
	125	+ out_be32(&scm1->pacrf, 0);
125	126
126	127	/* FlexBus Chipselect */
127	128	init_fbcs();
128	129
129	130
130	131
131	132
132	133
...	...	@@ -137,36 +138,36 @@
137	138
138	139	void uart_port_conf(int port)
139	140	{
140		- volatile gpio_t gpio = (gpio_t ) MMAP_GPIO;
	141	+ gpio_t gpio = (gpio_t ) MMAP_GPIO;
141	142
142	143	/* Setup Ports: */
143	144	switch (port) {
144	145	case 0:
145		- gpio->par_uart &= GPIO_PAR_UART0_UNMASK;
146		- gpio->par_uart \|= (GPIO_PAR_UART_U0TXD \| GPIO_PAR_UART_U0RXD);
	146	+ clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK);
	147	+ setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U0TXD \| GPIO_PAR_UART_U0RXD);
147	148	break;
148	149	case 1:
149		- gpio->par_uart &= GPIO_PAR_UART0_UNMASK;
150		- gpio->par_uart \|= (GPIO_PAR_UART_U1TXD \| GPIO_PAR_UART_U1RXD);
	150	+ clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK);
	151	+ setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U1TXD \| GPIO_PAR_UART_U1RXD);
151	152	break;
152	153	case 2:
153	154	#ifdef CONFIG_SYS_UART2_PRI_GPIO
154		- gpio->par_timer &=
155		- (GPIO_PAR_TMR_TIN0_UNMASK \| GPIO_PAR_TMR_TIN1_UNMASK);
156		- gpio->par_timer \|=
157		- (GPIO_PAR_TMR_TIN0_U2TXD \| GPIO_PAR_TMR_TIN1_U2RXD);
	155	+ clrbits_8(&gpio->par_timer,
	156	+ ~(GPIO_PAR_TMR_TIN0_UNMASK \| GPIO_PAR_TMR_TIN1_UNMASK));
	157	+ setbits_8(&gpio->par_timer,
	158	+ GPIO_PAR_TMR_TIN0_U2TXD \| GPIO_PAR_TMR_TIN1_U2RXD);
158	159	#endif
159	160	#ifdef CONFIG_SYS_UART2_ALT1_GPIO
160		- gpio->par_feci2c &=
161		- (GPIO_PAR_FECI2C_MDC_UNMASK \| GPIO_PAR_FECI2C_MDIO_UNMASK);
162		- gpio->par_feci2c \|=
163		- (GPIO_PAR_FECI2C_MDC_U2TXD \| GPIO_PAR_FECI2C_MDIO_U2RXD);
	161	+ clrbits_8(&gpio->par_feci2c,
	162	+ ~(GPIO_PAR_FECI2C_MDC_UNMASK \| GPIO_PAR_FECI2C_MDIO_UNMASK));
	163	+ setbits_8(&gpio->par_feci2c,
	164	+ GPIO_PAR_FECI2C_MDC_U2TXD \| GPIO_PAR_FECI2C_MDIO_U2RXD);
164	165	#endif
165	166	#ifdef CONFIG_SYS_UART2_ALT1_GPIO
166		- gpio->par_feci2c &=
167		- (GPIO_PAR_FECI2C_SDA_UNMASK \| GPIO_PAR_FECI2C_SCL_UNMASK);
168		- gpio->par_feci2c \|=
169		- (GPIO_PAR_FECI2C_SDA_U2TXD \| GPIO_PAR_FECI2C_SCL_U2RXD);
	167	+ clrbits_8(&gpio->par_feci2c,
	168	+ ~(GPIO_PAR_FECI2C_SDA_UNMASK \| GPIO_PAR_FECI2C_SCL_UNMASK));
	169	+ setbits_8(&gpio->par_feci2c,
	170	+ GPIO_PAR_FECI2C_SDA_U2TXD \| GPIO_PAR_FECI2C_SCL_U2RXD);
170	171	#endif
171	172	break;
172	173	}
173	174
174	175
...	...	@@ -175,17 +176,17 @@
175	176	#if defined(CONFIG_CMD_NET)
176	177	int fecpin_setclear(struct eth_device *dev, int setclear)
177	178	{
178		- volatile gpio_t gpio = (gpio_t ) MMAP_GPIO;
	179	+ gpio_t gpio = (gpio_t ) MMAP_GPIO;
179	180
180	181	if (setclear) {
181		- gpio->par_fec \|=
182		- GPIO_PAR_FEC_7W_FEC \| GPIO_PAR_FEC_MII_FEC;
183		- gpio->par_feci2c \|=
184		- GPIO_PAR_FECI2C_MDC_MDC \| GPIO_PAR_FECI2C_MDIO_MDIO;
	182	+ setbits_8(&gpio->par_fec,
	183	+ GPIO_PAR_FEC_7W_FEC \| GPIO_PAR_FEC_MII_FEC);
	184	+ setbits_8(&gpio->par_feci2c,
	185	+ GPIO_PAR_FECI2C_MDC_MDC \| GPIO_PAR_FECI2C_MDIO_MDIO);
185	186	} else {
186		- gpio->par_fec &=
187		- (GPIO_PAR_FEC_7W_UNMASK & GPIO_PAR_FEC_MII_UNMASK);
188		- gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII_UNMASK;
	187	+ clrbits_8(&gpio->par_fec,
	188	+ ~(GPIO_PAR_FEC_7W_UNMASK & GPIO_PAR_FEC_MII_UNMASK));
	189	+ clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII_UNMASK);
189	190	}
190	191	return 0;
191	192	}
192	193
193	194
...	...	@@ -249,17 +250,17 @@
249	250
250	251	void uart_port_conf(int port)
251	252	{
252		- volatile u32 par = (u32 ) MMAP_PAR;
	253	+ u32 par = (u32 ) MMAP_PAR;
253	254
254	255	/* Setup Ports: */
255	256	switch (port) {
256	257	case 1:
257		- *par &= 0xFFE7FFFF;
258		- *par \|= 0x00180000;
	258	+ clrbits_be32(par, 0x00180000);
	259	+ setbits_be32(par, 0x00180000);
259	260	break;
260	261	case 2:
261		- *par &= 0xFFFFFFFC;
262		- *par &= 0x00000003;
	262	+ clrbits_be32(par, 0x00000003);
	263	+ clrbits_be32(par, 0xFFFFFFFC);
263	264	break;
264	265	}
265	266	}
266	267
267	268
268	269
269	270
270	271
271	272
272	273
273	274
274	275
275	276
...	...	@@ -348,59 +349,59 @@
348	349	* already initialized.
349	350	*/
350	351	#ifndef CONFIG_MONITOR_IS_IN_RAM
351		- volatile sysctrl_t sysctrl = (sysctrl_t ) (CONFIG_SYS_MBAR);
352		- volatile gpio_t gpio = (gpio_t ) (MMAP_GPIO);
353		- volatile csctrl_t csctrl = (csctrl_t ) (MMAP_FBCS);
	352	+ sysctrl_t sysctrl = (sysctrl_t ) (CONFIG_SYS_MBAR);
	353	+ gpio_t gpio = (gpio_t ) (MMAP_GPIO);
	354	+ csctrl_t csctrl = (csctrl_t ) (MMAP_FBCS);
354	355
355		- sysctrl->sc_scr = CONFIG_SYS_SCR;
356		- sysctrl->sc_spr = CONFIG_SYS_SPR;
	356	+ out_be16(&sysctrl->sc_scr, CONFIG_SYS_SCR);
	357	+ out_be16(&sysctrl->sc_spr, CONFIG_SYS_SPR);
357	358
358	359	/* Setup Ports: */
359		- gpio->gpio_pacnt = CONFIG_SYS_PACNT;
360		- gpio->gpio_paddr = CONFIG_SYS_PADDR;
361		- gpio->gpio_padat = CONFIG_SYS_PADAT;
362		- gpio->gpio_pbcnt = CONFIG_SYS_PBCNT;
363		- gpio->gpio_pbddr = CONFIG_SYS_PBDDR;
364		- gpio->gpio_pbdat = CONFIG_SYS_PBDAT;
365		- gpio->gpio_pdcnt = CONFIG_SYS_PDCNT;
	360	+ out_be32(&gpio->gpio_pacnt, CONFIG_SYS_PACNT);
	361	+ out_be16(&gpio->gpio_paddr, CONFIG_SYS_PADDR);
	362	+ out_be16(&gpio->gpio_padat, CONFIG_SYS_PADAT);
	363	+ out_be32(&gpio->gpio_pbcnt, CONFIG_SYS_PBCNT);
	364	+ out_be16(&gpio->gpio_pbddr, CONFIG_SYS_PBDDR);
	365	+ out_be16(&gpio->gpio_pbdat, CONFIG_SYS_PBDAT);
	366	+ out_be32(&gpio->gpio_pdcnt, CONFIG_SYS_PDCNT);
366	367
367	368	/* Memory Controller: */
368		- csctrl->cs_br0 = CONFIG_SYS_BR0_PRELIM;
369		- csctrl->cs_or0 = CONFIG_SYS_OR0_PRELIM;
	369	+ out_be32(&csctrl->cs_br0, CONFIG_SYS_BR0_PRELIM);
	370	+ out_be32(&csctrl->cs_or0, CONFIG_SYS_OR0_PRELIM);
370	371
371	372	#if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
372		- csctrl->cs_br1 = CONFIG_SYS_BR1_PRELIM;
373		- csctrl->cs_or1 = CONFIG_SYS_OR1_PRELIM;
	373	+ out_be32(&csctrl->cs_br1, CONFIG_SYS_BR1_PRELIM);
	374	+ out_be32(&csctrl->cs_or1, CONFIG_SYS_OR1_PRELIM);
374	375	#endif
375	376
376	377	#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
377		- csctrl->cs_br2 = CONFIG_SYS_BR2_PRELIM;
378		- csctrl->cs_or2 = CONFIG_SYS_OR2_PRELIM;
	378	+ out_be32(&csctrl->cs_br2, CONFIG_SYS_BR2_PRELIM);
	379	+ out_be32(&csctrl->cs_or2, CONFIG_SYS_OR2_PRELIM);
379	380	#endif
380	381
381	382	#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
382		- csctrl->cs_br3 = CONFIG_SYS_BR3_PRELIM;
383		- csctrl->cs_or3 = CONFIG_SYS_OR3_PRELIM;
	383	+ out_be32(&csctrl->cs_br3, CONFIG_SYS_BR3_PRELIM);
	384	+ out_be32(&csctrl->cs_or3, CONFIG_SYS_OR3_PRELIM);
384	385	#endif
385	386
386	387	#if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
387		- csctrl->cs_br4 = CONFIG_SYS_BR4_PRELIM;
388		- csctrl->cs_or4 = CONFIG_SYS_OR4_PRELIM;
	388	+ out_be32(&csctrl->cs_br4, CONFIG_SYS_BR4_PRELIM);
	389	+ out_be32(&csctrl->cs_or4, CONFIG_SYS_OR4_PRELIM);
389	390	#endif
390	391
391	392	#if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
392		- csctrl->cs_br5 = CONFIG_SYS_BR5_PRELIM;
393		- csctrl->cs_or5 = CONFIG_SYS_OR5_PRELIM;
	393	+ out_be32(&csctrl->cs_br5, CONFIG_SYS_BR5_PRELIM);
	394	+ out_be32(&csctrl->cs_or5, CONFIG_SYS_OR5_PRELIM);
394	395	#endif
395	396
396	397	#if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
397		- csctrl->cs_br6 = CONFIG_SYS_BR6_PRELIM;
398		- csctrl->cs_or6 = CONFIG_SYS_OR6_PRELIM;
	398	+ out_be32(&csctrl->cs_br6, CONFIG_SYS_BR6_PRELIM);
	399	+ out_be32(&csctrl->cs_or6, CONFIG_SYS_OR6_PRELIM);
399	400	#endif
400	401
401	402	#if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
402		- csctrl->cs_br7 = CONFIG_SYS_BR7_PRELIM;
403		- csctrl->cs_or7 = CONFIG_SYS_OR7_PRELIM;
	403	+ out_be32(&csctrl->cs_br7, CONFIG_SYS_BR7_PRELIM);
	404	+ out_be32(&csctrl->cs_or7, CONFIG_SYS_OR7_PRELIM);
404	405	#endif
405	406
406	407	#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
407	408
408	409
...	...	@@ -420,17 +421,21 @@
420	421
421	422	void uart_port_conf(int port)
422	423	{
423		- volatile gpio_t gpio = (gpio_t ) MMAP_GPIO;
	424	+ gpio_t gpio = (gpio_t ) MMAP_GPIO;
424	425
425	426	/* Setup Ports: */
426	427	switch (port) {
427	428	case 0:
428		- gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK \| GPIO_PBCNT_PB1MSK);
429		- gpio->gpio_pbcnt \|= (GPIO_PBCNT_URT0_TXD \| GPIO_PBCNT_URT0_RXD);
	429	+ clrbits_be32(&gpio->gpio_pbcnt,
	430	+ GPIO_PBCNT_PB0MSK \| GPIO_PBCNT_PB1MSK);
	431	+ setbits_be32(&gpio->gpio_pbcnt,
	432	+ GPIO_PBCNT_URT0_TXD \| GPIO_PBCNT_URT0_RXD);
430	433	break;
431	434	case 1:
432		- gpio->gpio_pdcnt &= ~(GPIO_PDCNT_PD1MSK \| GPIO_PDCNT_PD4MSK);
433		- gpio->gpio_pdcnt \|= (GPIO_PDCNT_URT1_RXD \| GPIO_PDCNT_URT1_TXD);
	435	+ clrbits_be32(&gpio->gpio_pdcnt,
	436	+ GPIO_PDCNT_PD1MSK \| GPIO_PDCNT_PD4MSK);
	437	+ setbits_be32(&gpio->gpio_pdcnt,
	438	+ GPIO_PDCNT_URT1_RXD \| GPIO_PDCNT_URT1_TXD);
434	439	break;
435	440	}
436	441	}
437	442
...	...	@@ -438,13 +443,14 @@
438	443	#if defined(CONFIG_CMD_NET)
439	444	int fecpin_setclear(struct eth_device *dev, int setclear)
440	445	{
441		- volatile gpio_t gpio = (gpio_t ) MMAP_GPIO;
	446	+ gpio_t gpio = (gpio_t ) MMAP_GPIO;
442	447
443	448	if (setclear) {
444		- gpio->gpio_pbcnt \|= GPIO_PBCNT_E_MDC \| GPIO_PBCNT_E_RXER \|
445		- GPIO_PBCNT_E_RXD1 \| GPIO_PBCNT_E_RXD2 \|
446		- GPIO_PBCNT_E_RXD3 \| GPIO_PBCNT_E_TXD1 \|
447		- GPIO_PBCNT_E_TXD2 \| GPIO_PBCNT_E_TXD3;
	449	+ setbits_be32(&gpio->gpio_pbcnt,
	450	+ GPIO_PBCNT_E_MDC \| GPIO_PBCNT_E_RXER \|
	451	+ GPIO_PBCNT_E_RXD1 \| GPIO_PBCNT_E_RXD2 \|
	452	+ GPIO_PBCNT_E_RXD3 \| GPIO_PBCNT_E_TXD1 \|
	453	+ GPIO_PBCNT_E_TXD2 \| GPIO_PBCNT_E_TXD3);
448	454	} else {
449	455	}
450	456	return 0;
451	457
...	...	@@ -469,11 +475,11 @@
469	475	*/
470	476
471	477	#ifndef CONFIG_MONITOR_IS_IN_RAM
472		- volatile wdog_t wdog_reg = (wdog_t ) (MMAP_WDOG);
473		- volatile gpio_t gpio_reg = (gpio_t ) (MMAP_GPIO);
	478	+ wdog_t wdog_reg = (wdog_t ) (MMAP_WDOG);
	479	+ gpio_t gpio_reg = (gpio_t ) (MMAP_GPIO);
474	480
475	481	/* Kill watchdog so we can initialize the PLL */
476		- wdog_reg->wcr = 0;
	482	+ out_be16(&wdog_reg->wcr, 0);
477	483
478	484	/* FlexBus Chipselect */
479	485	init_fbcs();
480	486
481	487
482	488
...	...	@@ -498,21 +504,21 @@
498	504
499	505	void uart_port_conf(int port)
500	506	{
501		- volatile gpio_t gpio = (gpio_t ) MMAP_GPIO;
	507	+ gpio_t gpio = (gpio_t ) MMAP_GPIO;
502	508
503	509	/* Setup Ports: */
504	510	switch (port) {
505	511	case 0:
506		- gpio->par_uart &= ~UART0_ENABLE_MASK;
507		- gpio->par_uart \|= UART0_ENABLE_MASK;
	512	+ clrbits_be16(&gpio->par_uart, UART0_ENABLE_MASK);
	513	+ setbits_be16(&gpio->par_uart, UART0_ENABLE_MASK);
508	514	break;
509	515	case 1:
510		- gpio->par_uart &= ~UART1_ENABLE_MASK;
511		- gpio->par_uart \|= UART1_ENABLE_MASK;
	516	+ clrbits_be16(&gpio->par_uart, UART1_ENABLE_MASK);
	517	+ setbits_be16(&gpio->par_uart, UART1_ENABLE_MASK);
512	518	break;
513	519	case 2:
514		- gpio->par_uart &= ~UART2_ENABLE_MASK;
515		- gpio->par_uart \|= UART2_ENABLE_MASK;
	520	+ clrbits_be16(&gpio->par_uart, UART2_ENABLE_MASK);
	521	+ setbits_be16(&gpio->par_uart, UART2_ENABLE_MASK);
516	522	break;
517	523	}
518	524	}
519	525
520	526
521	527
522	528
...	...	@@ -521,24 +527,24 @@
521	527	int fecpin_setclear(struct eth_device *dev, int setclear)
522	528	{
523	529	struct fec_info_s info = (struct fec_info_s ) dev->priv;
524		- volatile gpio_t gpio = (gpio_t )MMAP_GPIO;
	530	+ gpio_t gpio = (gpio_t )MMAP_GPIO;
525	531
526	532	if (setclear) {
527	533	/* Enable Ethernet pins */
528	534	if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
529		- gpio->par_feci2c \|= 0x0F00;
530		- gpio->par_fec0hl \|= 0xC0;
	535	+ setbits_be16(&gpio->par_feci2c, 0x0f00);
	536	+ setbits_8(&gpio->par_fec0hl, 0xc0);
531	537	} else {
532		- gpio->par_feci2c \|= 0x00A0;
533		- gpio->par_fec1hl \|= 0xC0;
	538	+ setbits_be16(&gpio->par_feci2c, 0x00a0);
	539	+ setbits_8(&gpio->par_fec1hl, 0xc0);
534	540	}
535	541	} else {
536	542	if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
537		- gpio->par_feci2c &= ~0x0F00;
538		- gpio->par_fec0hl &= ~0xC0;
	543	+ clrbits_be16(&gpio->par_feci2c, 0x0f00);
	544	+ clrbits_8(&gpio->par_fec0hl, 0xc0);
539	545	} else {
540		- gpio->par_feci2c &= ~0x00A0;
541		- gpio->par_fec1hl &= ~0xC0;
	546	+ clrbits_be16(&gpio->par_feci2c, 0x00a0);
	547	+ clrbits_8(&gpio->par_fec1hl, 0xc0);
542	548	}
543	549	}
544	550
...	...	@@ -2,7 +2,7 @@
2	2	* (C) Copyright 2000-2004
3	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4	4	*
5		- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
	5	+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
6	6	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7	7	*
8	8	* See file CREDITS for list of people who contributed to this
9	9
10	10
11	11
...	...	@@ -28,20 +28,22 @@
28	28	#include <watchdog.h>
29	29	#include <asm/processor.h>
30	30	#include <asm/immap.h>
	31	+#include <asm/io.h>
31	32
32	33	#ifdef CONFIG_M5272
33	34	int interrupt_init(void)
34	35	{
35		- volatile intctrl_t intp = (intctrl_t ) (MMAP_INTC);
	36	+ intctrl_t intp = (intctrl_t ) (MMAP_INTC);
36	37
37	38	/* disable all external interrupts */
38		- intp->int_icr1 = 0x88888888;
39		- intp->int_icr2 = 0x88888888;
40		- intp->int_icr3 = 0x88888888;
41		- intp->int_icr4 = 0x88888888;
42		- intp->int_pitr = 0x00000000;
	39	+ out_be32(&intp->int_icr1, 0x88888888);
	40	+ out_be32(&intp->int_icr2, 0x88888888);
	41	+ out_be32(&intp->int_icr3, 0x88888888);
	42	+ out_be32(&intp->int_icr4, 0x88888888);
	43	+ out_be32(&intp->int_pitr, 0x00000000);
	44	+
43	45	/* initialize vector register */
44		- intp->int_pivr = 0x40;
	46	+ out_8(&intp->int_pivr, 0x40);
45	47
46	48	enable_interrupts();
47	49
48	50
...	...	@@ -51,10 +53,10 @@
51	53	#if defined(CONFIG_MCFTMR)
52	54	void dtimer_intr_setup(void)
53	55	{
54		- volatile intctrl_t intp = (intctrl_t ) (CONFIG_SYS_INTR_BASE);
	56	+ intctrl_t intp = (intctrl_t ) (CONFIG_SYS_INTR_BASE);
55	57
56		- intp->int_icr1 &= ~INT_ICR1_TMR3MASK;
57		- intp->int_icr1 \|= CONFIG_SYS_TMRINTR_PRI;
	58	+ clrbits_be32(&intp->int_icr1, INT_ICR1_TMR3MASK);
	59	+ setbits_be32(&intp->int_icr1, CONFIG_SYS_TMRINTR_PRI);
58	60	}
59	61	#endif /* CONFIG_MCFTMR */
60	62	#endif /* CONFIG_M5272 */
61	63
62	64
...	...	@@ -63,14 +65,14 @@
63	65	defined(CONFIG_M5271) \|\| defined(CONFIG_M5275)
64	66	int interrupt_init(void)
65	67	{
66		- volatile int0_t intp = (int0_t ) (CONFIG_SYS_INTR_BASE);
	68	+ int0_t intp = (int0_t ) (CONFIG_SYS_INTR_BASE);
67	69
68	70	/* Make sure all interrupts are disabled */
69	71	#if defined(CONFIG_M5208)
70		- intp->imrl0 = 0xFFFFFFFF;
71		- intp->imrh0 = 0xFFFFFFFF;
	72	+ out_be32(&intp->imrl0, 0xffffffff);
	73	+ out_be32(&intp->imrh0, 0xffffffff);
72	74	#else
73		- intp->imrl0 \|= 0x1;
	75	+ setbits_be32(&intp->imrl0, 0x1);
74	76	#endif
75	77
76	78	enable_interrupts();
77	79
...	...	@@ -80,11 +82,11 @@
80	82	#if defined(CONFIG_MCFTMR)
81	83	void dtimer_intr_setup(void)
82	84	{
83		- volatile int0_t intp = (int0_t ) (CONFIG_SYS_INTR_BASE);
	85	+ int0_t intp = (int0_t ) (CONFIG_SYS_INTR_BASE);
84	86
85		- intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
86		- intp->imrl0 &= 0xFFFFFFFE;
87		- intp->imrl0 &= ~CONFIG_SYS_TMRINTR_MASK;
	87	+ out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
	88	+ clrbits_be32(&intp->imrl0, 0x00000001);
	89	+ clrbits_be32(&intp->imrl0, CONFIG_SYS_TMRINTR_MASK);
88	90	}
89	91	#endif /* CONFIG_MCFTMR */
90	92	#endif /* CONFIG_M5282 \| CONFIG_M5271 \| CONFIG_M5275 */
...	...	@@ -2,7 +2,7 @@
2	2	* (C) Copyright 2003
3	3	* Josef Baumgartner <josef.baumgartner@telex.de>
4	4	*
5		- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
	5	+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
6	6	* Hayden Fraser (Hayden.Fraser@freescale.com)
7	7	*
8	8	* See file CREDITS for list of people who contributed to this
...	...	@@ -27,6 +27,7 @@
27	27	#include <common.h>
28	28	#include <asm/processor.h>
29	29	#include <asm/immap.h>
	30	+#include <asm/io.h>
30	31
31	32	DECLARE_GLOBAL_DATA_PTR;
32	33
33	34
...	...	@@ -34,10 +35,10 @@
34	35	int get_clocks (void)
35	36	{
36	37	#if defined(CONFIG_M5208)
37		- volatile pll_t pll = (pll_t ) MMAP_PLL;
	38	+ pll_t pll = (pll_t ) MMAP_PLL;
38	39
39		- pll->odr = CONFIG_SYS_PLL_ODR;
40		- pll->fdr = CONFIG_SYS_PLL_FDR;
	40	+ out_8(&pll->odr, CONFIG_SYS_PLL_ODR);
	41	+ out_8(&pll->fdr, CONFIG_SYS_PLL_FDR);
41	42	#endif
42	43
43	44	#if defined(CONFIG_M5249) \|\| defined(CONFIG_M5253)
44	45
45	46
...	...	@@ -70,14 +71,14 @@
70	71	#endif /* CONFIG_M5249 \|\| CONFIG_M5253 */
71	72
72	73	#if defined(CONFIG_M5275)
73		- volatile pll_t pll = (volatile pll_t )(MMAP_PLL);
	74	+ pll_t pll = (pll_t )(MMAP_PLL);
74	75
75	76	/* Setup PLL */
76		- pll->syncr = 0x01080000;
77		- while (!(pll->synsr & FMPLL_SYNSR_LOCK))
	77	+ out_be32(&pll->syncr, 0x01080000);
	78	+ while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK))
78	79	;
79		- pll->syncr = 0x01000000;
80		- while (!(pll->synsr & FMPLL_SYNSR_LOCK))
	80	+ out_be32(&pll->syncr, 0x01000000);
	81	+ while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK))
81	82	;
82	83	#endif
83	84
...	...	@@ -2,7 +2,7 @@
2	2	* (C) Copyright 2000-2003
3	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4	4	*
5		- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
	5	+ * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
6	6	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7	7	*
8	8	* See file CREDITS for list of people who contributed to this
...	...	@@ -27,6 +27,7 @@
27	27	#include <config.h>
28	28	#include <common.h>
29	29	#include <asm/immap.h>
	30	+#include <asm/io.h>
30	31
31	32	DECLARE_GLOBAL_DATA_PTR;
32	33
...	...	@@ -39,7 +40,7 @@
39	40
40	41	phys_size_t initdram(int board_type)
41	42	{
42		- volatile sdram_t sdram = (volatile sdram_t )(MMAP_SDRAM);
	43	+ sdram_t sdram = (sdram_t )(MMAP_SDRAM);
43	44	u32 dramsize, i;
44	45
45	46	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
46	47
47	48
48	49
49	50
50	51
51	52
52	53
53	54
...	...	@@ -50,34 +51,35 @@
50	51	}
51	52	i--;
52	53
53		- sdram->cs0 = (CONFIG_SYS_SDRAM_BASE \| i);
	54	+ out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE \| i);
54	55	#ifdef CONFIG_SYS_SDRAM_BASE1
55		- sdram->cs1 = (CONFIG_SYS_SDRAM_BASE \| i);
	56	+ out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE \| i);
56	57	#endif
57		- sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
58		- sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
	58	+ out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
	59	+ out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
59	60
60	61	udelay(500);
61	62
62	63	/* Issue PALL */
63		- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL \| 2);
	64	+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL \| 2);
64	65	asm("nop");
65	66
66	67	/* Perform two refresh cycles */
67		- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL \| 4;
68		- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL \| 4;
	68	+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL \| 4);
	69	+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL \| 4);
69	70	asm("nop");
70	71
71	72	/* Issue LEMR */
72		- sdram->mode = CONFIG_SYS_SDRAM_MODE;
	73	+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
73	74	asm("nop");
74		- sdram->mode = CONFIG_SYS_SDRAM_EMOD;
	75	+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
75	76	asm("nop");
76	77
77		- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL \| 2);
	78	+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL \| 2);
78	79	asm("nop");
79	80
80		- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) \| 0x10000F00;
	81	+ out_be32(&sdram->ctrl,
	82	+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) \| 0x10000F00);
81	83	asm("nop");
82	84
83	85	udelay(100);
...	...	@@ -2,6 +2,8 @@
2	2	* (C) Copyright 2000-2003
3	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4	4	*
	5	+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
	6	+ *
5	7	* See file CREDITS for list of people who contributed to this
6	8	* project.
7	9	*
...	...	@@ -23,6 +25,7 @@
23	25
24	26	#include <common.h>
25	27	#include <asm/immap.h>
	28	+#include <asm/io.h>
26	29
27	30
28	31	int checkboard (void) {
29	32
...	...	@@ -32,10 +35,10 @@
32	35	};
33	36
34	37	phys_size_t initdram (int board_type) {
35		- volatile sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM);
	38	+ sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM);
36	39
37		- sdp->sdram_sdtr = 0xf539;
38		- sdp->sdram_sdcr = 0x4211;
	40	+ out_be16(&sdp->sdram_sdtr, 0xf539);
	41	+ out_be16(&sdp->sdram_sdcr, 0x4211);
39	42
40	43	/* Dummy write to start SDRAM */
41	44	((volatile unsigned long )0) = 0;
...	...	@@ -4,6 +4,8 @@
4	4	*
5	5	* Copyright (C) 2005-2008 Arthur Shipkowski (art@videon-central.com)
6	6	*
	7	+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
	8	+ *
7	9	* See file CREDITS for list of people who contributed to this
8	10	* project.
9	11	*
...	...	@@ -25,6 +27,7 @@
25	27
26	28	#include <common.h>
27	29	#include <asm/immap.h>
	30	+#include <asm/io.h>
28	31
29	32	#define PERIOD 13 /* system bus period in ns */
30	33	#define SDRAM_TREFI 7800 /* in ns */
31	34
32	35
33	36
34	37
35	38
36	39
37	40
38	41
39	42
40	43
41	44
42	45
43	46
44	47
...	...	@@ -38,67 +41,68 @@
38	41
39	42	phys_size_t initdram(int board_type)
40	43	{
41		- volatile sdramctrl_t sdp = (sdramctrl_t )(MMAP_SDRAM);
42		- volatile gpio_t gpio_reg = (gpio_t )(MMAP_GPIO);
	44	+ sdramctrl_t sdp = (sdramctrl_t )(MMAP_SDRAM);
	45	+ gpio_t gpio_reg = (gpio_t )(MMAP_GPIO);
43	46
44		- gpio_reg->par_sdram = 0x3FF; /* Enable SDRAM */
	47	+ /* Enable SDRAM */
	48	+ out_be16(&gpio_reg->par_sdram, 0x3FF);
45	49
46	50	/* Set up chip select */
47		- sdp->sdbar0 = CONFIG_SYS_SDRAM_BASE;
48		- sdp->sdbmr0 = MCF_SDRAMC_SDMRn_BAM_32M \| MCF_SDRAMC_SDMRn_V;
	51	+ out_be32(&sdp->sdbar0, CONFIG_SYS_SDRAM_BASE);
	52	+ out_be32(&sdp->sdbmr0, MCF_SDRAMC_SDMRn_BAM_32M \| MCF_SDRAMC_SDMRn_V);
49	53
50	54	/* Set up timing */
51		- sdp->sdcfg1 = 0x83711630;
52		- sdp->sdcfg2 = 0x46770000;
	55	+ out_be32(&sdp->sdcfg1, 0x83711630);
	56	+ out_be32(&sdp->sdcfg2, 0x46770000);
53	57
54	58	/* Enable clock */
55		- sdp->sdcr = MCF_SDRAMC_SDCR_MODE_EN \| MCF_SDRAMC_SDCR_CKE;
	59	+ out_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN \| MCF_SDRAMC_SDCR_CKE);
56	60
57	61	/* Set precharge */
58		- sdp->sdcr \|= MCF_SDRAMC_SDCR_IPALL;
	62	+ setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
59	63
60	64	/* Dummy write to start SDRAM */
61	65	((volatile unsigned long )CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
62	66
63	67	/* Send LEMR */
64		- sdp->sdmr = MCF_SDRAMC_SDMR_BNKAD_LEMR
65		- \| MCF_SDRAMC_SDMR_AD(0x0)
66		- \| MCF_SDRAMC_SDMR_CMD;
	68	+ setbits_be32(&sdp->sdmr,
	69	+ MCF_SDRAMC_SDMR_BNKAD_LEMR \| MCF_SDRAMC_SDMR_AD(0x0) \|
	70	+ MCF_SDRAMC_SDMR_CMD);
67	71	((volatile unsigned long )CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
68	72
69	73	/* Send LMR */
70		- sdp->sdmr = 0x058d0000;
	74	+ out_be32(&sdp->sdmr, 0x058d0000);
71	75	((volatile unsigned long )CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
72	76
73	77	/* Stop sending commands */
74		- sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD);
	78	+ clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
75	79
76	80	/* Set precharge */
77		- sdp->sdcr \|= MCF_SDRAMC_SDCR_IPALL;
	81	+ setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
78	82	((volatile unsigned long )CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
79	83
80	84	/* Stop manual precharge, send 2 IREF */
81		- sdp->sdcr &= ~(MCF_SDRAMC_SDCR_IPALL);
82		- sdp->sdcr \|= MCF_SDRAMC_SDCR_IREF;
	85	+ clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
	86	+ setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IREF);
83	87	((volatile unsigned long )CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
84	88	((volatile unsigned long )CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
85	89
86		- /* Write mode register, clear reset DLL */
87		- sdp->sdmr = 0x018d0000;
	90	+
	91	+ out_be32(&sdp->sdmr, 0x018d0000);
88	92	((volatile unsigned long )CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
89	93
90	94	/* Stop sending commands */
91		- sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD);
92		- sdp->sdcr &= ~(MCF_SDRAMC_SDCR_MODE_EN);
	95	+ clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
	96	+ clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN);
93	97
94	98	/* Turn on auto refresh, lock SDMR */
95		- sdp->sdcr =
	99	+ out_be32(&sdp->sdcr,
96	100	MCF_SDRAMC_SDCR_CKE
97	101	\| MCF_SDRAMC_SDCR_REF
98	102	\| MCF_SDRAMC_SDCR_MUX(1)
99	103	/* 1 added to round up */
100	104	\| MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1)
101		- \| MCF_SDRAMC_SDCR_DQS_OE(0x3);
	105	+ \| MCF_SDRAMC_SDCR_DQS_OE(0x3));
102	106
103	107	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
104	108	};