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Commit aaa4ba930ca3bbc98f33651b175480ba86aa4dd2

Authored by Ludovic Desroches
Committed by Tom Rini
1 parent 48e4851f49
Exists in smarc_8mq_lf_v2020.04 and in 17 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

board: atmel: add sama5d2_ptc_ek board 

Add the SAMA5D2 PTC EK board and remove the SAMA5D2 PTC ENGI board
which was a prototype.

Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>

Showing 18 changed files with 566 additions and 500 deletions Side-by-side Diff

arch/arm/dts/Makefile
Diff comments   View file @ aaa4ba9
... ... @@ -427,6 +427,9 @@
427 427 logicpd-torpedo-37xx-devkit.dtb \
428 428 logicpd-som-lv-37xx-devkit.dtb
429 429  
  430 +dtb-$(CONFIG_TARGET_SAMA5D2_PTC_EK) += \
  431 + at91-sama5d2_ptc_ek.dtb
  432 +
430 433 dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \
431 434 at91-sama5d2_xplained.dtb
432 435  
arch/arm/dts/at91-sama5d2_ptc_ek.dts
Diff comments   View file @ aaa4ba9
  1 +/*
  2 + * at91-sama5d2_ptc_ek.dts - Device Tree file for SAMA5D2 PTC EK board
  3 + *
  4 + * Copyright (C) 2017 Microchip Technology Inc,
  5 + * Ludovic Desroches <ludovic.desroches@microchip.com>
  6 + *
  7 + * This file is dual-licensed: you can use it either under the terms
  8 + * of the GPL or the X11 license, at your option. Note that this dual
  9 + * licensing only applies to this file, and not this project as a
  10 + * whole.
  11 + *
  12 + * a) This file is free software; you can redistribute it and/or
  13 + * modify it under the terms of the GNU General Public License as
  14 + * published by the Free Software Foundation; either version 2 of the
  15 + * License, or (at your option) any later version.
  16 + *
  17 + * This file is distributed in the hope that it will be useful,
  18 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20 + * GNU General Public License for more details.
  21 + *
  22 + * Or, alternatively,
  23 + *
  24 + * b) Permission is hereby granted, free of charge, to any person
  25 + * obtaining a copy of this software and associated documentation
  26 + * files (the "Software"), to deal in the Software without
  27 + * restriction, including without limitation the rights to use,
  28 + * copy, modify, merge, publish, distribute, sublicense, and/or
  29 + * sell copies of the Software, and to permit persons to whom the
  30 + * Software is furnished to do so, subject to the following
  31 + * conditions:
  32 + *
  33 + * The above copyright notice and this permission notice shall be
  34 + * included in all copies or substantial portions of the Software.
  35 + *
  36 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  37 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  38 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  39 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  40 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  41 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  42 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  43 + * OTHER DEALINGS IN THE SOFTWARE.
  44 + */
  45 +/dts-v1/;
  46 +#include <dt-bindings/gpio/gpio.h>
  47 +#include "sama5d2.dtsi"
  48 +#include "sama5d2-pinfunc.h"
  49 +
  50 +/ {
  51 + model = "Atmel SAMA5D2 PTC EK";
  52 + compatible = "atmel,sama5d2-ptc_ek", "atmel,sama5d2", "atmel,sama5";
  53 +
  54 + chosen {
  55 + u-boot,dm-pre-reloc;
  56 + stdout-path = &uart0;
  57 + };
  58 +
  59 + ahb {
  60 + usb0: gadget@00300000 {
  61 + atmel,vbus-gpio = <&pioA PIN_PA27 GPIO_ACTIVE_HIGH>;
  62 + pinctrl-names = "default";
  63 + pinctrl-0 = <&pinctrl_usba_vbus>;
  64 + status = "okay";
  65 + };
  66 +
  67 + usb1: ohci@00400000 {
  68 + num-ports = <3>;
  69 + atmel,vbus-gpio = <0
  70 + &pioA PIN_PB12 GPIO_ACTIVE_HIGH
  71 + 0
  72 + >;
  73 + pinctrl-names = "default";
  74 + pinctrl-0 = <&pinctrl_usb_default>;
  75 + status = "okay";
  76 + };
  77 +
  78 + usb2: ehci@00500000 {
  79 + status = "okay";
  80 + };
  81 +
  82 + sdmmc0: sdio-host@a0000000 {
  83 + bus-width = <8>;
  84 + pinctrl-names = "default";
  85 + pinctrl-0 = <&pinctrl_sdmmc0_cmd_dat_default &pinctrl_sdmmc0_ck_cd_default>;
  86 + status = "okay";
  87 + u-boot,dm-pre-reloc;
  88 + };
  89 +
  90 + sdmmc1: sdio-host@b0000000 {
  91 + bus-width = <4>;
  92 + pinctrl-names = "default";
  93 + pinctrl-0 = <&pinctrl_sdmmc1_cmd_dat_default &pinctrl_sdmmc1_ck_cd_default>;
  94 + status = "disabled"; /* conflicts with nand and qspi0*/
  95 + u-boot,dm-pre-reloc;
  96 + };
  97 +
  98 + apb {
  99 + macb0: ethernet@f8008000 {
  100 + pinctrl-names = "default";
  101 + pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>;
  102 + phy-mode = "rmii";
  103 + status = "okay";
  104 +
  105 + ethernet-phy@1 {
  106 + reg = <0x1>;
  107 + };
  108 + };
  109 +
  110 + uart0: serial@f801c000 {
  111 + pinctrl-names = "default";
  112 + pinctrl-0 = <&pinctrl_uart0_default>;
  113 + status = "okay";
  114 + u-boot,dm-pre-reloc;
  115 + };
  116 +
  117 + i2c1: i2c@fc028000 {
  118 + pinctrl-names = "default";
  119 + pinctrl-0 = <&pinctrl_i2c1_default>;
  120 + status = "okay";
  121 +
  122 + i2c_eeprom: i2c_eeprom@50 {
  123 + compatible = "atmel,24mac402";
  124 + reg = <0x50>;
  125 + };
  126 + };
  127 +
  128 + pioA: gpio@fc038000 {
  129 + pinctrl {
  130 + pinctrl_i2c1_default: i2c1_default {
  131 + pinmux = <PIN_PC6__TWD1>,
  132 + <PIN_PC7__TWCK1>;
  133 + bias-disable;
  134 + };
  135 +
  136 + pinctrl_macb0_phy_irq: macb0_phy_irq {
  137 + pinmux = <PIN_PB24__GPIO>;
  138 + bias-disable;
  139 + };
  140 +
  141 + pinctrl_macb0_rmii: macb0_rmii {
  142 + pinmux = <PIN_PB14__GTXCK>,
  143 + <PIN_PB15__GTXEN>,
  144 + <PIN_PB16__GRXDV>,
  145 + <PIN_PB17__GRXER>,
  146 + <PIN_PB18__GRX0>,
  147 + <PIN_PB19__GRX1>,
  148 + <PIN_PB20__GTX0>,
  149 + <PIN_PB21__GTX1>,
  150 + <PIN_PB22__GMDC>,
  151 + <PIN_PB23__GMDIO>;
  152 + bias-disable;
  153 + };
  154 +
  155 + pinctrl_sdmmc0_cmd_dat_default: sdmmc0_cmd_dat_default {
  156 + pinmux = <PIN_PA1__SDMMC0_CMD>,
  157 + <PIN_PA2__SDMMC0_DAT0>,
  158 + <PIN_PA3__SDMMC0_DAT1>,
  159 + <PIN_PA4__SDMMC0_DAT2>,
  160 + <PIN_PA5__SDMMC0_DAT3>,
  161 + <PIN_PA6__SDMMC0_DAT4>,
  162 + <PIN_PA7__SDMMC0_DAT5>,
  163 + <PIN_PA8__SDMMC0_DAT6>,
  164 + <PIN_PA9__SDMMC0_DAT7>;
  165 + bias-pull-up;
  166 + u-boot,dm-pre-reloc;
  167 + };
  168 +
  169 + pinctrl_sdmmc0_ck_cd_default: sdmmc0_ck_cd_default {
  170 + pinmux = <PIN_PA0__SDMMC0_CK>,
  171 + <PIN_PA10__SDMMC0_RSTN>,
  172 + <PIN_PA11__SDMMC0_VDDSEL>,
  173 + <PIN_PA13__SDMMC0_CD>;
  174 + bias-disable;
  175 + u-boot,dm-pre-reloc;
  176 + };
  177 +
  178 + pinctrl_sdmmc1_cmd_dat_default: sdmmc1_cmd_dat_default {
  179 + pinmux = <PIN_PA28__SDMMC1_CMD>,
  180 + <PIN_PA18__SDMMC1_DAT0>,
  181 + <PIN_PA19__SDMMC1_DAT1>,
  182 + <PIN_PA20__SDMMC1_DAT2>,
  183 + <PIN_PA21__SDMMC1_DAT3>;
  184 + bias-pull-up;
  185 + u-boot,dm-pre-reloc;
  186 + };
  187 +
  188 + pinctrl_sdmmc1_ck_cd_default: sdmmc1_ck_cd_default {
  189 + pinmux = <PIN_PA22__SDMMC1_CK>,
  190 + <PIN_PA30__SDMMC1_CD>;
  191 + bias-disable;
  192 + u-boot,dm-pre-reloc;
  193 + };
  194 +
  195 + pinctrl_uart0_default: uart0_default {
  196 + pinmux = <PIN_PB26__URXD0>,
  197 + <PIN_PB27__UTXD0>;
  198 + bias-disable;
  199 + u-boot,dm-pre-reloc;
  200 + };
  201 +
  202 + pinctrl_usb_default: usb_default {
  203 + pinmux = <PIN_PB12__GPIO>;
  204 + bias-disable;
  205 + };
  206 +
  207 + pinctrl_usba_vbus: usba_vbus {
  208 + pinmux = <PIN_PB11__GPIO>;
  209 + bias-disable;
  210 + };
  211 + };
  212 + };
  213 + };
  214 + };
  215 +};
arch/arm/dts/sama5d2.dtsi
Diff comments   View file @ aaa4ba9
... ... @@ -302,6 +302,7 @@
302 302 #clock-cells = <0>;
303 303 reg = <24>;
304 304 atmel,clk-output-range = <0 83000000>;
  305 + u-boot,dm-pre-reloc;
305 306 };
306 307  
307 308 uart1_clk: uart1_clk@25 {
... ... @@ -315,6 +316,7 @@
315 316 #clock-cells = <0>;
316 317 reg = <26>;
317 318 atmel,clk-output-range = <0 83000000>;
  319 + u-boot,dm-pre-reloc;
318 320 };
319 321  
320 322 uart3_clk: uart3_clk@27 {
321 323  
... ... @@ -635,10 +637,26 @@
635 637 status = "disabled";
636 638 };
637 639  
  640 + uart0: serial@f801c000 {
  641 + compatible = "atmel,at91sam9260-usart";
  642 + reg = <0xf801c000 0x100>;
  643 + clocks = <&uart0_clk>;
  644 + clock-names = "usart";
  645 + status = "disabled";
  646 + };
  647 +
638 648 uart1: serial@f8020000 {
639 649 compatible = "atmel,at91sam9260-usart";
640 650 reg = <0xf8020000 0x100>;
641 651 clocks = <&uart1_clk>;
  652 + clock-names = "usart";
  653 + status = "disabled";
  654 + };
  655 +
  656 + uart2: serial@f8024000 {
  657 + compatible = "atmel,at91sam9260-usart";
  658 + reg = <0xf8024000 0x100>;
  659 + clocks = <&uart2_clk>;
642 660 clock-names = "usart";
643 661 status = "disabled";
644 662 };
arch/arm/mach-at91/Kconfig
Diff comments   View file @ aaa4ba9
... ... @@ -143,10 +143,9 @@
143 143 select BOARD_EARLY_INIT_F
144 144 select BOARD_LATE_INIT
145 145  
146   -config TARGET_SAMA5D2_PTC
147   - bool "SAMA5D2 PTC board"
  146 +config TARGET_SAMA5D2_PTC_EK
  147 + bool "SAMA5D2 PTC EK board"
148 148 select SAMA5D2
149   - select SUPPORT_SPL
150 149 select BOARD_EARLY_INIT_F
151 150  
152 151 config TARGET_SAMA5D2_XPLAINED
... ... @@ -251,7 +250,7 @@
251 250 source "board/atmel/at91sam9n12ek/Kconfig"
252 251 source "board/atmel/at91sam9rlek/Kconfig"
253 252 source "board/atmel/at91sam9x5ek/Kconfig"
254   -source "board/atmel/sama5d2_ptc/Kconfig"
  253 +source "board/atmel/sama5d2_ptc_ek/Kconfig"
255 254 source "board/atmel/sama5d2_xplained/Kconfig"
256 255 source "board/atmel/sama5d27_som1_ek/Kconfig"
257 256 source "board/atmel/sama5d3_xplained/Kconfig"
board/atmel/sama5d2_ptc/Kconfig
View file @ aaa4ba9
1   -if TARGET_SAMA5D2_PTC
2   -
3   -config SYS_BOARD
4   - default "sama5d2_ptc"
5   -
6   -config SYS_VENDOR
7   - default "atmel"
8   -
9   -config SYS_SOC
10   - default "at91"
11   -
12   -config SYS_CONFIG_NAME
13   - default "sama5d2_ptc"
14   -
15   -endif
board/atmel/sama5d2_ptc/MAINTAINERS
View file @ aaa4ba9
1   -SAMA5D2 PTC Engineering BOARD
2   -M: Wenyou Yang <wenyou.yang@atmel.com>
3   -S: Maintained
4   -F: board/atmel/sama5d2_ptc/
5   -F: include/configs/sama5d2_ptc.h
6   -F: configs/sama5d2_ptc_spiflash_defconfig
7   -F: configs/sama5d2_ptc_nandflash_defconfig
board/atmel/sama5d2_ptc/Makefile
View file @ aaa4ba9
1   -#
2   -# Copyright (C) 2016 Atmel
3   -# Wenyou Yang <wenyou.yang@atmel.com>
4   -#
5   -# SPDX-License-Identifier: GPL-2.0+
6   -#
7   -
8   -obj-y += sama5d2_ptc.o
board/atmel/sama5d2_ptc/sama5d2_ptc.c
View file @ aaa4ba9
1   -/*
2   - * Copyright (C) 2016 Atmel
3   - * Wenyou.Yang <wenyou.yang@atmel.com>
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <common.h>
9   -#include <atmel_hlcdc.h>
10   -#include <lcd.h>
11   -#include <mmc.h>
12   -#include <net.h>
13   -#include <netdev.h>
14   -#include <spi.h>
15   -#include <version.h>
16   -#include <asm/io.h>
17   -#include <asm/arch/at91_common.h>
18   -#include <asm/arch/atmel_pio4.h>
19   -#include <asm/arch/atmel_mpddrc.h>
20   -#include <asm/arch/atmel_usba_udc.h>
21   -#include <asm/arch/atmel_sdhci.h>
22   -#include <asm/arch/clk.h>
23   -#include <asm/arch/gpio.h>
24   -#include <asm/arch/sama5_sfr.h>
25   -#include <asm/arch/sama5d2.h>
26   -#include <asm/arch/sama5d3_smc.h>
27   -
28   -DECLARE_GLOBAL_DATA_PTR;
29   -
30   -int spi_cs_is_valid(unsigned int bus, unsigned int cs)
31   -{
32   - return bus == 0 && cs == 0;
33   -}
34   -
35   -void spi_cs_activate(struct spi_slave *slave)
36   -{
37   - atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 0);
38   -}
39   -
40   -void spi_cs_deactivate(struct spi_slave *slave)
41   -{
42   - atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);
43   -}
44   -
45   -static void board_spi0_hw_init(void)
46   -{
47   - atmel_pio4_set_a_periph(AT91_PIO_PORTA, 14, 0);
48   - atmel_pio4_set_a_periph(AT91_PIO_PORTA, 15, 0);
49   - atmel_pio4_set_a_periph(AT91_PIO_PORTA, 16, 0);
50   -
51   - atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);
52   -
53   - at91_periph_clk_enable(ATMEL_ID_SPI0);
54   -}
55   -
56   -static void board_nand_hw_init(void)
57   -{
58   - struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
59   - struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
60   -
61   - at91_periph_clk_enable(ATMEL_ID_HSMC);
62   -
63   - writel(AT91_SFR_EBICFG_DRIVE0_HIGH |
64   - AT91_SFR_EBICFG_PULL0_NONE |
65   - AT91_SFR_EBICFG_DRIVE1_HIGH |
66   - AT91_SFR_EBICFG_PULL1_NONE, &sfr->ebicfg);
67   -
68   - /* Configure SMC CS3 for NAND */
69   - writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
70   - AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
71   - &smc->cs[3].setup);
72   - writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
73   - AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
74   - &smc->cs[3].pulse);
75   - writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
76   - &smc->cs[3].cycle);
77   - writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
78   - AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) |
79   - AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3) |
80   - AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
81   - writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
82   - AT91_SMC_MODE_EXNW_DISABLE |
83   - AT91_SMC_MODE_DBW_8 |
84   - AT91_SMC_MODE_TDF_CYCLE(3),
85   - &smc->cs[3].mode);
86   -
87   - atmel_pio4_set_f_periph(AT91_PIO_PORTA, 0, 0); /* D0 */
88   - atmel_pio4_set_f_periph(AT91_PIO_PORTA, 1, 0); /* D1 */
89   - atmel_pio4_set_f_periph(AT91_PIO_PORTA, 2, 0); /* D2 */
90   - atmel_pio4_set_f_periph(AT91_PIO_PORTA, 3, 0); /* D3 */
91   - atmel_pio4_set_f_periph(AT91_PIO_PORTA, 4, 0); /* D4 */
92   - atmel_pio4_set_f_periph(AT91_PIO_PORTA, 5, 0); /* D5 */
93   - atmel_pio4_set_f_periph(AT91_PIO_PORTA, 6, 0); /* D6 */
94   - atmel_pio4_set_f_periph(AT91_PIO_PORTA, 7, 0); /* D7 */
95   - atmel_pio4_set_f_periph(AT91_PIO_PORTA, 12, 0); /* RE */
96   - atmel_pio4_set_f_periph(AT91_PIO_PORTA, 8, 0); /* WE */
97   - atmel_pio4_set_f_periph(AT91_PIO_PORTA, 9, 1); /* NCS */
98   - atmel_pio4_set_f_periph(AT91_PIO_PORTA, 21, 1); /* RDY */
99   - atmel_pio4_set_f_periph(AT91_PIO_PORTA, 10, 1); /* ALE */
100   - atmel_pio4_set_f_periph(AT91_PIO_PORTA, 11, 1); /* CLE */
101   -}
102   -
103   -static void board_usb_hw_init(void)
104   -{
105   - atmel_pio4_set_pio_output(AT91_PIO_PORTA, 28, 1);
106   -}
107   -
108   -static void board_gmac_hw_init(void)
109   -{
110   - atmel_pio4_set_f_periph(AT91_PIO_PORTB, 14, 0); /* GTXCK */
111   - atmel_pio4_set_f_periph(AT91_PIO_PORTB, 15, 0); /* GTXEN */
112   - atmel_pio4_set_f_periph(AT91_PIO_PORTB, 16, 0); /* GRXDV */
113   - atmel_pio4_set_f_periph(AT91_PIO_PORTB, 17, 0); /* GRXER */
114   - atmel_pio4_set_f_periph(AT91_PIO_PORTB, 18, 0); /* GRX0 */
115   - atmel_pio4_set_f_periph(AT91_PIO_PORTB, 19, 0); /* GRX1 */
116   - atmel_pio4_set_f_periph(AT91_PIO_PORTB, 20, 0); /* GTX0 */
117   - atmel_pio4_set_f_periph(AT91_PIO_PORTB, 21, 0); /* GTX1 */
118   - atmel_pio4_set_f_periph(AT91_PIO_PORTB, 22, 0); /* GMDC */
119   - atmel_pio4_set_f_periph(AT91_PIO_PORTB, 23, 0); /* GMDIO */
120   -
121   - at91_periph_clk_enable(ATMEL_ID_GMAC);
122   -}
123   -
124   -static void board_uart0_hw_init(void)
125   -{
126   - atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, 1); /* URXD0 */
127   - atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */
128   -
129   - at91_periph_clk_enable(CONFIG_USART_ID);
130   -}
131   -
132   -int board_early_init_f(void)
133   -{
134   - at91_periph_clk_enable(ATMEL_ID_PIOA);
135   - at91_periph_clk_enable(ATMEL_ID_PIOB);
136   - at91_periph_clk_enable(ATMEL_ID_PIOC);
137   - at91_periph_clk_enable(ATMEL_ID_PIOD);
138   -
139   - board_uart0_hw_init();
140   -
141   - return 0;
142   -}
143   -
144   -int board_init(void)
145   -{
146   - /* address of boot parameters */
147   - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
148   -
149   -#ifdef CONFIG_ATMEL_SPI
150   - board_spi0_hw_init();
151   -#endif
152   -#ifdef CONFIG_NAND_ATMEL
153   - board_nand_hw_init();
154   -#endif
155   -#ifdef CONFIG_MACB
156   - board_gmac_hw_init();
157   -#endif
158   -#ifdef CONFIG_CMD_USB
159   - board_usb_hw_init();
160   -#endif
161   -#ifdef CONFIG_USB_GADGET_ATMEL_USBA
162   - at91_udp_hw_init();
163   -#endif
164   -
165   - return 0;
166   -}
167   -
168   -int dram_init(void)
169   -{
170   - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
171   - CONFIG_SYS_SDRAM_SIZE);
172   - return 0;
173   -}
174   -
175   -int board_eth_init(bd_t *bis)
176   -{
177   - int rc = 0;
178   -
179   -#ifdef CONFIG_MACB
180   - rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
181   - if (rc)
182   - printf("GMAC register failed\n");
183   -#endif
184   -
185   -#ifdef CONFIG_USB_GADGET_ATMEL_USBA
186   - usba_udc_probe(&pdata);
187   -#ifdef CONFIG_USB_ETH_RNDIS
188   - usb_eth_initialize(bis);
189   -#endif
190   -#endif
191   -
192   - return rc;
193   -}
194   -
195   -/* SPL */
196   -#ifdef CONFIG_SPL_BUILD
197   -void spl_board_init(void)
198   -{
199   -#ifdef CONFIG_SPI_BOOT
200   - board_spi0_hw_init();
201   -#endif
202   -
203   -#ifdef CONFIG_NAND_BOOT
204   - board_nand_hw_init();
205   -#endif
206   -}
207   -
208   -static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
209   -{
210   - ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM);
211   -
212   - ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
213   - ATMEL_MPDDRC_CR_NR_ROW_14 |
214   - ATMEL_MPDDRC_CR_CAS_DDR_CAS5 |
215   - ATMEL_MPDDRC_CR_DIC_DS |
216   - ATMEL_MPDDRC_CR_DIS_DLL |
217   - ATMEL_MPDDRC_CR_NB_8BANKS |
218   - ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
219   - ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
220   -
221   - ddrc->rtr = 0x511;
222   -
223   - ddrc->tpr0 = ((6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
224   - (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) |
225   - (4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) |
226   - (9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) |
227   - (3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) |
228   - (4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) |
229   - (4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) |
230   - (4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));
231   -
232   - ddrc->tpr1 = ((27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
233   - (29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) |
234   - (0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) |
235   - (3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));
236   -
237   - ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
238   - (0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) |
239   - (0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) |
240   - (4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) |
241   - (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
242   -}
243   -
244   -void mem_init(void)
245   -{
246   - struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
247   - struct atmel_mpddrc_config ddrc_config;
248   - u32 reg;
249   -
250   - ddrc_conf(&ddrc_config);
251   -
252   - at91_periph_clk_enable(ATMEL_ID_MPDDRC);
253   - at91_system_clk_enable(AT91_PMC_DDR);
254   -
255   - reg = readl(&mpddrc->io_calibr);
256   - reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
257   - reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
258   - reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
259   - reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
260   - writel(reg, &mpddrc->io_calibr);
261   -
262   - writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE,
263   - &mpddrc->rd_data_path);
264   -
265   - ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
266   -
267   - writel(0x3, &mpddrc->cal_mr4);
268   - writel(64, &mpddrc->tim_cal);
269   -}
270   -
271   -void at91_pmc_init(void)
272   -{
273   - at91_plla_init(AT91_PMC_PLLAR_29 |
274   - AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
275   - AT91_PMC_PLLXR_MUL(82) |
276   - AT91_PMC_PLLXR_DIV(1));
277   -
278   - at91_pllicpr_init(0);
279   -
280   - at91_mck_init(AT91_PMC_MCKR_H32MXDIV |
281   - AT91_PMC_MCKR_PLLADIV_2 |
282   - AT91_PMC_MCKR_MDIV_3 |
283   - AT91_PMC_MCKR_CSS_PLLA);
284   -}
285   -#endif
board/atmel/sama5d2_ptc_ek/Kconfig
Diff comments   View file @ aaa4ba9
  1 +if TARGET_SAMA5D2_PTC_EK
  2 +
  3 +config SYS_BOARD
  4 + default "sama5d2_ptc_ek"
  5 +
  6 +config SYS_VENDOR
  7 + default "atmel"
  8 +
  9 +config SYS_SOC
  10 + default "at91"
  11 +
  12 +config SYS_CONFIG_NAME
  13 + default "sama5d2_ptc_ek"
  14 +
  15 +endif
board/atmel/sama5d2_ptc_ek/MAINTAINERS
Diff comments   View file @ aaa4ba9
  1 +SAMA5D2 PTC EK BOARD
  2 +M: Wenyou Yang <wenyou.yang@microchip.com>
  3 +M: Ludovic Desroches <ludovic.desroches@microchip.com>
  4 +S: Maintained
  5 +F: board/atmel/sama5d2_ptc_ek/
  6 +F: include/configs/sama5d2_ptc_ek.h
  7 +F: configs/sama5d2_ptc_ek_mmc_defconfig
  8 +F: configs/sama5d2_ptc_ek_nandflash_defconfig
board/atmel/sama5d2_ptc_ek/Makefile
Diff comments   View file @ aaa4ba9
  1 +#
  2 +# Copyright (C) 2017 Microchip Corporation
  3 +# Wenyou Yang <wenyou.yang@microchip.com>
  4 +#
  5 +# SPDX-License-Identifier: GPL-2.0+
  6 +#
  7 +
  8 +obj-y += sama5d2_ptc_ek.o
board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c
Diff comments   View file @ aaa4ba9
  1 +/*
  2 + * Copyright (C) 2017 Microchip Corporation
  3 + * Wenyou Yang <wenyou.yang@microchip.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <common.h>
  9 +#include <debug_uart.h>
  10 +#include <dm.h>
  11 +#include <i2c.h>
  12 +#include <nand.h>
  13 +#include <version.h>
  14 +#include <asm/io.h>
  15 +#include <asm/arch/at91_common.h>
  16 +#include <asm/arch/atmel_pio4.h>
  17 +#include <asm/arch/atmel_mpddrc.h>
  18 +#include <asm/arch/atmel_sdhci.h>
  19 +#include <asm/arch/clk.h>
  20 +#include <asm/arch/gpio.h>
  21 +#include <asm/arch/sama5d2.h>
  22 +#include <asm/arch/sama5d2_smc.h>
  23 +
  24 +DECLARE_GLOBAL_DATA_PTR;
  25 +
  26 +#ifdef CONFIG_NAND_ATMEL
  27 +static void board_nand_hw_init(void)
  28 +{
  29 + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  30 +
  31 + at91_periph_clk_enable(ATMEL_ID_HSMC);
  32 +
  33 + /* Configure SMC CS3 for NAND */
  34 + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
  35 + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
  36 + &smc->cs[3].setup);
  37 + writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
  38 + AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
  39 + &smc->cs[3].pulse);
  40 + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  41 + &smc->cs[3].cycle);
  42 + writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
  43 + AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) |
  44 + AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3) |
  45 + AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
  46 + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  47 + AT91_SMC_MODE_EXNW_DISABLE |
  48 + AT91_SMC_MODE_DBW_8 |
  49 + AT91_SMC_MODE_TDF_CYCLE(3),
  50 + &smc->cs[3].mode);
  51 +
  52 + atmel_pio4_set_b_periph(AT91_PIO_PORTA, 22, 0); /* D0 */
  53 + atmel_pio4_set_b_periph(AT91_PIO_PORTA, 23, 0); /* D1 */
  54 + atmel_pio4_set_b_periph(AT91_PIO_PORTA, 24, 0); /* D2 */
  55 + atmel_pio4_set_b_periph(AT91_PIO_PORTA, 25, 0); /* D3 */
  56 + atmel_pio4_set_b_periph(AT91_PIO_PORTA, 26, 0); /* D4 */
  57 + atmel_pio4_set_b_periph(AT91_PIO_PORTA, 27, 0); /* D5 */
  58 + atmel_pio4_set_b_periph(AT91_PIO_PORTA, 28, 0); /* D6 */
  59 + atmel_pio4_set_b_periph(AT91_PIO_PORTA, 29, 0); /* D7 */
  60 + atmel_pio4_set_b_periph(AT91_PIO_PORTB, 2, 0); /* RE */
  61 + atmel_pio4_set_b_periph(AT91_PIO_PORTA, 30, 0); /* WE */
  62 + atmel_pio4_set_b_periph(AT91_PIO_PORTA, 31, 1); /* NCS */
  63 + atmel_pio4_set_b_periph(AT91_PIO_PORTC, 8, 1); /* RDY */
  64 + atmel_pio4_set_b_periph(AT91_PIO_PORTB, 0, 1); /* ALE */
  65 + atmel_pio4_set_b_periph(AT91_PIO_PORTB, 1, 1); /* CLE */
  66 +}
  67 +#endif
  68 +
  69 +static void board_usb_hw_init(void)
  70 +{
  71 + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 12, 1);
  72 +}
  73 +
  74 +#ifdef CONFIG_DEBUG_UART_BOARD_INIT
  75 +static void board_uart0_hw_init(void)
  76 +{
  77 + atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, 1); /* URXD0 */
  78 + atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */
  79 +
  80 + at91_periph_clk_enable(ATMEL_ID_UART0);
  81 +}
  82 +
  83 +void board_debug_uart_init(void)
  84 +{
  85 + board_uart0_hw_init();
  86 +}
  87 +#endif
  88 +
  89 +#ifdef CONFIG_BOARD_EARLY_INIT_F
  90 +int board_early_init_f(void)
  91 +{
  92 +#ifdef CONFIG_DEBUG_UART
  93 + debug_uart_init();
  94 +#endif
  95 + return 0;
  96 +}
  97 +#endif
  98 +
  99 +int board_init(void)
  100 +{
  101 + /* address of boot parameters */
  102 + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  103 +
  104 +#ifdef CONFIG_NAND_ATMEL
  105 + board_nand_hw_init();
  106 +#endif
  107 +#ifdef CONFIG_CMD_USB
  108 + board_usb_hw_init();
  109 +#endif
  110 + return 0;
  111 +}
  112 +
  113 +int dram_init(void)
  114 +{
  115 + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  116 + CONFIG_SYS_SDRAM_SIZE);
  117 + return 0;
  118 +}
  119 +
  120 +#define AT24MAC_MAC_OFFSET 0xfa
  121 +
  122 +#ifdef CONFIG_MISC_INIT_R
  123 +int misc_init_r(void)
  124 +{
  125 +#ifdef CONFIG_I2C_EEPROM
  126 + at91_set_ethaddr(AT24MAC_MAC_OFFSET);
  127 +#endif
  128 + return 0;
  129 +}
  130 +#endif
configs/sama5d2_ptc_ek_mmc_defconfig
Diff comments   View file @ aaa4ba9
  1 +CONFIG_ARM=y
  2 +CONFIG_ARCH_AT91=y
  3 +CONFIG_TARGET_SAMA5D2_PTC_EK=y
  4 +CONFIG_SYS_MALLOC_F_LEN=0x2000
  5 +CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_ptc_ek"
  6 +CONFIG_DEBUG_UART=y
  7 +CONFIG_FIT=y
  8 +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC"
  9 +CONFIG_SD_BOOT=y
  10 +CONFIG_BOOTDELAY=3
  11 +CONFIG_CONSOLE_MUX=y
  12 +# CONFIG_DISPLAY_BOARDINFO is not set
  13 +CONFIG_HUSH_PARSER=y
  14 +CONFIG_CMD_BOOTZ=y
  15 +# CONFIG_CMD_IMI is not set
  16 +# CONFIG_CMD_FLASH is not set
  17 +# CONFIG_CMD_FPGA is not set
  18 +CONFIG_CMD_I2C=y
  19 +# CONFIG_CMD_LOADS is not set
  20 +CONFIG_CMD_MMC=y
  21 +CONFIG_CMD_NAND=y
  22 +CONFIG_CMD_USB=y
  23 +CONFIG_CMD_DHCP=y
  24 +CONFIG_CMD_PING=y
  25 +CONFIG_CMD_EXT4=y
  26 +CONFIG_CMD_FAT=y
  27 +CONFIG_OF_CONTROL=y
  28 +CONFIG_ENV_IS_IN_MMC=y
  29 +CONFIG_DM=y
  30 +CONFIG_SPL_DM_SEQ_ALIAS=y
  31 +CONFIG_CLK=y
  32 +CONFIG_CLK_AT91=y
  33 +CONFIG_AT91_UTMI=y
  34 +CONFIG_AT91_H32MX=y
  35 +CONFIG_AT91_GENERIC_CLK=y
  36 +CONFIG_DM_GPIO=y
  37 +CONFIG_ATMEL_PIO4=y
  38 +CONFIG_DM_I2C=y
  39 +CONFIG_SYS_I2C_AT91=y
  40 +CONFIG_I2C_EEPROM=y
  41 +CONFIG_DM_MMC=y
  42 +CONFIG_MMC_SDHCI=y
  43 +CONFIG_MMC_SDHCI_ATMEL=y
  44 +CONFIG_DM_ETH=y
  45 +CONFIG_MACB=y
  46 +CONFIG_PINCTRL=y
  47 +CONFIG_PINCTRL_AT91PIO4=y
  48 +CONFIG_DM_SERIAL=y
  49 +CONFIG_DEBUG_UART_ATMEL=y
  50 +CONFIG_DEBUG_UART_BASE=0xf801c000
  51 +CONFIG_DEBUG_UART_CLOCK=82000000
  52 +CONFIG_DEBUG_UART_BOARD_INIT=y
  53 +CONFIG_DEBUG_UART_ANNOUNCE=y
  54 +CONFIG_ATMEL_USART=y
  55 +CONFIG_TIMER=y
  56 +CONFIG_ATMEL_PIT_TIMER=y
  57 +CONFIG_USB=y
  58 +CONFIG_DM_USB=y
  59 +CONFIG_USB_EHCI_HCD=y
  60 +CONFIG_USB_STORAGE=y
configs/sama5d2_ptc_ek_nandflash_defconfig
Diff comments   View file @ aaa4ba9
  1 +CONFIG_ARM=y
  2 +CONFIG_ARCH_AT91=y
  3 +CONFIG_TARGET_SAMA5D2_PTC_EK=y
  4 +CONFIG_SYS_MALLOC_F_LEN=0x2000
  5 +CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_ptc_ek"
  6 +CONFIG_DEBUG_UART=y
  7 +CONFIG_FIT=y
  8 +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_NANDFLASH"
  9 +CONFIG_NAND_BOOT=y
  10 +CONFIG_BOOTDELAY=3
  11 +CONFIG_CONSOLE_MUX=y
  12 +# CONFIG_DISPLAY_BOARDINFO is not set
  13 +CONFIG_HUSH_PARSER=y
  14 +CONFIG_CMD_BOOTZ=y
  15 +# CONFIG_CMD_IMI is not set
  16 +# CONFIG_CMD_FLASH is not set
  17 +# CONFIG_CMD_FPGA is not set
  18 +CONFIG_CMD_I2C=y
  19 +# CONFIG_CMD_LOADS is not set
  20 +CONFIG_CMD_MMC=y
  21 +CONFIG_CMD_NAND=y
  22 +CONFIG_CMD_USB=y
  23 +CONFIG_CMD_DHCP=y
  24 +CONFIG_CMD_PING=y
  25 +CONFIG_CMD_EXT4=y
  26 +CONFIG_CMD_FAT=y
  27 +CONFIG_OF_CONTROL=y
  28 +CONFIG_ENV_IS_IN_NAND=y
  29 +CONFIG_DM=y
  30 +CONFIG_SPL_DM_SEQ_ALIAS=y
  31 +CONFIG_CLK=y
  32 +CONFIG_CLK_AT91=y
  33 +CONFIG_AT91_UTMI=y
  34 +CONFIG_AT91_H32MX=y
  35 +CONFIG_AT91_GENERIC_CLK=y
  36 +CONFIG_DM_GPIO=y
  37 +CONFIG_ATMEL_PIO4=y
  38 +CONFIG_DM_I2C=y
  39 +CONFIG_SYS_I2C_AT91=y
  40 +CONFIG_I2C_EEPROM=y
  41 +CONFIG_DM_MMC=y
  42 +CONFIG_MMC_SDHCI=y
  43 +CONFIG_MMC_SDHCI_ATMEL=y
  44 +CONFIG_DM_ETH=y
  45 +CONFIG_MACB=y
  46 +CONFIG_PINCTRL=y
  47 +CONFIG_PINCTRL_AT91PIO4=y
  48 +CONFIG_DM_SERIAL=y
  49 +CONFIG_DEBUG_UART_ATMEL=y
  50 +CONFIG_DEBUG_UART_BASE=0xf801c000
  51 +CONFIG_DEBUG_UART_CLOCK=82000000
  52 +CONFIG_DEBUG_UART_BOARD_INIT=y
  53 +CONFIG_DEBUG_UART_ANNOUNCE=y
  54 +CONFIG_ATMEL_USART=y
  55 +CONFIG_TIMER=y
  56 +CONFIG_ATMEL_PIT_TIMER=y
  57 +CONFIG_USB=y
  58 +CONFIG_DM_USB=y
  59 +CONFIG_USB_EHCI_HCD=y
  60 +CONFIG_USB_STORAGE=y
configs/sama5d2_ptc_nandflash_defconfig
View file @ aaa4ba9
1   -CONFIG_ARM=y
2   -CONFIG_ARCH_AT91=y
3   -CONFIG_TARGET_SAMA5D2_PTC=y
4   -CONFIG_SPL_GPIO_SUPPORT=y
5   -CONFIG_SPL_LIBCOMMON_SUPPORT=y
6   -CONFIG_SPL_LIBGENERIC_SUPPORT=y
7   -CONFIG_SPL_SERIAL_SUPPORT=y
8   -CONFIG_SPL_NAND_SUPPORT=y
9   -CONFIG_NAND_BOOT=y
10   -CONFIG_BOOTDELAY=3
11   -CONFIG_USE_BOOTARGS=y
12   -CONFIG_BOOTARGS="console=ttyS0,57600 earlyprintk mtdparts=atmel_nand:6M(bootstrap)ro, 6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=2 root=ubi0:rootfs"
13   -# CONFIG_DISPLAY_BOARDINFO is not set
14   -CONFIG_SPL=y
15   -# CONFIG_CMD_IMI is not set
16   -# CONFIG_CMD_FLASH is not set
17   -# CONFIG_CMD_FPGA is not set
18   -# CONFIG_CMD_LOADS is not set
19   -CONFIG_CMD_NAND=y
20   -CONFIG_CMD_NAND_TRIMFFS=y
21   -CONFIG_CMD_SF=y
22   -CONFIG_CMD_USB=y
23   -CONFIG_CMD_FAT=y
24   -CONFIG_ENV_IS_IN_NAND=y
25   -# CONFIG_MMC is not set
26   -CONFIG_SPI_FLASH=y
27   -CONFIG_USB=y
28   -CONFIG_USB_EHCI_HCD=y
29   -CONFIG_USB_STORAGE=y
30   -CONFIG_USB_GADGET=y
31   -CONFIG_USB_GADGET_MANUFACTURER="Atmel SAMA5D2_PTC"
32   -CONFIG_USB_GADGET_ATMEL_USBA=y
33   -CONFIG_USB_ETHER=y
configs/sama5d2_ptc_spiflash_defconfig
View file @ aaa4ba9
1   -CONFIG_ARM=y
2   -CONFIG_ARCH_AT91=y
3   -CONFIG_TARGET_SAMA5D2_PTC=y
4   -CONFIG_SPL_GPIO_SUPPORT=y
5   -CONFIG_SPL_LIBCOMMON_SUPPORT=y
6   -CONFIG_SPL_LIBGENERIC_SUPPORT=y
7   -CONFIG_SPL_SERIAL_SUPPORT=y
8   -CONFIG_SPL_SPI_FLASH_SUPPORT=y
9   -CONFIG_SPL_SPI_SUPPORT=y
10   -CONFIG_SPI_BOOT=y
11   -CONFIG_BOOTDELAY=3
12   -CONFIG_USE_BOOTARGS=y
13   -CONFIG_BOOTARGS="console=ttyS0,57600 earlyprintk mtdparts=atmel_nand:6M(bootstrap)ro, 6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=2 root=ubi0:rootfs"
14   -# CONFIG_DISPLAY_BOARDINFO is not set
15   -CONFIG_SPL=y
16   -# CONFIG_CMD_IMI is not set
17   -# CONFIG_CMD_FLASH is not set
18   -# CONFIG_CMD_FPGA is not set
19   -# CONFIG_CMD_LOADS is not set
20   -CONFIG_CMD_NAND=y
21   -CONFIG_CMD_NAND_TRIMFFS=y
22   -CONFIG_CMD_SF=y
23   -CONFIG_CMD_USB=y
24   -CONFIG_CMD_FAT=y
25   -CONFIG_ENV_IS_IN_SPI_FLASH=y
26   -# CONFIG_MMC is not set
27   -CONFIG_SPI_FLASH=y
28   -CONFIG_USB=y
29   -CONFIG_USB_EHCI_HCD=y
30   -CONFIG_USB_STORAGE=y
31   -CONFIG_USB_GADGET=y
32   -CONFIG_USB_GADGET_MANUFACTURER="Atmel SAMA5D2_PTC"
33   -CONFIG_USB_GADGET_ATMEL_USBA=y
34   -CONFIG_USB_ETHER=y
include/configs/sama5d2_ptc.h
View file @ aaa4ba9
1   -/*
2   - * Configuration settings for the SAMA5D2 PTC Engineering board.
3   - *
4   - * Copyright (C) 2016 Atmel
5   - * Wenyou Yang <wenyou.yang@atmel.com>
6   - *
7   - * SPDX-License-Identifier: GPL-2.0+
8   - */
9   -
10   -#ifndef __CONFIG_H
11   -#define __CONFIG_H
12   -
13   -#include "at91-sama5_common.h"
14   -
15   -/* serial console */
16   -#define CONFIG_ATMEL_USART
17   -#define CONFIG_USART_BASE 0xf801c000
18   -#define CONFIG_USART_ID 24
19   -
20   -#define CONFIG_SYS_SDRAM_BASE 0x20000000
21   -#define CONFIG_SYS_SDRAM_SIZE 0x20000000
22   -
23   -#define CONFIG_SYS_TIMER_COUNTER 0xf804803c
24   -
25   -#ifdef CONFIG_SPL_BUILD
26   -#define CONFIG_SYS_INIT_SP_ADDR 0x210000
27   -#else
28   -#define CONFIG_SYS_INIT_SP_ADDR \
29   - (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
30   -#endif
31   -
32   -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
33   -
34   -#undef CONFIG_AT91_GPIO
35   -#define CONFIG_ATMEL_PIO4
36   -
37   -/* SDRAM */
38   -#define CONFIG_NR_DRAM_BANKS 1
39   -
40   -/* SerialFlash */
41   -#ifdef CONFIG_CMD_SF
42   -#define CONFIG_ATMEL_SPI
43   -#define CONFIG_SPI_FLASH_ATMEL
44   -#define CONFIG_SF_DEFAULT_BUS 0
45   -#define CONFIG_SF_DEFAULT_CS 0
46   -#define CONFIG_SF_DEFAULT_SPEED 30000000
47   -#endif
48   -
49   -/* NAND flash */
50   -#ifdef CONFIG_CMD_NAND
51   -#define CONFIG_NAND_ATMEL
52   -#define CONFIG_SYS_MAX_NAND_DEVICE 1
53   -#define CONFIG_SYS_NAND_BASE 0x80000000
54   -/* our ALE is AD21 */
55   -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
56   -/* our CLE is AD22 */
57   -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
58   -#define CONFIG_SYS_NAND_ONFI_DETECTION
59   -/* PMECC & PMERRLOC */
60   -#define CONFIG_ATMEL_NAND_HWECC
61   -#define CONFIG_ATMEL_NAND_HW_PMECC
62   -#endif
63   -
64   -/* USB device */
65   -
66   -/* Ethernet Hardware */
67   -#define CONFIG_MACB
68   -#define CONFIG_RMII
69   -#define CONFIG_NET_RETRY_COUNT 20
70   -#define CONFIG_MACB_SEARCH_PHY
71   -
72   -#ifdef CONFIG_NAND_BOOT
73   -#undef CONFIG_ENV_OFFSET
74   -#undef CONFIG_ENV_OFFSET_REDUND
75   -#undef CONFIG_BOOTCOMMAND
76   -/* u-boot env in nand flash */
77   -#define CONFIG_ENV_OFFSET 0x200000
78   -#define CONFIG_ENV_OFFSET_REDUND 0x400000
79   -#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0xb80000 0x80000;" \
80   - "nand read 0x22000000 0x600000 0x600000;" \
81   - "bootz 0x22000000 - 0x21000000"
82   -#endif
83   -
84   -/* SPL */
85   -#define CONFIG_SPL_FRAMEWORK
86   -#define CONFIG_SPL_TEXT_BASE 0x200000
87   -#define CONFIG_SPL_MAX_SIZE 0x10000
88   -#define CONFIG_SPL_BSS_START_ADDR 0x20000000
89   -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
90   -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
91   -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
92   -
93   -#define CONFIG_SYS_MONITOR_LEN (512 << 10)
94   -
95   -#ifdef CONFIG_SPI_BOOT
96   -#define CONFIG_SPL_SPI_LOAD
97   -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
98   -
99   -#elif CONFIG_NAND_BOOT
100   -#define CONFIG_SPL_NAND_DRIVERS
101   -#define CONFIG_SPL_NAND_BASE
102   -#endif
103   -#define CONFIG_PMECC_CAP 8
104   -#define CONFIG_PMECC_SECTOR_SIZE 512
105   -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
106   -#define CONFIG_SYS_NAND_5_ADDR_CYCLE
107   -#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000
108   -#define CONFIG_SYS_NAND_PAGE_COUNT 64
109   -#define CONFIG_SYS_NAND_OOBSIZE 224
110   -#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
111   -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
112   -#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
113   -
114   -#endif
include/configs/sama5d2_ptc_ek.h
Diff comments   View file @ aaa4ba9
  1 +/*
  2 + * Configuration file for the SAMA5D2 PTC EK Board.
  3 + *
  4 + * Copyright (C) 2017 Microchip Technology Inc.
  5 + * Wenyou Yang <wenyou.yang@microchip.com>
  6 + * Ludovic Desroches <ludovic.desroches@microchip.com>
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +
  11 +#ifndef __CONFIG_H
  12 +#define __CONFIG_H
  13 +
  14 +#include "at91-sama5_common.h"
  15 +
  16 +#undef CONFIG_SYS_AT91_MAIN_CLOCK
  17 +#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
  18 +
  19 +#define CONFIG_MISC_INIT_R
  20 +
  21 +/* SDRAM */
  22 +#define CONFIG_NR_DRAM_BANKS 1
  23 +#define CONFIG_SYS_SDRAM_BASE 0x20000000
  24 +#define CONFIG_SYS_SDRAM_SIZE 0x20000000
  25 +
  26 +#define CONFIG_SYS_INIT_SP_ADDR \
  27 + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
  28 +
  29 +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
  30 +
  31 +/* NAND Flash */
  32 +#ifdef CONFIG_CMD_NAND
  33 +#define CONFIG_NAND_ATMEL
  34 +#define CONFIG_SYS_MAX_NAND_DEVICE 1
  35 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
  36 +/* our ALE is AD21 */
  37 +#define CONFIG_SYS_NAND_MASK_ALE BIT(21)
  38 +/* our CLE is AD22 */
  39 +#define CONFIG_SYS_NAND_MASK_CLE BIT(22)
  40 +#define CONFIG_SYS_NAND_ONFI_DETECTION
  41 +/* PMECC & PMERRLOC */
  42 +#define CONFIG_ATMEL_NAND_HWECC
  43 +#define CONFIG_ATMEL_NAND_HW_PMECC
  44 +#endif
  45 +
  46 +#endif /* __CONFIG_H */