Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit aaf224ab4ec400abefa17982cbd2ae995adc9978

Authored by wdenk
1 parent 3d3befa754
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

* Patch by Stephan Linz, 09 Mar 2004 

- Add support for the SSV ADNP/ESC1 (Nios Softcore)

* Patch by George G. Davis, 9 Mar 2004:
  fix recent build failure for SA1100 target

* Patch by Travis Sawyer, 09 Mar 2004:
  Support native interrupt mode for the IBM440GX.
  Previously it was running in 440GP compatibility mode.

Showing 23 changed files with 2967 additions and 6 deletions Side-by-side Diff

... ... @@ -2,6 +2,16 @@
2 2 Changes for U-Boot 1.0.2:
3 3 ======================================================================
4 4  
  5 +* Patch by Stephan Linz, 09 Mar 2004
  6 + - Add support for the SSV ADNP/ESC1 (Nios Softcore)
  7 +
  8 +* Patch by George G. Davis, 9 Mar 2004:
  9 + fix recent build failure for SA1100 target
  10 +
  11 +* Patch by Travis Sawyer, 09 Mar 2004:
  12 + Support native interrupt mode for the IBM440GX.
  13 + Previously it was running in 440GP compatibility mode.
  14 +
5 15 * Patch by Philippe Robin, 09 Mar 2004:
6 16 Added ARM Integrator AP, CP and Versatile PB926EJ-S Reference
7 17 Platform support.
... ... @@ -216,6 +216,7 @@
216 216 N: Stephan Linz
217 217 E: linz@li-pro.net
218 218 D: Support for Nios Stratix Development Kit (DK-1S10)
  219 +D: Support for SSV ADNP/ESC1 (Nios Cyclone)
219 220 W: http://www.li-pro.net
220 221  
221 222 N: Raymond Lo
... ... @@ -381,6 +381,7 @@
381 381 Stephan Linz <linz@li-pro.net>
382 382  
383 383 DK1S10 Nios-32
  384 + ADNPESC1 Nios-32
384 385  
385 386 Scott McNutt <smcnutt@psyent.com>
386 387  
... ... @@ -177,6 +177,8 @@
177 177 #########################################################################
178 178  
179 179 LIST_nios=" \
  180 + ADNPESC1 ADNPESC1_base_32 \
  181 + ADNPESC1_DNPEVA2_base_32 \
180 182 DK1C20 DK1C20_standard_32 \
181 183 DK1S10 DK1S10_standard_32 DK1S10_mtx_ldk_20 \
182 184 "
... ... @@ -1136,6 +1136,24 @@
1136 1136 }
1137 1137 @./mkconfig -a DK1S10 nios nios dk1s10 altera
1138 1138  
  1139 +ADNPESC1_DNPEVA2_base_32_config \
  1140 +ADNPESC1_base_32_config \
  1141 +ADNPESC1_config: unconfig
  1142 + @ >include/config.h
  1143 + @[ -z "$(findstring _DNPEVA2,$@)" ] || \
  1144 + { echo "#define CONFIG_DNPEVA2 1" >>include/config.h ; \
  1145 + echo "... DNP/EVA2 configuration" ; \
  1146 + }
  1147 + @[ -z "$(findstring _base_32,$@)" ] || \
  1148 + { echo "#define CONFIG_NIOS_BASE_32 1" >>include/config.h ; \
  1149 + echo "... NIOS 'base_32' configuration" ; \
  1150 + }
  1151 + @[ -z "$(findstring ADNPESC1_config,$@)" ] || \
  1152 + { echo "#define CONFIG_NIOS_BASE_32 1" >>include/config.h ; \
  1153 + echo "... NIOS 'base_32' configuration (DEFAULT)" ; \
  1154 + }
  1155 + @./mkconfig -a ADNPESC1 nios nios adnpesc1 ssv
  1156 +
1139 1157  
1140 1158 #########################################################################
1141 1159 ## MIPS32 AU1X00
board/ssv/adnpesc1/Makefile
Diff comments   View file @ aaf224a
  1 +#
  2 +# (C) Copyright 2001-2004
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# See file CREDITS for list of people who contributed to this
  6 +# project.
  7 +#
  8 +# This program is free software; you can redistribute it and/or
  9 +# modify it under the terms of the GNU General Public License as
  10 +# published by the Free Software Foundation; either version 2 of
  11 +# the License, or (at your option) any later version.
  12 +#
  13 +# This program is distributed in the hope that it will be useful,
  14 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 +# GNU General Public License for more details.
  17 +#
  18 +# You should have received a copy of the GNU General Public License
  19 +# along with this program; if not, write to the Free Software
  20 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 +# MA 02111-1307 USA
  22 +#
  23 +
  24 +include $(TOPDIR)/config.mk
  25 +
  26 +LIB = lib$(BOARD).a
  27 +
  28 +OBJS := $(BOARD).o flash.o misc.o
  29 +
  30 +SOBJS = vectors.o
  31 +
  32 +$(LIB): $(OBJS) $(SOBJS)
  33 + $(AR) crv $@ $^
  34 +
  35 +clean:
  36 + rm -f $(SOBJS) $(OBJS)
  37 +
  38 +distclean: clean
  39 + rm -f $(LIB) core *.bak .depend
  40 +
  41 +#########################################################################
  42 +
  43 +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
  44 + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
  45 +
  46 +-include .depend
  47 +
  48 +#########################################################################
board/ssv/adnpesc1/adnpesc1.c
Diff comments   View file @ aaf224a
  1 +/*
  2 + * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
  3 + * Stephan Linz <linz@li-pro.net>
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#include <common.h>
  25 +#include <nios-io.h>
  26 +#include <spi.h>
  27 +
  28 +#if defined(CONFIG_HW_WATCHDOG)
  29 +extern void ssv_wd_pio_init(void); /* comes from ../common/wd_pio.c
  30 + included by ./misc.c */
  31 +#endif
  32 +
  33 +void _default_hdlr (void)
  34 +{
  35 + printf ("default_hdlr\n");
  36 +}
  37 +
  38 +int board_early_init_f (void)
  39 +{
  40 +#if defined(CONFIG_HW_WATCHDOG)
  41 + ssv_wd_pio_init();
  42 +#endif
  43 + return 0;
  44 +}
  45 +
  46 +int checkboard (void)
  47 +{
  48 + puts ( "Board: SSV DilNetPC ADNP/ESC1"
  49 +#if defined(CONFIG_DNPEVA2)
  50 + " on DNP/EVA2"
  51 +#endif
  52 + "\n");
  53 +#if defined(CONFIG_NIOS_BASE_32)
  54 + puts ("Conf.: SSV Base 32 (nios_32)\n");
  55 +#endif
  56 +
  57 + return 0;
  58 +}
  59 +
  60 +long int initdram (int board_type)
  61 +{
  62 + return (0);
  63 +}
  64 +
  65 +/*
  66 + * The following are used to control the SPI chip selects for the SPI command.
  67 + */
  68 +#if (CONFIG_COMMANDS & CFG_CMD_SPI) && CONFIG_NIOS_SPI
  69 +
  70 +#define SPI_RTC_CS_MASK 0x00000001
  71 +
  72 +void spi_rtc_chipsel(int cs)
  73 +{
  74 + nios_spi_t *spi = (nios_spi_t *)CFG_NIOS_SPIBASE;
  75 +
  76 + if (cs)
  77 + spi->slaveselect = SPI_RTC_CS_MASK; /* activate (1) */
  78 + else
  79 + spi->slaveselect = 0; /* deactivate (0) */
  80 +}
  81 +
  82 +/*
  83 + * The SPI command uses this table of functions for controlling the SPI
  84 + * chip selects: it calls the appropriate function to control the SPI
  85 + * chip selects.
  86 + */
  87 +spi_chipsel_type spi_chipsel[] = {
  88 + spi_rtc_chipsel
  89 +};
  90 +int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
  91 +
  92 +#endif /* CFG_CMD_SPI */
  93 +
  94 +#if defined(CONFIG_POST)
  95 +/*
  96 + * Returns 1 if keys pressed to start the power-on long-running tests
  97 + * Called from board_init_f().
  98 + */
  99 +int post_hotkeys_pressed(void)
  100 +{
  101 + return 0; /* No hotkeys supported */
  102 +}
  103 +#endif /* CONFIG_POST */
board/ssv/adnpesc1/config.mk
Diff comments   View file @ aaf224a
  1 +#
  2 +# (C) Copyright 2004
  3 +# Li-Pro.Net <www.li-pro.net>
  4 +# Stephan Linz <linz@li-pro.net>
  5 +#
  6 +# See file CREDITS for list of people who contributed to this
  7 +# project.
  8 +#
  9 +# This program is free software; you can redistribute it and/or
  10 +# modify it under the terms of the GNU General Public License as
  11 +# published by the Free Software Foundation; either version 2 of
  12 +# the License, or (at your option) any later version.
  13 +#
  14 +# This program is distributed in the hope that it will be useful,
  15 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17 +# GNU General Public License for more details.
  18 +#
  19 +# You should have received a copy of the GNU General Public License
  20 +# along with this program; if not, write to the Free Software
  21 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 +# MA 02111-1307 USA
  23 +#
  24 +
  25 +TEXT_BASE = 0x02fc0000 # ATTENTION: notice your CFG_MONITOR_LEN setting
  26 +
  27 +ifeq ($(debug),1)
  28 +PLATFORM_CPPFLAGS += -DDEBUG
  29 +endif
board/ssv/adnpesc1/flash.c
Diff comments   View file @ aaf224a
  1 +/*
  2 + * (C) Copyright 2000-2004
  3 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 + *
  5 + * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
  6 + * Stephan Linz <linz@li-pro.net>
  7 + *
  8 + * See file CREDITS for list of people who contributed to this
  9 + * project.
  10 + *
  11 + * This program is free software; you can redistribute it and/or
  12 + * modify it under the terms of the GNU General Public License as
  13 + * published by the Free Software Foundation; either version 2 of
  14 + * the License, or (at your option) any later version.
  15 + *
  16 + * This program is distributed in the hope that it will be useful,
  17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19 + * GNU General Public License for more details.
  20 + *
  21 + * You should have received a copy of the GNU General Public License
  22 + * along with this program; if not, write to the Free Software
  23 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 + * MA 02111-1307 USA
  25 + */
  26 +
  27 +
  28 +#include <common.h>
  29 +#include <nios.h>
  30 +
  31 +/*
  32 + * include common flash code (for ssv boards)
  33 + */
  34 +#include "../common/flash.c"
  35 +
  36 +/*---------------------------------------------------------------------*/
  37 +#define BANKSZ (8 * 1024 * 1024)
  38 +#define SECTSZ (64 * 1024)
  39 +#define UBOOTSECS ((CFG_MONITOR_LEN + CFG_ENV_SIZE) / SECTSZ)
  40 +#define UBOOTAREA (UBOOTSECS * 64 * 1024) /* monitor / env area */
  41 +
  42 +/*---------------------------------------------------------------------*/
  43 +unsigned long flash_init (void)
  44 +{
  45 + int i;
  46 + unsigned long addr;
  47 + flash_info_t *fli = &flash_info[0];
  48 +
  49 + fli->size = BANKSZ;
  50 + fli->sector_count = CFG_MAX_FLASH_SECT;
  51 + fli->flash_id = FLASH_MAN_AMD + FLASH_AMLV640U;
  52 +
  53 + addr = CFG_FLASH_BASE;
  54 + for (i = 0; i < fli->sector_count; ++i) {
  55 + fli->start[i] = addr;
  56 + addr += SECTSZ;
  57 +
  58 + /* Protect monitor / environment area */
  59 + if (addr <= (CFG_FLASH_BASE + UBOOTAREA))
  60 + fli->protect[i] = 1;
  61 + else
  62 + fli->protect[i] = 0;
  63 + }
  64 +
  65 + return (BANKSZ);
  66 +}
board/ssv/adnpesc1/misc.c
Diff comments   View file @ aaf224a
  1 +/*
  2 + * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
  3 + * Stephan Linz <linz@li-pro.net>
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + *
  23 + * board/ssv/adnpesc1/misc.c
  24 + *
  25 + * miscellaneous board interfaces / drivers
  26 + */
  27 +
  28 +#include <common.h>
  29 +
  30 +#if defined(CONFIG_STATUS_LED)
  31 +#include "../common/cmd_sled.c"
  32 +#endif
  33 +
  34 +#if defined(CONFIG_HW_WATCHDOG)
  35 +#include "../common/wd_pio.c"
  36 +#endif
  37 +
  38 +#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
  39 +#include "../common/post.c"
  40 +#endif
board/ssv/adnpesc1/u-boot.lds
Diff comments   View file @ aaf224a
  1 +/*
  2 + * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
  3 + * Scott McNutt <smcnutt@psyent.com>
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +
  25 +OUTPUT_FORMAT("elf32-nios")
  26 +OUTPUT_ARCH(nios)
  27 +ENTRY(_start)
  28 +
  29 +SECTIONS
  30 +{
  31 + .text :
  32 + {
  33 + cpu/nios/start.o (.text)
  34 + *(.text)
  35 + }
  36 + __text_end = .;
  37 +
  38 + . = ALIGN(4);
  39 + .rodata :
  40 + {
  41 + *(.rodata)
  42 + }
  43 + __rodata_end = .;
  44 +
  45 + . = ALIGN(4);
  46 + .data :
  47 + {
  48 + *(.data)
  49 + }
  50 + . = ALIGN(4);
  51 + __data_end = .;
  52 +
  53 + __u_boot_cmd_start = .;
  54 + .u_boot_cmd :
  55 + {
  56 + *(.u_boot_cmd)
  57 + }
  58 + . = ALIGN(4);
  59 + __u_boot_cmd_end = .;
  60 +
  61 + __bss_start = .;
  62 + . = ALIGN(4);
  63 + .bss :
  64 + {
  65 + *(.bss)
  66 + }
  67 + . = ALIGN(4);
  68 + __bss_end = .;
  69 +}
board/ssv/adnpesc1/vectors.S
Diff comments   View file @ aaf224a
  1 +/*
  2 + * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
  3 + * Stephan Linz <linz@li-pro.net>
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#include <config.h>
  25 +
  26 +
  27 +/*************************************************************************
  28 + * Exception Vector Table
  29 + *
  30 + * This could have gone in the cpu soure tree, but the whole point of
  31 + * Nios is customization -- and polluting the cpu source tree with
  32 + * board-specific ifdef's really defeats the purpose, no? With this in
  33 + * the board-specific tree, each board has the freedom to organize
  34 + * vectors/traps, etc anyway it wants. The init code copies this table
  35 + * to the proper location.
  36 + *
  37 + * Each board can do what it likes here. But there are four "standard"
  38 + * handlers availble:
  39 + *
  40 + * _cwp_lolimit -Handles register window underflows.
  41 + * _cwp_hilimit -Handles register window overflows.
  42 + * _timebase_int -Increments the timebase.
  43 + * _def_xhandler -Default exception handler.
  44 + *
  45 + * _timebase_int handles a Nios Timer interrupt and increments the
  46 + * timestamp used for the get_timer(), reset_timer(), etc. routines. It
  47 + * expects the timer to be configured like the standard-32 low priority
  48 + * timer.
  49 + *
  50 + * _def_xhandler dispatches exceptions/traps via the external_interrupt()
  51 + * routine. This lets you use the irq_install_handler() and handle your
  52 + * interrupts/traps with code written in C.
  53 + ************************************************************************/
  54 +
  55 + .data
  56 + .global _vectors
  57 + .align 4
  58 +_vectors:
  59 +
  60 +#if defined(CFG_NIOS_CPU_OCI_BASE)
  61 + /* OCI does the reset job */
  62 + .long _def_xhandler@h /* Vector 0 - NMI / Reset */
  63 +#else
  64 + /* there is no OCI, so we have to do a direct reset jump here */
  65 + .long CFG_NIOS_CPU_RST_VECT /* Vector 0 - Reset to GERMS */
  66 +#endif
  67 + .long _cwp_lolimit@h /* Vector 1 - underflow */
  68 + .long _cwp_hilimit@h /* Vector 2 - overflow */
  69 +
  70 + .long _def_xhandler@h /* Vector 3 - GNUPro debug */
  71 + .long _def_xhandler@h /* Vector 4 - GNUPro debug */
  72 + .long _def_xhandler@h /* Vector 5 - GNUPro debug */
  73 + .long _def_xhandler@h /* Vector 6 - future reserved */
  74 + .long _def_xhandler@h /* Vector 7 - future reserved */
  75 + .long _def_xhandler@h /* Vector 8 - future reserved */
  76 + .long _def_xhandler@h /* Vector 9 - future reserved */
  77 + .long _def_xhandler@h /* Vector 10 - future reserved */
  78 + .long _def_xhandler@h /* Vector 11 - future reserved */
  79 + .long _def_xhandler@h /* Vector 12 - future reserved */
  80 + .long _def_xhandler@h /* Vector 13 - future reserved */
  81 + .long _def_xhandler@h /* Vector 14 - future reserved */
  82 + .long _def_xhandler@h /* Vector 15 - future reserved */
  83 +#if (CFG_NIOS_TMRIRQ == 16)
  84 + .long _timebase_int@h /* Vector 16 - lopri timer*/
  85 +#else
  86 + .long _def_xhandler@h /* Vector 16 */
  87 +#endif
  88 + .long _def_xhandler@h /* Vector 17 */
  89 + .long _def_xhandler@h /* Vector 18 */
  90 + .long _def_xhandler@h /* Vector 19 */
  91 + .long _def_xhandler@h /* Vector 20 */
  92 + .long _def_xhandler@h /* Vector 21 */
  93 + .long _def_xhandler@h /* Vector 22 */
  94 + .long _def_xhandler@h /* Vector 23 */
  95 + .long _def_xhandler@h /* Vector 24 */
  96 + .long _def_xhandler@h /* Vector 25 */
  97 + .long _def_xhandler@h /* Vector 26 */
  98 + .long _def_xhandler@h /* Vector 27 */
  99 + .long _def_xhandler@h /* Vector 28 */
  100 + .long _def_xhandler@h /* Vector 29 */
  101 + .long _def_xhandler@h /* Vector 30 */
  102 + .long _def_xhandler@h /* Vector 31 */
  103 + .long _def_xhandler@h /* Vector 32 */
  104 + .long _def_xhandler@h /* Vector 33 */
  105 + .long _def_xhandler@h /* Vector 34 */
  106 + .long _def_xhandler@h /* Vector 35 */
  107 + .long _def_xhandler@h /* Vector 36 */
  108 + .long _def_xhandler@h /* Vector 37 */
  109 + .long _def_xhandler@h /* Vector 38 */
  110 + .long _def_xhandler@h /* Vector 39 */
  111 + .long _def_xhandler@h /* Vector 40 */
  112 + .long _def_xhandler@h /* Vector 41 */
  113 + .long _def_xhandler@h /* Vector 42 */
  114 + .long _def_xhandler@h /* Vector 43 */
  115 + .long _def_xhandler@h /* Vector 44 */
  116 + .long _def_xhandler@h /* Vector 45 */
  117 + .long _def_xhandler@h /* Vector 46 */
  118 + .long _def_xhandler@h /* Vector 47 */
  119 + .long _def_xhandler@h /* Vector 48 */
  120 + .long _def_xhandler@h /* Vector 49 */
  121 +#if (CFG_NIOS_TMRIRQ == 50)
  122 + .long _timebase_int@h /* Vector 50 - lopri timer*/
  123 +#else
  124 + .long _def_xhandler@h /* Vector 50 */
  125 +#endif
  126 + .long _def_xhandler@h /* Vector 51 */
  127 + .long _def_xhandler@h /* Vector 52 */
  128 + .long _def_xhandler@h /* Vector 53 */
  129 + .long _def_xhandler@h /* Vector 54 */
  130 + .long _def_xhandler@h /* Vector 55 */
  131 + .long _def_xhandler@h /* Vector 56 */
  132 + .long _def_xhandler@h /* Vector 57 */
  133 + .long _def_xhandler@h /* Vector 58 */
  134 + .long _def_xhandler@h /* Vector 59 */
  135 + .long _def_xhandler@h /* Vector 60 */
  136 + .long _def_xhandler@h /* Vector 61 */
  137 + .long _def_xhandler@h /* Vector 62 */
  138 + .long _def_xhandler@h /* Vector 63 */
board/ssv/common/cmd_sled.c
Diff comments   View file @ aaf224a
  1 +/*
  2 + * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
  3 + * Stephan Linz <linz@li-pro.net>
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#include <common.h>
  25 +#include <command.h>
  26 +#include <status_led.h>
  27 +
  28 +#if defined(CONFIG_STATUS_LED)
  29 +
  30 +/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
  31 + * !!!!! Q u i c k & D i r t y H a c k !!!!!
  32 + * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
  33 + * !!!!! !!!!!
  34 + * !!!!! Next type definition was coming from original !!!!!
  35 + * !!!!! status LED driver drivers/status_led.c and !!!!!
  36 + * !!!!! should exported for using here. !!!!!
  37 + * !!!!! !!!!!
  38 + * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! */
  39 +
  40 +typedef struct {
  41 + led_id_t mask;
  42 + int state;
  43 + int period;
  44 + int cnt;
  45 +} led_dev_t;
  46 +
  47 +extern led_dev_t led_dev[];
  48 +
  49 +#if (CONFIG_COMMANDS & CFG_CMD_BSP)
  50 +int do_sled (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
  51 +{
  52 + int led_id = 0;
  53 +
  54 + if (argc > 1) {
  55 +#ifdef STATUS_LED_BOOT
  56 + if (!strcmp (argv[1], "boot")) {
  57 + led_id = STATUS_LED_BOOT + 1;
  58 + }
  59 +#endif
  60 +#ifdef STATUS_LED_RED
  61 + if (!strcmp (argv[1], "red")) {
  62 + led_id = STATUS_LED_RED + 1;
  63 + }
  64 +#endif
  65 +#ifdef STATUS_LED_YELLOW
  66 + if (!strcmp (argv[1], "yellow")) {
  67 + led_id = STATUS_LED_YELLOW + 1;
  68 + }
  69 +#endif
  70 +#ifdef STATUS_LED_GREEN
  71 + if (!strcmp (argv[1], "green")) {
  72 + led_id = STATUS_LED_GREEN + 1;
  73 + }
  74 +#endif
  75 + }
  76 +
  77 + switch (argc) {
  78 + case 1:
  79 +#if (STATUS_LED_BITS > 3)
  80 + for (; led_id < 4; led_id++)
  81 +#elif (STATUS_LED_BITS > 2)
  82 + for (; led_id < 3; led_id++)
  83 +#elif (STATUS_LED_BITS > 1)
  84 + for (; led_id < 2; led_id++)
  85 +#elif (STATUS_LED_BITS > 0)
  86 + for (; led_id < 1; led_id++)
  87 +#else
  88 +#error "*** STATUS_LED_BITS not correct defined ***"
  89 +#endif
  90 + {
  91 + printf ("Status LED '%s' is %s\n",
  92 + led_id == STATUS_LED_BOOT ? "boot"
  93 + : led_id == STATUS_LED_RED ? "red"
  94 + : led_id == STATUS_LED_YELLOW ? "yellow"
  95 + : led_id ==
  96 + STATUS_LED_GREEN ? "green" : "unknown",
  97 + led_dev[led_id].state ==
  98 + STATUS_LED_ON ? "on" : led_dev[led_id].
  99 + state ==
  100 + STATUS_LED_OFF ? "off" : led_dev[led_id].
  101 + state ==
  102 + STATUS_LED_BLINKING ? "blinking" : "unknown");
  103 + }
  104 + return 0;
  105 + case 2:
  106 + if (led_id) {
  107 + printf ("Status LED '%s' is %s\n", argv[1],
  108 + led_dev[led_id - 1].state ==
  109 + STATUS_LED_ON ? "on" : led_dev[led_id -
  110 + 1].state ==
  111 + STATUS_LED_OFF ? "off" : led_dev[led_id -
  112 + 1].state ==
  113 + STATUS_LED_BLINKING ? "blinking" : "unknown");
  114 + return 0;
  115 + } else
  116 + break;
  117 + case 3:
  118 + if (led_id) {
  119 + if (!strcmp (argv[2], "on")) {
  120 + status_led_set (led_id - 1, STATUS_LED_ON);
  121 + return 0;
  122 + } else if (!strcmp (argv[2], "off")) {
  123 + status_led_set (led_id - 1, STATUS_LED_OFF);
  124 + return 0;
  125 + } else if (!strcmp (argv[2], "blink")) {
  126 + status_led_set (led_id - 1,
  127 + STATUS_LED_BLINKING);
  128 + return 0;
  129 + } else
  130 + break;
  131 + } else
  132 + break;
  133 + default:
  134 + break;
  135 + }
  136 + printf ("Usage:\n%s\n", cmdtp->usage);
  137 + return 1;
  138 +}
  139 +
  140 +#ifdef STATUS_LED_BOOT
  141 +#ifdef STATUS_LED_RED
  142 +#ifdef STATUS_LED_YELLOW
  143 +#ifdef STATUS_LED_GREEN
  144 +#define __NAME_STR " - name: boot|red|yellow|green\n"
  145 +#else
  146 +#define __NAME_STR " - name: boot|red|yellow\n"
  147 +#endif
  148 +#else
  149 +#define __NAME_STR " - name: boot|red\n"
  150 +#endif
  151 +#else
  152 +#define __NAME_STR " - name: boot\n"
  153 +#endif
  154 +#else
  155 +#define __NAME_STR " - name: (no such defined)\n"
  156 +#endif
  157 +
  158 +U_BOOT_CMD (sled, 3, 0, do_sled,
  159 + "sled - check and set status led\n",
  160 + "sled [name [state]]\n" __NAME_STR " - state: on|off|blink\n");
  161 +#endif /* CFG_CMD_BSP */
  162 +#endif /* CONFIG_STATUS_LED */
board/ssv/common/flash.c
Diff comments   View file @ aaf224a
  1 +/*
  2 + * (C) Copyright 2000-2004
  3 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 + *
  5 + * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
  6 + * Stephan Linz <linz@li-pro.net>
  7 + *
  8 + * See file CREDITS for list of people who contributed to this
  9 + * project.
  10 + *
  11 + * This program is free software; you can redistribute it and/or
  12 + * modify it under the terms of the GNU General Public License as
  13 + * published by the Free Software Foundation; either version 2 of
  14 + * the License, or (at your option) any later version.
  15 + *
  16 + * This program is distributed in the hope that it will be useful,
  17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19 + * GNU General Public License for more details.
  20 + *
  21 + * You should have received a copy of the GNU General Public License
  22 + * along with this program; if not, write to the Free Software
  23 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 + * MA 02111-1307 USA
  25 + */
  26 +
  27 +
  28 +#include <common.h>
  29 +#include <watchdog.h>
  30 +#include <nios.h>
  31 +
  32 +flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
  33 +
  34 +/*--------------------------------------------------------------------*/
  35 +void flash_print_info (flash_info_t * info)
  36 +{
  37 + int i, k;
  38 + unsigned long size;
  39 + int erased;
  40 + volatile unsigned char *flash;
  41 +
  42 + printf (" Size: %ld KB in %d Sectors\n",
  43 + info->size >> 10, info->sector_count);
  44 + printf (" Sector Start Addresses:");
  45 + for (i = 0; i < info->sector_count; ++i) {
  46 +
  47 + /* Check if whole sector is erased */
  48 + if (i != (info->sector_count - 1))
  49 + size = info->start[i + 1] - info->start[i];
  50 + else
  51 + size = info->start[0] + info->size - info->start[i];
  52 + erased = 1;
  53 + flash = (volatile unsigned char *) info->start[i];
  54 + for (k = 0; k < size; k++) {
  55 + if (*flash++ != 0xff) {
  56 + erased = 0;
  57 + break;
  58 + }
  59 + }
  60 +
  61 + /* Print the info */
  62 + if ((i % 5) == 0)
  63 + printf ("\n ");
  64 + printf (" %08lX%s%s", info->start[i], erased ? " E" : " ",
  65 + info->protect[i] ? "RO " : " ");
  66 + }
  67 + printf ("\n");
  68 +}
  69 +
  70 +/*-------------------------------------------------------------------*/
  71 +
  72 +
  73 +int flash_erase (flash_info_t * info, int s_first, int s_last)
  74 +{
  75 + volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
  76 + volatile CFG_FLASH_WORD_SIZE *addr2;
  77 + int prot, sect, wait;
  78 + unsigned oldpri;
  79 + ulong start;
  80 +
  81 + /* Some sanity checking */
  82 + if ((s_first < 0) || (s_first > s_last)) {
  83 + printf ("- no sectors to erase\n");
  84 + return 1;
  85 + }
  86 +
  87 + prot = 0;
  88 + for (sect = s_first; sect <= s_last; ++sect) {
  89 + if (info->protect[sect]) {
  90 + prot++;
  91 + }
  92 + }
  93 + if (prot) {
  94 + printf ("- Warning: %d protected sectors will not be erased!\n",
  95 + prot);
  96 + } else {
  97 + printf ("\n");
  98 + }
  99 +
  100 +#ifdef DEBUG
  101 + for (sect = s_first; sect <= s_last; sect++) {
  102 + printf("- Erase: Sect: %i @ 0x%08x\n", sect, info->start[sect]);
  103 + }
  104 +#endif
  105 +
  106 + /* NOTE: disabling interrupts on Nios can be very bad since it
  107 + * also disables the LO_LIMIT exception. It's better here to
  108 + * set the interrupt priority to 3 & restore it when we're done.
  109 + */
  110 + oldpri = ipri (3);
  111 +
  112 + /* It's ok to erase multiple sectors provided we don't delay more
  113 + * than 50 usec between cmds ... at which point the erase time-out
  114 + * occurs. So don't go and put printf() calls in the loop ... it
  115 + * won't be very helpful ;-)
  116 + */
  117 + for (sect = s_first; sect <= s_last; sect++) {
  118 + if (info->protect[sect] == 0) { /* not protected */
  119 + addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
  120 + *addr = 0xf0;
  121 + *(addr+0xAAA/2) = 0xaa;
  122 + *(addr+0x554/2) = 0x55;
  123 + *(addr+0xAAA/2) = 0x80;
  124 + *(addr+0xAAA/2) = 0xaa;
  125 + *(addr+0x554/2) = 0x55;
  126 + *addr2 = 0x30;
  127 + /* Now just wait for 0xffff & provide some user
  128 + * feedback while we wait. Here we have to grant
  129 + * timer interrupts. Otherwise get_timer() can't
  130 + * work right. */
  131 + ipri(oldpri);
  132 + start = get_timer (0);
  133 + while (*addr2 != 0xffff) {
  134 + for (wait = 8; wait; wait--) {
  135 + udelay (125 * 1000);
  136 + }
  137 + putc ('.');
  138 + if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
  139 + printf ("timeout\n");
  140 + return 1;
  141 + }
  142 + }
  143 + oldpri = ipri (3); /* disallow non important irqs again */
  144 + }
  145 + }
  146 +
  147 + printf ("\n");
  148 + *addr = 0xf0;
  149 +
  150 + /* Restore interrupt priority */
  151 + ipri (oldpri);
  152 +
  153 + return 0;
  154 +}
  155 +
  156 +/*-----------------------------------------------------------------------
  157 + * Copy memory to flash, returns:
  158 + * 0 - OK
  159 + * 1 - write timeout
  160 + * 2 - Flash not erased
  161 + */
  162 +
  163 +int write_buff (flash_info_t * info, uchar * srcbuffer, ulong addr, ulong cnt)
  164 +{
  165 +
  166 + volatile CFG_FLASH_WORD_SIZE *cmd = (vu_short *) info->start[0];
  167 + volatile CFG_FLASH_WORD_SIZE *dst = (vu_short *) addr;
  168 + CFG_FLASH_WORD_SIZE *src = (void *) srcbuffer;
  169 + CFG_FLASH_WORD_SIZE b;
  170 + unsigned oldpri;
  171 + ulong start;
  172 +
  173 + cnt /= sizeof(CFG_FLASH_WORD_SIZE);
  174 + while (cnt) {
  175 + /* Check for sufficient erase */
  176 + b = *src;
  177 + if ((*dst & b) != b) {
  178 + printf ("%02x : %02x\n", *dst, b);
  179 + return (2);
  180 + }
  181 +
  182 + /* Disable interrupts other than window underflow
  183 + * (interrupt priority 2)
  184 + */
  185 + oldpri = ipri (3);
  186 + *(cmd+0xAAA/2) = 0xaa;
  187 + *(cmd+0x554/2) = 0x55;
  188 + *(cmd+0xAAA/2) = 0xa0;
  189 + ipri (oldpri);
  190 + *dst = b;
  191 +
  192 + /* Verify write */
  193 + start = get_timer (0);
  194 + while (*dst != b) {
  195 + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
  196 + *cmd = 0xf0;
  197 + return 1;
  198 + }
  199 + }
  200 + dst++;
  201 + src++;
  202 + cnt--;
  203 + }
  204 +
  205 + *cmd = 0xf0;
  206 + return (0);
  207 +}
board/ssv/common/post.c
Diff comments   View file @ aaf224a
  1 +/*
  2 + * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
  3 + * Stephan Linz <linz@li-pro.net>
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#include <common.h>
  25 +
  26 +#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
  27 +
  28 +#if !defined(CFG_NIOS_POST_WORD_ADDR)
  29 +#error "*** CFG_NIOS_POST_WORD_ADDR not defined ***"
  30 +#endif
  31 +
  32 +void post_word_store (ulong a)
  33 +{
  34 + volatile void *save_addr = (void *)(CFG_NIOS_POST_WORD_ADDR);
  35 + *(volatile ulong *) save_addr = a;
  36 +}
  37 +
  38 +ulong post_word_load (void)
  39 +{
  40 + volatile void *save_addr = (void *)(CFG_NIOS_POST_WORD_ADDR);
  41 + return *(volatile ulong *) save_addr;
  42 +}
  43 +
  44 +#endif /* CONFIG_POST || CONFIG_LOGBUFFER*/
board/ssv/common/wd_pio.c
Diff comments   View file @ aaf224a
  1 +/*
  2 + * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
  3 + * Stephan Linz <linz@li-pro.net>
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#include <common.h>
  25 +#include <command.h>
  26 +#include <nios.h>
  27 +#include <nios-io.h>
  28 +
  29 +#if defined(CONFIG_HW_WATCHDOG)
  30 +
  31 +#if !defined(CONFIG_HW_WDENA_BASE)
  32 +#error "*** CONFIG_HW_WDENA_BASE not defined ***"
  33 +#if !defined(CONFIG_HW_WDENA_BIT)
  34 +#error "*** CONFIG_HW_WDENA_BIT not defined ***"
  35 +#endif
  36 +#endif
  37 +
  38 +#if !defined(CONFIG_HW_WDTOG_BASE)
  39 +#error "*** CONFIG_HW_WDTOG_BASE not defined ***"
  40 +#if !defined(CONFIG_HW_WDTOG_BIT)
  41 +#error "*** CONFIG_HW_WDTOG_BIT not defined ***"
  42 +#endif
  43 +#endif
  44 +
  45 +#ifdef CONFIG_HW_WDPORT_WRONLY /* emulate read access */
  46 +static unsigned __wd_ena_pio_portval = 0;
  47 +#endif
  48 +
  49 +#define WD_PIO_INIT_DONE(V) ((V) & (1 << CONFIG_HW_WDENA_BIT))
  50 +
  51 +void ssv_wd_pio_init(void)
  52 +{
  53 + nios_pio_t *ena_piop = (nios_pio_t*)CONFIG_HW_WDENA_BASE;
  54 + nios_pio_t *trg_piop = (nios_pio_t*)CONFIG_HW_WDTOG_BASE;
  55 +
  56 + trg_piop->data &= ~(1 << CONFIG_HW_WDTOG_BIT);
  57 +
  58 +#ifdef CONFIG_HW_WDPORT_WRONLY /* emulate read access */
  59 +
  60 + __wd_ena_pio_portval |= (1 << CONFIG_HW_WDENA_BIT);
  61 + ena_piop->data = __wd_ena_pio_portval;
  62 +
  63 +#else /* !CONFIG_HW_WDPORT_WRONLY */
  64 +
  65 + trg_piop->direction |= (1 << CONFIG_HW_WDTOG_BIT);
  66 +
  67 + ena_piop->data |= (1 << CONFIG_HW_WDENA_BIT);
  68 + ena_piop->direction |= (1 << CONFIG_HW_WDENA_BIT);
  69 +
  70 +#endif /* CONFIG_HW_WDPORT_WRONLY */
  71 +}
  72 +
  73 +void ssv_wd_pio_done(void)
  74 +{
  75 + nios_pio_t *piop = (nios_pio_t*)CONFIG_HW_WDENA_BASE;
  76 +
  77 +#ifdef CONFIG_HW_WDPORT_WRONLY /* emulate read access */
  78 +
  79 + __wd_ena_pio_portval &= ~(1 << CONFIG_HW_WDENA_BIT);
  80 + piop->data = __wd_ena_pio_portval;
  81 +
  82 +#else /* !CONFIG_HW_WDPORT_WRONLY */
  83 +
  84 + piop->data &= ~(1 << CONFIG_HW_WDENA_BIT);
  85 +
  86 +#endif /* CONFIG_HW_WDPORT_WRONLY */
  87 +}
  88 +
  89 +void ssv_wd_pio_reset(void)
  90 +{
  91 + nios_pio_t *trg_piop = (nios_pio_t*)CONFIG_HW_WDTOG_BASE;
  92 +
  93 +#ifdef CONFIG_HW_WDPORT_WRONLY
  94 + if (WD_PIO_INIT_DONE(__wd_ena_pio_portval))
  95 +#else
  96 + nios_pio_t *ena_piop = (nios_pio_t*)CONFIG_HW_WDENA_BASE;
  97 +
  98 + if (WD_PIO_INIT_DONE(ena_piop->data))
  99 +#endif
  100 + {
  101 + trg_piop->data |= (1 << CONFIG_HW_WDTOG_BIT);
  102 + trg_piop->data &= ~(1 << CONFIG_HW_WDTOG_BIT);
  103 + }
  104 +}
  105 +
  106 +void hw_watchdog_reset(void)
  107 +{
  108 + int re_enable = disable_interrupts ();
  109 +
  110 + ssv_wd_pio_reset();
  111 + if (re_enable)
  112 + enable_interrupts ();
  113 +}
  114 +
  115 +#if (CONFIG_COMMANDS & CFG_CMD_BSP)
  116 +int do_wd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
  117 +{
  118 + nios_pio_t *ena_piop = (nios_pio_t*)CONFIG_HW_WDENA_BASE;
  119 +
  120 + switch (argc)
  121 + {
  122 + case 1:
  123 + printf ("Watchdog timer status is %s\n",
  124 +#ifdef CONFIG_HW_WDPORT_WRONLY
  125 + WD_PIO_INIT_DONE(__wd_ena_pio_portval)
  126 +#else
  127 + WD_PIO_INIT_DONE(ena_piop->data)
  128 +#endif
  129 + ? "on" : "off");
  130 + return 0;
  131 + case 2:
  132 + if (!strcmp(argv[1],"on"))
  133 + {
  134 + ssv_wd_pio_init();
  135 + printf("Watchdog timer now is on\n");
  136 + return 0;
  137 + }
  138 + else if (!strcmp(argv[1],"off"))
  139 + {
  140 + ssv_wd_pio_done();
  141 + printf("Watchdog timer now is off\n");
  142 + return 0;
  143 + }
  144 + break;
  145 + default:
  146 + break;
  147 + }
  148 + printf ("Usage:\n%s\n", cmdtp->usage);
  149 + return 1;
  150 +}
  151 +
  152 +U_BOOT_CMD(
  153 + wd, 2, 1, do_wd,
  154 + "wd - check and set watchdog\n",
  155 + "on - switch watchDog on\n"
  156 + "wd off - switch watchdog off\n"
  157 + "wd - print current status\n"
  158 +);
  159 +#endif /* CFG_CMD_BSP */
  160 +#endif /* CONFIG_HW_WATCHDOG */
cpu/ppc4xx/interrupts.c
Diff comments   View file @ aaf224a
... ... @@ -170,9 +170,21 @@
170 170 #endif
171 171  
172 172 #if defined(CONFIG_440_GX)
  173 + /* Take the GX out of compatibility mode
  174 + * Travis Sawyer, 9 Mar 2004
  175 + * NOTE: 440gx user manual inconsistency here
  176 + * Compatibility mode and Ethernet Clock select are not
  177 + * correct in the manual
  178 + */
  179 + mfsdr(sdr_mfr, val);
  180 + val &= ~0x10000000;
  181 + mtsdr(sdr_mfr,val);
  182 +
173 183 /* Enable UIC interrupts via UIC Base Enable Register */
174   - mtdcr(uicb0er, UICB0_ALL);
175   - mtdcr(uicb0cr, UICB0_ALL);
  184 + mtdcr(uicb0sr, UICB0_ALL);
  185 + mtdcr(uicb0er, 0x54000000);
  186 + /* None are critical */
  187 + mtdcr(uicb0cr, 0);
176 188 #endif
177 189  
178 190 return (0);
179 191  
... ... @@ -194,11 +206,16 @@
194 206 /* 440 GX uses base uic register */
195 207 uic_msr = mfdcr(uicb0msr);
196 208  
197   - uic0_interrupt(0);
198   - uic1_interrupt(0);
199   - uic2_interrupt(0);
  209 + if ( (UICB0_UIC0CI & uic_msr) || (UICB0_UIC0NCI & uic_msr) )
  210 + uic0_interrupt(0);
200 211  
201   - mtdcr(uicb0sr, UICB0_ALL);
  212 + if ( (UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr) )
  213 + uic1_interrupt(0);
  214 +
  215 + if ( (UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr) )
  216 + uic2_interrupt(0);
  217 +
  218 + mtdcr(uicb0sr, uic_msr);
202 219  
203 220 return;
204 221  
cpu/sa1100/interrupts.c
Diff comments   View file @ aaf224a
... ... @@ -218,4 +218,25 @@
218 218 while (tmo >= get_timer_masked ())
219 219 /*NOP*/;
220 220 }
  221 +
  222 +/*
  223 + * This function is derived from PowerPC code (read timebase as long long).
  224 + * On ARM it just returns the timer value.
  225 + */
  226 +unsigned long long get_ticks(void)
  227 +{
  228 + return get_timer(0);
  229 +}
  230 +
  231 +/*
  232 + * This function is derived from PowerPC code (timebase clock frequency).
  233 + * On ARM it returns the number of timer ticks per second.
  234 + */
  235 +ulong get_tbclk (void)
  236 +{
  237 + ulong tbclk;
  238 +
  239 + tbclk = CFG_HZ;
  240 + return tbclk;
  241 +}
  1 +
  2 + SSV ADNP/ESC1 Embedded Softcore Computing
  3 + Nios Softcore, Altera Cyclone FPGA
  4 +
  5 + Last Update: February 27, 2004
  6 +====================================================================
  7 +
  8 +This file contains information regarding U-Boot and the SSV Embedded
  9 +Nios Softcore Computing platform ADNP/ESC1. For general Nios
  10 +information see doc/README.nios.
  11 +
  12 +Most stuff of this file was borrowed and based on README.dk1s10,
  13 +the Altera DK-1S10 related information file.
  14 +
  15 +For those interested in contributing ... see HELP WANTED section
  16 +in doc/README.nios.
  17 +
  18 +Contents:
  19 +
  20 + 1. Files
  21 + 2. Memory Organization
  22 + 3. CPU Variations
  23 + 4. Examples
  24 + 5. Programming U-Boot into FLASH with GERMS
  25 + 6. Autoboot
  26 + 7. U-Boot environment convention and update philosophy
  27 +
  28 +====================================================================
  29 +
  30 +1. Files
  31 +=========
  32 + board/ssv/adnpesc1/*
  33 + include/configs/ADNPESC1.h
  34 + include/configs/ADNPESC1_base_32.h
  35 +
  36 +
  37 +2. Memory Organization
  38 +=======================
  39 +
  40 +For the most part, you can put things pretty much anywhere.
  41 +This is pretty flexible for Nios. So here we make some arbitrary
  42 +choices & assume that the monitor is placed at the end of a memory
  43 +resource. So you must make sure TEXT_BASE is chosen appropriately.
  44 +This is very important if you plan to move your memory to another
  45 +place as configured at this time!
  46 +
  47 + -The heap is placed below the monitor (U-Boot code).
  48 + -Global data is placed below the heap.
  49 + -The stack is placed below global data (&grows down).
  50 +
  51 +(see doc/README.adnpesc1_base32 too)
  52 +
  53 +
  54 +3. CPU Variations
  55 +=================
  56 +
  57 +There are more than one NIOS CPU variation for the ADNP/ESC1 possible.
  58 +U-Boot supports the following CPU configurations:
  59 +
  60 + - SSV Basis 32 (make ADNPESC1_base_32_config)
  61 + - SSV Basis 32 at DNP evaluation base board 2
  62 + (make ADNPESC1_DNPEVA2_base_32_config)
  63 +
  64 +
  65 +4. Examples
  66 +============
  67 +
  68 +The hello_world example works fine. To try out you have to change
  69 +the default load address from 0x0100_0000 to 0x0204_0000 in
  70 +examples/Makefile (the real SDRAM for default board configuration).
  71 +
  72 +
  73 +5. Programming U-Boot into FLASH with GERMS
  74 +============================================
  75 +
  76 +The current version of the ADNP/ESC1 port with the default
  77 +configuration settings occupies about 97 KBytes of flash.
  78 +A minimal configuration occupies less than 70 KByte
  79 +(network, SPI, POST and board command support disabled). You
  80 +can save more memory by deactivating the Hu-Shell support and
  81 +long command help (CFG_HUSH_PARSER, CFG_LONGHELP).
  82 +
  83 +To program U-Boot into the ADNP/ESC1 flash using GERMS do the
  84 +following:
  85 +
  86 +1. Download U-Boot to its target run space in SDRAM:
  87 +
  88 + a. Close jumper RCM_EN# and push the reset button.
  89 +
  90 + b. From the command line, download U-Boot using the
  91 + nios-run:
  92 +
  93 + $ nios-run -r u-boot.srec
  94 +
  95 + NOTE: In some cases this want fail. I don't know why,
  96 + but try again.
  97 +
  98 +This takes about 1 minute (GERMS is not very speedy here).
  99 +After u-boot is downloaded it will be executed. You should
  100 +see the following:
  101 +
  102 + U-Boot 1.0.2 (Jan 30 2004 - 12:59:15)
  103 +
  104 + CPU: Nios-32 Rev. 3.3 (0x3038)
  105 + Reg file size: 512 LO_LIMIT/HI_LIMIT: 1/30
  106 + Board: SSV DilNetPC ADNP/ESC1
  107 + Conf.: SSV Base 32 (nios_32)
  108 + In: serial
  109 + Out: serial
  110 + Err: serial
  111 + ADNPESC1 >
  112 +
  113 +
  114 +2. Quit nios-run and start your terminal application (e.g. start
  115 + Hyperterminal or minicom).
  116 +
  117 +3. Download the u-boot code to RAM. When using Hyperterminal, do the
  118 + following:
  119 +
  120 + a. From the u-boot command prompt start a binary download to SDRAM:
  121 +
  122 + at the SSV Basis 32 to SDRAM:
  123 +
  124 + ==> loadb 2000100
  125 +
  126 + b. Download u-boot.bin using kermit.
  127 +
  128 +4. From the U-Boot command prompt, erase flash:
  129 +
  130 + at the SSV Basis 32 from 0x1000000 to 0x103ffff:
  131 +
  132 + ==> protect off 1:0-3
  133 + ==> erase 1:0-3
  134 +
  135 +5. Copy the binary image from SDRAM to flash:
  136 +
  137 + at the SSV Basis 32 from SDRAM:
  138 +
  139 + ==> cp.b 2000100 1000000 $filesize
  140 +
  141 +U-Boot will now automatically start when the board is powered on or
  142 +reset using the SSV Basis 32 configuration without closed RCM jumper.
  143 +To start U-Boot with closed RCM Jumper, enter the following GERMS
  144 +command:
  145 +
  146 + + g 1000000
  147 +
  148 +
  149 +6. Autoboot
  150 +===========
  151 +
  152 +U-Boot will try to boot a valid Nios application from Flash. For this
  153 +it will use the deposited Hu-Shell script in environment variable
  154 +'bootcmd' which is looking for a valid Nios application identifier
  155 +string in Flash and go on at even its entry address. For more
  156 +information see the next chapter.
  157 +
  158 +
  159 +7. U-Boot environment convention and update philosophy
  160 +======================================================
  161 +
  162 +U-Boot for the SSV ADNP/ESC1 target knows about many environment
  163 +variables used to control the startup process, update process for
  164 +raw Nios applications, and optionally file system image updates.
  165 +In default configuration there are two Hu-Shell scripts to update
  166 +the Nios application and/or the file system image:
  167 +
  168 +1. Update Nios application (ex. the uCLinux kernel):
  169 +
  170 + run 'appl_update'
  171 +
  172 +2. Update optional file system image (ex. RomFS image used by uCLinux):
  173 +
  174 + run 'fs_update'
  175 +
  176 +The Nios application can be any programm code generated in relation
  177 +to the Nios application identifier -- the string "Nios" at offset
  178 +address 0x0c. To use the scripts like described above in a secure way
  179 +you have to check-up the next environment variables:
  180 +
  181 +1. update_allowed
  182 +
  183 + - Update switch -- must be set to '1' (one) to allow any update
  184 + - default is '0' (zero)
  185 +
  186 + NOTE: You should avoid to save this variable with non zero
  187 + value to Flash. Otherwise it would be allow any
  188 + update process at any time!
  189 +
  190 +2. appl_entry_addr
  191 +
  192 + - Nios application area start address (usually in Flash)
  193 + - this is the startup address for autoboot
  194 + - each Nios application code we want to update will be copied
  195 + to this address
  196 + - default is CFG_ADNPESC1_NIOS_APPL_ENTRY
  197 +
  198 +3. appl_end_addr
  199 +
  200 + - Nios application area end address (usually in Flash)
  201 + - will be used to unprotect/erase the Flash area while updating
  202 + - default is CFG_ADNPESC1_NIOS_APPL_END
  203 +
  204 +4. appl_ident_addr
  205 +
  206 + - address of the Nios application identification string
  207 + - this is the address checked-up by autoboot
  208 + - default is CFG_ADNPESC1_NIOS_APPL_IDENT
  209 +
  210 +5. appl_ident_str
  211 +
  212 + - the Nios application identification string itself
  213 + - default is CFG_ADNPESC1_NIOS_IDENTIFIER
  214 +
  215 +6. appl_name
  216 +
  217 + - name of file we have to download/update
  218 + - default is ADNPESC1/base32/linux.bin
  219 +
  220 +7. fs_base_addr
  221 +
  222 + - optionally file system area start address (usually in Flash)
  223 + - each file system we want to update will be copied to this address
  224 + - default is CFG_ADNPESC1_FILESYSTEM_BASE
  225 +
  226 +8. fs_end_addr
  227 +
  228 + - optionally file system area end address (usually in Flash)
  229 + - will be used to unprotect/erase the Flash area while updating
  230 + - default is CFG_ADNPESC1_FILESYSTEM_END
  231 +
  232 +9. fs_name
  233 +
  234 + - name of file we have to download/update
  235 + - default is ADNPESC1/base32/romfs.img
doc/README.adnpesc1_base32
Diff comments   View file @ aaf224a
  1 +
  2 +TODO: specify IDE i/f
  3 +
  4 +
  5 +===============================================================================
  6 + C P U , M E M O R Y , I N / O U T C O M P O N E N T S
  7 +===============================================================================
  8 +see also [1]-[5]
  9 +
  10 +CPU: "DNP_ESC1"
  11 + 32 bit NIOS for 50 MHz
  12 + 512 Byte for register file (30 levels)
  13 + with out instruction cache
  14 + with out data cache
  15 + 2 KByte On Chip ROM with GERMS boot monitor
  16 + with out On Chip RAM
  17 + MSTEP multiplier
  18 + no Debug Core
  19 + no On Chip Instrumentation (OCI)
  20 +
  21 + U-Boot CFG: CFG_NIOS_CPU_CLK = 50000000
  22 + CFG_NIOS_CPU_ICACHE = (not present)
  23 + CFG_NIOS_CPU_DCACHE = (not present)
  24 + CFG_NIOS_CPU_REG_NUMS = 512
  25 + CFG_NIOS_CPU_MUL = 0
  26 + CFG_NIOS_CPU_MSTEP = 1
  27 + CFG_NIOS_CPU_DBG_CORE = 0
  28 +
  29 +IRQ: Nr. | used by
  30 + ------+--------------------------------------------------------
  31 + 16 | TIMER0 | CFG_NIOS_CPU_TIMER0_IRQ = 16
  32 + 17 | UART0 | CFG_NIOS_CPU_UART0_IRQ = 17
  33 + 18 | UART1 | CFG_NIOS_CPU_UART1_IRQ = 18
  34 + 20 | LAN91C111 | CFG_NIOS_CPU_LAN0_IRQ =
  35 + | PIO6 | CFG_NIOS_CPU_PIO6_IRQ = 20
  36 + 25 | SPI0 | CFG_NIOS_CPU_SPI0_IRQ = 25
  37 + 31 | PIO7 | CFG_NIOS_CPU_PIO7_IRQ = 31
  38 + 32 | PIO8 | CFG_NIOS_CPU_PIO8_IRQ = 32
  39 + 33 | PIO9 | CFG_NIOS_CPU_PIO9_IRQ = 33
  40 + 34 | PIO10 | CFG_NIOS_CPU_PIO10_IRQ = 34
  41 + 35 | PIO11 | CFG_NIOS_CPU_PIO11_IRQ = 35
  42 + 36 | PIO12 | CFG_NIOS_CPU_PIO12_IRQ =
  43 + | IDE0 | CFG_NIOS_CPU_IDE0_IRQ = 36
  44 + 37 | PIO13 | CFG_NIOS_CPU_PIO13_IRQ =
  45 + | IDE1 | CFG_NIOS_CPU_IDE1_IRQ = 37
  46 +
  47 +MEMORY: 8 MByte Flash
  48 + 16 MByte SDRAM
  49 +
  50 +Timer: TIMER0: high priority programmable timer (IRQ16)
  51 +
  52 + U-Boot CFG: CFG_NIOS_CPU_TICK_TIMER = 0
  53 + CFG_NIOS_CPU_USER_TIMER = (not present)
  54 +
  55 +PIO: Nr. | description
  56 + ------+--------------------------------------------------------
  57 + PIO0 | PORTA: 8 in/outputs for general purpose usage
  58 + PIO1 | PORTB: 8 in/outputs for general purpose usage
  59 + PIO2 | PORTC: 4 in/outputs for general purpose usage
  60 + PIO3 | RCM: 1 input for RCM_EN# jumper (Req.Conf.Mon.)
  61 + PIO4 | WDTENA: 1 output to enable the on-board watchdog
  62 + PIO5 | WDTTRIG: 1 output to trigger the on-board watchdog
  63 + PIO6 | LAN0INT: 1 input for LAN91C111 irq input (IRQ20)
  64 + PIO7 | INT1: 1 input for general purpose irq (IRQ31)
  65 + PIO8 | INT2: 1 input for general purpose irq (IRQ32)
  66 + PIO9 | INT3: 1 input for general purpose irq (IRQ33)
  67 + PIO10| INT4: 1 input for general purpose irq (IRQ34)
  68 + PIO11| INT5: 1 input for general purpose irq (IRQ35)
  69 + PIO12| INT6: 1 input for general purpose irq (IRQ36)
  70 + | IDE0INT: (same) for IDE0 irq input
  71 + PIO13| INT7: 1 input for general purpose irq (IRQ37)
  72 + | IDE1INT: (same) for IDE1 irq input
  73 +
  74 + U-Boot CFG: CFG_NIOS_CPU_PORTA_PIO = 0
  75 + CFG_NIOS_CPU_PORTB_PIO = 1
  76 + CFG_NIOS_CPU_PORTC_PIO = 2
  77 + CFG_NIOS_CPU_RCM_PIO = 3
  78 + CFG_NIOS_CPU_WDTENA_PIO = 4
  79 + CFG_NIOS_CPU_WDTTRIG_PIO = 5
  80 + CFG_NIOS_CPU_LED_PIO = (not present)
  81 +
  82 +UART: UART0: fixed baudrate of 115200, fixed protocol 8N1, RTS/CTS (IRQ17)
  83 + UART1: fixed baudrate of 115200, fixed protocol 8N1,
  84 + without handshake RTS/CTS (IRQ18)
  85 +
  86 +SPI: SPI0: master capable, 1 slave selectable, 250kHz target clock,
  87 + 2 usec targets delay between slave select and clock,
  88 + data is transferred MSB-first / LSB-last (IRQ25)
  89 +
  90 +LAN: SMsC LAN91C111 with:
  91 + - without offset
  92 + - data bus width 16 bit (on-board hard wired at 32 bit bus)
  93 + - !!! 32 bit bus access --> each address * 2 !!!
  94 +
  95 +IDE: (TODO)
  96 +
  97 +
  98 +===============================================================================
  99 + M E M O R Y M A P
  100 +===============================================================================
  101 +
  102 +- - - - - - - - - - - external extension - - - - - - - - - - - - - - - - - - -
  103 +
  104 + 0x44000000 ---32-----------16|15------------0-
  105 + | | | \
  106 + : (real size : : |
  107 + EXT3 (CS4) : and content : : > CFG_NIOS_CPU_CS3_SIZE
  108 + : unknown) : : | = 0x01000000
  109 + | | | /
  110 + 0x43000000 ---32-----------16|15------------0- CFG_NIOS_CPU_CS3_BASE
  111 + | | | \
  112 + : (real size : : |
  113 + EXT2 (CS3) : and content : : > CFG_NIOS_CPU_CS2_SIZE
  114 + : unknown) : : | = 0x01000000
  115 + | | | /
  116 + 0x42000000 ---32-----------16|15------------0- CFG_NIOS_CPU_CS2_BASE
  117 + | | | \
  118 + : (real size : : |
  119 + EXT1 (CS2) : and content : : > CFG_NIOS_CPU_CS1_SIZE
  120 + : unknown) : : | = 0x01000000
  121 + | | | /
  122 + 0x41000000 ---32-----------16|15------------0- CFG_NIOS_CPU_CS1_BASE
  123 + | | | \
  124 + : (real size : : |
  125 + EXT0 (CS1) : and content : : > CFG_NIOS_CPU_CS0_SIZE
  126 + : unknown) : : | = 0x01000000
  127 + | | | /
  128 + 0x40000000 ---32-----------16|15------------0- CFG_NIOS_CPU_CS0_BASE
  129 + | |
  130 + : gap :
  131 + : :
  132 +
  133 +- - - - - - - - - - - external memory - - - - - - - - - - - - - - - - - - -
  134 +
  135 + : :
  136 + : gap :
  137 + | |
  138 + 0x03000000 ---32-----------16|15------------0- CFG_NIOS_CPU_STACK
  139 + | . | \
  140 + | . | | (U-Boot run-time system)
  141 + | . | |
  142 + | . | > CFG_MONITOR_LEN
  143 + | . | | = 0x00040000
  144 + | . | |
  145 + | . | /
  146 + 0x02fc0000 --+32-----------16|15------------0+ TEXT_BASE
  147 + | . | \
  148 + | . | > CFG_MALLOC_LEN (heap)
  149 + | . | /
  150 + --+32-----------16|15------------0+
  151 + | . | \
  152 + | . | > CFG_GBL_DATA_SIZE (global)
  153 + | . | /
  154 + --+32-----------16|15------------0+ CFG_INIT_SP (u-boot stack)
  155 + | . | \ \
  156 + | . | | |
  157 + | . | | > stack area
  158 + | . | | |
  159 + | . | | V
  160 + | . | |
  161 + | . | |
  162 + SDRAM | . | > CFG_NIOS_CPU_SDRAM_SIZE
  163 + | . | | = 0x01000000
  164 + | . | |
  165 + 0x02000100 |- - - - - - - - - - - - - - - -+-|-
  166 + | . | | \
  167 + | . | | |
  168 + | . | | > CFG_NIOS_CPU_VEC_SIZE
  169 + | . | | | = 0x00000100
  170 + | | / /
  171 + 0x02000000 |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_VEC_BASE
  172 + 0x02000000 ---32-----------16|15------------0- CFG_NIOS_CPU_SDRAM_BASE
  173 + | | \
  174 + : gap : > (space for 2nd Flash)
  175 + | | /
  176 + 0x01800000 ---32-----------16|15------------0-
  177 + | sector 127 | \
  178 + + 0x7f0000 |- - - - - - - - - - - - - - - -| |
  179 + | : | |
  180 + Flash |- - - - : - - - -| > CFG_NIOS_CPU_FLASH_SIZE
  181 + | sector 1 : | | = 0x00800000
  182 + + 0x010000 |- - - - - - - - - - - - - - - -| |
  183 + | sector 0 (size = 0x10000) | /
  184 + 0x01000000 ---8-------------4|3-------------0- CFG_NIOS_CPU_FLASH_BASE
  185 + | |
  186 + : gap :
  187 + : :
  188 +
  189 +- - - - - - - - - - - external i/o - - - - - - - - - - - - - - - - - - -
  190 +
  191 + : :
  192 + : gap :
  193 + | |
  194 + 0x00010020 ---32-----------16|15------------0-
  195 + | | \
  196 + | register bank | |
  197 + | size = (real_size << 1) | |
  198 + | real_size = 0x10 | |
  199 + | +--------.---.---.--- | |
  200 + | | bank 0 \ 1 \ 2 \ 3 \ | |
  201 + | |---------------------------+ | |
  202 + LAN91C111 | | BANK | RESERVED | | > na_enet_size
  203 + | |- - - - - - -|- - - - - - -| | | = 0x00000020
  204 + | | RPCR | MIR | | |
  205 + | |- - - - - - -|- - - - - - -| | |
  206 + | | COUNTER | RCR | | |
  207 + | |- - - - - - -|- - - - - - -| | |
  208 + | | EPH STATUS | TCR | | |
  209 + | +---------------------------+ | /
  210 + 0x00010000 ---32-----------16|15------------0- CFG_NIOS_CPU_LAN0_BASE
  211 + | |
  212 + : gap :
  213 + : :
  214 +
  215 +- - - - - - - - - - - on chip i/o - - - - - - - - - - - - - - - - - - -
  216 +
  217 + : :
  218 + : gap :
  219 + | |
  220 + 0x00001040 ---32-----------16|15------------0-
  221 + | | | \
  222 + : : : |
  223 + IDE1 i/f : : : > 0x00000020
  224 + [5] : : : |
  225 + | | | /
  226 + 0x00001020 ---32-----------16|15------------0- CFG_NIOS_CPU_IDE1
  227 + | | | \
  228 + : : : |
  229 + IDE0 i/f : : : > 0x00000020
  230 + [5] : : : |
  231 + | | | /
  232 + 0x00001000 ---32-----------16|15------------0- CFG_NIOS_CPU_IDE0
  233 + | |
  234 + : gap :
  235 + | |
  236 + 0x00000980 ---32-----------16|15------------0-
  237 + | edgecapture (1 bit) (rw) | \
  238 + + 0x0c |- - - - - - - - - - - - - - - -| |
  239 + PIO13 | interruptmask (1 bit) (rw) | |
  240 + [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
  241 + | (unused) | |
  242 + + 0x04 |- - - - - - - - - - - - - - - -| |
  243 + | data (1 bit) (ro) | /
  244 + 0x00000970 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO13
  245 + | edgecapture (1 bit) (rw) | \
  246 + + 0x0c |- - - - - - - - - - - - - - - -| |
  247 + PIO12 | interruptmask (1 bit) (rw) | |
  248 + [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
  249 + | (unused) | |
  250 + + 0x04 |- - - - - - - - - - - - - - - -| |
  251 + | data (1 bit) (ro) | /
  252 + 0x00000960 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO12
  253 + | edgecapture (1 bit) (rw) | \
  254 + + 0x0c |- - - - - - - - - - - - - - - -| |
  255 + PIO11 | interruptmask (1 bit) (rw) | |
  256 + [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
  257 + | (unused) | |
  258 + + 0x04 |- - - - - - - - - - - - - - - -| |
  259 + | data (1 bit) (ro) | /
  260 + 0x00000950 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO11
  261 + | edgecapture (1 bit) (rw) | \
  262 + + 0x0c |- - - - - - - - - - - - - - - -| |
  263 + PIO10 | interruptmask (1 bit) (rw) | |
  264 + [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
  265 + | (unused) | |
  266 + + 0x04 |- - - - - - - - - - - - - - - -| |
  267 + | data (1 bit) (ro) | /
  268 + 0x00000940 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO10
  269 + | edgecapture (1 bit) (rw) | \
  270 + + 0x0c |- - - - - - - - - - - - - - - -| |
  271 + PIO9 | interruptmask (1 bit) (rw) | |
  272 + [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
  273 + | (unused) | |
  274 + + 0x04 |- - - - - - - - - - - - - - - -| |
  275 + | data (1 bit) (ro) | /
  276 + 0x00000930 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO9
  277 + | edgecapture (1 bit) (rw) | \
  278 + + 0x0c |- - - - - - - - - - - - - - - -| |
  279 + PIO8 | interruptmask (1 bit) (rw) | |
  280 + [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
  281 + | (unused) | |
  282 + + 0x04 |- - - - - - - - - - - - - - - -| |
  283 + | data (1 bit) (ro) | /
  284 + 0x00000920 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO8
  285 + | edgecapture (1 bit) (rw) | \
  286 + + 0x0c |- - - - - - - - - - - - - - - -| |
  287 + PIO7 | interruptmask (1 bit) (rw) | |
  288 + [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
  289 + | (unused) | |
  290 + + 0x04 |- - - - - - - - - - - - - - - -| |
  291 + | data (1 bit) (ro) | /
  292 + 0x00000910 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO7
  293 + | edgecapture (1 bit) (rw) | \
  294 + + 0x0c |- - - - - - - - - - - - - - - -| |
  295 + PIO6 | interruptmask (1 bit) (rw) | |
  296 + [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
  297 + | (unused) | |
  298 + + 0x04 |- - - - - - - - - - - - - - - -| |
  299 + | data (1 bit) (ro) | /
  300 + 0x00000900 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO6
  301 + | |
  302 + : gap :
  303 + | |
  304 + 0x000008e0 ---32-----------16|15------------0-
  305 + | (unused) | \
  306 + + 0x1c |- - - - - - - - - - - - - - - -| |
  307 + | endofpacket (16 bit) (rw) | |
  308 + + 0x18 |- - - - - - - - - - - - - - - -| |
  309 + | slaveselect (1 bit) (rw) | |
  310 + + 0x14 |- - - - - - - - - - - - - - - -| |
  311 + SPI0 | (reserved) | |
  312 + [4] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020
  313 + | control (11 bit) (rw) | |
  314 + + 0x0c |- - - - - - - - - - - - - - - -| |
  315 + | status (9 bit) (rw) | |
  316 + + 0x08 |- - - - - - - - - - - - - - - -| |
  317 + | txdata (16 bit) (wo) | |
  318 + + 0x04 |- - - - - - - - - - - - - - - -| |
  319 + | rxdata (16 bit) (ro) | /
  320 + 0x000008c0 ---32-----------16|15------------0- CFG_NIOS_CPU_SPI0
  321 + | (unused) | \
  322 + + 0x0c |- - - - - - - - - - - - - - - -| |
  323 + PIO5 | (unused) | |
  324 + [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
  325 + | (unused) | |
  326 + + 0x04 |- - - - - - - - - - - - - - - -| |
  327 + | data (1 bit) (wo) | /
  328 + 0x000008b0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO5
  329 + | (unused) | \
  330 + + 0x0c |- - - - - - - - - - - - - - - -| |
  331 + PIO4 | (unused) | |
  332 + [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
  333 + | (unused) | |
  334 + + 0x04 |- - - - - - - - - - - - - - - -| |
  335 + | data (1 bit) (wo) | /
  336 + 0x000008a0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO4
  337 + | (unused) | \
  338 + + 0x0c |- - - - - - - - - - - - - - - -| |
  339 + PIO3 | (unused) | |
  340 + [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
  341 + | (unused) | |
  342 + + 0x04 |- - - - - - - - - - - - - - - -| |
  343 + | data (1 bit) (ro) | /
  344 + 0x00000890 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO3
  345 + | (unused) | \
  346 + + 0x0c |- - - - - - - - - - - - - - - -| |
  347 + PIO2 | (unused) | |
  348 + [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
  349 + | direction (4 bit) (rw) | |
  350 + + 0x04 |- - - - - - - - - - - - - - - -| |
  351 + | data (4 bit) (rw) | /
  352 + 0x00000880 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO2
  353 + | (unused) | \
  354 + + 0x0c |- - - - - - - - - - - - - - - -| |
  355 + PIO1 | (unused) | |
  356 + [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
  357 + | direction (8 bit) (rw) | |
  358 + + 0x04 |- - - - - - - - - - - - - - - -| |
  359 + | data (8 bit) (rw) | /
  360 + 0x00000870 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO1
  361 + | (unused) | \
  362 + + 0x0c |- - - - - - - - - - - - - - - -| |
  363 + PIO0 | (unused) | |
  364 + [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
  365 + | direction (8 bit) (rw) | |
  366 + + 0x04 |- - - - - - - - - - - - - - - -| |
  367 + | data (8 bit) (rw) | /
  368 + 0x00000860 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO0
  369 + | (unused) | \
  370 + + 0x1c |- - - - - - - - - - - - - - - -| |
  371 + | (unused) | |
  372 + + 0x18 |- - - - - - - - - - - - - - - -| |
  373 + | snaph (16 bit) (rw) | |
  374 + + 0x14 |- - - - - - - - - - - - - - - -| |
  375 + TIMER0 | snapl (16 bit) (rw) | |
  376 + [2] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020
  377 + | periodh (16 bit) (rw) | |
  378 + + 0x0c |- - - - - - - - - - - - - - - -| |
  379 + | periodl (16 bit) (rw) | |
  380 + + 0x08 |- - - - - - - - - - - - - - - -| |
  381 + | control (4 bit) (rw) | |
  382 + + 0x04 |- - - - - - - - - - - - - - - -| |
  383 + | status (2 bit) (rw) | /
  384 + 0x00000840 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER0
  385 + | (unused) | \
  386 + + 0x1c |- - - - - - - - - - - - - - - -| |
  387 + | (unused) | |
  388 + + 0x18 |- - - - - - - - - - - - - - - -| |
  389 + | (unused) | |
  390 + + 0x14 |- - - - - - - - - - - - - - - -| |
  391 + UART1 | (unused) | > 0x00000020
  392 + [1] + 0x10 |- - - - - - - - - - - - - - - -| |
  393 + | control (10 bit) (rw) | |
  394 + + 0x0c |- - - - - - - - - - - - - - - -| |
  395 + | status (10 bit) (rw) | |
  396 + + 0x08 |- - - - - - - - - - - - - - - -| |
  397 + | txdata (8 bit) (wo) | |
  398 + + 0x04 |- - - - - - - - - - - - - - - -| |
  399 + | rxdata (8 bit) (ro) | /
  400 + 0x00000820 ---32-----------16|15------------0- CFG_NIOS_CPU_UART1
  401 + | (unused) | \
  402 + + 0x1c |- - - - - - - - - - - - - - - -| |
  403 + | (unused) | |
  404 + + 0x18 |- - - - - - - - - - - - - - - -| |
  405 + | (unused) | |
  406 + + 0x14 |- - - - - - - - - - - - - - - -| |
  407 + UART0 | (unused) | > 0x00000020
  408 + [1] + 0x10 |- - - - - - - - - - - - - - - -| |
  409 + | control (10 bit) (rw) | |
  410 + + 0x0c |- - - - - - - - - - - - - - - -| |
  411 + | status (10 bit) (rw) | |
  412 + + 0x08 |- - - - - - - - - - - - - - - -| |
  413 + | txdata (8 bit) (wo) | |
  414 + + 0x04 |- - - - - - - - - - - - - - - -| |
  415 + | rxdata (8 bit) (ro) | /
  416 + 0x00000800 ---32-----------16|15------------0- CFG_NIOS_CPU_UART0
  417 +
  418 +- - - - - - - - - - - on chip memory 1 - - - - - - - - - - -
  419 +
  420 + 0x00000800 ---32-----------16|15------------0-
  421 + | : | \
  422 + | : | |
  423 + GERMS | : | > CFG_NIOS_CPU_ROM_SIZE
  424 + | : | | = 0x00000800
  425 + | : | /
  426 + 0x00000000 |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_RST_VECT
  427 + 0x00000000 ---32-----------16|15------------0- CFG_NIOS_CPU_ROM_BASE
  428 +
  429 +
  430 +===============================================================================
  431 + F L A S H M E M O R Y A L L O C A T I O N
  432 +===============================================================================
  433 +
  434 + 0x01800000 ---8-------------4|3-------------0-
  435 + | : | \
  436 + | : | |
  437 + | : | > 6 MByte ROM FS
  438 + | : | |
  439 + | : | /
  440 + 0x01200000 --+- - - - - - - -:- - - - - - - -+- - file system image(s)
  441 + | : | \
  442 + | : | |
  443 + | : | > 1728 kByte ucLinux
  444 + | : | |
  445 + | : | /
  446 + 0x01050000 --+- - - - - - - -:- - - - - - - -+- - os image(s)
  447 + | : | \
  448 + 0x01040000 --+- - - - - - - -:- - - - - - - -+-|- u-boot environment
  449 + | : | |
  450 + | : | > 320 kByte U-Boot
  451 + | : | |
  452 + | : | |
  453 + | : | /
  454 + 0x01000000 --+- - - - - - - -:- - - - - - - -+- - u-boot _start()
  455 + 0x01000000 ---8-------------4|3-------------0-
  456 +
  457 +
  458 +===============================================================================
  459 + R E F E R E N C E S
  460 +===============================================================================
  461 +[1] http://www.altera.com/literature/ds/ds_nios_uart.pdf
  462 +[2] http://www.altera.com/literature/ds/ds_nios_timer.pdf
  463 +[3] http://www.altera.com/literature/ds/ds_nios_pio.pdf
  464 +[4] http://www.altera.com/literature/ds/ds_nios_spi.pdf
  465 +[5] http://www.t13.org/index.html
  466 +
  467 +
  468 +===============================================================================
  469 +Stephan Linz <linz@li-pro.net>
... ... @@ -143,10 +143,18 @@
143 143 * We have only 16 Bit PCMCIA access on Socket 0
144 144 */
145 145  
  146 +#ifdef CONFIG_ADNPESC1
  147 +#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1))))
  148 +#else
146 149 #define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))))
  150 +#endif
147 151 #define SMC_inb(r) (((r)&1) ? SMC_inw((r)&~1)>>8 : SMC_inw(r)&0xFF)
148 152  
  153 +#ifdef CONFIG_ADNPESC1
  154 +#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1))) = d)
  155 +#else
149 156 #define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d)
  157 +#endif
150 158 #define SMC_outb(d,r) ({ word __d = (byte)(d); \
151 159 word __w = SMC_inw((r)&~1); \
152 160 __w &= ((r)&1) ? 0x00FF : 0xFF00; \
... ... @@ -308,6 +316,11 @@
308 316 #define RPC_LED_RX (0x07) /* LED = RX packet occurred */
309 317 #if defined(CONFIG_DK1C20) || defined(CONFIG_DK1S10)
310 318 /* buggy schematic: LEDa -> yellow, LEDb --> green */
  319 +#define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \
  320 + | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \
  321 + | (RPC_LED_100_10 << RPC_LSXB_SHFT) )
  322 +#elif defined(CONFIG_ADNPESC1)
  323 +/* SSV ADNP/ESC1 has only one LED: LEDa -> Rx/Tx indicator */
311 324 #define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \
312 325 | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \
313 326 | (RPC_LED_100_10 << RPC_LSXB_SHFT) )
include/configs/ADNPESC1.h
Diff comments   View file @ aaf224a
  1 +/*
  2 + * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
  3 + * Stephan Linz <linz@li-pro.net>
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#ifndef __CONFIG_H
  25 +#define __CONFIG_H
  26 +
  27 +/***********************************************************************
  28 + * Include the whole NIOS CPU configuration.
  29 + *
  30 + * !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!!
  31 + *
  32 + ***********************************************************************/
  33 +
  34 +#if defined(CONFIG_NIOS_BASE_32)
  35 +#include <configs/ADNPESC1_base_32.h>
  36 +#else
  37 +#error *** CFG_ERROR: you have to setup right NIOS CPU configuration
  38 +#endif
  39 +
  40 +/*------------------------------------------------------------------------
  41 + * BOARD/CPU -- TOP-LEVEL
  42 + *----------------------------------------------------------------------*/
  43 +#define CONFIG_NIOS 1 /* NIOS-32 core */
  44 +#define CONFIG_ADNPESC1 1 /* SSV ADNP/ESC1 board */
  45 +#define CONFIG_SYS_CLK_FREQ CFG_NIOS_CPU_CLK/* 50 MHz core clock */
  46 +#define CFG_HZ 1000 /* 1 msec time tick */
  47 +#undef CFG_CLKS_IN_HZ
  48 +#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/
  49 +
  50 +/*------------------------------------------------------------------------
  51 + * BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM)
  52 + *----------------------------------------------------------------------*/
  53 +#if (CFG_NIOS_CPU_SDRAM_SIZE != 0)
  54 +
  55 +#define CFG_SDRAM_BASE CFG_NIOS_CPU_SDRAM_BASE
  56 +#define CFG_SDRAM_SIZE CFG_NIOS_CPU_SDRAM_SIZE
  57 +
  58 +#else
  59 +#error *** CFG_ERROR: you have to setup any SDRAM in NIOS CPU config
  60 +#endif
  61 +
  62 +#if defined(CFG_NIOS_CPU_SRAM_BASE) && defined(CFG_NIOS_CPU_SRAM_SIZE)
  63 +
  64 +#define CFG_SRAM_BASE CFG_NIOS_CPU_SRAM_BASE
  65 +#define CFG_SRAM_SIZE CFG_NIOS_CPU_SRAM_SIZE
  66 +
  67 +#else
  68 +
  69 +#undef CFG_SRAM_BASE
  70 +#undef CFG_SRAM_SIZE
  71 +
  72 +#endif
  73 +
  74 +#define CFG_VECT_BASE CFG_NIOS_CPU_VEC_BASE
  75 +
  76 +/*------------------------------------------------------------------------
  77 + * MEMORY ORGANIZATION - For the most part, you can put things pretty
  78 + * much anywhere. This is pretty flexible for Nios. So here we make some
  79 + * arbitrary choices & assume that the monitor is placed at the end of
  80 + * a memory resource (so you must make sure TEXT_BASE is chosen
  81 + * appropriately -- this is very important if you plan to move your
  82 + * memory to another place as configured at this time !!!).
  83 + *
  84 + * -The heap is placed below the monitor.
  85 + * -Global data is placed below the heap.
  86 + * -The stack is placed below global data (&grows down).
  87 + *----------------------------------------------------------------------*/
  88 +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256k */
  89 +#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/
  90 +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
  91 +
  92 +#define CFG_MONITOR_BASE TEXT_BASE
  93 +#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
  94 +#define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
  95 +#define CFG_INIT_SP CFG_GBL_DATA_OFFSET
  96 +
  97 +/*------------------------------------------------------------------------
  98 + * FLASH (AM29LV065D)
  99 + *----------------------------------------------------------------------*/
  100 +#if (CFG_NIOS_CPU_FLASH_SIZE != 0)
  101 +
  102 +#define CFG_FLASH_BASE CFG_NIOS_CPU_FLASH_BASE
  103 +#define CFG_FLASH_SIZE CFG_NIOS_CPU_FLASH_SIZE
  104 +#define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */
  105 +#define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */
  106 +#define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */
  107 +#define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */
  108 +#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size */
  109 +
  110 +#else
  111 +#error *** CFG_ERROR: you have to setup any Flash memory in NIOS CPU config
  112 +#endif
  113 +
  114 +/*------------------------------------------------------------------------
  115 + * ENVIRONMENT
  116 + *----------------------------------------------------------------------*/
  117 +#if (CFG_NIOS_CPU_FLASH_SIZE != 0)
  118 +
  119 +#define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */
  120 +
  121 +/* Mem addr of environment */
  122 +#if defined(CONFIG_NIOS_BASE_32)
  123 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN)
  124 +#else
  125 +#error *** CFG_ERROR: you have to setup the environment base address CFG_ENV_ADDR
  126 +#endif
  127 +
  128 +#define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */
  129 +#define CONFIG_ENV_OVERWRITE /* Serial/eth change Ok */
  130 +
  131 +#else
  132 +#define CFG_ENV_IS_NOWHERE 1 /* NO Environment */
  133 +#endif
  134 +
  135 +/*------------------------------------------------------------------------
  136 + * NIOS APPLICATION CODE BASE AREA
  137 + *----------------------------------------------------------------------*/
  138 +#if ((CFG_ENV_ADDR + CFG_ENV_SIZE) == 0x1050000)
  139 +#define CFG_ADNPESC1_UPDATE_LOAD_ADDR "0x2000100"
  140 +#define CFG_ADNPESC1_NIOS_APPL_ENTRY "0x1050000"
  141 +#define CFG_ADNPESC1_NIOS_APPL_IDENT "0x105000c"
  142 +#define CFG_ADNPESC1_NIOS_APPL_END "0x11fffff"
  143 +#define CFG_ADNPESC1_FILESYSTEM_BASE "0x1200000"
  144 +#define CFG_ADNPESC1_FILESYSTEM_END "0x17fffff"
  145 +#else
  146 +#error *** CFG_ERROR: missing right appl.code base configuration, expand your config.h
  147 +#endif
  148 +#define CFG_ADNPESC1_NIOS_IDENTIFIER "Nios"
  149 +
  150 +/*------------------------------------------------------------------------
  151 + * BOOT ENVIRONMENT
  152 + *----------------------------------------------------------------------*/
  153 +#ifdef CONFIG_DNPEVA2 /* DNP/EVA2 base board */
  154 +#define CFG_ADNPESC1_SLED_BOOT_OFF "sled boot off; "
  155 +#define CFG_ADNPESC1_SLED_RED_BLINK "sled red blink; "
  156 +#else
  157 +#define CFG_ADNPESC1_SLED_BOOT_OFF
  158 +#define CFG_ADNPESC1_SLED_RED_BLINK
  159 +#endif
  160 +
  161 +#define CONFIG_BOOTDELAY 5
  162 +#define CONFIG_BOOTCOMMAND \
  163 + "if itest.s *$appl_ident_addr == \"$appl_ident_str\"; " \
  164 + "then " \
  165 + "wd off; " \
  166 + CFG_ADNPESC1_SLED_BOOT_OFF \
  167 + "go $appl_entry_addr; " \
  168 + "else " \
  169 + CFG_ADNPESC1_SLED_RED_BLINK \
  170 + "echo *** missing \"$appl_ident_str\" at $appl_ident_addr; "\
  171 + "echo *** invalid application at $appl_entry_addr; " \
  172 + "echo *** stop bootup...; " \
  173 + "fi"
  174 +
  175 +/*------------------------------------------------------------------------
  176 + * EXTRA ENVIRONMENT
  177 + *----------------------------------------------------------------------*/
  178 +#ifdef CONFIG_DNPEVA2 /* DNP/EVA2 base board */
  179 +#define CFG_ADNPESC1_SLED_YELLO_ON "sled yellow on; "
  180 +#define CFG_ADNPESC1_SLED_YELLO_OFF "sled yellow off; "
  181 +#else
  182 +#define CFG_ADNPESC1_SLED_YELLO_ON
  183 +#define CFG_ADNPESC1_SLED_YELLO_OFF
  184 +#endif
  185 +
  186 +#define CONFIG_EXTRA_ENV_SETTINGS \
  187 + "update_allowed=0\0" \
  188 + "update_load_addr=" CFG_ADNPESC1_UPDATE_LOAD_ADDR "\0" \
  189 + "appl_entry_addr=" CFG_ADNPESC1_NIOS_APPL_ENTRY "\0" \
  190 + "appl_end_addr=" CFG_ADNPESC1_NIOS_APPL_END "\0" \
  191 + "appl_ident_addr=" CFG_ADNPESC1_NIOS_APPL_IDENT "\0" \
  192 + "appl_ident_str=" CFG_ADNPESC1_NIOS_IDENTIFIER "\0" \
  193 + "appl_name=ADNPESC1/base32/linux.bin\0" \
  194 + "appl_update=" \
  195 + "if itest.b $update_allowed != 0; " \
  196 + "then " \
  197 + CFG_ADNPESC1_SLED_YELLO_ON \
  198 + "tftp $update_load_addr $appl_name; " \
  199 + "protect off $appl_entry_addr $appl_end_addr; " \
  200 + "era $appl_entry_addr $appl_end_addr; " \
  201 + "cp.b $update_load_addr $appl_entry_addr $filesize; "\
  202 + CFG_ADNPESC1_SLED_YELLO_OFF \
  203 + "else " \
  204 + "echo *** update not allowed (update_allowed=$update_allowed); "\
  205 + "fi\0" \
  206 + "fs_base_addr=" CFG_ADNPESC1_FILESYSTEM_BASE "\0" \
  207 + "fs_end_addr=" CFG_ADNPESC1_FILESYSTEM_END "\0" \
  208 + "fs_name=ADNPESC1/base32/romfs.img\0" \
  209 + "fs_update=" \
  210 + "if itest.b $update_allowed != 0; " \
  211 + "then " \
  212 + CFG_ADNPESC1_SLED_YELLO_ON \
  213 + "tftp $update_load_addr $fs_name; " \
  214 + "protect off $fs_base_addr $fs_end_addr; " \
  215 + "era $fs_base_addr $fs_end_addr; " \
  216 + "cp.b $update_load_addr $fs_base_addr $filesize; "\
  217 + CFG_ADNPESC1_SLED_YELLO_OFF \
  218 + "else " \
  219 + "echo *** update not allowed (update_allowed=$update_allowed); "\
  220 + "fi\0" \
  221 + "uboot_name=ADNPESC1/base32/u-boot.bin\0" \
  222 + "uboot_loadnrun=" \
  223 + "if ping $serverip; " \
  224 + "then " \
  225 + CFG_ADNPESC1_SLED_YELLO_ON \
  226 + "tftp $update_load_addr $uboot_name; " \
  227 + "wd off; " \
  228 + "go $update_load_addr; " \
  229 + "else " \
  230 + "echo *** missing connection to $serverip; " \
  231 + "echo *** check your network and try again...; "\
  232 + "fi\0"
  233 +
  234 +/*------------------------------------------------------------------------
  235 + * CONSOLE
  236 + *----------------------------------------------------------------------*/
  237 +#if (CFG_NIOS_CPU_UART_NUMS != 0)
  238 +
  239 +#define CFG_NIOS_CONSOLE CFG_NIOS_CPU_UART0 /* 1st UART is Cons. */
  240 +
  241 +#if (CFG_NIOS_CPU_UART0_BR != 0)
  242 +#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */
  243 +#define CONFIG_BAUDRATE CFG_NIOS_CPU_UART0_BR
  244 +#else
  245 +#undef CFG_NIOS_FIXEDBAUD
  246 +#define CONFIG_BAUDRATE 115200
  247 +#endif
  248 +
  249 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  250 +
  251 +#else
  252 +#error *** CFG_ERROR: you have to setup at least one UART in NIOS CPU config
  253 +#endif
  254 +
  255 +/*------------------------------------------------------------------------
  256 + * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc PIT,
  257 + * so an avalon bus timer is required.
  258 + *----------------------------------------------------------------------*/
  259 +#if (CFG_NIOS_CPU_TIMER_NUMS != 0) && defined(CFG_NIOS_CPU_TICK_TIMER)
  260 +
  261 +#if (CFG_NIOS_CPU_TICK_TIMER == 0)
  262 +
  263 +#define CFG_NIOS_TMRBASE CFG_NIOS_CPU_TIMER0 /* TIMER0 as tick */
  264 +#define CFG_NIOS_TMRIRQ CFG_NIOS_CPU_TIMER0_IRQ
  265 +
  266 +#if (CFG_NIOS_CPU_TIMER0_FP == 1) /* fixed period */
  267 +
  268 +#if (CFG_NIOS_CPU_TIMER0_PER >= CFG_HZ)
  269 +#define CFG_NIOS_TMRMS (CFG_NIOS_CPU_TIMER0_PER / CFG_HZ)
  270 +#else
  271 +#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
  272 +#endif
  273 +
  274 +#undef CFG_NIOS_TMRCNT /* no preloadable counter value */
  275 +
  276 +#elif (CFG_NIOS_CPU_TIMER0_FP == 0) /* variable period */
  277 +
  278 +#if (CFG_HZ <= 1000)
  279 +#define CFG_NIOS_TMRMS (1000 / CFG_HZ)
  280 +#else
  281 +#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
  282 +#endif
  283 +
  284 +#define CFG_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CFG_HZ)
  285 +
  286 +#else
  287 +#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER0_FP correct
  288 +#endif
  289 +
  290 +#elif (CFG_NIOS_CPU_TICK_TIMER == 1)
  291 +
  292 +#define CFG_NIOS_TMRBASE CFG_NIOS_CPU_TIMER1 /* TIMER1 as tick */
  293 +#define CFG_NIOS_TMRIRQ CFG_NIOS_CPU_TIMER1_IRQ
  294 +
  295 +#if (CFG_NIOS_CPU_TIMER1_FP == 1) /* fixed period */
  296 +
  297 +#if (CFG_NIOS_CPU_TIMER1_PER >= CFG_HZ)
  298 +#define CFG_NIOS_TMRMS (CFG_NIOS_CPU_TIMER1_PER / CFG_HZ)
  299 +#else
  300 +#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
  301 +#endif
  302 +
  303 +#undef CFG_NIOS_TMRCNT /* no preloadable counter value */
  304 +
  305 +#elif (CFG_NIOS_CPU_TIMER1_FP == 0) /* variable period */
  306 +
  307 +#if (CFG_HZ <= 1000)
  308 +#define CFG_NIOS_TMRMS (1000 / CFG_HZ)
  309 +#else
  310 +#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
  311 +#endif
  312 +
  313 +#define CFG_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CFG_HZ)
  314 +
  315 +#else
  316 +#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER1_FP correct
  317 +#endif
  318 +
  319 +#endif /* CFG_NIOS_CPU_TICK_TIMER */
  320 +
  321 +#else
  322 +#error *** CFG_ERROR: you have to setup at least one TIMER in NIOS CPU config
  323 +#endif
  324 +
  325 +/*------------------------------------------------------------------------
  326 + * WATCHDOG (or better MAX823 supervisory circuite access)
  327 + *----------------------------------------------------------------------*/
  328 +#define CONFIG_HW_WATCHDOG 1 /* board specific WD */
  329 +
  330 +#ifdef CONFIG_HW_WATCHDOG
  331 +
  332 +/* MAX823 supervisor -- watchdog enable port at: */
  333 +#if (CFG_NIOS_CPU_WDENA_PIO == 0)
  334 +#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO0 /* PIO0 */
  335 +#elif (CFG_NIOS_CPU_WDENA_PIO == 1)
  336 +#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO1 /* PIO1 */
  337 +#elif (CFG_NIOS_CPU_WDENA_PIO == 2)
  338 +#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO2 /* PIO2 */
  339 +#elif (CFG_NIOS_CPU_WDENA_PIO == 3)
  340 +#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO3 /* PIO3 */
  341 +#elif (CFG_NIOS_CPU_WDENA_PIO == 4)
  342 +#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO4 /* PIO4 */
  343 +#elif (CFG_NIOS_CPU_WDENA_PIO == 5)
  344 +#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO5 /* PIO5 */
  345 +#elif (CFG_NIOS_CPU_WDENA_PIO == 6)
  346 +#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO6 /* PIO6 */
  347 +#elif (CFG_NIOS_CPU_WDENA_PIO == 7)
  348 +#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO7 /* PIO7 */
  349 +#elif (CFG_NIOS_CPU_WDENA_PIO == 8)
  350 +#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO8 /* PIO8 */
  351 +#elif (CFG_NIOS_CPU_WDENA_PIO == 9)
  352 +#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO9 /* PIO9 */
  353 +#else
  354 +#error *** CFG_ERROR: you have to setup at least one WDENA_PIO in NIOS CPU config
  355 +#endif
  356 +
  357 +/* MAX823 supervisor -- watchdog trigger port at: */
  358 +#if (CFG_NIOS_CPU_WDTOG_PIO == 0)
  359 +#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO0 /* PIO0 */
  360 +#elif (CFG_NIOS_CPU_WDTOG_PIO == 1)
  361 +#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO1 /* PIO1 */
  362 +#elif (CFG_NIOS_CPU_WDTOG_PIO == 2)
  363 +#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO2 /* PIO2 */
  364 +#elif (CFG_NIOS_CPU_WDTOG_PIO == 3)
  365 +#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO3 /* PIO3 */
  366 +#elif (CFG_NIOS_CPU_WDTOG_PIO == 4)
  367 +#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO4 /* PIO4 */
  368 +#elif (CFG_NIOS_CPU_WDTOG_PIO == 5)
  369 +#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO5 /* PIO5 */
  370 +#elif (CFG_NIOS_CPU_WDTOG_PIO == 6)
  371 +#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO6 /* PIO6 */
  372 +#elif (CFG_NIOS_CPU_WDTOG_PIO == 7)
  373 +#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO7 /* PIO7 */
  374 +#elif (CFG_NIOS_CPU_WDTOG_PIO == 8)
  375 +#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO8 /* PIO8 */
  376 +#elif (CFG_NIOS_CPU_WDTOG_PIO == 9)
  377 +#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO9 /* PIO9 */
  378 +#else
  379 +#error *** CFG_ERROR: you have to setup at least one WDTOG_PIO in NIOS CPU config
  380 +#endif
  381 +
  382 +#if defined(CONFIG_NIOS_BASE_32) /* NIOS CPU specifics */
  383 +#define CONFIG_HW_WDENA_BIT 0 /* WD enable @ Bit 0 */
  384 +#define CONFIG_HW_WDTOG_BIT 0 /* WD trigger @ Bit 0 */
  385 +#define CONFIG_HW_WDPORT_WRONLY 1 /* each WD port wr/only*/
  386 +#else
  387 +#error *** CFG_ERROR: missing watchdog bit configuration, expand your config.h
  388 +#endif
  389 +
  390 +#endif /* CONFIG_HW_WATCHDOG */
  391 +
  392 +/*------------------------------------------------------------------------
  393 + * SERIAL PERIPHAREL INTERFACE
  394 + *----------------------------------------------------------------------*/
  395 +#if (CFG_NIOS_CPU_SPI_NUMS == 1)
  396 +
  397 +#define CONFIG_NIOS_SPI 1 /* SPI support active */
  398 +#define CFG_NIOS_SPIBASE CFG_NIOS_CPU_SPI0
  399 +#define CFG_NIOS_SPIBITS CFG_NIOS_CPU_SPI0_BITS
  400 +
  401 +#define CONFIG_RTC_DS1306 1 /* Dallas 1306 real time clock */
  402 +#define CFG_SPI_RTC_DEVID 0 /* as 1st SPI device */
  403 +
  404 +#define __SPI_CMD_OFF 0 /* allow default commands: */
  405 + /* CFG_CMD_SPI */
  406 + /* CFG_CMD_DATE */
  407 +
  408 +#else
  409 +#undef CONFIG_NIOS_SPI /* NO SPI support */
  410 +#define __SPI_CMD_OFF ( CFG_CMD_SPI \
  411 + | CFG_CMD_DATE \
  412 + )
  413 +#endif
  414 +
  415 +/*------------------------------------------------------------------------
  416 + * Ethernet -- needs work!
  417 + *----------------------------------------------------------------------*/
  418 +#if (CFG_NIOS_CPU_LAN_NUMS == 1)
  419 +
  420 +#if (CFG_NIOS_CPU_LAN0_TYPE == 0) /* LAN91C111 */
  421 +
  422 +#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */
  423 +#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
  424 +#define CONFIG_SMC91111_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
  425 +
  426 +#if (CFG_NIOS_CPU_LAN0_BUSW == 32)
  427 +#define CONFIG_SMC_USE_32_BIT 1
  428 +#else /* no */
  429 +#undef CONFIG_SMC_USE_32_BIT
  430 +#endif
  431 +
  432 +#elif (CFG_NIOS_CPU_LAN0_TYPE == 1) /* CS8900A */
  433 +
  434 + /********************************************/
  435 + /* !!! CS8900 is __not__ tested on NIOS !!! */
  436 + /********************************************/
  437 +#define CONFIG_DRIVER_CS8900 /* Using CS8900 */
  438 +#define CS8900_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
  439 +
  440 +#if (CFG_NIOS_CPU_LAN0_BUSW == 32)
  441 +#undef CS8900_BUS16
  442 +#define CS8900_BUS32 1
  443 +#else /* no */
  444 +#define CS8900_BUS16 1
  445 +#undef CS8900_BUS32
  446 +#endif
  447 +
  448 +#else
  449 +#error *** CFG_ERROR: invalid LAN0 chip type, check your NIOS CPU config
  450 +#endif
  451 +
  452 +#define CONFIG_ETHADDR 02:80:ae:20:60:6f
  453 +#define CONFIG_NETMASK 255.255.255.248
  454 +#define CONFIG_IPADDR 192.168.161.84
  455 +#define CONFIG_SERVERIP 192.168.161.85
  456 +
  457 +#else
  458 +#error *** CFG_ERROR: you have to setup just one LAN only or expand your config.h
  459 +#endif
  460 +
  461 +/*------------------------------------------------------------------------
  462 + * STATUS LEDs
  463 + *----------------------------------------------------------------------*/
  464 +#if (CFG_NIOS_CPU_PIO_NUMS != 0) && defined(CFG_NIOS_CPU_LED_PIO)
  465 +
  466 +#if (CFG_NIOS_CPU_LED_PIO == 0)
  467 +
  468 +#define STATUS_LED_BASE CFG_NIOS_CPU_PIO0
  469 +#define STATUS_LED_BITS CFG_NIOS_CPU_PIO0_BITS
  470 +#define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
  471 +
  472 +#if (CFG_NIOS_CPU_PIO0_TYPE == 1)
  473 +#define STATUS_LED_WRONLY 1
  474 +#else
  475 +#undef STATUS_LED_WRONLY
  476 +#endif
  477 +
  478 +#elif (CFG_NIOS_CPU_LED_PIO == 1)
  479 +
  480 +#define STATUS_LED_BASE CFG_NIOS_CPU_PIO1
  481 +#define STATUS_LED_BITS CFG_NIOS_CPU_PIO1_BITS
  482 +#define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
  483 +
  484 +#if (CFG_NIOS_CPU_PIO1_TYPE == 1)
  485 +#define STATUS_LED_WRONLY 1
  486 +#else
  487 +#undef STATUS_LED_WRONLY
  488 +#endif
  489 +
  490 +#elif (CFG_NIOS_CPU_LED_PIO == 2)
  491 +
  492 +#define STATUS_LED_BASE CFG_NIOS_CPU_PIO2
  493 +#define STATUS_LED_BITS CFG_NIOS_CPU_PIO2_BITS
  494 +#define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
  495 +
  496 +#if (CFG_NIOS_CPU_PIO2_TYPE == 1)
  497 +#define STATUS_LED_WRONLY 1
  498 +#else
  499 +#undef STATUS_LED_WRONLY
  500 +#endif
  501 +
  502 +#elif (CFG_NIOS_CPU_LED_PIO == 3)
  503 +
  504 +#error *** CFG_ERROR: status LEDs at PIO3 not supported, expand your config.h
  505 +
  506 +#elif (CFG_NIOS_CPU_LED_PIO == 4)
  507 +
  508 +#error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h
  509 +
  510 +#elif (CFG_NIOS_CPU_LED_PIO == 5)
  511 +
  512 +#error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h
  513 +
  514 +#elif (CFG_NIOS_CPU_LED_PIO == 6)
  515 +
  516 +#error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h
  517 +
  518 +#elif (CFG_NIOS_CPU_LED_PIO == 7)
  519 +
  520 +#error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h
  521 +
  522 +#elif (CFG_NIOS_CPU_LED_PIO == 8)
  523 +
  524 +#error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h
  525 +
  526 +#elif (CFG_NIOS_CPU_LED_PIO == 9)
  527 +
  528 +#error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h
  529 +
  530 +#else
  531 +#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_LED_PIO in right case
  532 +#endif
  533 +
  534 +#define CONFIG_STATUS_LED 1 /* enable status led driver */
  535 +
  536 +#define STATUS_LED_BIT (1 << 0) /* LED[0] */
  537 +#define STATUS_LED_STATE STATUS_LED_BLINKING
  538 +#define STATUS_LED_BOOT_STATE STATUS_LED_OFF
  539 +#define STATUS_LED_PERIOD (CFG_HZ / 2) /* ca. 1 Hz */
  540 +#define STATUS_LED_BOOT 0 /* boot LED */
  541 +
  542 +#if (STATUS_LED_BITS > 1)
  543 +#define STATUS_LED_BIT1 (1 << 1) /* LED[1] */
  544 +#define STATUS_LED_STATE1 STATUS_LED_OFF
  545 +#define STATUS_LED_PERIOD1 (CFG_HZ / 10) /* ca. 5 Hz */
  546 +#define STATUS_LED_RED 1 /* fail LED */
  547 +#endif
  548 +
  549 +#if (STATUS_LED_BITS > 2)
  550 +#define STATUS_LED_BIT2 (1 << 2) /* LED[2] */
  551 +#define STATUS_LED_STATE2 STATUS_LED_OFF
  552 +#define STATUS_LED_PERIOD2 (CFG_HZ / 2) /* ca. 1 Hz */
  553 +#define STATUS_LED_YELLOW 2 /* info LED */
  554 +#endif
  555 +
  556 +#if (STATUS_LED_BITS > 3)
  557 +#define STATUS_LED_BIT3 (1 << 3) /* LED[3] */
  558 +#define STATUS_LED_STATE3 STATUS_LED_OFF
  559 +#define STATUS_LED_PERIOD3 (CFG_HZ / 2) /* ca. 1 Hz */
  560 +#define STATUS_LED_GREEN 3 /* info LED */
  561 +#endif
  562 +
  563 +#define STATUS_LED_PAR 1 /* makes status_led.h happy */
  564 +
  565 +#endif /* CFG_NIOS_CPU_PIO_NUMS */
  566 +
  567 +/*------------------------------------------------------------------------
  568 + * Diagnostics / Power On Self Tests
  569 + *----------------------------------------------------------------------*/
  570 +#define CONFIG_POST CFG_POST_RTC
  571 +#define CFG_NIOS_POST_WORD_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
  572 +
  573 +/*------------------------------------------------------------------------
  574 + * COMMANDS
  575 + *----------------------------------------------------------------------*/
  576 +#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
  577 + CFG_CMD_ASKENV | \
  578 + CFG_CMD_BEDBUG | \
  579 + CFG_CMD_BMP | \
  580 + CFG_CMD_CACHE | \
  581 + CFG_CMD_DOC | \
  582 + CFG_CMD_DTT | \
  583 + CFG_CMD_EEPROM | \
  584 + CFG_CMD_ELF | \
  585 + CFG_CMD_FAT | \
  586 + CFG_CMD_FDC | \
  587 + CFG_CMD_FDOS | \
  588 + CFG_CMD_HWFLOW | \
  589 + CFG_CMD_IDE | \
  590 + CFG_CMD_I2C | \
  591 + CFG_CMD_JFFS2 | \
  592 + CFG_CMD_KGDB | \
  593 + CFG_CMD_NAND | \
  594 + CFG_CMD_NFS | \
  595 + CFG_CMD_MMC | \
  596 + CFG_CMD_MII | \
  597 + CFG_CMD_PCI | \
  598 + CFG_CMD_PCMCIA | \
  599 + CFG_CMD_SCSI | \
  600 + CFG_CMD_VFD | \
  601 + CFG_CMD_USB | \
  602 + __SPI_CMD_OFF ) )
  603 +
  604 +
  605 +#include <cmd_confdefs.h>
  606 +
  607 +/*------------------------------------------------------------------------
  608 + * KGDB
  609 + *----------------------------------------------------------------------*/
  610 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  611 +#define CONFIG_KGDB_BAUDRATE 9600
  612 +#endif
  613 +
  614 +/*------------------------------------------------------------------------
  615 + * MISC
  616 + *----------------------------------------------------------------------*/
  617 +#define CFG_LONGHELP /* undef to save memory */
  618 +#define CFG_HUSH_PARSER 1 /* use "hush" command parser
  619 + undef to save memory */
  620 +#define CFG_PROMPT "ADNPESC1 > " /* Monitor Command Prompt */
  621 +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  622 +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  623 +#define CFG_MAXARGS 64 /* max number of command args*/
  624 +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  625 +
  626 +#ifdef CFG_HUSH_PARSER
  627 +#define CFG_PROMPT_HUSH_PS2 "[]> "
  628 +#endif
  629 +
  630 +/* Default load address */
  631 +#if (CFG_SRAM_SIZE != 0)
  632 +
  633 +/* default in SRAM */
  634 +#define CFG_LOAD_ADDR CFG_SRAM_BASE
  635 +
  636 +#elif (CFG_SDRAM_SIZE != 0)
  637 +
  638 +/* default in SDRAM */
  639 +#if (CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE)
  640 +#if 1
  641 +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE)
  642 +#else
  643 +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x400000)
  644 +#endif
  645 +#else
  646 +#define CFG_LOAD_ADDR CFG_SDRAM_BASE
  647 +#endif
  648 +
  649 +#else
  650 +#undef CFG_LOAD_ADDR /* force error break */
  651 +#endif
  652 +
  653 +
  654 +/* MEM test area */
  655 +#if (CFG_SDRAM_SIZE != 0)
  656 +
  657 +/* SDRAM begin to stack area (1MB stack) */
  658 +#if (CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE)
  659 +#if 0
  660 +#define CFG_MEMTEST_START (CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE)
  661 +#else
  662 +#define CFG_MEMTEST_START (CFG_SDRAM_BASE + 0x400000)
  663 +#endif
  664 +#else
  665 +#define CFG_MEMTEST_START CFG_SDRAM_BASE
  666 +#endif
  667 +
  668 +#define CFG_MEMTEST_END (CFG_INIT_SP - (1024 * 1024))
  669 +#define CFG_MEMTEST_END (CFG_INIT_SP - (1024 * 1024))
  670 +
  671 +#else
  672 +#undef CFG_MEMTEST_START /* force error break */
  673 +#undef CFG_MEMTEST_END
  674 +#endif
  675 +
  676 +
  677 +#endif /* __CONFIG_H */
include/configs/ADNPESC1_base_32.h
Diff comments   View file @ aaf224a
  1 +/*
  2 + * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
  3 + * Stephan Linz <linz@li-pro.net>
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#ifndef __CONFIG_ADNPESC1_BASE_32_H
  25 +#define __CONFIG_ADNPESC1_BASE_32_H
  26 +
  27 +/*
  28 + * NIOS CPU configuration. (PART OF configs/ADNPESC1.h)
  29 + *
  30 + * Here we must define CPU dependencies. Any unsupported option have to
  31 + * be undefined or defined with zero, example CPU without data cache / OCI:
  32 + *
  33 + * #define CFG_NIOS_CPU_ICACHE 4096
  34 + * #define CFG_NIOS_CPU_DCACHE 0
  35 + * #undef CFG_NIOS_CPU_OCI_BASE
  36 + * #undef CFG_NIOS_CPU_OCI_SIZE
  37 + */
  38 +
  39 +/* CPU core */
  40 +#define CFG_NIOS_CPU_CLK 50000000 /* NIOS CPU clock */
  41 +#define CFG_NIOS_CPU_ICACHE (0) /* instruction cache */
  42 +#define CFG_NIOS_CPU_DCACHE (0) /* data cache */
  43 +#define CFG_NIOS_CPU_REG_NUMS 512 /* number of register */
  44 +#define CFG_NIOS_CPU_MUL 0 /* 16x16 MUL: no(0) */
  45 + /* yes(1) */
  46 +#define CFG_NIOS_CPU_MSTEP 1 /* 16x16 MSTEP: no(0) */
  47 + /* yes(1) */
  48 +#define CFG_NIOS_CPU_STACK 0x03000000 /* stack top addr */
  49 +#define CFG_NIOS_CPU_VEC_BASE 0x02000000 /* IRQ vectors addr */
  50 +#define CFG_NIOS_CPU_VEC_SIZE 256 /* size */
  51 +#define CFG_NIOS_CPU_VEC_NUMS 64 /* numbers */
  52 +#define CFG_NIOS_CPU_RST_VECT 0x00000000 /* RESET vector addr */
  53 +#define CFG_NIOS_CPU_DBG_CORE 0 /* CPU debug: no(0) */
  54 + /* yes(1) */
  55 +
  56 +/* The offset address in flash to check for the Nios signature "Ni".
  57 + * (see GM_FlashExec in germs_monitor.s) */
  58 +#define CFG_NIOS_CPU_EXES_OFFS 0x0C
  59 +
  60 +/* on-chip extensions */
  61 +#undef CFG_NIOS_CPU_RAM_BASE /* on chip RAM addr */
  62 +#undef CFG_NIOS_CPU_RAM_SIZE /* 64 KB size */
  63 +
  64 +#define CFG_NIOS_CPU_ROM_BASE 0x00000000 /* on chip ROM addr */
  65 +#define CFG_NIOS_CPU_ROM_SIZE (2 * 1024) /* 2 KB size */
  66 +
  67 +#undef CFG_NIOS_CPU_OCI_BASE /* OCI core addr */
  68 +#undef CFG_NIOS_CPU_OCI_SIZE /* size */
  69 +
  70 +/* timer */
  71 +#define CFG_NIOS_CPU_TIMER_NUMS 1 /* number of timer */
  72 +
  73 +#define CFG_NIOS_CPU_TIMER0 0x00000840 /* TIMER0 addr */
  74 +#define CFG_NIOS_CPU_TIMER0_IRQ 16 /* IRQ */
  75 +#define CFG_NIOS_CPU_TIMER0_PER 1000 /* periode usec */
  76 +#define CFG_NIOS_CPU_TIMER0_AR 0 /* always run: no(0) */
  77 + /* yes(1) */
  78 +#define CFG_NIOS_CPU_TIMER0_FP 0 /* fixed per: no(0) */
  79 + /* yes(1) */
  80 +#define CFG_NIOS_CPU_TIMER0_SS 1 /* snaphot: no(0) */
  81 + /* yes(1) */
  82 +
  83 +/* serial i/o */
  84 +#define CFG_NIOS_CPU_UART_NUMS 2 /* number of uarts */
  85 +
  86 +#define CFG_NIOS_CPU_UART0 0x00000800 /* UART0 addr */
  87 +#define CFG_NIOS_CPU_UART0_IRQ 17 /* IRQ */
  88 +#define CFG_NIOS_CPU_UART0_BR 115200 /* baudrate var(0) */
  89 +#define CFG_NIOS_CPU_UART0_DB 8 /* data bit */
  90 +#define CFG_NIOS_CPU_UART0_SB 1 /* stop bit */
  91 +#define CFG_NIOS_CPU_UART0_PA 0 /* parity none(0) */
  92 + /* odd(1) */
  93 + /* even(2) */
  94 +#define CFG_NIOS_CPU_UART0_HS 1 /* handshake: no(0) */
  95 + /* crts(1) */
  96 +#define CFG_NIOS_CPU_UART0_EOP 0 /* eop reg: no(0) */
  97 + /* yes(1) */
  98 +
  99 +#define CFG_NIOS_CPU_UART1 0x00000820 /* UART1 addr */
  100 +#define CFG_NIOS_CPU_UART1_IRQ 18 /* IRQ */
  101 +#define CFG_NIOS_CPU_UART1_BR 115200 /* baudrate var(0) */
  102 +#define CFG_NIOS_CPU_UART1_DB 8 /* data bit */
  103 +#define CFG_NIOS_CPU_UART1_SB 1 /* stop bit */
  104 +#define CFG_NIOS_CPU_UART1_PA 0 /* parity none(0) */
  105 + /* odd(1) */
  106 + /* even(2) */
  107 +#define CFG_NIOS_CPU_UART1_HS 0 /* handshake: no(0) */
  108 + /* crts(1) */
  109 +#define CFG_NIOS_CPU_UART1_EOP 0 /* eop reg: no(0) */
  110 + /* yes(1) */
  111 +
  112 +/* serial peripheral i/o */
  113 +#define CFG_NIOS_CPU_SPI_NUMS 1 /* number of spis */
  114 +
  115 +#define CFG_NIOS_CPU_SPI0 0x000008c0 /* SPI0 addr */
  116 +#define CFG_NIOS_CPU_SPI0_IRQ 25 /* IRQ */
  117 +#define CFG_NIOS_CPU_SPI0_BITS 16 /* data bit */
  118 +#define CFG_NIOS_CPU_SPI0_MA 1 /* is master: no(0) */
  119 + /* yes(1) */
  120 +#define CFG_NIOS_CPU_SPI0_SLN 1 /* num slaves */
  121 +#define CFG_NIOS_CPU_SPI0_TCLK 250000 /* clock (Hz) */
  122 +#define CFG_NIOS_CPU_SPI0_TDELAY 2 /* delay (usec) */
  123 +#define CFG_NIOS_CPU_SPI0_FB 0 /* first bit msb(0) */
  124 + /* lsb(1) */
  125 +
  126 +/* parallel i/o */
  127 +#define CFG_NIOS_CPU_PIO_NUMS 14 /* number of parports */
  128 +
  129 +#define CFG_NIOS_CPU_PIO0 0x00000860 /* PIO0 addr */
  130 +#undef CFG_NIOS_CPU_PIO0_IRQ /* w/o IRQ */
  131 +#define CFG_NIOS_CPU_PIO0_BITS 8 /* number of bits */
  132 +#define CFG_NIOS_CPU_PIO0_TYPE 0 /* io type: tris(0) */
  133 + /* out(1) */
  134 + /* in(2) */
  135 +#define CFG_NIOS_CPU_PIO0_CAP 0 /* capture: no(0) */
  136 + /* yes(1) */
  137 +#define CFG_NIOS_CPU_PIO0_EDGE 0 /* edge type: none(0) */
  138 + /* fall(1) */
  139 + /* rise(2) */
  140 + /* any(3) */
  141 +#define CFG_NIOS_CPU_PIO0_ITYPE 0 /* IRQ type: none(0) */
  142 + /* level(1)*/
  143 + /* edge(2) */
  144 +
  145 +#define CFG_NIOS_CPU_PIO1 0x00000870 /* PIO1 addr */
  146 +#undef CFG_NIOS_CPU_PIO1_IRQ /* w/o IRQ */
  147 +#define CFG_NIOS_CPU_PIO1_BITS 8 /* number of bits */
  148 +#define CFG_NIOS_CPU_PIO1_TYPE 0 /* io type: tris(0) */
  149 + /* out(1) */
  150 + /* in(2) */
  151 +#define CFG_NIOS_CPU_PIO1_CAP 0 /* capture: no(0) */
  152 + /* yes(1) */
  153 +#define CFG_NIOS_CPU_PIO1_EDGE 0 /* edge type: none(0) */
  154 + /* fall(1) */
  155 + /* rise(2) */
  156 + /* any(3) */
  157 +#define CFG_NIOS_CPU_PIO1_ITYPE 0 /* IRQ type: none(0) */
  158 + /* level(1)*/
  159 + /* edge(2) */
  160 +
  161 +#define CFG_NIOS_CPU_PIO2 0x00000880 /* PIO2 addr */
  162 +#undef CFG_NIOS_CPU_PIO2_IRQ /* w/o IRQ */
  163 +#define CFG_NIOS_CPU_PIO2_BITS 4 /* number of bits */
  164 +#define CFG_NIOS_CPU_PIO2_TYPE 0 /* io type: tris(0) */
  165 + /* out(1) */
  166 + /* in(2) */
  167 +#define CFG_NIOS_CPU_PIO2_CAP 0 /* capture: no(0) */
  168 + /* yes(1) */
  169 +#define CFG_NIOS_CPU_PIO2_EDGE 0 /* edge type: none(0) */
  170 + /* fall(1) */
  171 + /* rise(2) */
  172 + /* any(3) */
  173 +#define CFG_NIOS_CPU_PIO2_ITYPE 0 /* IRQ type: none(0) */
  174 + /* level(1)*/
  175 + /* edge(2) */
  176 +
  177 +#define CFG_NIOS_CPU_PIO3 0x00000890 /* PIO3 addr */
  178 +#undef CFG_NIOS_CPU_PIO3_IRQ /* w/o IRQ */
  179 +#define CFG_NIOS_CPU_PIO3_BITS 1 /* number of bits */
  180 +#define CFG_NIOS_CPU_PIO3_TYPE 2 /* io type: tris(0) */
  181 + /* out(1) */
  182 + /* in(2) */
  183 +#define CFG_NIOS_CPU_PIO3_CAP 0 /* capture: no(0) */
  184 + /* yes(1) */
  185 +#define CFG_NIOS_CPU_PIO3_EDGE 0 /* edge type: none(0) */
  186 + /* fall(1) */
  187 + /* rise(2) */
  188 + /* any(3) */
  189 +#define CFG_NIOS_CPU_PIO3_ITYPE 0 /* IRQ type: none(0) */
  190 + /* level(1)*/
  191 + /* edge(2) */
  192 +
  193 +#define CFG_NIOS_CPU_PIO3 0x00000890 /* PIO3 addr */
  194 +#undef CFG_NIOS_CPU_PIO3_IRQ /* w/o IRQ */
  195 +#define CFG_NIOS_CPU_PIO3_BITS 1 /* number of bits */
  196 +#define CFG_NIOS_CPU_PIO3_TYPE 2 /* io type: tris(0) */
  197 + /* out(1) */
  198 + /* in(2) */
  199 +#define CFG_NIOS_CPU_PIO3_CAP 0 /* capture: no(0) */
  200 + /* yes(1) */
  201 +#define CFG_NIOS_CPU_PIO3_EDGE 0 /* edge type: none(0) */
  202 + /* fall(1) */
  203 + /* rise(2) */
  204 + /* any(3) */
  205 +#define CFG_NIOS_CPU_PIO3_ITYPE 0 /* IRQ type: none(0) */
  206 + /* level(1)*/
  207 + /* edge(2) */
  208 +
  209 +#define CFG_NIOS_CPU_PIO4 0x000008a0 /* PIO4 addr */
  210 +#undef CFG_NIOS_CPU_PIO4_IRQ /* w/o IRQ */
  211 +#define CFG_NIOS_CPU_PIO4_BITS 1 /* number of bits */
  212 +#define CFG_NIOS_CPU_PIO4_TYPE 1 /* io type: tris(0) */
  213 + /* out(1) */
  214 + /* in(2) */
  215 +#define CFG_NIOS_CPU_PIO4_CAP 0 /* capture: no(0) */
  216 + /* yes(1) */
  217 +#define CFG_NIOS_CPU_PIO4_EDGE 0 /* edge type: none(0) */
  218 + /* fall(1) */
  219 + /* rise(2) */
  220 + /* any(3) */
  221 +#define CFG_NIOS_CPU_PIO4_ITYPE 0 /* IRQ type: none(0) */
  222 + /* level(1)*/
  223 + /* edge(2) */
  224 +
  225 +#define CFG_NIOS_CPU_PIO5 0x000008b0 /* PIO5 addr */
  226 +#undef CFG_NIOS_CPU_PIO5_IRQ /* w/o IRQ */
  227 +#define CFG_NIOS_CPU_PIO5_BITS 1 /* number of bits */
  228 +#define CFG_NIOS_CPU_PIO5_TYPE 1 /* io type: tris(0) */
  229 + /* out(1) */
  230 + /* in(2) */
  231 +#define CFG_NIOS_CPU_PIO5_CAP 0 /* capture: no(0) */
  232 + /* yes(1) */
  233 +#define CFG_NIOS_CPU_PIO5_EDGE 0 /* edge type: none(0) */
  234 + /* fall(1) */
  235 + /* rise(2) */
  236 + /* any(3) */
  237 +#define CFG_NIOS_CPU_PIO5_ITYPE 0 /* IRQ type: none(0) */
  238 + /* level(1)*/
  239 + /* edge(2) */
  240 +
  241 +#define CFG_NIOS_CPU_PIO6 0x00000900 /* PIO6 addr */
  242 +#define CFG_NIOS_CPU_PIO6_IRQ 20 /* IRQ */
  243 +#define CFG_NIOS_CPU_PIO6_BITS 1 /* number of bits */
  244 +#define CFG_NIOS_CPU_PIO6_TYPE 2 /* io type: tris(0) */
  245 + /* out(1) */
  246 + /* in(2) */
  247 +#define CFG_NIOS_CPU_PIO6_CAP 1 /* capture: no(0) */
  248 + /* yes(1) */
  249 +#define CFG_NIOS_CPU_PIO6_EDGE 2 /* edge type: none(0) */
  250 + /* fall(1) */
  251 + /* rise(2) */
  252 + /* any(3) */
  253 +#define CFG_NIOS_CPU_PIO6_ITYPE 1 /* IRQ type: none(0) */
  254 + /* level(1)*/
  255 + /* edge(2) */
  256 +
  257 +#define CFG_NIOS_CPU_PIO7 0x00000910 /* PIO7 addr */
  258 +#define CFG_NIOS_CPU_PIO7_IRQ 31 /* IRQ */
  259 +#define CFG_NIOS_CPU_PIO7_BITS 1 /* number of bits */
  260 +#define CFG_NIOS_CPU_PIO7_TYPE 2 /* io type: tris(0) */
  261 + /* out(1) */
  262 + /* in(2) */
  263 +#define CFG_NIOS_CPU_PIO7_CAP 1 /* capture: no(0) */
  264 + /* yes(1) */
  265 +#define CFG_NIOS_CPU_PIO7_EDGE 2 /* edge type: none(0) */
  266 + /* fall(1) */
  267 + /* rise(2) */
  268 + /* any(3) */
  269 +#define CFG_NIOS_CPU_PIO7_ITYPE 1 /* IRQ type: none(0) */
  270 + /* level(1)*/
  271 + /* edge(2) */
  272 +
  273 +#define CFG_NIOS_CPU_PIO8 0x00000920 /* PIO8 addr */
  274 +#define CFG_NIOS_CPU_PIO8_IRQ 32 /* IRQ */
  275 +#define CFG_NIOS_CPU_PIO8_BITS 1 /* number of bits */
  276 +#define CFG_NIOS_CPU_PIO8_TYPE 2 /* io type: tris(0) */
  277 + /* out(1) */
  278 + /* in(2) */
  279 +#define CFG_NIOS_CPU_PIO8_CAP 1 /* capture: no(0) */
  280 + /* yes(1) */
  281 +#define CFG_NIOS_CPU_PIO8_EDGE 2 /* edge type: none(0) */
  282 + /* fall(1) */
  283 + /* rise(2) */
  284 + /* any(3) */
  285 +#define CFG_NIOS_CPU_PIO8_ITYPE 1 /* IRQ type: none(0) */
  286 + /* level(1)*/
  287 + /* edge(2) */
  288 +
  289 +#define CFG_NIOS_CPU_PIO9 0x00000930 /* PIO9 addr */
  290 +#define CFG_NIOS_CPU_PIO9_IRQ 33 /* IRQ */
  291 +#define CFG_NIOS_CPU_PIO9_BITS 1 /* number of bits */
  292 +#define CFG_NIOS_CPU_PIO9_TYPE 2 /* io type: tris(0) */
  293 + /* out(1) */
  294 + /* in(2) */
  295 +#define CFG_NIOS_CPU_PIO9_CAP 1 /* capture: no(0) */
  296 + /* yes(1) */
  297 +#define CFG_NIOS_CPU_PIO9_EDGE 2 /* edge type: none(0) */
  298 + /* fall(1) */
  299 + /* rise(2) */
  300 + /* any(3) */
  301 +#define CFG_NIOS_CPU_PIO9_ITYPE 1 /* IRQ type: none(0) */
  302 + /* level(1)*/
  303 + /* edge(2) */
  304 +
  305 +#define CFG_NIOS_CPU_PIO10 0x00000940 /* PIO10 addr */
  306 +#define CFG_NIOS_CPU_PIO10_IRQ 34 /* IRQ */
  307 +#define CFG_NIOS_CPU_PIO10_BITS 1 /* number of bits */
  308 +#define CFG_NIOS_CPU_PIO10_TYPE 2 /* io type: tris(0) */
  309 + /* out(1) */
  310 + /* in(2) */
  311 +#define CFG_NIOS_CPU_PIO10_CAP 1 /* capture: no(0) */
  312 + /* yes(1) */
  313 +#define CFG_NIOS_CPU_PIO10_EDGE 2 /* edge type: none(0) */
  314 + /* fall(1) */
  315 + /* rise(2) */
  316 + /* any(3) */
  317 +#define CFG_NIOS_CPU_PIO10_ITYPE 1 /* IRQ type: none(0) */
  318 + /* level(1)*/
  319 + /* edge(2) */
  320 +
  321 +#define CFG_NIOS_CPU_PIO11 0x00000950 /* PIO11 addr */
  322 +#define CFG_NIOS_CPU_PIO11_IRQ 35 /* IRQ */
  323 +#define CFG_NIOS_CPU_PIO11_BITS 1 /* number of bits */
  324 +#define CFG_NIOS_CPU_PIO11_TYPE 2 /* io type: tris(0) */
  325 + /* out(1) */
  326 + /* in(2) */
  327 +#define CFG_NIOS_CPU_PIO11_CAP 1 /* capture: no(0) */
  328 + /* yes(1) */
  329 +#define CFG_NIOS_CPU_PIO11_EDGE 2 /* edge type: none(0) */
  330 + /* fall(1) */
  331 + /* rise(2) */
  332 + /* any(3) */
  333 +#define CFG_NIOS_CPU_PIO11_ITYPE 1 /* IRQ type: none(0) */
  334 + /* level(1)*/
  335 + /* edge(2) */
  336 +
  337 +#define CFG_NIOS_CPU_PIO12 0x00000960 /* PIO12 addr */
  338 +#define CFG_NIOS_CPU_PIO12_IRQ 36 /* IRQ */
  339 +#define CFG_NIOS_CPU_PIO12_BITS 1 /* number of bits */
  340 +#define CFG_NIOS_CPU_PIO12_TYPE 2 /* io type: tris(0) */
  341 + /* out(1) */
  342 + /* in(2) */
  343 +#define CFG_NIOS_CPU_PIO12_CAP 1 /* capture: no(0) */
  344 + /* yes(1) */
  345 +#define CFG_NIOS_CPU_PIO12_EDGE 2 /* edge type: none(0) */
  346 + /* fall(1) */
  347 + /* rise(2) */
  348 + /* any(3) */
  349 +#define CFG_NIOS_CPU_PIO12_ITYPE 1 /* IRQ type: none(0) */
  350 + /* level(1)*/
  351 + /* edge(2) */
  352 +
  353 +#define CFG_NIOS_CPU_PIO13 0x00000970 /* PIO113 addr */
  354 +#define CFG_NIOS_CPU_PIO13_IRQ 37 /* IRQ */
  355 +#define CFG_NIOS_CPU_PIO13_BITS 1 /* number of bits */
  356 +#define CFG_NIOS_CPU_PIO13_TYPE 2 /* io type: tris(0) */
  357 + /* out(1) */
  358 + /* in(2) */
  359 +#define CFG_NIOS_CPU_PIO13_CAP 1 /* capture: no(0) */
  360 + /* yes(1) */
  361 +#define CFG_NIOS_CPU_PIO13_EDGE 2 /* edge type: none(0) */
  362 + /* fall(1) */
  363 + /* rise(2) */
  364 + /* any(3) */
  365 +#define CFG_NIOS_CPU_PIO13_ITYPE 1 /* IRQ type: none(0) */
  366 + /* level(1)*/
  367 + /* edge(2) */
  368 +
  369 +/* IDE i/f */
  370 +#define CFG_NIOS_CPU_IDE_NUMS 2 /* number of IDE contr. */
  371 +
  372 +#define CFG_NIOS_CPU_IDE0 0x00001000 /* IDE0 addr */
  373 +#define CFG_NIOS_CPU_IDE0_IRQ 36 /* IRQ */
  374 +
  375 +#define CFG_NIOS_CPU_IDE1 0x00001020 /* IDE1 addr */
  376 +#define CFG_NIOS_CPU_IDE1_IRQ 37 /* IRQ */
  377 +
  378 +/* memory accessibility */
  379 +#undef CFG_NIOS_CPU_SRAM_BASE /* board SRAM addr */
  380 +#undef CFG_NIOS_CPU_SRAM_SIZE /* 1 MB size */
  381 +
  382 +#define CFG_NIOS_CPU_SDRAM_BASE 0x02000000 /* board SDRAM addr */
  383 +#define CFG_NIOS_CPU_SDRAM_SIZE (16*1024*1024) /* 16 MB size */
  384 +
  385 +#define CFG_NIOS_CPU_FLASH_BASE 0x01000000 /* board Flash addr */
  386 +#define CFG_NIOS_CPU_FLASH_SIZE (8*1024*1024) /* 8 MB size */
  387 +
  388 +/* LAN */
  389 +#define CFG_NIOS_CPU_LAN_NUMS 1 /* number of LAN i/f */
  390 +
  391 +#define CFG_NIOS_CPU_LAN0_BASE 0x00010000 /* LAN0 addr */
  392 +#define CFG_NIOS_CPU_LAN0_OFFS (0) /* offset */
  393 +#define CFG_NIOS_CPU_LAN0_IRQ 20 /* IRQ */
  394 +#define CFG_NIOS_CPU_LAN0_BUSW 16 /* buswidth*/
  395 +#define CFG_NIOS_CPU_LAN0_TYPE 0 /* smc91111(0) */
  396 + /* cs8900(1) */
  397 + /* ex: openmac(2) */
  398 + /* ex: alteramac(3) */
  399 +
  400 +/* external extension */
  401 +#define CFG_NIOS_CPU_CS0_BASE 0x40000000 /* board EXT0 addr */
  402 +#define CFG_NIOS_CPU_CS0_SIZE (16*1024*1024) /* max. 16 MB size */
  403 +
  404 +#define CFG_NIOS_CPU_CS1_BASE 0x41000000 /* board EXT1 addr */
  405 +#define CFG_NIOS_CPU_CS1_SIZE (16*1024*1024) /* max. 16 MB size */
  406 +
  407 +#define CFG_NIOS_CPU_CS2_BASE 0x42000000 /* board EXT2 addr */
  408 +#define CFG_NIOS_CPU_CS2_SIZE (16*1024*1024) /* max. 16 MB size */
  409 +
  410 +#define CFG_NIOS_CPU_CS3_BASE 0x43000000 /* board EXT3 addr */
  411 +#define CFG_NIOS_CPU_CS3_SIZE (16*1024*1024) /* max. 16 MB size */
  412 +
  413 +/* symbolic redefinition (undef, if not present) */
  414 +#define CFG_NIOS_CPU_TICK_TIMER 0 /* TIMER0: tick (needed)*/
  415 +#undef CFG_NIOS_CPU_USER_TIMER /* TIMERx: users choice */
  416 +
  417 +#define CFG_NIOS_CPU_PORTA_PIO 0 /* PIO0: Port A */
  418 +#define CFG_NIOS_CPU_PORTB_PIO 1 /* PIO1: Port D */
  419 +#define CFG_NIOS_CPU_PORTC_PIO 2 /* PIO2: Port C */
  420 +#define CFG_NIOS_CPU_RCM_PIO 3 /* PIO3: RCM jumper */
  421 +#define CFG_NIOS_CPU_WDENA_PIO 4 /* PIO4: watchdog enable*/
  422 +#define CFG_NIOS_CPU_WDTOG_PIO 5 /* PIO5: watchdog trigg.*/
  423 +
  424 +/* PIOx: LED bar */
  425 +#ifdef CONFIG_DNPEVA2 /* DNP/EVA2 base board */
  426 +#define CFG_NIOS_CPU_LED_PIO CFG_NIOS_CPU_PORTA_PIO
  427 +#else
  428 +#undef CFG_NIOS_CPU_LED_PIO /* no LED bar */
  429 +#endif
  430 +
  431 +#endif /* __CONFIG_ADNPESC1_BASE_32_H */