MLK-16273-1 usb: dwc3: add suspend clock setting interface

Some dwc3 based USB3 IP may have a wrong default suspend clk setting, so add an interface to correct it by board setting. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Li Jun <jun.li@nxp.com> (cherry picked from commit 240b636718313e03db505a713e66e3f893cb7727)

MLK-16273-1 usb: dwc3: add suspend clock setting interface
Some dwc3 based USB3 IP may have a wrong default suspend clk setting, so add an interface to correct it by board setting. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Li Jun <jun.li@nxp.com> (cherry picked from commit 240b636718313e03db505a713e66e3f893cb7727)
Li Jun · Ye Li · Eric Lee · Eric Lee · Eric Lee · Eric Lee
1 parent b81241ee36
Showing 3 changed files with 27 additions and 0 deletions Side-by-side Diff
drivers/usb/dwc3/core.c
drivers/usb/dwc3/core.h
include/dwc3-uboot.h
@@ -395,6 +395,25 @@
 	mdelay(100);
 }
  
+void dwc3_set_suspend_clk(struct dwc3 *dwc)
+{
+	u32 reg;
+
+	/*
+	 * DWC3_GCTL.PWRDNSCALE: The USB3 suspend_clk input replaces
+	 * pipe3_rx_pclk as a clock source to a small part of the USB3
+	 * core that operates when the SS PHY is in its lowest power
+	 * (P3) state, and therefore does not provide a clock.
+	 * The Power Down Scale field specifies how many suspend_clk
+	 * periods fit into a 16 kHz clock period. When performing the
+	 * division, round up the remainder.
+	 */
+	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
+	reg &= ~(DWC3_GCTL_PWRDNSCALE(0x1fff));
+	reg |= DWC3_GCTL_PWRDNSCALE(dwc->power_down_scale);
+	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
+}
+
 /**
  * dwc3_core_init - Low-level initialization of DWC3 Core
  * @dwc: Pointer to our controller context structure
@@ -443,6 +462,9 @@
 	if (ret)
 		goto err0;
  
+	if (dwc->power_down_scale)
+		dwc3_set_suspend_clk(dwc);
+
 	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 	reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
  
@@ -671,6 +693,8 @@
 	dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk;
 	if (dwc3_dev->tx_de_emphasis)
 		tx_de_emphasis = dwc3_dev->tx_de_emphasis;
+
+	dwc->power_down_scale = dwc3_dev->power_down_scale;
  
 	/* default to superspeed if no maximum_speed passed */
 	if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
@@ -643,6 +643,7 @@
  * @dr_mode: requested mode of operation
  * @dcfg: saved contents of DCFG register
  * @gctl: saved contents of GCTL register
+ * @power_down_scale: 16KHz clock periods for suspend_clk
  * @isoch_delay: wValue from Set Isochronous Delay request;
  * @u2sel: parameter from Set SEL request.
  * @u2pel: parameter from Set SEL request.
@@ -763,6 +764,7 @@
 	enum dwc3_ep0_state	ep0state;
 	enum dwc3_link_state	link_state;
  
+	u16			power_down_scale;
 	u16			isoch_delay;
 	u16			u2sel;
 	u16			u2pel;
@@ -16,6 +16,7 @@
 	unsigned long base;
 	enum usb_dr_mode dr_mode;
 	u32 maximum_speed;
+	u16 power_down_scale;
 	unsigned tx_fifo_resize:1;
 	unsigned has_lpm_erratum;
 	u8 lpm_nyet_threshold;
...	...	@@ -395,6 +395,25 @@
395	395	mdelay(100);
396	396	}
397	397
	398	+void dwc3_set_suspend_clk(struct dwc3 *dwc)
	399	+{
	400	+ u32 reg;
	401	+
	402	+ /*
	403	+ * DWC3_GCTL.PWRDNSCALE: The USB3 suspend_clk input replaces
	404	+ * pipe3_rx_pclk as a clock source to a small part of the USB3
	405	+ * core that operates when the SS PHY is in its lowest power
	406	+ * (P3) state, and therefore does not provide a clock.
	407	+ * The Power Down Scale field specifies how many suspend_clk
	408	+ * periods fit into a 16 kHz clock period. When performing the
	409	+ * division, round up the remainder.
	410	+ */
	411	+ reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	412	+ reg &= ~(DWC3_GCTL_PWRDNSCALE(0x1fff));
	413	+ reg \|= DWC3_GCTL_PWRDNSCALE(dwc->power_down_scale);
	414	+ dwc3_writel(dwc->regs, DWC3_GCTL, reg);
	415	+}
	416	+
398	417	/**
399	418	* dwc3_core_init - Low-level initialization of DWC3 Core
400	419	* @dwc: Pointer to our controller context structure
...	...	@@ -443,6 +462,9 @@
443	462	if (ret)
444	463	goto err0;
445	464
	465	+ if (dwc->power_down_scale)
	466	+ dwc3_set_suspend_clk(dwc);
	467	+
446	468	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
447	469	reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
448	470
...	...	@@ -671,6 +693,8 @@
671	693	dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk;
672	694	if (dwc3_dev->tx_de_emphasis)
673	695	tx_de_emphasis = dwc3_dev->tx_de_emphasis;
	696	+
	697	+ dwc->power_down_scale = dwc3_dev->power_down_scale;
674	698
675	699	/* default to superspeed if no maximum_speed passed */
676	700	if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
...	...	@@ -643,6 +643,7 @@
643	643	* @dr_mode: requested mode of operation
644	644	* @dcfg: saved contents of DCFG register
645	645	* @gctl: saved contents of GCTL register
	646	+ * @power_down_scale: 16KHz clock periods for suspend_clk
646	647	* @isoch_delay: wValue from Set Isochronous Delay request;
647	648	* @u2sel: parameter from Set SEL request.
648	649	* @u2pel: parameter from Set SEL request.
...	...	@@ -763,6 +764,7 @@
763	764	enum dwc3_ep0_state ep0state;
764	765	enum dwc3_link_state link_state;
765	766
	767	+ u16 power_down_scale;
766	768	u16 isoch_delay;
767	769	u16 u2sel;
768	770	u16 u2pel;
...	...	@@ -16,6 +16,7 @@
16	16	unsigned long base;
17	17	enum usb_dr_mode dr_mode;
18	18	u32 maximum_speed;
	19	+ u16 power_down_scale;
19	20	unsigned tx_fifo_resize:1;
20	21	unsigned has_lpm_erratum;
21	22	u8 lpm_nyet_threshold;