MLK-16273-1 usb: dwc3: add suspend clock setting interface

Some dwc3 based USB3 IP may have a wrong default suspend clk setting, so add an interface to correct it by board setting. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Li Jun <jun.li@nxp.com> (cherry picked from commit 240b636718313e03db505a713e66e3f893cb7727) (cherry picked from commit ac64f460533f734ac5b2659f8e8ba9fbdd56e539) (cherry picked from commit 45cf59ff70696a147e39034c6b8418cb687c9f84)

MLK-16273-1 usb: dwc3: add suspend clock setting interface
Some dwc3 based USB3 IP may have a wrong default suspend clk setting, so add an interface to correct it by board setting. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Li Jun <jun.li@nxp.com> (cherry picked from commit 240b636718313e03db505a713e66e3f893cb7727) (cherry picked from commit ac64f460533f734ac5b2659f8e8ba9fbdd56e539) (cherry picked from commit 45cf59ff70696a147e39034c6b8418cb687c9f84)
Li Jun · Ye Li
1 parent 4cd816a170
Showing 3 changed files with 27 additions and 0 deletions Side-by-side Diff
drivers/usb/dwc3/core.c
drivers/usb/dwc3/core.h
include/dwc3-uboot.h
@@ -400,6 +400,25 @@
 	mdelay(100);
 }
  
+void dwc3_set_suspend_clk(struct dwc3 *dwc)
+{
+	u32 reg;
+
+	/*
+	 * DWC3_GCTL.PWRDNSCALE: The USB3 suspend_clk input replaces
+	 * pipe3_rx_pclk as a clock source to a small part of the USB3
+	 * core that operates when the SS PHY is in its lowest power
+	 * (P3) state, and therefore does not provide a clock.
+	 * The Power Down Scale field specifies how many suspend_clk
+	 * periods fit into a 16 kHz clock period. When performing the
+	 * division, round up the remainder.
+	 */
+	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
+	reg &= ~(DWC3_GCTL_PWRDNSCALE(0x1fff));
+	reg |= DWC3_GCTL_PWRDNSCALE(dwc->power_down_scale);
+	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
+}
+
 /**
  * dwc3_core_init - Low-level initialization of DWC3 Core
  * @dwc: Pointer to our controller context structure
@@ -450,6 +469,9 @@
 	if (ret)
 		goto err0;
  
+	if (dwc->power_down_scale)
+		dwc3_set_suspend_clk(dwc);
+
 	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 	reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
  
@@ -719,6 +741,8 @@
 	dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk;
 	if (dwc3_dev->tx_de_emphasis)
 		tx_de_emphasis = dwc3_dev->tx_de_emphasis;
+
+	dwc->power_down_scale = dwc3_dev->power_down_scale;
  
 	/* default to superspeed if no maximum_speed passed */
 	if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
@@ -650,6 +650,7 @@
  * @dr_mode: requested mode of operation
  * @dcfg: saved contents of DCFG register
  * @gctl: saved contents of GCTL register
+ * @power_down_scale: 16KHz clock periods for suspend_clk
  * @isoch_delay: wValue from Set Isochronous Delay request;
  * @u2sel: parameter from Set SEL request.
  * @u2pel: parameter from Set SEL request.
@@ -774,6 +775,7 @@
 	enum dwc3_ep0_state	ep0state;
 	enum dwc3_link_state	link_state;
  
+	u16			power_down_scale;
 	u16			isoch_delay;
 	u16			u2sel;
 	u16			u2pel;
@@ -17,6 +17,7 @@
 	enum usb_dr_mode dr_mode;
 	enum usb_phy_interface hsphy_mode;
 	u32 maximum_speed;
+	u16 power_down_scale;
 	unsigned tx_fifo_resize:1;
 	unsigned has_lpm_erratum;
 	u8 lpm_nyet_threshold;
...	...	@@ -400,6 +400,25 @@
400	400	mdelay(100);
401	401	}
402	402
	403	+void dwc3_set_suspend_clk(struct dwc3 *dwc)
	404	+{
	405	+ u32 reg;
	406	+
	407	+ /*
	408	+ * DWC3_GCTL.PWRDNSCALE: The USB3 suspend_clk input replaces
	409	+ * pipe3_rx_pclk as a clock source to a small part of the USB3
	410	+ * core that operates when the SS PHY is in its lowest power
	411	+ * (P3) state, and therefore does not provide a clock.
	412	+ * The Power Down Scale field specifies how many suspend_clk
	413	+ * periods fit into a 16 kHz clock period. When performing the
	414	+ * division, round up the remainder.
	415	+ */
	416	+ reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	417	+ reg &= ~(DWC3_GCTL_PWRDNSCALE(0x1fff));
	418	+ reg \|= DWC3_GCTL_PWRDNSCALE(dwc->power_down_scale);
	419	+ dwc3_writel(dwc->regs, DWC3_GCTL, reg);
	420	+}
	421	+
403	422	/**
404	423	* dwc3_core_init - Low-level initialization of DWC3 Core
405	424	* @dwc: Pointer to our controller context structure
...	...	@@ -450,6 +469,9 @@
450	469	if (ret)
451	470	goto err0;
452	471
	472	+ if (dwc->power_down_scale)
	473	+ dwc3_set_suspend_clk(dwc);
	474	+
453	475	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
454	476	reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
455	477
...	...	@@ -719,6 +741,8 @@
719	741	dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk;
720	742	if (dwc3_dev->tx_de_emphasis)
721	743	tx_de_emphasis = dwc3_dev->tx_de_emphasis;
	744	+
	745	+ dwc->power_down_scale = dwc3_dev->power_down_scale;
722	746
723	747	/* default to superspeed if no maximum_speed passed */
724	748	if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
...	...	@@ -650,6 +650,7 @@
650	650	* @dr_mode: requested mode of operation
651	651	* @dcfg: saved contents of DCFG register
652	652	* @gctl: saved contents of GCTL register
	653	+ * @power_down_scale: 16KHz clock periods for suspend_clk
653	654	* @isoch_delay: wValue from Set Isochronous Delay request;
654	655	* @u2sel: parameter from Set SEL request.
655	656	* @u2pel: parameter from Set SEL request.
...	...	@@ -774,6 +775,7 @@
774	775	enum dwc3_ep0_state ep0state;
775	776	enum dwc3_link_state link_state;
776	777
	778	+ u16 power_down_scale;
777	779	u16 isoch_delay;
778	780	u16 u2sel;
779	781	u16 u2pel;
...	...	@@ -17,6 +17,7 @@
17	17	enum usb_dr_mode dr_mode;
18	18	enum usb_phy_interface hsphy_mode;
19	19	u32 maximum_speed;
	20	+ u16 power_down_scale;
20	21	unsigned tx_fifo_resize:1;
21	22	unsigned has_lpm_erratum;
22	23	u8 lpm_nyet_threshold;