Eric Lee / smarc-uboot

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Commit b392a6d4b05b7409283cd75b4ac6bd12018d187a

Authored by Hou Zhiqiang
Committed by York Sun
1 parent 664b652058
Exists in v2017.01-smarct4x and in 25 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2017.01-smarct3x, v2017.01-smarct3x-emmc

fsl-layerscape: Add workaround for PCIe erratum A010315 

As the access to serders protocol unselected PCIe controller will
hang. So disable the R/W permission to unselected PCIe controller
including its CCSR, IO space and memory space according to the
serders protocol field of RCW.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

Showing 12 changed files with 65 additions and 0 deletions Side-by-side Diff

arch/arm/cpu/armv7/ls102xa/soc.c
Diff comments   View file @ b392a6d
... ... @@ -7,6 +7,7 @@
7 7 #include <common.h>
8 8 #include <asm/arch/clock.h>
9 9 #include <asm/io.h>
  10 +#include <asm/arch/fsl_serdes.h>
10 11 #include <asm/arch/immap_ls102xa.h>
11 12 #include <asm/arch/ls102xa_soc.h>
12 13 #include <asm/arch/ls102xa_stream_id.h>
... ... @@ -58,6 +59,19 @@
58 59  
59 60 return major;
60 61 }
  62 +
  63 +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  64 +void erratum_a010315(void)
  65 +{
  66 + int i;
  67 +
  68 + for (i = PCIE1; i <= PCIE2; i++)
  69 + if (!is_serdes_configured(i)) {
  70 + debug("PCIe%d: disabled all R/W permission!\n", i);
  71 + set_pcie_ns_access(i, 0);
  72 + }
  73 +}
  74 +#endif
61 75  
62 76 int arch_soc_init(void)
63 77 {
arch/arm/cpu/armv8/fsl-layerscape/soc.c
Diff comments   View file @ b392a6d
... ... @@ -8,11 +8,14 @@
8 8 #include <fsl_ifc.h>
9 9 #include <ahci.h>
10 10 #include <scsi.h>
  11 +#include <asm/arch/fsl_serdes.h>
11 12 #include <asm/arch/soc.h>
12 13 #include <asm/io.h>
13 14 #include <asm/global_data.h>
14 15 #include <asm/arch-fsl-layerscape/config.h>
  16 +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
15 17 #include <fsl_csu.h>
  18 +#endif
16 19 #ifdef CONFIG_SYS_FSL_DDR
17 20 #include <fsl_ddr_sdram.h>
18 21 #include <fsl_ddr.h>
... ... @@ -300,6 +303,19 @@
300 303 ddr_out32(&ddr->eor, tmp);
301 304 #endif
302 305 }
  306 +
  307 +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  308 +void erratum_a010315(void)
  309 +{
  310 + int i;
  311 +
  312 + for (i = PCIE1; i <= PCIE4; i++)
  313 + if (!is_serdes_configured(i)) {
  314 + debug("PCIe%d: disabled all R/W permission!\n", i);
  315 + set_pcie_ns_access(i, 0);
  316 + }
  317 +}
  318 +#endif
303 319  
304 320 void fsl_lsch2_early_init_f(void)
305 321 {
arch/arm/include/asm/arch-fsl-layerscape/config.h
Diff comments   View file @ b392a6d
... ... @@ -165,6 +165,8 @@
165 165 #define CONFIG_SYS_FSL_SEC_BE
166 166  
167 167 #define CONFIG_SYS_FSL_SRDS_1
  168 +
  169 +#define CONFIG_SYS_FSL_ERRATUM_A010315
168 170 /* SoC related */
169 171 #ifdef CONFIG_LS1043A
170 172 #define CONFIG_MAX_CPUS 4
arch/arm/include/asm/arch-fsl-layerscape/soc.h
Diff comments   View file @ b392a6d
... ... @@ -100,6 +100,10 @@
100 100 void erratum_a009635(void);
101 101 #endif
102 102  
  103 +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  104 +void erratum_a010315(void);
  105 +#endif
  106 +
103 107 bool soc_has_dp_ddr(void);
104 108 bool soc_has_aiop(void);
105 109 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */
arch/arm/include/asm/arch-ls102xa/config.h
Diff comments   View file @ b392a6d
... ... @@ -129,6 +129,7 @@
129 129 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
130 130 #define CONFIG_SYS_FSL_ERRATUM_A008378
131 131 #define CONFIG_SYS_FSL_ERRATUM_A009663
  132 +#define CONFIG_SYS_FSL_ERRATUM_A010315
132 133 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
133 134 #else
134 135 #error SoC not defined
arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h
Diff comments   View file @ b392a6d
... ... @@ -11,5 +11,9 @@
11 11 int arch_soc_init(void);
12 12 int ls102xa_smmu_stream_id_init(void);
13 13  
  14 +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  15 +void erratum_a010315(void);
  16 +#endif
  17 +
14 18 #endif /* __FSL_LS102XA_SOC_H */
board/freescale/ls1012aqds/ls1012aqds.c
Diff comments   View file @ b392a6d
... ... @@ -206,6 +206,10 @@
206 206 out_le32(&cci->ctrl_ord,
207 207 CCI400_CTRLORD_EN_BARRIER);
208 208  
  209 +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  210 + erratum_a010315();
  211 +#endif
  212 +
209 213 #ifdef CONFIG_ENV_IS_NOWHERE
210 214 gd->env_addr = (ulong)&default_environment[0];
211 215 #endif
board/freescale/ls1012ardb/ls1012ardb.c
Diff comments   View file @ b392a6d
... ... @@ -202,6 +202,10 @@
202 202 */
203 203 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
204 204  
  205 +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  206 + erratum_a010315();
  207 +#endif
  208 +
205 209 #ifdef CONFIG_ENV_IS_NOWHERE
206 210 gd->env_addr = (ulong)&default_environment[0];
207 211 #endif
board/freescale/ls1021aqds/ls1021aqds.c
Diff comments   View file @ b392a6d
... ... @@ -430,6 +430,10 @@
430 430 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
431 431 unsigned int major;
432 432  
  433 +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  434 + erratum_a010315();
  435 +#endif
  436 +
433 437 major = get_soc_major_rev();
434 438 if (major == SOC_MAJOR_VER_1_0) {
435 439 /* Set CCI-400 control override register to
board/freescale/ls1021atwr/ls1021atwr.c
Diff comments   View file @ b392a6d
... ... @@ -480,6 +480,10 @@
480 480  
481 481 int board_init(void)
482 482 {
  483 +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  484 + erratum_a010315();
  485 +#endif
  486 +
483 487 #ifndef CONFIG_SYS_FSL_NO_SERDES
484 488 fsl_serdes_init();
485 489 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
board/freescale/ls1043aqds/ls1043aqds.c
Diff comments   View file @ b392a6d
... ... @@ -308,6 +308,10 @@
308 308  
309 309 int board_init(void)
310 310 {
  311 +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  312 + erratum_a010315();
  313 +#endif
  314 +
311 315 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
312 316 board_retimer_init();
313 317  
board/freescale/ls1043ardb/ls1043ardb.c
Diff comments   View file @ b392a6d
... ... @@ -85,6 +85,10 @@
85 85 {
86 86 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
87 87  
  88 +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  89 + erratum_a010315();
  90 +#endif
  91 +
88 92 #ifdef CONFIG_FSL_IFC
89 93 init_final_memctl_regs();
90 94 #endif