Commit b5e9b296251f138ef9f9cfc15f408710a24831cd
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40e7bcdee7
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arm: socfpga: cache: Enable PL310 L2 cache
Enable the PL310 L2 cache controller support for the SoCFPGA. With the cache related issues resolved, this is safe to be done. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
Showing 1 changed file with 2 additions and 0 deletions Inline Diff
include/configs/socfpga_cyclone5.h
1 | /* | 1 | /* |
2 | * Copyright (C) 2012 Altera Corporation <www.altera.com> | 2 | * Copyright (C) 2012 Altera Corporation <www.altera.com> |
3 | * | 3 | * |
4 | * SPDX-License-Identifier: GPL-2.0+ | 4 | * SPDX-License-Identifier: GPL-2.0+ |
5 | */ | 5 | */ |
6 | #ifndef __CONFIG_H | 6 | #ifndef __CONFIG_H |
7 | #define __CONFIG_H | 7 | #define __CONFIG_H |
8 | 8 | ||
9 | #include <asm/arch/socfpga_base_addrs.h> | 9 | #include <asm/arch/socfpga_base_addrs.h> |
10 | #include "../../board/altera/socfpga/pinmux_config.h" | 10 | #include "../../board/altera/socfpga/pinmux_config.h" |
11 | #include "../../board/altera/socfpga/iocsr_config.h" | 11 | #include "../../board/altera/socfpga/iocsr_config.h" |
12 | #include "../../board/altera/socfpga/pll_config.h" | 12 | #include "../../board/altera/socfpga/pll_config.h" |
13 | 13 | ||
14 | /* | 14 | /* |
15 | * High level configuration | 15 | * High level configuration |
16 | */ | 16 | */ |
17 | /* Virtual target or real hardware */ | 17 | /* Virtual target or real hardware */ |
18 | #undef CONFIG_SOCFPGA_VIRTUAL_TARGET | 18 | #undef CONFIG_SOCFPGA_VIRTUAL_TARGET |
19 | 19 | ||
20 | #define CONFIG_ARMV7 | 20 | #define CONFIG_ARMV7 |
21 | #undef CONFIG_USE_IRQ | 21 | #undef CONFIG_USE_IRQ |
22 | 22 | ||
23 | #define CONFIG_MISC_INIT_R | 23 | #define CONFIG_MISC_INIT_R |
24 | #define CONFIG_SINGLE_BOOTLOADER | 24 | #define CONFIG_SINGLE_BOOTLOADER |
25 | #define CONFIG_SOCFPGA | 25 | #define CONFIG_SOCFPGA |
26 | #define CONFIG_CLOCKS | 26 | #define CONFIG_CLOCKS |
27 | 27 | ||
28 | #define CONFIG_SYS_ARM_CACHE_WRITEALLOC | 28 | #define CONFIG_SYS_ARM_CACHE_WRITEALLOC |
29 | #define CONFIG_SYS_CACHELINE_SIZE 32 | 29 | #define CONFIG_SYS_CACHELINE_SIZE 32 |
30 | #define CONFIG_SYS_L2_PL310 | ||
31 | #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS | ||
30 | 32 | ||
31 | /* base address for .text section */ | 33 | /* base address for .text section */ |
32 | #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET | 34 | #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET |
33 | #define CONFIG_SYS_TEXT_BASE 0x08000040 | 35 | #define CONFIG_SYS_TEXT_BASE 0x08000040 |
34 | #else | 36 | #else |
35 | #define CONFIG_SYS_TEXT_BASE 0x01000040 | 37 | #define CONFIG_SYS_TEXT_BASE 0x01000040 |
36 | #endif | 38 | #endif |
37 | #define CONFIG_SYS_LOAD_ADDR 0x7fc0 | 39 | #define CONFIG_SYS_LOAD_ADDR 0x7fc0 |
38 | 40 | ||
39 | /* Console I/O Buffer Size */ | 41 | /* Console I/O Buffer Size */ |
40 | #define CONFIG_SYS_CBSIZE 256 | 42 | #define CONFIG_SYS_CBSIZE 256 |
41 | /* Monitor Command Prompt */ | 43 | /* Monitor Command Prompt */ |
42 | #define CONFIG_SYS_PROMPT "SOCFPGA_CYCLONE5 # " | 44 | #define CONFIG_SYS_PROMPT "SOCFPGA_CYCLONE5 # " |
43 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | 45 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
44 | sizeof(CONFIG_SYS_PROMPT) + 16) | 46 | sizeof(CONFIG_SYS_PROMPT) + 16) |
45 | 47 | ||
46 | /* | 48 | /* |
47 | * Display CPU and Board Info | 49 | * Display CPU and Board Info |
48 | */ | 50 | */ |
49 | #define CONFIG_DISPLAY_CPUINFO | 51 | #define CONFIG_DISPLAY_CPUINFO |
50 | #define CONFIG_DISPLAY_BOARDINFO | 52 | #define CONFIG_DISPLAY_BOARDINFO |
51 | 53 | ||
52 | /* | 54 | /* |
53 | * Enable early stage initialization at C environment | 55 | * Enable early stage initialization at C environment |
54 | */ | 56 | */ |
55 | #define CONFIG_BOARD_EARLY_INIT_F | 57 | #define CONFIG_BOARD_EARLY_INIT_F |
56 | 58 | ||
57 | /* flat device tree */ | 59 | /* flat device tree */ |
58 | #define CONFIG_OF_LIBFDT | 60 | #define CONFIG_OF_LIBFDT |
59 | /* skip updating the FDT blob */ | 61 | /* skip updating the FDT blob */ |
60 | #define CONFIG_FDT_BLOB_SKIP_UPDATE | 62 | #define CONFIG_FDT_BLOB_SKIP_UPDATE |
61 | /* Initial Memory map size for Linux, minus 4k alignment for DFT blob */ | 63 | /* Initial Memory map size for Linux, minus 4k alignment for DFT blob */ |
62 | #define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024)) | 64 | #define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024)) |
63 | 65 | ||
64 | #define CONFIG_SPL_RAM_DEVICE | 66 | #define CONFIG_SPL_RAM_DEVICE |
65 | #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR | 67 | #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR |
66 | #define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start)) | 68 | #define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start)) |
67 | #define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start) | 69 | #define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start) |
68 | 70 | ||
69 | /* | 71 | /* |
70 | * Memory allocation (MALLOC) | 72 | * Memory allocation (MALLOC) |
71 | */ | 73 | */ |
72 | /* Room required on the stack for the environment data */ | 74 | /* Room required on the stack for the environment data */ |
73 | #define CONFIG_ENV_SIZE 1024 | 75 | #define CONFIG_ENV_SIZE 1024 |
74 | /* Size of DRAM reserved for malloc() use */ | 76 | /* Size of DRAM reserved for malloc() use */ |
75 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) | 77 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) |
76 | 78 | ||
77 | /* SP location before relocation, must use scratch RAM */ | 79 | /* SP location before relocation, must use scratch RAM */ |
78 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 | 80 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 |
79 | /* Reserving 0x100 space at back of scratch RAM for debug info */ | 81 | /* Reserving 0x100 space at back of scratch RAM for debug info */ |
80 | #define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100) | 82 | #define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100) |
81 | /* Stack pointer prior relocation, must situated at on-chip RAM */ | 83 | /* Stack pointer prior relocation, must situated at on-chip RAM */ |
82 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | 84 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ |
83 | CONFIG_SYS_INIT_RAM_SIZE - \ | 85 | CONFIG_SYS_INIT_RAM_SIZE - \ |
84 | GENERATED_GBL_DATA_SIZE) | 86 | GENERATED_GBL_DATA_SIZE) |
85 | 87 | ||
86 | 88 | ||
87 | /* | 89 | /* |
88 | * Command line configuration. | 90 | * Command line configuration. |
89 | */ | 91 | */ |
90 | #define CONFIG_SYS_NO_FLASH | 92 | #define CONFIG_SYS_NO_FLASH |
91 | #include <config_cmd_default.h> | 93 | #include <config_cmd_default.h> |
92 | /* FAT file system support */ | 94 | /* FAT file system support */ |
93 | #define CONFIG_CMD_FAT | 95 | #define CONFIG_CMD_FAT |
94 | 96 | ||
95 | 97 | ||
96 | /* | 98 | /* |
97 | * Misc | 99 | * Misc |
98 | */ | 100 | */ |
99 | #define CONFIG_DOS_PARTITION 1 | 101 | #define CONFIG_DOS_PARTITION 1 |
100 | 102 | ||
101 | #ifdef CONFIG_SPL_BUILD | 103 | #ifdef CONFIG_SPL_BUILD |
102 | #undef CONFIG_PARTITIONS | 104 | #undef CONFIG_PARTITIONS |
103 | #endif | 105 | #endif |
104 | 106 | ||
105 | /* | 107 | /* |
106 | * Environment setup | 108 | * Environment setup |
107 | */ | 109 | */ |
108 | 110 | ||
109 | /* Delay before automatically booting the default image */ | 111 | /* Delay before automatically booting the default image */ |
110 | #define CONFIG_BOOTDELAY 3 | 112 | #define CONFIG_BOOTDELAY 3 |
111 | /* Enable auto completion of commands using TAB */ | 113 | /* Enable auto completion of commands using TAB */ |
112 | #define CONFIG_AUTO_COMPLETE | 114 | #define CONFIG_AUTO_COMPLETE |
113 | /* use "hush" command parser */ | 115 | /* use "hush" command parser */ |
114 | #define CONFIG_SYS_HUSH_PARSER | 116 | #define CONFIG_SYS_HUSH_PARSER |
115 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | 117 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
116 | #define CONFIG_CMD_RUN | 118 | #define CONFIG_CMD_RUN |
117 | 119 | ||
118 | #define CONFIG_BOOTCOMMAND "run ramboot" | 120 | #define CONFIG_BOOTCOMMAND "run ramboot" |
119 | 121 | ||
120 | /* | 122 | /* |
121 | * arguments passed to the bootm command. The value of | 123 | * arguments passed to the bootm command. The value of |
122 | * CONFIG_BOOTARGS goes into the environment value "bootargs". | 124 | * CONFIG_BOOTARGS goes into the environment value "bootargs". |
123 | * Do note the value will overide also the chosen node in FDT blob. | 125 | * Do note the value will overide also the chosen node in FDT blob. |
124 | */ | 126 | */ |
125 | #define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M@0x0" | 127 | #define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M@0x0" |
126 | 128 | ||
127 | #define CONFIG_EXTRA_ENV_SETTINGS \ | 129 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
128 | "verify=n\0" \ | 130 | "verify=n\0" \ |
129 | "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ | 131 | "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ |
130 | "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ | 132 | "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ |
131 | "bootm ${loadaddr} - ${fdt_addr}\0" \ | 133 | "bootm ${loadaddr} - ${fdt_addr}\0" \ |
132 | "bootimage=uImage\0" \ | 134 | "bootimage=uImage\0" \ |
133 | "fdt_addr=100\0" \ | 135 | "fdt_addr=100\0" \ |
134 | "fsloadcmd=ext2load\0" \ | 136 | "fsloadcmd=ext2load\0" \ |
135 | "bootm ${loadaddr} - ${fdt_addr}\0" \ | 137 | "bootm ${loadaddr} - ${fdt_addr}\0" \ |
136 | "qspiroot=/dev/mtdblock0\0" \ | 138 | "qspiroot=/dev/mtdblock0\0" \ |
137 | "qspirootfstype=jffs2\0" \ | 139 | "qspirootfstype=jffs2\0" \ |
138 | "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ | 140 | "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ |
139 | " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ | 141 | " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ |
140 | "bootm ${loadaddr} - ${fdt_addr}\0" | 142 | "bootm ${loadaddr} - ${fdt_addr}\0" |
141 | 143 | ||
142 | /* using environment setting for stdin, stdout, stderr */ | 144 | /* using environment setting for stdin, stdout, stderr */ |
143 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV | 145 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV |
144 | /* Enable the call to overwrite_console() */ | 146 | /* Enable the call to overwrite_console() */ |
145 | #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE | 147 | #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE |
146 | /* Enable overwrite of previous console environment settings */ | 148 | /* Enable overwrite of previous console environment settings */ |
147 | #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE | 149 | #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE |
148 | 150 | ||
149 | /* max number of command args */ | 151 | /* max number of command args */ |
150 | #define CONFIG_SYS_MAXARGS 16 | 152 | #define CONFIG_SYS_MAXARGS 16 |
151 | 153 | ||
152 | 154 | ||
153 | /* | 155 | /* |
154 | * Hardware drivers | 156 | * Hardware drivers |
155 | */ | 157 | */ |
156 | 158 | ||
157 | /* | 159 | /* |
158 | * SDRAM Memory Map | 160 | * SDRAM Memory Map |
159 | */ | 161 | */ |
160 | /* We have 1 bank of DRAM */ | 162 | /* We have 1 bank of DRAM */ |
161 | #define CONFIG_NR_DRAM_BANKS 1 | 163 | #define CONFIG_NR_DRAM_BANKS 1 |
162 | /* SDRAM Bank #1 */ | 164 | /* SDRAM Bank #1 */ |
163 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | 165 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
164 | /* SDRAM memory size */ | 166 | /* SDRAM memory size */ |
165 | #define PHYS_SDRAM_1_SIZE 0x40000000 | 167 | #define PHYS_SDRAM_1_SIZE 0x40000000 |
166 | 168 | ||
167 | #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE | 169 | #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE |
168 | #define CONFIG_SYS_MEMTEST_START 0x00000000 | 170 | #define CONFIG_SYS_MEMTEST_START 0x00000000 |
169 | #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE | 171 | #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE |
170 | 172 | ||
171 | /* | 173 | /* |
172 | * NS16550 Configuration | 174 | * NS16550 Configuration |
173 | */ | 175 | */ |
174 | #define UART0_BASE SOCFPGA_UART0_ADDRESS | 176 | #define UART0_BASE SOCFPGA_UART0_ADDRESS |
175 | #define CONFIG_SYS_NS16550 | 177 | #define CONFIG_SYS_NS16550 |
176 | #define CONFIG_SYS_NS16550_SERIAL | 178 | #define CONFIG_SYS_NS16550_SERIAL |
177 | #define CONFIG_SYS_NS16550_REG_SIZE -4 | 179 | #define CONFIG_SYS_NS16550_REG_SIZE -4 |
178 | #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK | 180 | #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK |
179 | #define CONFIG_CONS_INDEX 1 | 181 | #define CONFIG_CONS_INDEX 1 |
180 | #define CONFIG_SYS_NS16550_COM1 UART0_BASE | 182 | #define CONFIG_SYS_NS16550_COM1 UART0_BASE |
181 | #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} | 183 | #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} |
182 | #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET | 184 | #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET |
183 | #define V_NS16550_CLK 1000000 | 185 | #define V_NS16550_CLK 1000000 |
184 | #else | 186 | #else |
185 | #define V_NS16550_CLK 100000000 | 187 | #define V_NS16550_CLK 100000000 |
186 | #endif | 188 | #endif |
187 | #define CONFIG_BAUDRATE 115200 | 189 | #define CONFIG_BAUDRATE 115200 |
188 | 190 | ||
189 | /* | 191 | /* |
190 | * FLASH | 192 | * FLASH |
191 | */ | 193 | */ |
192 | #define CONFIG_SYS_NO_FLASH | 194 | #define CONFIG_SYS_NO_FLASH |
193 | 195 | ||
194 | /* | 196 | /* |
195 | * L4 OSC1 Timer 0 | 197 | * L4 OSC1 Timer 0 |
196 | */ | 198 | */ |
197 | /* This timer use eosc1 where the clock frequency is fixed | 199 | /* This timer use eosc1 where the clock frequency is fixed |
198 | * throughout any condition */ | 200 | * throughout any condition */ |
199 | #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS | 201 | #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS |
200 | /* Timer info */ | 202 | /* Timer info */ |
201 | #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET | 203 | #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET |
202 | #define CONFIG_SYS_TIMER_RATE 2400000 | 204 | #define CONFIG_SYS_TIMER_RATE 2400000 |
203 | #else | 205 | #else |
204 | #define CONFIG_SYS_TIMER_RATE 25000000 | 206 | #define CONFIG_SYS_TIMER_RATE 25000000 |
205 | #endif | 207 | #endif |
206 | #define CONFIG_SYS_TIMER_COUNTS_DOWN | 208 | #define CONFIG_SYS_TIMER_COUNTS_DOWN |
207 | #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) | 209 | #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) |
208 | 210 | ||
209 | #define CONFIG_ENV_IS_NOWHERE | 211 | #define CONFIG_ENV_IS_NOWHERE |
210 | 212 | ||
211 | /* | 213 | /* |
212 | * network support | 214 | * network support |
213 | */ | 215 | */ |
214 | #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET | 216 | #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET |
215 | #define CONFIG_DESIGNWARE_ETH 1 | 217 | #define CONFIG_DESIGNWARE_ETH 1 |
216 | #endif | 218 | #endif |
217 | 219 | ||
218 | #ifdef CONFIG_DESIGNWARE_ETH | 220 | #ifdef CONFIG_DESIGNWARE_ETH |
219 | #define CONFIG_EMAC0_BASE SOCFPGA_EMAC0_ADDRESS | 221 | #define CONFIG_EMAC0_BASE SOCFPGA_EMAC0_ADDRESS |
220 | #define CONFIG_EMAC1_BASE SOCFPGA_EMAC1_ADDRESS | 222 | #define CONFIG_EMAC1_BASE SOCFPGA_EMAC1_ADDRESS |
221 | /* console support for network */ | 223 | /* console support for network */ |
222 | #define CONFIG_CMD_DHCP | 224 | #define CONFIG_CMD_DHCP |
223 | #define CONFIG_CMD_MII | 225 | #define CONFIG_CMD_MII |
224 | #define CONFIG_CMD_NET | 226 | #define CONFIG_CMD_NET |
225 | #define CONFIG_CMD_PING | 227 | #define CONFIG_CMD_PING |
226 | /* designware */ | 228 | /* designware */ |
227 | #define CONFIG_NET_MULTI | 229 | #define CONFIG_NET_MULTI |
228 | #define CONFIG_DW_ALTDESCRIPTOR | 230 | #define CONFIG_DW_ALTDESCRIPTOR |
229 | #define CONFIG_MII | 231 | #define CONFIG_MII |
230 | #define CONFIG_PHY_GIGE | 232 | #define CONFIG_PHY_GIGE |
231 | #define CONFIG_DW_AUTONEG | 233 | #define CONFIG_DW_AUTONEG |
232 | #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) | 234 | #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) |
233 | #define CONFIG_PHYLIB | 235 | #define CONFIG_PHYLIB |
234 | #define CONFIG_PHY_MICREL | 236 | #define CONFIG_PHY_MICREL |
235 | #define CONFIG_PHY_MICREL_KSZ9021 | 237 | #define CONFIG_PHY_MICREL_KSZ9021 |
236 | /* EMAC controller and PHY used */ | 238 | /* EMAC controller and PHY used */ |
237 | #define CONFIG_EMAC_BASE CONFIG_EMAC1_BASE | 239 | #define CONFIG_EMAC_BASE CONFIG_EMAC1_BASE |
238 | #define CONFIG_EPHY_PHY_ADDR CONFIG_EPHY1_PHY_ADDR | 240 | #define CONFIG_EPHY_PHY_ADDR CONFIG_EPHY1_PHY_ADDR |
239 | #define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII | 241 | #define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII |
240 | #endif /* CONFIG_DESIGNWARE_ETH */ | 242 | #endif /* CONFIG_DESIGNWARE_ETH */ |
241 | 243 | ||
242 | /* | 244 | /* |
243 | * L4 Watchdog | 245 | * L4 Watchdog |
244 | */ | 246 | */ |
245 | #define CONFIG_HW_WATCHDOG | 247 | #define CONFIG_HW_WATCHDOG |
246 | #define CONFIG_HW_WATCHDOG_TIMEOUT_MS 2000 | 248 | #define CONFIG_HW_WATCHDOG_TIMEOUT_MS 2000 |
247 | #define CONFIG_DESIGNWARE_WATCHDOG | 249 | #define CONFIG_DESIGNWARE_WATCHDOG |
248 | #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS | 250 | #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS |
249 | /* Clocks source frequency to watchdog timer */ | 251 | /* Clocks source frequency to watchdog timer */ |
250 | #define CONFIG_DW_WDT_CLOCK_KHZ 25000 | 252 | #define CONFIG_DW_WDT_CLOCK_KHZ 25000 |
251 | 253 | ||
252 | 254 | ||
253 | /* | 255 | /* |
254 | * SPL "Second Program Loader" aka Initial Software | 256 | * SPL "Second Program Loader" aka Initial Software |
255 | */ | 257 | */ |
256 | 258 | ||
257 | /* Enable building of SPL globally */ | 259 | /* Enable building of SPL globally */ |
258 | #define CONFIG_SPL_FRAMEWORK | 260 | #define CONFIG_SPL_FRAMEWORK |
259 | 261 | ||
260 | /* TEXT_BASE for linking the SPL binary */ | 262 | /* TEXT_BASE for linking the SPL binary */ |
261 | #define CONFIG_SPL_TEXT_BASE 0xFFFF0000 | 263 | #define CONFIG_SPL_TEXT_BASE 0xFFFF0000 |
262 | 264 | ||
263 | /* Stack size for SPL */ | 265 | /* Stack size for SPL */ |
264 | #define CONFIG_SPL_STACK_SIZE (4 * 1024) | 266 | #define CONFIG_SPL_STACK_SIZE (4 * 1024) |
265 | 267 | ||
266 | /* MALLOC size for SPL */ | 268 | /* MALLOC size for SPL */ |
267 | #define CONFIG_SPL_MALLOC_SIZE (5 * 1024) | 269 | #define CONFIG_SPL_MALLOC_SIZE (5 * 1024) |
268 | 270 | ||
269 | #define CONFIG_SPL_SERIAL_SUPPORT | 271 | #define CONFIG_SPL_SERIAL_SUPPORT |
270 | #define CONFIG_SPL_BOARD_INIT | 272 | #define CONFIG_SPL_BOARD_INIT |
271 | 273 | ||
272 | #define CHUNKSZ_CRC32 (1 * 1024) | 274 | #define CHUNKSZ_CRC32 (1 * 1024) |
273 | 275 | ||
274 | #define CONFIG_CRC32_VERIFY | 276 | #define CONFIG_CRC32_VERIFY |
275 | 277 | ||
276 | /* Linker script for SPL */ | 278 | /* Linker script for SPL */ |
277 | #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds" | 279 | #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds" |
278 | 280 | ||
279 | /* Support for common/libcommon.o in SPL binary */ | 281 | /* Support for common/libcommon.o in SPL binary */ |
280 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | 282 | #define CONFIG_SPL_LIBCOMMON_SUPPORT |
281 | /* Support for lib/libgeneric.o in SPL binary */ | 283 | /* Support for lib/libgeneric.o in SPL binary */ |
282 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | 284 | #define CONFIG_SPL_LIBGENERIC_SUPPORT |
283 | 285 | ||
284 | /* Support for watchdog */ | 286 | /* Support for watchdog */ |
285 | #define CONFIG_SPL_WATCHDOG_SUPPORT | 287 | #define CONFIG_SPL_WATCHDOG_SUPPORT |
286 | 288 | ||
287 | #endif /* __CONFIG_H */ | 289 | #endif /* __CONFIG_H */ |
288 | 290 |