Commit b5e9b296251f138ef9f9cfc15f408710a24831cd
1 parent
40e7bcdee7
Exists in
v2017.01-smarct4x
and in
37 other branches
arm: socfpga: cache: Enable PL310 L2 cache
Enable the PL310 L2 cache controller support for the SoCFPGA. With the cache related issues resolved, this is safe to be done. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
Showing 1 changed file with 2 additions and 0 deletions Side-by-side Diff
include/configs/socfpga_cyclone5.h
| ... | ... | @@ -27,6 +27,8 @@ |
| 27 | 27 | |
| 28 | 28 | #define CONFIG_SYS_ARM_CACHE_WRITEALLOC |
| 29 | 29 | #define CONFIG_SYS_CACHELINE_SIZE 32 |
| 30 | +#define CONFIG_SYS_L2_PL310 | |
| 31 | +#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS | |
| 30 | 32 | |
| 31 | 33 | /* base address for .text section */ |
| 32 | 34 | #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET |