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Commit b66521a6c1f6721cd7c5857718f3dfe585fb6594

Authored by Wolfgang Denk
1 parent 5df092d781
Exists in master and in 55 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

ARM: PXA: remove broken "zylonite" board. 

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>

Showing 9 changed files with 1 additions and 1743 deletions Side-by-side Diff

board/zylonite/Makefile
View file @ b66521a
1   -#
2   -# (C) Copyright 2000-2006
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# See file CREDITS for list of people who contributed to this
6   -# project.
7   -#
8   -# This program is free software; you can redistribute it and/or
9   -# modify it under the terms of the GNU General Public License as
10   -# published by the Free Software Foundation; either version 2 of
11   -# the License, or (at your option) any later version.
12   -#
13   -# This program is distributed in the hope that it will be useful,
14   -# but WITHOUT ANY WARRANTY; without even the implied warranty of
15   -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16   -# GNU General Public License for more details.
17   -#
18   -# You should have received a copy of the GNU General Public License
19   -# along with this program; if not, write to the Free Software
20   -# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21   -# MA 02111-1307 USA
22   -#
23   -
24   -include $(TOPDIR)/config.mk
25   -
26   -LIB = $(obj)lib$(BOARD).o
27   -
28   -COBJS := zylonite.o nand.o
29   -SOBJS := lowlevel_init.o
30   -
31   -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
32   -OBJS := $(addprefix $(obj),$(COBJS))
33   -SOBJS := $(addprefix $(obj),$(SOBJS))
34   -
35   -$(LIB): $(obj).depend $(OBJS) $(SOBJS)
36   - $(call cmd_link_o_target, $(OBJS) $(SOBJS))
37   -
38   -clean:
39   - rm -f $(SOBJS) $(OBJS)
40   -
41   -distclean: clean
42   - rm -f $(LIB) core *.bak $(obj).depend
43   -
44   -#########################################################################
45   -
46   -# defines $(obj).depend target
47   -include $(SRCTREE)/rules.mk
48   -
49   -sinclude $(obj).depend
50   -
51   -#########################################################################
board/zylonite/config.mk
View file @ b66521a
1   -#CONFIG_SYS_TEXT_BASE = 0x0
2   -#CONFIG_SYS_TEXT_BASE = 0xa1700000
3   -#CONFIG_SYS_TEXT_BASE = 0xa3080000
4   -CONFIG_SYS_TEXT_BASE = 0xa3008000
board/zylonite/flash.c
View file @ b66521a
1   -/*
2   - * (C) Copyright 2001
3   - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4   - *
5   - * (C) Copyright 2001
6   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7   - *
8   - * See file CREDITS for list of people who contributed to this
9   - * project.
10   - *
11   - * This program is free software; you can redistribute it and/or
12   - * modify it under the terms of the GNU General Public License as
13   - * published by the Free Software Foundation; either version 2 of
14   - * the License, or (at your option) any later version.
15   - *
16   - * This program is distributed in the hope that it will be useful,
17   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
18   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19   - * GNU General Public License for more details.
20   - *
21   - * You should have received a copy of the GNU General Public License
22   - * along with this program; if not, write to the Free Software
23   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24   - * MA 02111-1307 USA
25   - */
26   -
27   -#include <common.h>
28   -#include <linux/byteorder/swab.h>
29   -
30   -
31   -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
32   -
33   -/* Board support for 1 or 2 flash devices */
34   -#define FLASH_PORT_WIDTH32
35   -#undef FLASH_PORT_WIDTH16
36   -
37   -#ifdef FLASH_PORT_WIDTH16
38   -#define FLASH_PORT_WIDTH ushort
39   -#define FLASH_PORT_WIDTHV vu_short
40   -#define SWAP(x) __swab16(x)
41   -#else
42   -#define FLASH_PORT_WIDTH ulong
43   -#define FLASH_PORT_WIDTHV vu_long
44   -#define SWAP(x) __swab32(x)
45   -#endif
46   -
47   -#define FPW FLASH_PORT_WIDTH
48   -#define FPWV FLASH_PORT_WIDTHV
49   -
50   -#define mb() __asm__ __volatile__ ("" : : : "memory")
51   -
52   -/*-----------------------------------------------------------------------
53   - * Functions
54   - */
55   -static ulong flash_get_size (FPW *addr, flash_info_t *info);
56   -static int write_data (flash_info_t *info, ulong dest, FPW data);
57   -static void flash_get_offsets (ulong base, flash_info_t *info);
58   -void inline spin_wheel (void);
59   -
60   -/*-----------------------------------------------------------------------
61   - */
62   -
63   -unsigned long flash_init (void)
64   -{
65   -#if 0
66   - int i;
67   - ulong size = 0;
68   -
69   - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
70   - switch (i) {
71   - case 0:
72   - flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
73   - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
74   - break;
75   - case 1:
76   - flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]);
77   - flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
78   - break;
79   - default:
80   - panic ("configured too many flash banks!\n");
81   - break;
82   - }
83   - size += flash_info[i].size;
84   - }
85   -
86   - /* Protect monitor and environment sectors
87   - */
88   - flash_protect ( FLAG_PROTECT_SET,
89   - CONFIG_SYS_FLASH_BASE,
90   - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
91   - &flash_info[0] );
92   -
93   - flash_protect ( FLAG_PROTECT_SET,
94   - CONFIG_ENV_ADDR,
95   - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] );
96   -
97   - return size;
98   -#endif
99   - return 0;
100   -}
101   -
102   -/*-----------------------------------------------------------------------
103   - */
104   -static void flash_get_offsets (ulong base, flash_info_t *info)
105   -{
106   - int i;
107   -
108   - if (info->flash_id == FLASH_UNKNOWN) {
109   - return;
110   - }
111   -
112   - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
113   - for (i = 0; i < info->sector_count; i++) {
114   - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
115   - info->protect[i] = 0;
116   - }
117   - }
118   -}
119   -
120   -/*-----------------------------------------------------------------------
121   - */
122   -void flash_print_info (flash_info_t *info)
123   -{
124   - int i;
125   -
126   - if (info->flash_id == FLASH_UNKNOWN) {
127   - printf ("missing or unknown FLASH type\n");
128   - return;
129   - }
130   -
131   - switch (info->flash_id & FLASH_VENDMASK) {
132   - case FLASH_MAN_INTEL:
133   - printf ("INTEL ");
134   - break;
135   - default:
136   - printf ("Unknown Vendor ");
137   - break;
138   - }
139   -
140   - switch (info->flash_id & FLASH_TYPEMASK) {
141   - case FLASH_28F128J3A:
142   - printf ("28F128J3A\n");
143   - break;
144   - default:
145   - printf ("Unknown Chip Type\n");
146   - break;
147   - }
148   -
149   - printf (" Size: %ld MB in %d Sectors\n",
150   - info->size >> 20, info->sector_count);
151   -
152   - printf (" Sector Start Addresses:");
153   - for (i = 0; i < info->sector_count; ++i) {
154   - if ((i % 5) == 0)
155   - printf ("\n ");
156   - printf (" %08lX%s",
157   - info->start[i],
158   - info->protect[i] ? " (RO)" : " ");
159   - }
160   - printf ("\n");
161   - return;
162   -}
163   -
164   -/*
165   - * The following code cannot be run from FLASH!
166   - */
167   -static ulong flash_get_size (FPW *addr, flash_info_t *info)
168   -{
169   - volatile FPW value;
170   -
171   - /* Write auto select command: read Manufacturer ID */
172   - addr[0x5555] = (FPW) 0x00AA00AA;
173   - addr[0x2AAA] = (FPW) 0x00550055;
174   - addr[0x5555] = (FPW) 0x00900090;
175   -
176   - mb ();
177   - value = addr[0];
178   -
179   - switch (value) {
180   -
181   - case (FPW) INTEL_MANUFACT:
182   - info->flash_id = FLASH_MAN_INTEL;
183   - break;
184   -
185   - default:
186   - info->flash_id = FLASH_UNKNOWN;
187   - info->sector_count = 0;
188   - info->size = 0;
189   - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
190   - return (0); /* no or unknown flash */
191   - }
192   -
193   - mb ();
194   - value = addr[1]; /* device ID */
195   -
196   - switch (value) {
197   -
198   - case (FPW) INTEL_ID_28F128J3A:
199   - info->flash_id += FLASH_28F128J3A;
200   - info->sector_count = 128;
201   - info->size = 0x02000000;
202   - break; /* => 16 MB */
203   -
204   - default:
205   - info->flash_id = FLASH_UNKNOWN;
206   - break;
207   - }
208   -
209   - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
210   - printf ("** ERROR: sector count %d > max (%d) **\n",
211   - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
212   - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
213   - }
214   -
215   - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
216   -
217   - return (info->size);
218   -}
219   -
220   -
221   -/*-----------------------------------------------------------------------
222   - */
223   -
224   -int flash_erase (flash_info_t *info, int s_first, int s_last)
225   -{
226   - int flag, prot, sect;
227   - ulong type, start;
228   - int rcode = 0;
229   -
230   - if ((s_first < 0) || (s_first > s_last)) {
231   - if (info->flash_id == FLASH_UNKNOWN) {
232   - printf ("- missing\n");
233   - } else {
234   - printf ("- no sectors to erase\n");
235   - }
236   - return 1;
237   - }
238   -
239   - type = (info->flash_id & FLASH_VENDMASK);
240   - if ((type != FLASH_MAN_INTEL)) {
241   - printf ("Can't erase unknown flash type %08lx - aborted\n",
242   - info->flash_id);
243   - return 1;
244   - }
245   -
246   - prot = 0;
247   - for (sect = s_first; sect <= s_last; ++sect) {
248   - if (info->protect[sect]) {
249   - prot++;
250   - }
251   - }
252   -
253   - if (prot) {
254   - printf ("- Warning: %d protected sectors will not be erased!\n",
255   - prot);
256   - } else {
257   - printf ("\n");
258   - }
259   -
260   - /* Disable interrupts which might cause a timeout here */
261   - flag = disable_interrupts ();
262   -
263   - /* Start erase on unprotected sectors */
264   - for (sect = s_first; sect <= s_last; sect++) {
265   - if (info->protect[sect] == 0) { /* not protected */
266   - FPWV *addr = (FPWV *) (info->start[sect]);
267   - FPW status;
268   -
269   - printf ("Erasing sector %2d ... ", sect);
270   -
271   - /* arm simple, non interrupt dependent timer */
272   - start = get_timer(0);
273   -
274   - *addr = (FPW) 0x00500050; /* clear status register */
275   - *addr = (FPW) 0x00200020; /* erase setup */
276   - *addr = (FPW) 0x00D000D0; /* erase confirm */
277   -
278   - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
279   - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
280   - printf ("Timeout\n");
281   - *addr = (FPW) 0x00B000B0; /* suspend erase */
282   - *addr = (FPW) 0x00FF00FF; /* reset to read mode */
283   - rcode = 1;
284   - break;
285   - }
286   - }
287   -
288   - *addr = 0x00500050; /* clear status register cmd. */
289   - *addr = 0x00FF00FF; /* resest to read mode */
290   -
291   - printf (" done\n");
292   - }
293   - }
294   - return rcode;
295   -}
296   -
297   -/*-----------------------------------------------------------------------
298   - * Copy memory to flash, returns:
299   - * 0 - OK
300   - * 1 - write timeout
301   - * 2 - Flash not erased
302   - * 4 - Flash not identified
303   - */
304   -
305   -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
306   -{
307   - ulong cp, wp;
308   - FPW data;
309   - int count, i, l, rc, port_width;
310   -
311   - if (info->flash_id == FLASH_UNKNOWN) {
312   - return 4;
313   - }
314   -/* get lower word aligned address */
315   -#ifdef FLASH_PORT_WIDTH16
316   - wp = (addr & ~1);
317   - port_width = 2;
318   -#else
319   - wp = (addr & ~3);
320   - port_width = 4;
321   -#endif
322   -
323   - /*
324   - * handle unaligned start bytes
325   - */
326   - if ((l = addr - wp) != 0) {
327   - data = 0;
328   - for (i = 0, cp = wp; i < l; ++i, ++cp) {
329   - data = (data << 8) | (*(uchar *) cp);
330   - }
331   - for (; i < port_width && cnt > 0; ++i) {
332   - data = (data << 8) | *src++;
333   - --cnt;
334   - ++cp;
335   - }
336   - for (; cnt == 0 && i < port_width; ++i, ++cp) {
337   - data = (data << 8) | (*(uchar *) cp);
338   - }
339   -
340   - if ((rc = write_data (info, wp, SWAP (data))) != 0) {
341   - return (rc);
342   - }
343   - wp += port_width;
344   - }
345   -
346   - /*
347   - * handle word aligned part
348   - */
349   - count = 0;
350   - while (cnt >= port_width) {
351   - data = 0;
352   - for (i = 0; i < port_width; ++i) {
353   - data = (data << 8) | *src++;
354   - }
355   - if ((rc = write_data (info, wp, SWAP (data))) != 0) {
356   - return (rc);
357   - }
358   - wp += port_width;
359   - cnt -= port_width;
360   - if (count++ > 0x800) {
361   - spin_wheel ();
362   - count = 0;
363   - }
364   - }
365   -
366   - if (cnt == 0) {
367   - return (0);
368   - }
369   -
370   - /*
371   - * handle unaligned tail bytes
372   - */
373   - data = 0;
374   - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
375   - data = (data << 8) | *src++;
376   - --cnt;
377   - }
378   - for (; i < port_width; ++i, ++cp) {
379   - data = (data << 8) | (*(uchar *) cp);
380   - }
381   -
382   - return (write_data (info, wp, SWAP (data)));
383   -}
384   -
385   -/*-----------------------------------------------------------------------
386   - * Write a word or halfword to Flash, returns:
387   - * 0 - OK
388   - * 1 - write timeout
389   - * 2 - Flash not erased
390   - */
391   -static int write_data (flash_info_t *info, ulong dest, FPW data)
392   -{
393   - FPWV *addr = (FPWV *) dest;
394   - ulong status;
395   - int flag;
396   - ulong start;
397   -
398   - /* Check if Flash is (sufficiently) erased */
399   - if ((*addr & data) != data) {
400   - printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
401   - return (2);
402   - }
403   - /* Disable interrupts which might cause a timeout here */
404   - flag = disable_interrupts ();
405   -
406   - *addr = (FPW) 0x00400040; /* write setup */
407   - *addr = data;
408   -
409   - /* arm simple, non interrupt dependent timer */
410   - start = get_timer(0);
411   -
412   - /* wait while polling the status register */
413   - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
414   - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
415   - *addr = (FPW) 0x00FF00FF; /* restore read mode */
416   - return (1);
417   - }
418   - }
419   -
420   - *addr = (FPW) 0x00FF00FF; /* restore read mode */
421   -
422   - return (0);
423   -}
424   -
425   -void inline spin_wheel (void)
426   -{
427   - static int p = 0;
428   - static char w[] = "\\/-";
429   -
430   - printf ("\010%c", w[p]);
431   - (++p == 3) ? (p = 0) : 0;
432   -}
board/zylonite/lowlevel_init.S
View file @ b66521a
1   -/*
2   - * Most of this taken from Redboot hal_platform_setup.h with cleanup
3   - *
4   - * NOTE: I haven't clean this up considerably, just enough to get it
5   - * running. See hal_platform_setup.h for the source. See
6   - * board/cradle/lowlevel_init.S for another PXA250 setup that is
7   - * much cleaner.
8   - *
9   - * See file CREDITS for list of people who contributed to this
10   - * project.
11   - *
12   - * This program is free software; you can redistribute it and/or
13   - * modify it under the terms of the GNU General Public License as
14   - * published by the Free Software Foundation; either version 2 of
15   - * the License, or (at your option) any later version.
16   - *
17   - * This program is distributed in the hope that it will be useful,
18   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
19   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20   - * GNU General Public License for more details.
21   - *
22   - * You should have received a copy of the GNU General Public License
23   - * along with this program; if not, write to the Free Software
24   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25   - * MA 02111-1307 USA
26   - */
27   -
28   -#include <config.h>
29   -#include <version.h>
30   -#include <asm/arch/pxa-regs.h>
31   -
32   -DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
33   -
34   -/* wait for coprocessor write complete */
35   -.macro CPWAIT reg
36   - mrc p15,0,\reg,c2,c0,0
37   - mov \reg,\reg
38   - sub pc,pc,#4
39   -.endm
40   -
41   -
42   -.macro wait time
43   - ldr r2, =OSCR
44   - mov r3, #0
45   - str r3, [r2]
46   -0:
47   - ldr r3, [r2]
48   - cmp r3, \time
49   - bls 0b
50   -.endm
51   -
52   -/*
53   - * Memory setup
54   - */
55   -
56   -.globl lowlevel_init
57   -lowlevel_init:
58   - /* Set up GPIO pins first ----------------------------------------- */
59   - mov r10, lr
60   -
61   - /* Configure GPIO Pins 41 - 48 as UART1 / altern. Fkt. 2 */
62   - ldr r0, =0x40E10438 @ GPIO41 FFRXD
63   - ldr r1, =0x802
64   - str r1, [r0]
65   -
66   - ldr r0, =0x40E1043C @ GPIO42 FFTXD
67   - ldr r1, =0x802
68   - str r1, [r0]
69   -
70   - ldr r0, =0x40E10440 @ GPIO43 FFCTS
71   - ldr r1, =0x802
72   - str r1, [r0]
73   -
74   - ldr r0, =0x40E10444 @ GPIO 44 FFDCD
75   - ldr r1, =0x802
76   - str r1, [r0]
77   -
78   - ldr r0, =0x40E10448 @ GPIO 45 FFDSR
79   - ldr r1, =0x802
80   - str r1, [r0]
81   -
82   - ldr r0, =0x40E1044C @ GPIO 46 FFRI
83   - ldr r1, =0x802
84   - str r1, [r0]
85   -
86   - ldr r0, =0x40E10450 @ GPIO 47 FFDTR
87   - ldr r1, =0x802
88   - str r1, [r0]
89   -
90   - ldr r0, =0x40E10454 @ GPIO 48
91   - ldr r1, =0x802
92   - str r1, [r0]
93   -
94   - /* tebrandt - ASCR, clear the RDH bit */
95   - ldr r0, =ASCR
96   - ldr r1, [r0]
97   - bic r1, r1, #0x80000000
98   - str r1, [r0]
99   -
100   - /* ---------------------------------------------------------------- */
101   - /* Enable memory interface */
102   - /* */
103   - /* The sequence below is based on the recommended init steps */
104   - /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
105   - /* Chapter 10. */
106   - /* ---------------------------------------------------------------- */
107   -
108   - /* ---------------------------------------------------------------- */
109   - /* Step 1: Wait for at least 200 microsedonds to allow internal */
110   - /* clocks to settle. Only necessary after hard reset... */
111   - /* FIXME: can be optimized later */
112   - /* ---------------------------------------------------------------- */
113   -
114   - /* mk: replaced with wait macro */
115   -/* ldr r3, =OSCR /\* reset the OS Timer Count to zero *\/ */
116   -/* mov r2, #0 */
117   -/* str r2, [r3] */
118   -/* ldr r4, =0x300 /\* really 0x2E1 is about 200usec, *\/ */
119   -/* /\* so 0x300 should be plenty *\/ */
120   -/* 1: */
121   -/* ldr r2, [r3] */
122   -/* cmp r4, r2 */
123   -/* bgt 1b */
124   - wait #0x300
125   -
126   -mem_init:
127   -
128   - /* configure the MEMCLKCFG register */
129   - ldr r1, =MEMCLKCFG
130   - ldr r2, =0x00010001
131   - str r2, [r1] @ WRITE
132   - ldr r2, [r1] @ DELAY UNTIL WRITTEN
133   -
134   - /* set CSADRCFG[0] to data flash SRAM mode */
135   - ldr r1, =CSADRCFG0
136   - ldr r2, =0x00320809
137   - str r2, [r1] @ WRITE
138   - ldr r2, [r1] @ DELAY UNTIL WRITTEN
139   -
140   - /* set CSADRCFG[1] to data flash SRAM mode */
141   - ldr r1, =CSADRCFG1
142   - ldr r2, =0x00320809
143   - str r2, [r1] @ WRITE
144   - ldr r2, [r1] @ DELAY UNTIL WRITTEN
145   -
146   - /* set MSC 0 register for SRAM memory */
147   - ldr r1, =MSC0
148   - ldr r2, =0x11191119
149   - str r2, [r1] @ WRITE
150   - ldr r2, [r1] @ DELAY UNTIL WRITTEN
151   -
152   - /* set CSADRCFG[2] to data flash SRAM mode */
153   - ldr r1, =CSADRCFG2
154   - ldr r2, =0x00320809
155   - str r2, [r1] @ WRITE
156   - ldr r2, [r1] @ DELAY UNTIL WRITTEN
157   -
158   - /* set CSADRCFG[3] to VLIO mode */
159   - ldr r1, =CSADRCFG3
160   - ldr r2, =0x0032080B
161   - str r2, [r1] @ WRITE
162   - ldr r2, [r1] @ DELAY UNTIL WRITTEN
163   -
164   - /* set MSC 1 register for VLIO memory */
165   - ldr r1, =MSC1
166   - ldr r2, =0x123C1119
167   - str r2, [r1] @ WRITE
168   - ldr r2, [r1] @ DELAY UNTIL WRITTEN
169   -
170   -#if 0
171   - /* This does not work in Zylonite. -SC */
172   - ldr r0, =0x15fffff0
173   - ldr r1, =0xb10b
174   - str r1, [r0]
175   - str r1, [r0, #4]
176   -#endif
177   -
178   - /* Configure ACCR Register */
179   - ldr r0, =ACCR @ ACCR
180   - ldr r1, =0x0180b108
181   - str r1, [r0]
182   - ldr r1, [r0]
183   -
184   - /* Configure MDCNFG Register */
185   - ldr r0, =MDCNFG @ MDCNFG
186   - ldr r1, =0x403
187   - str r1, [r0]
188   - ldr r1, [r0]
189   -
190   - /* Perform Resistive Compensation by configuring RCOMP register */
191   - ldr r1, =RCOMP @ RCOMP
192   - ldr r2, =0x000000ff
193   - str r2, [r1]
194   - ldr r2, [r1]
195   -
196   - /* Configure MDMRS Register for SDCS0 */
197   - ldr r1, =MDMRS @ MDMRS
198   - ldr r2, =0x60000023
199   - ldr r3, [r1]
200   - orr r2, r2, r3
201   - str r2, [r1]
202   - ldr r2, [r1]
203   -
204   - /* Configure MDMRS Register for SDCS1 */
205   - ldr r1, =MDMRS @ MDMRS
206   - ldr r2, =0xa0000023
207   - ldr r3, [r1]
208   - orr r2, r2, r3
209   - str r2, [r1]
210   - ldr r2, [r1]
211   -
212   - /* Configure MDREFR */
213   - ldr r1, =MDREFR @ MDREFR
214   - ldr r2, =0x00000006
215   - str r2, [r1]
216   - ldr r2, [r1]
217   -
218   - /* Configure EMPI */
219   - ldr r1, =EMPI @ EMPI
220   - ldr r2, =0x80000000
221   - str r2, [r1]
222   - ldr r2, [r1]
223   -
224   - /* Hardware DDR Read-Strobe Delay Calibration */
225   - ldr r0, =DDR_HCAL @ DDR_HCAL
226   - ldr r1, =0x803ffc07 @ the offset is correct? -SC
227   - str r1, [r0]
228   - wait #5
229   - ldr r1, [r0]
230   -
231   - /* Here we assume the hardware calibration alwasy be successful. -SC */
232   - /* Set DMCEN bit in MDCNFG Register */
233   - ldr r0, =MDCNFG @ MDCNFG
234   - ldr r1, [r0]
235   - orr r1, r1, #0x40000000 @ enable SDRAM for Normal Access
236   - str r1, [r0]
237   -
238   -#ifndef CONFIG_SYS_SKIP_DRAM_SCRUB
239   - /* scrub/init SDRAM if enabled/present */
240   -/* ldr r11, =0xa0000000 /\* base address of SDRAM (CONFIG_SYS_DRAM_BASE) *\/ */
241   -/* ldr r12, =0x04000000 /\* size of memory to scrub (CONFIG_SYS_DRAM_SIZE) *\/ */
242   -/* mov r8,r12 /\* save DRAM size (mk: why???) *\/ */
243   - ldr r8, =0xa0000000 /* base address of SDRAM (CONFIG_SYS_DRAM_BASE) */
244   - ldr r9, =0x04000000 /* size of memory to scrub (CONFIG_SYS_DRAM_SIZE) */
245   - mov r0, #0 /* scrub with 0x0000:0000 */
246   - mov r1, #0
247   - mov r2, #0
248   - mov r3, #0
249   - mov r4, #0
250   - mov r5, #0
251   - mov r6, #0
252   - mov r7, #0
253   -10: /* fastScrubLoop */
254   - subs r9, r9, #32 /* 32 bytes/line */
255   - stmia r8!, {r0-r7}
256   - beq 15f
257   - b 10b
258   -#endif /* CONFIG_SYS_SKIP_DRAM_SCRUB */
259   -
260   -15:
261   - /* Mask all interrupts */
262   - mov r1, #0
263   - mcr p6, 0, r1, c1, c0, 0 @ ICMR
264   -
265   - /* Disable software and data breakpoints */
266   - mov r0, #0
267   - mcr p15,0,r0,c14,c8,0 /* ibcr0 */
268   - mcr p15,0,r0,c14,c9,0 /* ibcr1 */
269   - mcr p15,0,r0,c14,c4,0 /* dbcon */
270   -
271   - /* Enable all debug functionality */
272   - mov r0,#0x80000000
273   - mcr p14,0,r0,c10,c0,0 /* dcsr */
274   -
275   - /* We are finished with Intel's memory controller initialisation */
276   -
277   - /* ---------------------------------------------------------------- */
278   - /* End lowlevel_init */
279   - /* ---------------------------------------------------------------- */
280   -
281   -endlowlevel_init:
282   -
283   - mov pc, lr
284   -
285   -/*
286   -@********************************************************************************
287   -@ DDR calibration
288   -@
289   -@ This function is used to calibrate DQS delay lines.
290   -@ Monahans supports three ways to do it. One is software
291   -@ calibration. Two is hardware calibration. Three is hybrid
292   -@ calibration.
293   -@
294   -@ TBD
295   -@ -SC
296   -ddr_calibration:
297   -
298   - @ Case 1: Write the correct delay value once
299   - @ Configure DDR_SCAL Register
300   - ldr r0, =DDR_SCAL @ DDR_SCAL
301   -q ldr r1, =0xaf2f2f2f
302   - str r1, [r0]
303   - ldr r1, [r0]
304   -*/
305   -/* @ Case 2: Software Calibration
306   - @ Write test pattern to memory
307   - ldr r5, =0x0faf0faf @ Data Pattern
308   - ldr r4, =0xa0000000 @ DDR ram
309   - str r5, [r4]
310   -
311   - mov r1, =0x0 @ delay count
312   - mov r6, =0x0
313   - mov r7, =0x0
314   -ddr_loop1:
315   - add r1, r1, =0x1
316   - cmp r1, =0xf
317   - ble end_loop
318   - mov r3, r1
319   - mov r0, r1, lsl #30
320   - orr r3, r3, r0
321   - mov r0, r1, lsl #22
322   - orr r3, r3, r0
323   - mov r0, r1, lsl #14
324   - orr r3, r3, r0
325   - orr r3, r3, =0x80000000
326   - ldr r2, =DDR_SCAL
327   - str r3, [r2]
328   -
329   - ldr r2, [r4]
330   - cmp r2, r5
331   - bne ddr_loop1
332   - mov r6, r1
333   -ddr_loop2:
334   - add r1, r1, =0x1
335   - cmp r1, =0xf
336   - ble end_loop
337   - mov r3, r1
338   - mov r0, r1, lsl #30
339   - orr r3, r3, r0
340   - mov r0, r1, lsl #22
341   - orr r3, r3, r0
342   - mov r0, r1, lsl #14
343   - orr r3, r3, r0
344   - orr r3, r3, =0x80000000
345   - ldr r2, =DDR_SCAL
346   - str r3, [r2]
347   -
348   - ldr r2, [r4]
349   - cmp r2, r5
350   - be ddr_loop2
351   - mov r7, r2
352   -
353   - add r3, r6, r7
354   - lsr r3, r3, =0x1
355   - mov r0, r1, lsl #30
356   - orr r3, r3, r0
357   - mov r0, r1, lsl #22
358   - orr r3, r3, r0
359   - mov r0, r1, lsl #14
360   - orr r3, r3, r0
361   - orr r3, r3, =0x80000000
362   - ldr r2, =DDR_SCAL
363   -
364   -end_loop:
365   -
366   - @ Case 3: Hardware Calibratoin
367   - ldr r0, =DDR_HCAL @ DDR_HCAL
368   - ldr r1, =0x803ffc07 @ the offset is correct? -SC
369   - str r1, [r0]
370   - wait #5
371   - ldr r1, [r0]
372   - mov pc, lr
373   -*/
board/zylonite/nand.c
View file @ b66521a
1   -/*
2   - * (C) Copyright 2006 DENX Software Engineering
3   - *
4   - * See file CREDITS for list of people who contributed to this
5   - * project.
6   - *
7   - * This program is free software; you can redistribute it and/or
8   - * modify it under the terms of the GNU General Public License as
9   - * published by the Free Software Foundation; either version 2 of
10   - * the License, or (at your option) any later version.
11   - *
12   - * This program is distributed in the hope that it will be useful,
13   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
14   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15   - * GNU General Public License for more details.
16   - *
17   - * You should have received a copy of the GNU General Public License
18   - * along with this program; if not, write to the Free Software
19   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20   - * MA 02111-1307 USA
21   - */
22   -
23   -#include <common.h>
24   -#include <asm/io.h>
25   -
26   -#if defined(CONFIG_CMD_NAND)
27   -
28   -#include <nand.h>
29   -#include <asm/arch/pxa-regs.h>
30   -
31   -#ifdef CONFIG_SYS_DFC_DEBUG1
32   -# define DFC_DEBUG1(fmt, args...) printf(fmt, ##args)
33   -#else
34   -# define DFC_DEBUG1(fmt, args...)
35   -#endif
36   -
37   -#ifdef CONFIG_SYS_DFC_DEBUG2
38   -# define DFC_DEBUG2(fmt, args...) printf(fmt, ##args)
39   -#else
40   -# define DFC_DEBUG2(fmt, args...)
41   -#endif
42   -
43   -#ifdef CONFIG_SYS_DFC_DEBUG3
44   -# define DFC_DEBUG3(fmt, args...) printf(fmt, ##args)
45   -#else
46   -# define DFC_DEBUG3(fmt, args...)
47   -#endif
48   -
49   -/* These really don't belong here, as they are specific to the NAND Model */
50   -static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
51   -
52   -static struct nand_bbt_descr delta_bbt_descr = {
53   - .options = 0,
54   - .offs = 0,
55   - .len = 2,
56   - .pattern = scan_ff_pattern
57   -};
58   -
59   -static struct nand_ecclayout delta_oob = {
60   - .eccbytes = 6,
61   - .eccpos = {2, 3, 4, 5, 6, 7},
62   - .oobfree = { {8, 2}, {12, 4} }
63   -};
64   -
65   -/*
66   - * not required for Monahans DFC
67   - */
68   -static void dfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
69   -{
70   - return;
71   -}
72   -
73   -#if 0
74   -/* read device ready pin */
75   -static int dfc_device_ready(struct mtd_info *mtdinfo)
76   -{
77   - if(NDSR & NDSR_RDY)
78   - return 1;
79   - else
80   - return 0;
81   - return 0;
82   -}
83   -#endif
84   -
85   -/*
86   - * Write buf to the DFC Controller Data Buffer
87   - */
88   -static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
89   -{
90   - unsigned long bytes_multi = len & 0xfffffffc;
91   - unsigned long rest = len & 0x3;
92   - unsigned long *long_buf;
93   - int i;
94   -
95   - DFC_DEBUG2("dfc_write_buf: writing %d bytes starting with 0x%x.\n", len, *((unsigned long*) buf));
96   - if(bytes_multi) {
97   - for(i=0; i<bytes_multi; i+=4) {
98   - long_buf = (unsigned long*) &buf[i];
99   - writel(*long_buf, NDDB);
100   - }
101   - }
102   - if(rest) {
103   - printf("dfc_write_buf: ERROR, writing non 4-byte aligned data.\n");
104   - }
105   - return;
106   -}
107   -
108   -
109   -/* The original:
110   - * static void dfc_read_buf(struct mtd_info *mtd, const u_char *buf, int len)
111   - *
112   - * Shouldn't this be "u_char * const buf" ?
113   - */
114   -static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
115   -{
116   - int i=0, j;
117   -
118   - /* we have to be carefull not to overflow the buffer if len is
119   - * not a multiple of 4 */
120   - unsigned long bytes_multi = len & 0xfffffffc;
121   - unsigned long rest = len & 0x3;
122   - unsigned long *long_buf;
123   -
124   - DFC_DEBUG3("dfc_read_buf: reading %d bytes.\n", len);
125   - /* if there are any, first copy multiple of 4 bytes */
126   - if(bytes_multi) {
127   - for(i=0; i<bytes_multi; i+=4) {
128   - long_buf = (unsigned long*) &buf[i];
129   - *long_buf = readl(NDDB);
130   - }
131   - }
132   -
133   - /* ...then the rest */
134   - if(rest) {
135   - unsigned long rest_data = NDDB;
136   - for(j=0;j<rest; j++)
137   - buf[i+j] = (u_char) ((rest_data>>j) & 0xff);
138   - }
139   -
140   - return;
141   -}
142   -
143   -/*
144   - * read a word. Not implemented as not used in NAND code.
145   - */
146   -static u16 dfc_read_word(struct mtd_info *mtd)
147   -{
148   - printf("dfc_read_word: UNIMPLEMENTED.\n");
149   - return 0;
150   -}
151   -
152   -/* global var, too bad: mk@tbd: move to ->priv pointer */
153   -static unsigned long read_buf = 0;
154   -static int bytes_read = -1;
155   -
156   -/*
157   - * read a byte from NDDB Because we can only read 4 bytes from NDDB at
158   - * a time, we buffer the remaining bytes. The buffer is reset when a
159   - * new command is sent to the chip.
160   - *
161   - * WARNING:
162   - * This function is currently only used to read status and id
163   - * bytes. For these commands always 8 bytes need to be read from
164   - * NDDB. So we read and discard these bytes right now. In case this
165   - * function is used for anything else in the future, we must check
166   - * what was the last command issued and read the appropriate amount of
167   - * bytes respectively.
168   - */
169   -static u_char dfc_read_byte(struct mtd_info *mtd)
170   -{
171   - unsigned char byte;
172   - unsigned long dummy;
173   -
174   - if(bytes_read < 0) {
175   - read_buf = readl(NDDB);
176   - dummy = readl(NDDB);
177   - bytes_read = 0;
178   - }
179   - byte = (unsigned char) (read_buf>>(8 * bytes_read++));
180   - if(bytes_read >= 4)
181   - bytes_read = -1;
182   -
183   - DFC_DEBUG2("dfc_read_byte: byte %u: 0x%x of (0x%x).\n", bytes_read - 1, byte, read_buf);
184   - return byte;
185   -}
186   -
187   -/* calculate delta between OSCR values start and now */
188   -static unsigned long get_delta(unsigned long start)
189   -{
190   - unsigned long cur = readl(OSCR);
191   -
192   - if(cur < start) /* OSCR overflowed */
193   - return (cur + (start^0xffffffff));
194   - else
195   - return (cur - start);
196   -}
197   -
198   -/* delay function, this doesn't belong here */
199   -static void wait_us(unsigned long us)
200   -{
201   - unsigned long start = readl(OSCR);
202   - us = DIV_ROUND_UP(us * OSCR_CLK_FREQ, 1000);
203   -
204   - while (get_delta(start) < us) {
205   - /* do nothing */
206   - }
207   -}
208   -
209   -static void dfc_clear_nddb(void)
210   -{
211   - writel(readl(NDCR) & ~NDCR_ND_RUN, NDCR);
212   - wait_us(CONFIG_SYS_NAND_OTHER_TO);
213   -}
214   -
215   -/* wait_event with timeout */
216   -static unsigned long dfc_wait_event(unsigned long event)
217   -{
218   - unsigned long ndsr, timeout, start = readl(OSCR);
219   -
220   - if(!event)
221   - return 0xff000000;
222   - else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD))
223   - timeout = DIV_ROUND_UP(CONFIG_SYS_NAND_PROG_ERASE_TO
224   - * OSCR_CLK_FREQ, 1000);
225   - else
226   - timeout = DIV_ROUND_UP(CONFIG_SYS_NAND_OTHER_TO
227   - * OSCR_CLK_FREQ, 1000);
228   -
229   - while(1) {
230   - ndsr = readl(NDSR);
231   - if(ndsr & event) {
232   - writel(readl(NDSR) | event, NDSR);
233   - break;
234   - }
235   - if(get_delta(start) > timeout) {
236   - DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%lx.\n", event);
237   - return 0xff000000;
238   - }
239   -
240   - }
241   - return ndsr;
242   -}
243   -
244   -/* we don't always wan't to do this */
245   -static void dfc_new_cmd(void)
246   -{
247   - int retry = 0;
248   - unsigned long status;
249   -
250   - while(retry++ <= CONFIG_SYS_NAND_SENDCMD_RETRY) {
251   - /* Clear NDSR */
252   - writel(0xFFF, NDSR);
253   -
254   - /* set NDCR[NDRUN] */
255   - if (!(readl(NDCR) & NDCR_ND_RUN))
256   - writel(readl(NDCR) | NDCR_ND_RUN, NDCR);
257   -
258   - status = dfc_wait_event(NDSR_WRCMDREQ);
259   -
260   - if(status & NDSR_WRCMDREQ)
261   - return;
262   -
263   - DFC_DEBUG2("dfc_new_cmd: FAILED to get WRITECMDREQ, retry: %d.\n", retry);
264   - dfc_clear_nddb();
265   - }
266   - DFC_DEBUG1("dfc_new_cmd: giving up after %d retries.\n", retry);
267   -}
268   -
269   -/* this function is called after Programm and Erase Operations to
270   - * check for success or failure */
271   -static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this)
272   -{
273   - unsigned long ndsr=0, event=0;
274   - int state = this->state;
275   -
276   - if(state == FL_WRITING) {
277   - event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
278   - } else if(state == FL_ERASING) {
279   - event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
280   - }
281   -
282   - ndsr = dfc_wait_event(event);
283   -
284   - if((ndsr & NDSR_CS0_BBD) || (ndsr & 0xff000000))
285   - return(0x1); /* Status Read error */
286   - return 0;
287   -}
288   -
289   -/* cmdfunc send commands to the DFC */
290   -static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command,
291   - int column, int page_addr)
292   -{
293   - /* register struct nand_chip *this = mtd->priv; */
294   - unsigned long ndcb0=0, ndcb1=0, ndcb2=0, event=0;
295   -
296   - /* clear the ugly byte read buffer */
297   - bytes_read = -1;
298   - read_buf = 0;
299   -
300   - switch (command) {
301   - case NAND_CMD_READ0:
302   - DFC_DEBUG3("dfc_cmdfunc: NAND_CMD_READ0, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
303   - dfc_new_cmd();
304   - ndcb0 = (NAND_CMD_READ0 | (4<<16));
305   - column >>= 1; /* adjust for 16 bit bus */
306   - ndcb1 = (((column>>1) & 0xff) |
307   - ((page_addr<<8) & 0xff00) |
308   - ((page_addr<<8) & 0xff0000) |
309   - ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
310   - event = NDSR_RDDREQ;
311   - goto write_cmd;
312   - case NAND_CMD_READ1:
313   - DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READ1 unimplemented!\n");
314   - goto end;
315   - case NAND_CMD_READOOB:
316   - DFC_DEBUG1("dfc_cmdfunc: NAND_CMD_READOOB unimplemented!\n");
317   - goto end;
318   - case NAND_CMD_READID:
319   - dfc_new_cmd();
320   - DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READID.\n");
321   - ndcb0 = (NAND_CMD_READID | (3 << 21) | (1 << 16)); /* addr cycles*/
322   - event = NDSR_RDDREQ;
323   - goto write_cmd;
324   - case NAND_CMD_PAGEPROG:
325   - /* sent as a multicommand in NAND_CMD_SEQIN */
326   - DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_PAGEPROG empty due to multicmd.\n");
327   - goto end;
328   - case NAND_CMD_ERASE1:
329   - DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE1, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
330   - dfc_new_cmd();
331   - ndcb0 = (0xd060 | (1<<25) | (2<<21) | (1<<19) | (3<<16));
332   - ndcb1 = (page_addr & 0x00ffffff);
333   - goto write_cmd;
334   - case NAND_CMD_ERASE2:
335   - DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE2 empty due to multicmd.\n");
336   - goto end;
337   - case NAND_CMD_SEQIN:
338   - /* send PAGE_PROG command(0x1080) */
339   - dfc_new_cmd();
340   - DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
341   - ndcb0 = (0x1080 | (1<<25) | (1<<21) | (1<<19) | (4<<16));
342   - column >>= 1; /* adjust for 16 bit bus */
343   - ndcb1 = (((column>>1) & 0xff) |
344   - ((page_addr<<8) & 0xff00) |
345   - ((page_addr<<8) & 0xff0000) |
346   - ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
347   - event = NDSR_WRDREQ;
348   - goto write_cmd;
349   - case NAND_CMD_STATUS:
350   - DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_STATUS.\n");
351   - dfc_new_cmd();
352   - ndcb0 = NAND_CMD_STATUS | (4<<21);
353   - event = NDSR_RDDREQ;
354   - goto write_cmd;
355   - case NAND_CMD_RESET:
356   - DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_RESET.\n");
357   - ndcb0 = NAND_CMD_RESET | (5<<21);
358   - event = NDSR_CS0_CMDD;
359   - goto write_cmd;
360   - default:
361   - printk("dfc_cmdfunc: error, unsupported command.\n");
362   - goto end;
363   - }
364   -
365   - write_cmd:
366   - writel(ndcb0, NDCB0);
367   - writel(ndcb1, NDCB0);
368   - writel(ndcb2, NDCB0);
369   -
370   - /* wait_event: */
371   - dfc_wait_event(event);
372   - end:
373   - return;
374   -}
375   -
376   -static void dfc_gpio_init(void)
377   -{
378   - DFC_DEBUG2("Setting up DFC GPIO's.\n");
379   -
380   - /* no idea what is done here, see zylonite.c */
381   - writel(0x1, GPIO4);
382   -
383   - writel(0x00000001, DF_ALE_nWE1);
384   - writel(0x00000001, DF_ALE_nWE2);
385   - writel(0x00000001, DF_nCS0);
386   - writel(0x00000001, DF_nCS1);
387   - writel(0x00000001, DF_nWE);
388   - writel(0x00000001, DF_nRE);
389   - writel(0x00000001, DF_IO0);
390   - writel(0x00000001, DF_IO8);
391   - writel(0x00000001, DF_IO1);
392   - writel(0x00000001, DF_IO9);
393   - writel(0x00000001, DF_IO2);
394   - writel(0x00000001, DF_IO10);
395   - writel(0x00000001, DF_IO3);
396   - writel(0x00000001, DF_IO11);
397   - writel(0x00000001, DF_IO4);
398   - writel(0x00000001, DF_IO12);
399   - writel(0x00000001, DF_IO5);
400   - writel(0x00000001, DF_IO13);
401   - writel(0x00000001, DF_IO6);
402   - writel(0x00000001, DF_IO14);
403   - writel(0x00000001, DF_IO7);
404   - writel(0x00000001, DF_IO15);
405   -
406   - writel(0x1901, DF_nWE);
407   - writel(0x1901, DF_nRE);
408   - writel(0x1900, DF_CLE_nOE);
409   - writel(0x1901, DF_ALE_nWE1);
410   - writel(0x1900, DF_INT_RnB);
411   -}
412   -
413   -/*
414   - * Board-specific NAND initialization. The following members of the
415   - * argument are board-specific (per include/linux/mtd/nand_new.h):
416   - * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
417   - * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
418   - * - cmd_ctrl: hardwarespecific function for accesing control-lines
419   - * - dev_ready: hardwarespecific function for accesing device ready/busy line
420   - * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
421   - * only be provided if a hardware ECC is available
422   - * - ecc.mode: mode of ecc, see defines
423   - * - chip_delay: chip dependent delay for transfering data from array to
424   - * read regs (tR)
425   - * - options: various chip options. They can partly be set to inform
426   - * nand_scan about special functionality. See the defines for further
427   - * explanation
428   - * Members with a "?" were not set in the merged testing-NAND branch,
429   - * so they are not set here either.
430   - */
431   -int board_nand_init(struct nand_chip *nand)
432   -{
433   - unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR;
434   -
435   - /* set up GPIO Control Registers */
436   - dfc_gpio_init();
437   -
438   - /* turn on the NAND Controller Clock (104 MHz @ D0) */
439   - writel(readl(CKENA) | (CKENA_4_NAND | CKENA_9_SMC), CKENA);
440   -
441   -#undef CONFIG_SYS_TIMING_TIGHT
442   -#ifndef CONFIG_SYS_TIMING_TIGHT
443   - tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1),
444   - DFC_MAX_tCH);
445   - tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1),
446   - DFC_MAX_tCS);
447   - tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1),
448   - DFC_MAX_tWH);
449   - tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US) + 1),
450   - DFC_MAX_tWP);
451   - tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US) + 1),
452   - DFC_MAX_tRH);
453   - tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US) + 1),
454   - DFC_MAX_tRP);
455   - tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) + 1),
456   - DFC_MAX_tR);
457   - tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) + 1),
458   - DFC_MAX_tWHR);
459   - tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) + 1),
460   - DFC_MAX_tAR);
461   -#else /* this is the tight timing */
462   -
463   - tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)),
464   - DFC_MAX_tCH);
465   - tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)),
466   - DFC_MAX_tCS);
467   - tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US)),
468   - DFC_MAX_tWH);
469   - tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US)),
470   - DFC_MAX_tWP);
471   - tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US)),
472   - DFC_MAX_tRH);
473   - tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US)),
474   - DFC_MAX_tRP);
475   - tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) - tCH - 2),
476   - DFC_MAX_tR);
477   - tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) - tCH - 2),
478   - DFC_MAX_tWHR);
479   - tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) - 2),
480   - DFC_MAX_tAR);
481   -#endif /* CONFIG_SYS_TIMING_TIGHT */
482   -
483   -
484   - DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR);
485   -
486   - /* tRP value is split in the register */
487   - if(tRP & (1 << 4)) {
488   - tRP_high = 1;
489   - tRP &= ~(1 << 4);
490   - } else {
491   - tRP_high = 0;
492   - }
493   -
494   - writel((tCH << 19) |
495   - (tCS << 16) |
496   - (tWH << 11) |
497   - (tWP << 8) |
498   - (tRP_high << 6) |
499   - (tRH << 3) |
500   - (tRP << 0),
501   - NDTR0CS0);
502   -
503   - writel((tR << 16) |
504   - (tWHR << 4) |
505   - (tAR << 0),
506   - NDTR1CS0);
507   -
508   - /* If it doesn't work (unlikely) think about:
509   - * - ecc enable
510   - * - chip select don't care
511   - * - read id byte count
512   - *
513   - * Intentionally enabled by not setting bits:
514   - * - dma (DMA_EN)
515   - * - page size = 512
516   - * - cs don't care, see if we can enable later!
517   - * - row address start position (after second cycle)
518   - * - pages per block = 32
519   - * - ND_RDY : clears command buffer
520   - */
521   - /* NDCR_NCSX | /\* Chip select busy don't care *\/ */
522   -
523   - writel(NDCR_SPARE_EN | /* use the spare area */
524   - NDCR_DWIDTH_C | /* 16bit DFC data bus width */
525   - NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */
526   - (2 << 16) | /* read id count = 7 ???? mk@tbd */
527   - NDCR_ND_ARB_EN | /* enable bus arbiter */
528   - NDCR_RDYM | /* flash device ready ir masked */
529   - NDCR_CS0_PAGEDM | /* ND_nCSx page done ir masked */
530   - NDCR_CS1_PAGEDM |
531   - NDCR_CS0_CMDDM | /* ND_CSx command done ir masked */
532   - NDCR_CS1_CMDDM |
533   - NDCR_CS0_BBDM | /* ND_CSx bad block detect ir masked */
534   - NDCR_CS1_BBDM |
535   - NDCR_DBERRM | /* double bit error ir masked */
536   - NDCR_SBERRM | /* single bit error ir masked */
537   - NDCR_WRDREQM | /* write data request ir masked */
538   - NDCR_RDDREQM | /* read data request ir masked */
539   - NDCR_WRCMDREQM, /* write command request ir masked */
540   - NDCR);
541   -
542   -
543   - /* wait 10 us due to cmd buffer clear reset */
544   - /* wait(10); */
545   -
546   - nand->cmd_ctrl = dfc_hwcontrol;
547   -/* nand->dev_ready = dfc_device_ready; */
548   - nand->ecc.mode = NAND_ECC_SOFT;
549   - nand->ecc.layout = &delta_oob;
550   - nand->options = NAND_BUSWIDTH_16;
551   - nand->waitfunc = dfc_wait;
552   - nand->read_byte = dfc_read_byte;
553   - nand->read_word = dfc_read_word;
554   - nand->read_buf = dfc_read_buf;
555   - nand->write_buf = dfc_write_buf;
556   -
557   - nand->cmdfunc = dfc_cmdfunc;
558   - nand->badblock_pattern = &delta_bbt_descr;
559   - return 0;
560   -}
561   -
562   -#endif
board/zylonite/zylonite.c
View file @ b66521a
1   -/*
2   - * (C) Copyright 2002
3   - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4   - *
5   - * (C) Copyright 2002
6   - * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7   - * Marius Groeger <mgroeger@sysgo.de>
8   - *
9   - * See file CREDITS for list of people who contributed to this
10   - * project.
11   - *
12   - * This program is free software; you can redistribute it and/or
13   - * modify it under the terms of the GNU General Public License as
14   - * published by the Free Software Foundation; either version 2 of
15   - * the License, or (at your option) any later version.
16   - *
17   - * This program is distributed in the hope that it will be useful,
18   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
19   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20   - * GNU General Public License for more details.
21   - *
22   - * You should have received a copy of the GNU General Public License
23   - * along with this program; if not, write to the Free Software
24   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25   - * MA 02111-1307 USA
26   - */
27   -
28   -#include <common.h>
29   -#include <netdev.h>
30   -
31   -DECLARE_GLOBAL_DATA_PTR;
32   -
33   -/*
34   - * Miscelaneous platform dependent initialisations
35   - */
36   -
37   -int board_init (void)
38   -{
39   - /* memory and cpu-speed are setup before relocation */
40   - /* so we do _nothing_ here */
41   -
42   - /* arch number of Lubbock-Board */
43   - gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK;
44   -
45   - /* adress of boot parameters */
46   - gd->bd->bi_boot_params = 0xa0000100;
47   -
48   - return 0;
49   -}
50   -
51   -int board_late_init(void)
52   -{
53   - setenv("stdout", "serial");
54   - setenv("stderr", "serial");
55   - return 0;
56   -}
57   -
58   -
59   -int dram_init (void)
60   -{
61   - gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
62   - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
63   - gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
64   - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
65   - gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
66   - gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
67   - gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
68   - gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
69   -
70   - return 0;
71   -}
72   -
73   -#ifdef CONFIG_CMD_NET
74   -int board_eth_init(bd_t *bis)
75   -{
76   - int rc = 0;
77   -#ifdef CONFIG_SMC91111
78   - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
79   -#endif
80   - return rc;
81   -}
82   -#endif
... ... @@ -215,7 +215,6 @@
215 215 xaeniax arm pxa
216 216 xm250 arm pxa
217 217 zipitz2 arm pxa
218   -zylonite arm pxa
219 218 jornada arm sa1100
220 219 atngw100 avr32 at32ap - atmel at32ap700x
221 220 atstk1002 avr32 at32ap atstk1000 atmel at32ap700x
doc/README.scrapyard
Diff comments   View file @ b66521a
... ... @@ -11,6 +11,7 @@
11 11  
12 12 Board Arch CPU removed Commit last known maintainer/contact
13 13 =============================================================================
  14 +zylonite arm pxa - 2011-09-05
14 15 shannon arm sa1100 - 2011-09-05 Rolf Offermanns <rof@sysgo.de>
15 16 modnet50 arm arm720t - 2011-09-05 Thomas Elste <info@elste.org>
16 17 lpc2292sodimm arm arm720t - 2011-09-05
include/configs/zylonite.h
View file @ b66521a
1   -/*
2   - * (C) Copyright 2002
3   - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4   - *
5   - * (C) Copyright 2002
6   - * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7   - * Marius Groeger <mgroeger@sysgo.de>
8   - *
9   - * Configuation settings for the Zylonite board.
10   - *
11   - * See file CREDITS for list of people who contributed to this
12   - * project.
13   - *
14   - * This program is free software; you can redistribute it and/or
15   - * modify it under the terms of the GNU General Public License as
16   - * published by the Free Software Foundation; either version 2 of
17   - * the License, or (at your option) any later version.
18   - *
19   - * This program is distributed in the hope that it will be useful,
20   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
21   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22   - * GNU General Public License for more details.
23   - *
24   - * You should have received a copy of the GNU General Public License
25   - * along with this program; if not, write to the Free Software
26   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27   - * MA 02111-1307 USA
28   - */
29   -
30   -#ifndef __CONFIG_H
31   -#define __CONFIG_H
32   -
33   -/*
34   - * High Level Configuration Options
35   - * (easy to change)
36   - */
37   -#define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */
38   -#define CONFIG_CPU_PXA320
39   -#define CONFIG_ZYLONITE 1 /* Zylonite board */
40   -
41   -/* #define CONFIG_LCD 1 */
42   -#ifdef CONFIG_LCD
43   -#define CONFIG_SHARP_LM8V31
44   -#endif
45   -#undef CONFIG_MMC
46   -#define BOARD_LATE_INIT 1
47   -
48   -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
49   -
50   -/* we will never enable dcache, because we have to setup MMU first */
51   -#define CONFIG_SYS_DCACHE_OFF
52   -
53   -/*
54   - * Size of malloc() pool
55   - */
56   -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
57   -
58   -/*
59   - * Hardware drivers
60   - */
61   -
62   -#undef TURN_ON_ETHERNET
63   -#ifdef TURN_ON_ETHERNET
64   -# define CONFIG_SMC91111 1
65   -# define CONFIG_SMC91111_BASE 0x14000300
66   -# define CONFIG_SMC91111_EXT_PHY
67   -# define CONFIG_SMC_USE_32_BIT
68   -# undef CONFIG_SMC_USE_IOFUNCS /* just for use with the kernel */
69   -#endif
70   -
71   -/*
72   - * select serial console configuration
73   - */
74   -#define CONFIG_PXA_SERIAL
75   -#define CONFIG_FFUART 1
76   -
77   -/* allow to overwrite serial and ethaddr */
78   -#define CONFIG_ENV_OVERWRITE
79   -
80   -#define CONFIG_BAUDRATE 115200
81   -
82   -
83   -/*
84   - * BOOTP options
85   - */
86   -#define CONFIG_BOOTP_BOOTFILESIZE
87   -#define CONFIG_BOOTP_BOOTPATH
88   -#define CONFIG_BOOTP_GATEWAY
89   -#define CONFIG_BOOTP_HOSTNAME
90   -
91   -
92   -/*
93   - * Command line configuration.
94   - */
95   -#include <config_cmd_default.h>
96   -
97   -#ifdef TURN_ON_ETHERNET
98   - #define CONFIG_CMD_PING
99   -#else
100   - #define CONFIG_CMD_SAVEENV
101   - #define CONFIG_CMD_NAND
102   -
103   - #undef CONFIG_CMD_NET
104   - #undef CONFIG_CMD_FLASH
105   - #undef CONFIG_CMD_IMLS
106   -#endif
107   -
108   -
109   -#define CONFIG_BOOTDELAY -1
110   -#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
111   -#define CONFIG_NETMASK 255.255.0.0
112   -#define CONFIG_IPADDR 192.168.0.21
113   -#define CONFIG_SERVERIP 192.168.0.250
114   -#define CONFIG_BOOTCOMMAND "bootm 80000"
115   -#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
116   -#define CONFIG_CMDLINE_TAG
117   -#define CONFIG_TIMESTAMP
118   -
119   -#if defined(CONFIG_CMD_KGDB)
120   -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
121   -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
122   -#endif
123   -
124   -/*
125   - * Miscellaneous configurable options
126   - */
127   -#define CONFIG_SYS_HUSH_PARSER 1
128   -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
129   -
130   -#define CONFIG_SYS_LONGHELP /* undef to save memory */
131   -#ifdef CONFIG_SYS_HUSH_PARSER
132   -#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
133   -#else
134   -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
135   -#endif
136   -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
137   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
138   -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
139   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
140   -#define CONFIG_SYS_DEVICE_NULLDEV 1
141   -
142   -#define CONFIG_SYS_MEMTEST_START 0x9c000000 /* memtest works on */
143   -#define CONFIG_SYS_MEMTEST_END 0x9c400000 /* 4 ... 8 MB in DRAM */
144   -
145   -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
146   -
147   -#define CONFIG_SYS_HZ 1000
148   -
149   -/* Monahans Core Frequency */
150   -#define CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO 16 /* valid values: 8, 16, 24, 31 */
151   -#define CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO 1 /* valid values: 1, 2 */
152   -
153   - /* valid baudrates */
154   -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
155   -
156   -#ifdef CONFIG_MMC
157   -#define CONFIG_PXA_MMC
158   -#define CONFIG_CMD_MMC
159   -#define CONFIG_SYS_MMC_BASE 0xF0000000
160   -#endif
161   -
162   -/*
163   - * Stack sizes
164   - *
165   - * The stack sizes are set up in start.S using the settings below
166   - */
167   -#define CONFIG_STACKSIZE (128*1024) /* regular stack */
168   -#ifdef CONFIG_USE_IRQ
169   -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
170   -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
171   -#endif
172   -
173   -/*
174   - * Physical Memory Map
175   - */
176   -#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
177   -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
178   -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
179   -#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
180   -#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
181   -#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
182   -#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
183   -#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
184   -#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
185   -
186   -#define CONFIG_SYS_DRAM_BASE 0x80000000 /* at CS0 */
187   -#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB Ram */
188   -
189   -#undef CONFIG_SYS_SKIP_DRAM_SCRUB
190   -
191   -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
192   -#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
193   -
194   -/*
195   - * NAND Flash
196   - */
197   -#define CONFIG_SYS_NAND0_BASE 0x0
198   -#undef CONFIG_SYS_NAND1_BASE
199   -
200   -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE }
201   -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
202   -
203   -/* nand timeout values */
204   -#define CONFIG_SYS_NAND_PROG_ERASE_TO 3000
205   -#define CONFIG_SYS_NAND_OTHER_TO 100
206   -#define CONFIG_SYS_NAND_SENDCMD_RETRY 3
207   -#undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */
208   -
209   -/* NAND Timing Parameters (in ns) */
210   -#define NAND_TIMING_tCH 10
211   -#define NAND_TIMING_tCS 0
212   -#define NAND_TIMING_tWH 20
213   -#define NAND_TIMING_tWP 40
214   -
215   -#define NAND_TIMING_tRH 20
216   -#define NAND_TIMING_tRP 40
217   -
218   -#define NAND_TIMING_tR 11123
219   -#define NAND_TIMING_tWHR 100
220   -#define NAND_TIMING_tAR 10
221   -
222   -/* NAND debugging */
223   -#define CONFIG_SYS_DFC_DEBUG1 /* usefull */
224   -#undef CONFIG_SYS_DFC_DEBUG2 /* noisy */
225   -#undef CONFIG_SYS_DFC_DEBUG3 /* extremly noisy */
226   -
227   -#define CONFIG_MTD_DEBUG
228   -#define CONFIG_MTD_DEBUG_VERBOSE 1
229   -
230   -#define CONFIG_SYS_NO_FLASH 1
231   -
232   -#define CONFIG_ENV_IS_IN_NAND 1
233   -#define CONFIG_ENV_OFFSET 0x40000
234   -#define CONFIG_ENV_OFFSET_REDUND 0x44000
235   -#define CONFIG_ENV_SIZE 0x4000
236   -
237   -
238   -#endif /* __CONFIG_H */