Commit b7723f3f303d3b847e1adcb226328f432fe4b233
Committed by
Tom Warren
Tom Warren
1 parent
d3f8752ed6
Exists in
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53 other branches
tegra: fdt: sort dts files
Sort nodes in dts files according the the following rules: 1) Any nodes that already exist in any /include/d file, in the order they appear in the /include/d file. 2) Any nodes with a reg property, in order of their address. 3) Any nodes without a reg property, alphabetically by node name. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Showing 5 changed files with 268 additions and 281 deletions Side-by-side Diff
arch/arm/dts/tegra20.dtsi
| ... | ... | @@ -4,10 +4,102 @@ |
| 4 | 4 | compatible = "nvidia,tegra20"; |
| 5 | 5 | interrupt-parent = <&intc>; |
| 6 | 6 | |
| 7 | - tegra_car: clock@60006000 { | |
| 8 | - compatible = "nvidia,tegra20-car"; | |
| 9 | - reg = <0x60006000 0x1000>; | |
| 10 | - #clock-cells = <1>; | |
| 7 | + host1x { | |
| 8 | + compatible = "nvidia,tegra20-host1x", "simple-bus"; | |
| 9 | + reg = <0x50000000 0x00024000>; | |
| 10 | + interrupts = <0 65 0x04 /* mpcore syncpt */ | |
| 11 | + 0 67 0x04>; /* mpcore general */ | |
| 12 | + status = "disabled"; | |
| 13 | + | |
| 14 | + #address-cells = <1>; | |
| 15 | + #size-cells = <1>; | |
| 16 | + | |
| 17 | + ranges = <0x54000000 0x54000000 0x04000000>; | |
| 18 | + | |
| 19 | + /* video-encoding/decoding */ | |
| 20 | + mpe { | |
| 21 | + reg = <0x54040000 0x00040000>; | |
| 22 | + interrupts = <0 68 0x04>; | |
| 23 | + status = "disabled"; | |
| 24 | + }; | |
| 25 | + | |
| 26 | + /* video input */ | |
| 27 | + vi { | |
| 28 | + reg = <0x54080000 0x00040000>; | |
| 29 | + interrupts = <0 69 0x04>; | |
| 30 | + status = "disabled"; | |
| 31 | + }; | |
| 32 | + | |
| 33 | + /* EPP */ | |
| 34 | + epp { | |
| 35 | + reg = <0x540c0000 0x00040000>; | |
| 36 | + interrupts = <0 70 0x04>; | |
| 37 | + status = "disabled"; | |
| 38 | + }; | |
| 39 | + | |
| 40 | + /* ISP */ | |
| 41 | + isp { | |
| 42 | + reg = <0x54100000 0x00040000>; | |
| 43 | + interrupts = <0 71 0x04>; | |
| 44 | + status = "disabled"; | |
| 45 | + }; | |
| 46 | + | |
| 47 | + /* 2D engine */ | |
| 48 | + gr2d { | |
| 49 | + reg = <0x54140000 0x00040000>; | |
| 50 | + interrupts = <0 72 0x04>; | |
| 51 | + status = "disabled"; | |
| 52 | + }; | |
| 53 | + | |
| 54 | + /* 3D engine */ | |
| 55 | + gr3d { | |
| 56 | + reg = <0x54180000 0x00040000>; | |
| 57 | + status = "disabled"; | |
| 58 | + }; | |
| 59 | + | |
| 60 | + /* display controllers */ | |
| 61 | + dc@54200000 { | |
| 62 | + compatible = "nvidia,tegra20-dc"; | |
| 63 | + reg = <0x54200000 0x00040000>; | |
| 64 | + interrupts = <0 73 0x04>; | |
| 65 | + status = "disabled"; | |
| 66 | + | |
| 67 | + rgb { | |
| 68 | + status = "disabled"; | |
| 69 | + }; | |
| 70 | + }; | |
| 71 | + | |
| 72 | + dc@54240000 { | |
| 73 | + compatible = "nvidia,tegra20-dc"; | |
| 74 | + reg = <0x54240000 0x00040000>; | |
| 75 | + interrupts = <0 74 0x04>; | |
| 76 | + status = "disabled"; | |
| 77 | + | |
| 78 | + rgb { | |
| 79 | + status = "disabled"; | |
| 80 | + }; | |
| 81 | + }; | |
| 82 | + | |
| 83 | + /* outputs */ | |
| 84 | + hdmi { | |
| 85 | + compatible = "nvidia,tegra20-hdmi"; | |
| 86 | + reg = <0x54280000 0x00040000>; | |
| 87 | + interrupts = <0 75 0x04>; | |
| 88 | + status = "disabled"; | |
| 89 | + }; | |
| 90 | + | |
| 91 | + tvo { | |
| 92 | + compatible = "nvidia,tegra20-tvo"; | |
| 93 | + reg = <0x542c0000 0x00040000>; | |
| 94 | + interrupts = <0 76 0x04>; | |
| 95 | + status = "disabled"; | |
| 96 | + }; | |
| 97 | + | |
| 98 | + dsi { | |
| 99 | + compatible = "nvidia,tegra20-dsi"; | |
| 100 | + reg = <0x54300000 0x00040000>; | |
| 101 | + status = "disabled"; | |
| 102 | + }; | |
| 11 | 103 | }; |
| 12 | 104 | |
| 13 | 105 | intc: interrupt-controller@50041000 { |
| 14 | 106 | |
| 15 | 107 | |
| 16 | 108 | |
| 17 | 109 | |
| ... | ... | @@ -18,44 +110,33 @@ |
| 18 | 110 | < 0x50040100 0x0100 >; |
| 19 | 111 | }; |
| 20 | 112 | |
| 21 | - i2c@7000c000 { | |
| 22 | - #address-cells = <1>; | |
| 23 | - #size-cells = <0>; | |
| 24 | - compatible = "nvidia,tegra20-i2c"; | |
| 25 | - reg = <0x7000C000 0x100>; | |
| 26 | - interrupts = < 70 >; | |
| 27 | - /* PERIPH_ID_I2C1, PLL_P_OUT3 */ | |
| 28 | - clocks = <&tegra_car 12>, <&tegra_car 124>; | |
| 113 | + tegra_car: clock@60006000 { | |
| 114 | + compatible = "nvidia,tegra20-car"; | |
| 115 | + reg = <0x60006000 0x1000>; | |
| 116 | + #clock-cells = <1>; | |
| 29 | 117 | }; |
| 30 | 118 | |
| 31 | - i2c@7000c400 { | |
| 32 | - #address-cells = <1>; | |
| 33 | - #size-cells = <0>; | |
| 34 | - compatible = "nvidia,tegra20-i2c"; | |
| 35 | - reg = <0x7000C400 0x100>; | |
| 36 | - interrupts = < 116 >; | |
| 37 | - /* PERIPH_ID_I2C2, PLL_P_OUT3 */ | |
| 38 | - clocks = <&tegra_car 54>, <&tegra_car 124>; | |
| 119 | + gpio: gpio@6000d000 { | |
| 120 | + compatible = "nvidia,tegra20-gpio"; | |
| 121 | + reg = < 0x6000d000 0x1000 >; | |
| 122 | + interrupts = < 64 65 66 67 87 119 121 >; | |
| 123 | + #gpio-cells = <2>; | |
| 124 | + gpio-controller; | |
| 39 | 125 | }; |
| 40 | 126 | |
| 41 | - i2c@7000c500 { | |
| 42 | - #address-cells = <1>; | |
| 43 | - #size-cells = <0>; | |
| 44 | - compatible = "nvidia,tegra20-i2c"; | |
| 45 | - reg = <0x7000C500 0x100>; | |
| 46 | - interrupts = < 124 >; | |
| 47 | - /* PERIPH_ID_I2C3, PLL_P_OUT3 */ | |
| 48 | - clocks = <&tegra_car 67>, <&tegra_car 124>; | |
| 127 | + pinmux: pinmux@70000000 { | |
| 128 | + compatible = "nvidia,tegra20-pinmux"; | |
| 129 | + reg = < 0x70000014 0x10 /* Tri-state registers */ | |
| 130 | + 0x70000080 0x20 /* Mux registers */ | |
| 131 | + 0x700000a0 0x14 /* Pull-up/down registers */ | |
| 132 | + 0x70000868 0xa8 >; /* Pad control registers */ | |
| 49 | 133 | }; |
| 50 | 134 | |
| 51 | - i2c@7000d000 { | |
| 135 | + das@70000c00 { | |
| 52 | 136 | #address-cells = <1>; |
| 53 | 137 | #size-cells = <0>; |
| 54 | - compatible = "nvidia,tegra20-i2c-dvc"; | |
| 55 | - reg = <0x7000D000 0x200>; | |
| 56 | - interrupts = < 85 >; | |
| 57 | - /* PERIPH_ID_DVC_I2C, PLL_P_OUT3 */ | |
| 58 | - clocks = <&tegra_car 47>, <&tegra_car 124>; | |
| 138 | + compatible = "nvidia,tegra20-das"; | |
| 139 | + reg = <0x70000c00 0x80>; | |
| 59 | 140 | }; |
| 60 | 141 | |
| 61 | 142 | i2s@70002800 { |
| ... | ... | @@ -76,29 +157,6 @@ |
| 76 | 157 | dma-channel = < 1 >; |
| 77 | 158 | }; |
| 78 | 159 | |
| 79 | - das@70000c00 { | |
| 80 | - #address-cells = <1>; | |
| 81 | - #size-cells = <0>; | |
| 82 | - compatible = "nvidia,tegra20-das"; | |
| 83 | - reg = <0x70000c00 0x80>; | |
| 84 | - }; | |
| 85 | - | |
| 86 | - gpio: gpio@6000d000 { | |
| 87 | - compatible = "nvidia,tegra20-gpio"; | |
| 88 | - reg = < 0x6000d000 0x1000 >; | |
| 89 | - interrupts = < 64 65 66 67 87 119 121 >; | |
| 90 | - #gpio-cells = <2>; | |
| 91 | - gpio-controller; | |
| 92 | - }; | |
| 93 | - | |
| 94 | - pinmux: pinmux@70000000 { | |
| 95 | - compatible = "nvidia,tegra20-pinmux"; | |
| 96 | - reg = < 0x70000014 0x10 /* Tri-state registers */ | |
| 97 | - 0x70000080 0x20 /* Mux registers */ | |
| 98 | - 0x700000a0 0x14 /* Pull-up/down registers */ | |
| 99 | - 0x70000868 0xa8 >; /* Pad control registers */ | |
| 100 | - }; | |
| 101 | - | |
| 102 | 160 | serial@70006000 { |
| 103 | 161 | compatible = "nvidia,tegra20-uart"; |
| 104 | 162 | reg = <0x70006000 0x40>; |
| 105 | 163 | |
| 106 | 164 | |
| 107 | 165 | |
| 108 | 166 | |
| ... | ... | @@ -134,30 +192,71 @@ |
| 134 | 192 | interrupts = < 123 >; |
| 135 | 193 | }; |
| 136 | 194 | |
| 137 | - sdhci@c8000000 { | |
| 138 | - compatible = "nvidia,tegra20-sdhci"; | |
| 139 | - reg = <0xc8000000 0x200>; | |
| 140 | - interrupts = < 46 >; | |
| 195 | + nand: nand-controller@70008000 { | |
| 196 | + #address-cells = <1>; | |
| 197 | + #size-cells = <0>; | |
| 198 | + compatible = "nvidia,tegra20-nand"; | |
| 199 | + reg = <0x70008000 0x100>; | |
| 141 | 200 | }; |
| 142 | 201 | |
| 143 | - sdhci@c8000200 { | |
| 144 | - compatible = "nvidia,tegra20-sdhci"; | |
| 145 | - reg = <0xc8000200 0x200>; | |
| 146 | - interrupts = < 47 >; | |
| 202 | + pwm: pwm@7000a000 { | |
| 203 | + compatible = "nvidia,tegra20-pwm"; | |
| 204 | + reg = <0x7000a000 0x100>; | |
| 205 | + #pwm-cells = <2>; | |
| 147 | 206 | }; |
| 148 | 207 | |
| 149 | - sdhci@c8000400 { | |
| 150 | - compatible = "nvidia,tegra20-sdhci"; | |
| 151 | - reg = <0xc8000400 0x200>; | |
| 152 | - interrupts = < 51 >; | |
| 208 | + i2c@7000c000 { | |
| 209 | + #address-cells = <1>; | |
| 210 | + #size-cells = <0>; | |
| 211 | + compatible = "nvidia,tegra20-i2c"; | |
| 212 | + reg = <0x7000C000 0x100>; | |
| 213 | + interrupts = < 70 >; | |
| 214 | + /* PERIPH_ID_I2C1, PLL_P_OUT3 */ | |
| 215 | + clocks = <&tegra_car 12>, <&tegra_car 124>; | |
| 153 | 216 | }; |
| 154 | 217 | |
| 155 | - sdhci@c8000600 { | |
| 156 | - compatible = "nvidia,tegra20-sdhci"; | |
| 157 | - reg = <0xc8000600 0x200>; | |
| 158 | - interrupts = < 63 >; | |
| 218 | + i2c@7000c400 { | |
| 219 | + #address-cells = <1>; | |
| 220 | + #size-cells = <0>; | |
| 221 | + compatible = "nvidia,tegra20-i2c"; | |
| 222 | + reg = <0x7000C400 0x100>; | |
| 223 | + interrupts = < 116 >; | |
| 224 | + /* PERIPH_ID_I2C2, PLL_P_OUT3 */ | |
| 225 | + clocks = <&tegra_car 54>, <&tegra_car 124>; | |
| 159 | 226 | }; |
| 160 | 227 | |
| 228 | + i2c@7000c500 { | |
| 229 | + #address-cells = <1>; | |
| 230 | + #size-cells = <0>; | |
| 231 | + compatible = "nvidia,tegra20-i2c"; | |
| 232 | + reg = <0x7000C500 0x100>; | |
| 233 | + interrupts = < 124 >; | |
| 234 | + /* PERIPH_ID_I2C3, PLL_P_OUT3 */ | |
| 235 | + clocks = <&tegra_car 67>, <&tegra_car 124>; | |
| 236 | + }; | |
| 237 | + | |
| 238 | + i2c@7000d000 { | |
| 239 | + #address-cells = <1>; | |
| 240 | + #size-cells = <0>; | |
| 241 | + compatible = "nvidia,tegra20-i2c-dvc"; | |
| 242 | + reg = <0x7000D000 0x200>; | |
| 243 | + interrupts = < 85 >; | |
| 244 | + /* PERIPH_ID_DVC_I2C, PLL_P_OUT3 */ | |
| 245 | + clocks = <&tegra_car 47>, <&tegra_car 124>; | |
| 246 | + }; | |
| 247 | + | |
| 248 | + kbc@7000e200 { | |
| 249 | + compatible = "nvidia,tegra20-kbc"; | |
| 250 | + reg = <0x7000e200 0x0078>; | |
| 251 | + }; | |
| 252 | + | |
| 253 | + emc@7000f400 { | |
| 254 | + #address-cells = < 1 >; | |
| 255 | + #size-cells = < 0 >; | |
| 256 | + compatible = "nvidia,tegra20-emc"; | |
| 257 | + reg = <0x7000f400 0x200>; | |
| 258 | + }; | |
| 259 | + | |
| 161 | 260 | usb@c5000000 { |
| 162 | 261 | compatible = "nvidia,tegra20-ehci", "usb-ehci"; |
| 163 | 262 | reg = <0xc5000000 0x4000>; |
| 164 | 263 | |
| 165 | 264 | |
| 166 | 265 | |
| 167 | 266 | |
| ... | ... | @@ -183,128 +282,28 @@ |
| 183 | 282 | clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */ |
| 184 | 283 | }; |
| 185 | 284 | |
| 186 | - emc@7000f400 { | |
| 187 | - #address-cells = < 1 >; | |
| 188 | - #size-cells = < 0 >; | |
| 189 | - compatible = "nvidia,tegra20-emc"; | |
| 190 | - reg = <0x7000f400 0x200>; | |
| 285 | + sdhci@c8000000 { | |
| 286 | + compatible = "nvidia,tegra20-sdhci"; | |
| 287 | + reg = <0xc8000000 0x200>; | |
| 288 | + interrupts = < 46 >; | |
| 191 | 289 | }; |
| 192 | 290 | |
| 193 | - kbc@7000e200 { | |
| 194 | - compatible = "nvidia,tegra20-kbc"; | |
| 195 | - reg = <0x7000e200 0x0078>; | |
| 291 | + sdhci@c8000200 { | |
| 292 | + compatible = "nvidia,tegra20-sdhci"; | |
| 293 | + reg = <0xc8000200 0x200>; | |
| 294 | + interrupts = < 47 >; | |
| 196 | 295 | }; |
| 197 | 296 | |
| 198 | - nand: nand-controller@70008000 { | |
| 199 | - #address-cells = <1>; | |
| 200 | - #size-cells = <0>; | |
| 201 | - compatible = "nvidia,tegra20-nand"; | |
| 202 | - reg = <0x70008000 0x100>; | |
| 297 | + sdhci@c8000400 { | |
| 298 | + compatible = "nvidia,tegra20-sdhci"; | |
| 299 | + reg = <0xc8000400 0x200>; | |
| 300 | + interrupts = < 51 >; | |
| 203 | 301 | }; |
| 204 | 302 | |
| 205 | - pwm: pwm@7000a000 { | |
| 206 | - compatible = "nvidia,tegra20-pwm"; | |
| 207 | - reg = <0x7000a000 0x100>; | |
| 208 | - #pwm-cells = <2>; | |
| 303 | + sdhci@c8000600 { | |
| 304 | + compatible = "nvidia,tegra20-sdhci"; | |
| 305 | + reg = <0xc8000600 0x200>; | |
| 306 | + interrupts = < 63 >; | |
| 209 | 307 | }; |
| 210 | - | |
| 211 | - host1x { | |
| 212 | - compatible = "nvidia,tegra20-host1x", "simple-bus"; | |
| 213 | - reg = <0x50000000 0x00024000>; | |
| 214 | - interrupts = <0 65 0x04 /* mpcore syncpt */ | |
| 215 | - 0 67 0x04>; /* mpcore general */ | |
| 216 | - status = "disabled"; | |
| 217 | - | |
| 218 | - #address-cells = <1>; | |
| 219 | - #size-cells = <1>; | |
| 220 | - | |
| 221 | - ranges = <0x54000000 0x54000000 0x04000000>; | |
| 222 | - | |
| 223 | - /* video-encoding/decoding */ | |
| 224 | - mpe { | |
| 225 | - reg = <0x54040000 0x00040000>; | |
| 226 | - interrupts = <0 68 0x04>; | |
| 227 | - status = "disabled"; | |
| 228 | - }; | |
| 229 | - | |
| 230 | - /* video input */ | |
| 231 | - vi { | |
| 232 | - reg = <0x54080000 0x00040000>; | |
| 233 | - interrupts = <0 69 0x04>; | |
| 234 | - status = "disabled"; | |
| 235 | - }; | |
| 236 | - | |
| 237 | - /* EPP */ | |
| 238 | - epp { | |
| 239 | - reg = <0x540c0000 0x00040000>; | |
| 240 | - interrupts = <0 70 0x04>; | |
| 241 | - status = "disabled"; | |
| 242 | - }; | |
| 243 | - | |
| 244 | - /* ISP */ | |
| 245 | - isp { | |
| 246 | - reg = <0x54100000 0x00040000>; | |
| 247 | - interrupts = <0 71 0x04>; | |
| 248 | - status = "disabled"; | |
| 249 | - }; | |
| 250 | - | |
| 251 | - /* 2D engine */ | |
| 252 | - gr2d { | |
| 253 | - reg = <0x54140000 0x00040000>; | |
| 254 | - interrupts = <0 72 0x04>; | |
| 255 | - status = "disabled"; | |
| 256 | - }; | |
| 257 | - | |
| 258 | - /* 3D engine */ | |
| 259 | - gr3d { | |
| 260 | - reg = <0x54180000 0x00040000>; | |
| 261 | - status = "disabled"; | |
| 262 | - }; | |
| 263 | - | |
| 264 | - /* display controllers */ | |
| 265 | - dc@54200000 { | |
| 266 | - compatible = "nvidia,tegra20-dc"; | |
| 267 | - reg = <0x54200000 0x00040000>; | |
| 268 | - interrupts = <0 73 0x04>; | |
| 269 | - status = "disabled"; | |
| 270 | - | |
| 271 | - rgb { | |
| 272 | - status = "disabled"; | |
| 273 | - }; | |
| 274 | - }; | |
| 275 | - | |
| 276 | - dc@54240000 { | |
| 277 | - compatible = "nvidia,tegra20-dc"; | |
| 278 | - reg = <0x54240000 0x00040000>; | |
| 279 | - interrupts = <0 74 0x04>; | |
| 280 | - status = "disabled"; | |
| 281 | - | |
| 282 | - rgb { | |
| 283 | - status = "disabled"; | |
| 284 | - }; | |
| 285 | - }; | |
| 286 | - | |
| 287 | - /* outputs */ | |
| 288 | - hdmi { | |
| 289 | - compatible = "nvidia,tegra20-hdmi"; | |
| 290 | - reg = <0x54280000 0x00040000>; | |
| 291 | - interrupts = <0 75 0x04>; | |
| 292 | - status = "disabled"; | |
| 293 | - }; | |
| 294 | - | |
| 295 | - tvo { | |
| 296 | - compatible = "nvidia,tegra20-tvo"; | |
| 297 | - reg = <0x542c0000 0x00040000>; | |
| 298 | - interrupts = <0 76 0x04>; | |
| 299 | - status = "disabled"; | |
| 300 | - }; | |
| 301 | - | |
| 302 | - dsi { | |
| 303 | - compatible = "nvidia,tegra20-dsi"; | |
| 304 | - reg = <0x54300000 0x00040000>; | |
| 305 | - status = "disabled"; | |
| 306 | - }; | |
| 307 | - }; | |
| 308 | - | |
| 309 | 308 | }; |
board/avionic-design/dts/tegra20-tec.dts
| ... | ... | @@ -31,6 +31,17 @@ |
| 31 | 31 | clock-frequency = <216000000>; |
| 32 | 32 | }; |
| 33 | 33 | |
| 34 | + nand-controller@70008000 { | |
| 35 | + nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */ | |
| 36 | + nvidia,width = <8>; | |
| 37 | + nvidia,timing = <26 100 20 80 20 10 12 10 70>; | |
| 38 | + | |
| 39 | + nand@0 { | |
| 40 | + reg = <0>; | |
| 41 | + compatible = "hynix,hy27uf4g2b", "nand-flash"; | |
| 42 | + }; | |
| 43 | + }; | |
| 44 | + | |
| 34 | 45 | i2c@7000c000 { |
| 35 | 46 | status = "disabled"; |
| 36 | 47 | }; |
| ... | ... | @@ -53,17 +64,6 @@ |
| 53 | 64 | |
| 54 | 65 | usb@c5004000 { |
| 55 | 66 | status = "disabled"; |
| 56 | - }; | |
| 57 | - | |
| 58 | - nand-controller@70008000 { | |
| 59 | - nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */ | |
| 60 | - nvidia,width = <8>; | |
| 61 | - nvidia,timing = <26 100 20 80 20 10 12 10 70>; | |
| 62 | - | |
| 63 | - nand@0 { | |
| 64 | - reg = <0>; | |
| 65 | - compatible = "hynix,hy27uf4g2b", "nand-flash"; | |
| 66 | - }; | |
| 67 | 67 | }; |
| 68 | 68 | |
| 69 | 69 | lcd_panel: panel { |
board/compal/dts/tegra20-paz00.dts
| ... | ... | @@ -14,6 +14,17 @@ |
| 14 | 14 | reg = <0x00000000 0x20000000>; |
| 15 | 15 | }; |
| 16 | 16 | |
| 17 | + host1x { | |
| 18 | + status = "okay"; | |
| 19 | + dc@54200000 { | |
| 20 | + status = "okay"; | |
| 21 | + rgb { | |
| 22 | + status = "okay"; | |
| 23 | + nvidia,panel = <&lcd_panel>; | |
| 24 | + }; | |
| 25 | + }; | |
| 26 | + }; | |
| 27 | + | |
| 17 | 28 | serial@70006000 { |
| 18 | 29 | clock-frequency = < 216000000 >; |
| 19 | 30 | }; |
| ... | ... | @@ -40,17 +51,6 @@ |
| 40 | 51 | |
| 41 | 52 | usb@c5004000 { |
| 42 | 53 | status = "disabled"; |
| 43 | - }; | |
| 44 | - | |
| 45 | - host1x { | |
| 46 | - status = "okay"; | |
| 47 | - dc@54200000 { | |
| 48 | - status = "okay"; | |
| 49 | - rgb { | |
| 50 | - status = "okay"; | |
| 51 | - nvidia,panel = <&lcd_panel>; | |
| 52 | - }; | |
| 53 | - }; | |
| 54 | 54 | }; |
| 55 | 55 | |
| 56 | 56 | lcd_panel: panel { |
board/nvidia/dts/tegra20-harmony.dts
| ... | ... | @@ -19,6 +19,16 @@ |
| 19 | 19 | clock-frequency = < 216000000 >; |
| 20 | 20 | }; |
| 21 | 21 | |
| 22 | + nand-controller@70008000 { | |
| 23 | + nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */ | |
| 24 | + nvidia,width = <8>; | |
| 25 | + nvidia,timing = <26 100 20 80 20 10 12 10 70>; | |
| 26 | + nand@0 { | |
| 27 | + reg = <0>; | |
| 28 | + compatible = "hynix,hy27uf4g2b", "nand-flash"; | |
| 29 | + }; | |
| 30 | + }; | |
| 31 | + | |
| 22 | 32 | i2c@7000c000 { |
| 23 | 33 | status = "disabled"; |
| 24 | 34 | }; |
| ... | ... | @@ -41,16 +51,6 @@ |
| 41 | 51 | |
| 42 | 52 | usb@c5004000 { |
| 43 | 53 | nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ |
| 44 | - }; | |
| 45 | - | |
| 46 | - nand-controller@70008000 { | |
| 47 | - nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */ | |
| 48 | - nvidia,width = <8>; | |
| 49 | - nvidia,timing = <26 100 20 80 20 10 12 10 70>; | |
| 50 | - nand@0 { | |
| 51 | - reg = <0>; | |
| 52 | - compatible = "hynix,hy27uf4g2b", "nand-flash"; | |
| 53 | - }; | |
| 54 | 54 | }; |
| 55 | 55 | }; |
board/nvidia/dts/tegra20-seaboard.dts
| ... | ... | @@ -49,25 +49,16 @@ |
| 49 | 49 | clock-frequency = < 216000000 >; |
| 50 | 50 | }; |
| 51 | 51 | |
| 52 | - sdhci@c8000400 { | |
| 53 | - cd-gpios = <&gpio 69 0>; /* gpio PI5 */ | |
| 54 | - wp-gpios = <&gpio 57 0>; /* gpio PH1 */ | |
| 55 | - power-gpios = <&gpio 70 0>; /* gpio PI6 */ | |
| 52 | + nand-controller@70008000 { | |
| 53 | + nvidia,wp-gpios = <&gpio 59 0>; /* PH3 */ | |
| 54 | + nvidia,width = <8>; | |
| 55 | + nvidia,timing = <26 100 20 80 20 10 12 10 70>; | |
| 56 | + nand@0 { | |
| 57 | + reg = <0>; | |
| 58 | + compatible = "hynix,hy27uf4g2b", "nand-flash"; | |
| 59 | + }; | |
| 56 | 60 | }; |
| 57 | 61 | |
| 58 | - sdhci@c8000600 { | |
| 59 | - support-8bit; | |
| 60 | - }; | |
| 61 | - | |
| 62 | - usb@c5000000 { | |
| 63 | - nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */ | |
| 64 | - dr_mode = "otg"; | |
| 65 | - }; | |
| 66 | - | |
| 67 | - usb@c5004000 { | |
| 68 | - status = "disabled"; | |
| 69 | - }; | |
| 70 | - | |
| 71 | 62 | i2c@7000c000 { |
| 72 | 63 | clock-frequency = <100000>; |
| 73 | 64 | }; |
| ... | ... | @@ -80,6 +71,33 @@ |
| 80 | 71 | clock-frequency = <100000>; |
| 81 | 72 | }; |
| 82 | 73 | |
| 74 | + kbc@7000e200 { | |
| 75 | + linux,keymap = <0x00020011 0x0003001f 0x0004001e 0x0005002c | |
| 76 | + 0x000701d0 0x0107007d 0x02060064 0x02070038 0x03000006 | |
| 77 | + 0x03010005 0x03020013 0x03030012 0x03040021 0x03050020 | |
| 78 | + 0x0306002d 0x04000008 0x04010007 0x04020014 0x04030023 | |
| 79 | + 0x04040022 0x0405002f 0x0406002e 0x04070039 0x0500000a | |
| 80 | + 0x05010009 0x05020016 0x05030015 0x05040024 0x05050031 | |
| 81 | + 0x05060030 0x0507002b 0x0600000c 0x0601000b 0x06020018 | |
| 82 | + 0x06030017 0x06040026 0x06050025 0x06060033 0x06070032 | |
| 83 | + 0x0701000d 0x0702001b 0x0703001c 0x0707008b 0x08040036 | |
| 84 | + 0x0805002a 0x09050061 0x0907001d 0x0b00001a 0x0b010019 | |
| 85 | + 0x0b020028 0x0b030027 0x0b040035 0x0b050034 0x0c000044 | |
| 86 | + 0x0c010043 0x0c02000e 0x0c030004 0x0c040003 0x0c050067 | |
| 87 | + 0x0c0600d2 0x0c070077 0x0d00006e 0x0d01006f 0x0d030068 | |
| 88 | + 0x0d04006d 0x0d05006a 0x0d06006c 0x0d070069 0x0e000057 | |
| 89 | + 0x0e010058 0x0e020042 0x0e030010 0x0e04003e 0x0e05003d | |
| 90 | + 0x0e060002 0x0e070041 0x0f000001 0x0f010029 0x0f02003f | |
| 91 | + 0x0f03000f 0x0f04003b 0x0f05003c 0x0f06003a 0x0f070040 | |
| 92 | + 0x14000047 0x15000049 0x15010048 0x1502004b 0x1504004f | |
| 93 | + 0x16010062 0x1602004d 0x1603004c 0x16040051 0x16050050 | |
| 94 | + 0x16070052 0x1b010037 0x1b03004a 0x1b04004e 0x1b050053 | |
| 95 | + 0x1c050073 0x1d030066 0x1d04006b 0x1d0500e0 0x1d060072 | |
| 96 | + 0x1d0700e1 0x1e000045 0x1e010046 0x1e020071 | |
| 97 | + 0x1f04008a>; | |
| 98 | + linux,fn-keymap = <0x05040002>; | |
| 99 | + }; | |
| 100 | + | |
| 83 | 101 | emc@7000f400 { |
| 84 | 102 | emc-table@190000 { |
| 85 | 103 | reg = < 190000 >; |
| 86 | 104 | |
| 87 | 105 | |
| 88 | 106 | |
| ... | ... | @@ -117,54 +135,25 @@ |
| 117 | 135 | }; |
| 118 | 136 | }; |
| 119 | 137 | |
| 120 | - kbc@7000e200 { | |
| 121 | - linux,keymap = <0x00020011 0x0003001f 0x0004001e 0x0005002c | |
| 122 | - 0x000701d0 0x0107007d 0x02060064 0x02070038 0x03000006 | |
| 123 | - 0x03010005 0x03020013 0x03030012 0x03040021 0x03050020 | |
| 124 | - 0x0306002d 0x04000008 0x04010007 0x04020014 0x04030023 | |
| 125 | - 0x04040022 0x0405002f 0x0406002e 0x04070039 0x0500000a | |
| 126 | - 0x05010009 0x05020016 0x05030015 0x05040024 0x05050031 | |
| 127 | - 0x05060030 0x0507002b 0x0600000c 0x0601000b 0x06020018 | |
| 128 | - 0x06030017 0x06040026 0x06050025 0x06060033 0x06070032 | |
| 129 | - 0x0701000d 0x0702001b 0x0703001c 0x0707008b 0x08040036 | |
| 130 | - 0x0805002a 0x09050061 0x0907001d 0x0b00001a 0x0b010019 | |
| 131 | - 0x0b020028 0x0b030027 0x0b040035 0x0b050034 0x0c000044 | |
| 132 | - 0x0c010043 0x0c02000e 0x0c030004 0x0c040003 0x0c050067 | |
| 133 | - 0x0c0600d2 0x0c070077 0x0d00006e 0x0d01006f 0x0d030068 | |
| 134 | - 0x0d04006d 0x0d05006a 0x0d06006c 0x0d070069 0x0e000057 | |
| 135 | - 0x0e010058 0x0e020042 0x0e030010 0x0e04003e 0x0e05003d | |
| 136 | - 0x0e060002 0x0e070041 0x0f000001 0x0f010029 0x0f02003f | |
| 137 | - 0x0f03000f 0x0f04003b 0x0f05003c 0x0f06003a 0x0f070040 | |
| 138 | - 0x14000047 0x15000049 0x15010048 0x1502004b 0x1504004f | |
| 139 | - 0x16010062 0x1602004d 0x1603004c 0x16040051 0x16050050 | |
| 140 | - 0x16070052 0x1b010037 0x1b03004a 0x1b04004e 0x1b050053 | |
| 141 | - 0x1c050073 0x1d030066 0x1d04006b 0x1d0500e0 0x1d060072 | |
| 142 | - 0x1d0700e1 0x1e000045 0x1e010046 0x1e020071 | |
| 143 | - 0x1f04008a>; | |
| 144 | - linux,fn-keymap = <0x05040002>; | |
| 138 | + usb@c5000000 { | |
| 139 | + nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */ | |
| 140 | + dr_mode = "otg"; | |
| 145 | 141 | }; |
| 146 | 142 | |
| 147 | - nand-controller@70008000 { | |
| 148 | - nvidia,wp-gpios = <&gpio 59 0>; /* PH3 */ | |
| 149 | - nvidia,width = <8>; | |
| 150 | - nvidia,timing = <26 100 20 80 20 10 12 10 70>; | |
| 151 | - nand@0 { | |
| 152 | - reg = <0>; | |
| 153 | - compatible = "hynix,hy27uf4g2b", "nand-flash"; | |
| 154 | - }; | |
| 143 | + usb@c5004000 { | |
| 144 | + status = "disabled"; | |
| 155 | 145 | }; |
| 156 | 146 | |
| 157 | - host1x { | |
| 158 | - status = "okay"; | |
| 159 | - dc@54200000 { | |
| 160 | - status = "okay"; | |
| 161 | - rgb { | |
| 162 | - status = "okay"; | |
| 163 | - nvidia,panel = <&lcd_panel>; | |
| 164 | - }; | |
| 165 | - }; | |
| 147 | + sdhci@c8000400 { | |
| 148 | + cd-gpios = <&gpio 69 0>; /* gpio PI5 */ | |
| 149 | + wp-gpios = <&gpio 57 0>; /* gpio PH1 */ | |
| 150 | + power-gpios = <&gpio 70 0>; /* gpio PI6 */ | |
| 166 | 151 | }; |
| 167 | 152 | |
| 153 | + sdhci@c8000600 { | |
| 154 | + support-8bit; | |
| 155 | + }; | |
| 156 | + | |
| 168 | 157 | lcd_panel: panel { |
| 169 | 158 | /* Seaboard has 1366x768 */ |
| 170 | 159 | clock = <70600000>; |
| ... | ... | @@ -185,6 +174,5 @@ |
| 185 | 174 | nvidia,panel-vdd-gpios = <&gpio 22 0>; /* PC6 */ |
| 186 | 175 | nvidia,panel-timings = <400 4 203 17 15>; |
| 187 | 176 | }; |
| 188 | - | |
| 189 | 177 | }; |