Eric Lee / smarc-uboot

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Commit b79dadf846e5e140e261bbfa4decd024357702d7

Authored by Tom Rini
2 parents 1fc42018a0 d5338c693e
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

Merge branch 'master' of git://git.denx.de/u-boot-tegra 

Conflicts:
	README

Signed-off-by: Tom Rini <trini@konsulko.com>

Showing 53 changed files Side-by-side Diff

... ... @@ -690,6 +690,125 @@
690 690 exists, unlike the similar options in the Linux kernel. Do not
691 691 set these options unless they apply!
692 692  
  693 +- Tegra SoC options:
  694 + CONFIG_TEGRA_SUPPORT_NON_SECURE
  695 +
  696 + Support executing U-Boot in non-secure (NS) mode. Certain
  697 + impossible actions will be skipped if the CPU is in NS mode,
  698 + such as ARM architectural timer initialization.
  699 +
  700 +- Driver Model
  701 + Driver model is a new framework for devices in U-Boot
  702 + introduced in early 2014. U-Boot is being progressively
  703 + moved over to this. It offers a consistent device structure,
  704 + supports grouping devices into classes and has built-in
  705 + handling of platform data and device tree.
  706 +
  707 + To enable transition to driver model in a relatively
  708 + painful fashion, each subsystem can be independently
  709 + switched between the legacy/ad-hoc approach and the new
  710 + driver model using the options below. Also, many uclass
  711 + interfaces include compatibility features which may be
  712 + removed once the conversion of that subsystem is complete.
  713 + As a result, the API provided by the subsystem may in fact
  714 + not change with driver model.
  715 +
  716 + See doc/driver-model/README.txt for more information.
  717 +
  718 + CONFIG_DM
  719 +
  720 + Enable driver model. This brings in the core support,
  721 + including scanning of platform data on start-up. If
  722 + CONFIG_OF_CONTROL is enabled, the device tree will be
  723 + scanned also when available.
  724 +
  725 + CONFIG_CMD_DM
  726 +
  727 + Enable driver model test commands. These allow you to print
  728 + out the driver model tree and the uclasses.
  729 +
  730 + CONFIG_DM_DEMO
  731 +
  732 + Enable some demo devices and the 'demo' command. These are
  733 + really only useful for playing around while trying to
  734 + understand driver model in sandbox.
  735 +
  736 + CONFIG_SPL_DM
  737 +
  738 + Enable driver model in SPL. You will need to provide a
  739 + suitable malloc() implementation. If you are not using the
  740 + full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START,
  741 + consider using CONFIG_SYS_MALLOC_SIMPLE. In that case you
  742 + must provide CONFIG_SYS_MALLOC_F_LEN to set the size.
  743 + In most cases driver model will only allocate a few uclasses
  744 + and devices in SPL, so 1KB should be enable. See
  745 + CONFIG_SYS_MALLOC_F_LEN for more details on how to enable
  746 + it.
  747 +
  748 + CONFIG_DM_SERIAL
  749 +
  750 + Enable driver model for serial. This replaces
  751 + drivers/serial/serial.c with the serial uclass, which
  752 + implements serial_putc() etc. The uclass interface is
  753 + defined in include/serial.h.
  754 +
  755 + CONFIG_DM_GPIO
  756 +
  757 + Enable driver model for GPIO access. The standard GPIO
  758 + interface (gpio_get_value(), etc.) is then implemented by
  759 + the GPIO uclass. Drivers provide methods to query the
  760 + particular GPIOs that they provide. The uclass interface
  761 + is defined in include/asm-generic/gpio.h.
  762 +
  763 + CONFIG_DM_SPI
  764 +
  765 + Enable driver model for SPI. The SPI slave interface
  766 + (spi_setup_slave(), spi_xfer(), etc.) is then implemented by
  767 + the SPI uclass. Drivers provide methods to access the SPI
  768 + buses that they control. The uclass interface is defined in
  769 + include/spi.h. The existing spi_slave structure is attached
  770 + as 'parent data' to every slave on each bus. Slaves
  771 + typically use driver-private data instead of extending the
  772 + spi_slave structure.
  773 +
  774 + CONFIG_DM_SPI_FLASH
  775 +
  776 + Enable driver model for SPI flash. This SPI flash interface
  777 + (spi_flash_probe(), spi_flash_write(), etc.) is then
  778 + implemented by the SPI flash uclass. There is one standard
  779 + SPI flash driver which knows how to probe most chips
  780 + supported by U-Boot. The uclass interface is defined in
  781 + include/spi_flash.h, but is currently fully compatible
  782 + with the old interface to avoid confusion and duplication
  783 + during the transition parent. SPI and SPI flash must be
  784 + enabled together (it is not possible to use driver model
  785 + for one and not the other).
  786 +
  787 + CONFIG_DM_CROS_EC
  788 +
  789 + Enable driver model for the Chrome OS EC interface. This
  790 + allows the cros_ec SPI driver to operate with CONFIG_DM_SPI
  791 + but otherwise makes few changes. Since cros_ec also supports
  792 + I2C and LPC (which don't support driver model yet), a full
  793 + conversion is not yet possible.
  794 +
  795 +
  796 + ** Code size options: The following options are enabled by
  797 + default except in SPL. Enable them explicitly to get these
  798 + features in SPL.
  799 +
  800 + CONFIG_DM_WARN
  801 +
  802 + Enable the dm_warn() function. This can use up quite a bit
  803 + of space for its strings.
  804 +
  805 + CONFIG_DM_STDIO
  806 +
  807 + Enable registering a serial device with the stdio library.
  808 +
  809 + CONFIG_DM_DEVICE_REMOVE
  810 +
  811 + Enable removing of devices.
693 812  
694 813 - Linux Kernel Interface:
695 814 CONFIG_CLOCKS_IN_MHZ
arch/arm/cpu/arm926ejs/orion5x/u-boot-spl.lds
Diff comments   View file @ b79dadf
  1 +/*
  2 + * (C) Copyright 2014 Albert ARIBAUD <albert.u.boot@aribaud.net>
  3 + *
  4 + * Based on:
  5 + *
  6 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  7 + * Tom Cubie <tangliang@allwinnertech.com>
  8 + *
  9 + * Based on omap-common/u-boot-spl.lds:
  10 + *
  11 + * (C) Copyright 2002
  12 + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
  13 + *
  14 + * (C) Copyright 2010
  15 + * Texas Instruments, <www.ti.com>
  16 + * Aneesh V <aneesh@ti.com>
  17 + *
  18 + * SPDX-License-Identifier: GPL-2.0+
  19 + */
  20 +MEMORY { .nor : ORIGIN = CONFIG_SPL_TEXT_BASE,\
  21 + LENGTH = CONFIG_SPL_MAX_SIZE }
  22 +MEMORY { .bss : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
  23 + LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
  24 +
  25 +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
  26 +OUTPUT_ARCH(arm)
  27 +ENTRY(_start)
  28 +SECTIONS
  29 +{
  30 + .text :
  31 + {
  32 + __start = .;
  33 + *(.vectors)
  34 + CPUDIR/start.o (.text)
  35 + *(.text*)
  36 + } > .nor
  37 +
  38 + . = ALIGN(4);
  39 + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.nor
  40 +
  41 + . = ALIGN(4);
  42 + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.nor
  43 +
  44 + . = ALIGN(4);
  45 + .u_boot_list : {
  46 + KEEP(*(SORT(.u_boot_list*)));
  47 + } > .nor
  48 +
  49 + . = ALIGN(4);
  50 + __image_copy_end = .;
  51 + _end = .;
  52 +
  53 + .bss :
  54 + {
  55 + . = ALIGN(4);
  56 + __bss_start = .;
  57 + *(.bss*)
  58 + . = ALIGN(4);
  59 + __bss_end = .;
  60 + } > .bss
  61 +}
arch/arm/cpu/armv7/virt-v7.c
Diff comments   View file @ b79dadf
... ... @@ -112,13 +112,20 @@
112 112 for (i = 1; i <= itlinesnr; i++)
113 113 writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i);
114 114  
  115 + /*
  116 + * Relocate secure section before any cpu runs in secure ram.
  117 + * smp_kick_all_cpus may enable other cores and runs into secure
  118 + * ram, so need to relocate secure section before enabling other
  119 + * cores.
  120 + */
  121 + relocate_secure_section();
  122 +
115 123 #ifndef CONFIG_ARMV7_PSCI
116 124 smp_set_core_boot_addr((unsigned long)secure_ram_addr(_smp_pen), -1);
117 125 smp_kick_all_cpus();
118 126 #endif
119 127  
120 128 /* call the non-sec switching code on this CPU also */
121   - relocate_secure_section();
122 129 secure_ram_addr(_nonsec_init)();
123 130 return 0;
124 131 }
arch/arm/cpu/armv8/start.S
Diff comments   View file @ b79dadf
... ... @@ -67,6 +67,9 @@
67 67 msr cpacr_el1, x0 /* Enable FP/SIMD */
68 68 0:
69 69  
  70 + /* Apply ARM core specific erratas */
  71 + bl apply_core_errata
  72 +
70 73 /*
71 74 * Cache/BPB/TLB Invalidate
72 75 * i-cache is invalidated before enabled in icache_enable()
... ... @@ -94,6 +97,48 @@
94 97 #endif /* CONFIG_ARMV8_MULTIENTRY */
95 98  
96 99 bl _main
  100 +
  101 +/*-----------------------------------------------------------------------*/
  102 +
  103 +WEAK(apply_core_errata)
  104 +
  105 + mov x29, lr /* Save LR */
  106 + /* For now, we support Cortex-A57 specific errata only */
  107 +
  108 + /* Check if we are running on a Cortex-A57 core */
  109 + branch_if_a57_core x0, apply_a57_core_errata
  110 +0:
  111 + mov lr, x29 /* Restore LR */
  112 + ret
  113 +
  114 +apply_a57_core_errata:
  115 +
  116 +#ifdef CONFIG_ARM_ERRATA_828024
  117 + mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
  118 + /* Disable non-allocate hint of w-b-n-a memory type */
  119 + mov x0, #0x1 << 49
  120 + /* Disable write streaming no L1-allocate threshold */
  121 + mov x0, #0x3 << 25
  122 + /* Disable write streaming no-allocate threshold */
  123 + mov x0, #0x3 << 27
  124 + msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
  125 +#endif
  126 +
  127 +#ifdef CONFIG_ARM_ERRATA_826974
  128 + mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
  129 + /* Disable speculative load execution ahead of a DMB */
  130 + mov x0, #0x1 << 59
  131 + msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
  132 +#endif
  133 +
  134 +#ifdef CONFIG_ARM_ERRATA_833069
  135 + mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
  136 + /* Disable Enable Invalidates of BTB bit */
  137 + and x0, x0, #0xE
  138 + msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
  139 +#endif
  140 + b 0b
  141 +ENDPROC(apply_core_errata)
97 142  
98 143 /*-----------------------------------------------------------------------*/
99 144  
arch/arm/cpu/tegra210-common/pinmux.c
Diff comments   View file @ b79dadf
  1 +/*
  2 + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <asm/io.h>
  9 +#include <asm/arch/pinmux.h>
  10 +
  11 +#define PIN(pin, f0, f1, f2, f3) \
  12 + { \
  13 + .funcs = { \
  14 + PMUX_FUNC_##f0, \
  15 + PMUX_FUNC_##f1, \
  16 + PMUX_FUNC_##f2, \
  17 + PMUX_FUNC_##f3, \
  18 + }, \
  19 + }
  20 +
  21 +#define PIN_RESERVED {}
  22 +
  23 +static const struct pmux_pingrp_desc tegra210_pingroups[] = {
  24 + /* pin, f0, f1, f2, f3 */
  25 + /* Offset 0x3000 */
  26 + PIN(SDMMC1_CLK_PM0, SDMMC1, RSVD1, RSVD2, RSVD3),
  27 + PIN(SDMMC1_CMD_PM1, SDMMC1, SPI3, RSVD2, RSVD3),
  28 + PIN(SDMMC1_DAT3_PM2, SDMMC1, SPI3, RSVD2, RSVD3),
  29 + PIN(SDMMC1_DAT2_PM3, SDMMC1, SPI3, RSVD2, RSVD3),
  30 + PIN(SDMMC1_DAT1_PM4, SDMMC1, SPI3, RSVD2, RSVD3),
  31 + PIN(SDMMC1_DAT0_PM5, SDMMC1, RSVD1, RSVD2, RSVD3),
  32 + PIN_RESERVED,
  33 + /* Offset 0x301c */
  34 + PIN(SDMMC3_CLK_PP0, SDMMC3, RSVD1, RSVD2, RSVD3),
  35 + PIN(SDMMC3_CMD_PP1, SDMMC3, RSVD1, RSVD2, RSVD3),
  36 + PIN(SDMMC3_DAT0_PP5, SDMMC3, RSVD1, RSVD2, RSVD3),
  37 + PIN(SDMMC3_DAT1_PP4, SDMMC3, RSVD1, RSVD2, RSVD3),
  38 + PIN(SDMMC3_DAT2_PP3, SDMMC3, RSVD1, RSVD2, RSVD3),
  39 + PIN(SDMMC3_DAT3_PP2, SDMMC3, RSVD1, RSVD2, RSVD3),
  40 + PIN_RESERVED,
  41 + /* Offset 0x3038 */
  42 + PIN(PEX_L0_RST_N_PA0, PE0, RSVD1, RSVD2, RSVD3),
  43 + PIN(PEX_L0_CLKREQ_N_PA1, PE0, RSVD1, RSVD2, RSVD3),
  44 + PIN(PEX_WAKE_N_PA2, PE, RSVD1, RSVD2, RSVD3),
  45 + PIN(PEX_L1_RST_N_PA3, PE1, RSVD1, RSVD2, RSVD3),
  46 + PIN(PEX_L1_CLKREQ_N_PA4, PE1, RSVD1, RSVD2, RSVD3),
  47 + PIN(SATA_LED_ACTIVE_PA5, SATA, RSVD1, RSVD2, RSVD3),
  48 + PIN(SPI1_MOSI_PC0, SPI1, RSVD1, RSVD2, RSVD3),
  49 + PIN(SPI1_MISO_PC1, SPI1, RSVD1, RSVD2, RSVD3),
  50 + PIN(SPI1_SCK_PC2, SPI1, RSVD1, RSVD2, RSVD3),
  51 + PIN(SPI1_CS0_PC3, SPI1, RSVD1, RSVD2, RSVD3),
  52 + PIN(SPI1_CS1_PC4, SPI1, RSVD1, RSVD2, RSVD3),
  53 + PIN(SPI2_MOSI_PB4, SPI2, DTV, RSVD2, RSVD3),
  54 + PIN(SPI2_MISO_PB5, SPI2, DTV, RSVD2, RSVD3),
  55 + PIN(SPI2_SCK_PB6, SPI2, DTV, RSVD2, RSVD3),
  56 + PIN(SPI2_CS0_PB7, SPI2, DTV, RSVD2, RSVD3),
  57 + PIN(SPI2_CS1_PDD0, SPI2, RSVD1, RSVD2, RSVD3),
  58 + PIN(SPI4_MOSI_PC7, SPI4, RSVD1, RSVD2, RSVD3),
  59 + PIN(SPI4_MISO_PD0, SPI4, RSVD1, RSVD2, RSVD3),
  60 + PIN(SPI4_SCK_PC5, SPI4, RSVD1, RSVD2, RSVD3),
  61 + PIN(SPI4_CS0_PC6, SPI4, RSVD1, RSVD2, RSVD3),
  62 + PIN(QSPI_SCK_PEE0, QSPI, RSVD1, RSVD2, RSVD3),
  63 + PIN(QSPI_CS_N_PEE1, QSPI, RSVD1, RSVD2, RSVD3),
  64 + PIN(QSPI_IO0_PEE2, QSPI, RSVD1, RSVD2, RSVD3),
  65 + PIN(QSPI_IO1_PEE3, QSPI, RSVD1, RSVD2, RSVD3),
  66 + PIN(QSPI_IO2_PEE4, QSPI, RSVD1, RSVD2, RSVD3),
  67 + PIN(QSPI_IO3_PEE5, QSPI, RSVD1, RSVD2, RSVD3),
  68 + PIN_RESERVED,
  69 + /* Offset 0x30a4 */
  70 + PIN(DMIC1_CLK_PE0, DMIC1, I2S3, RSVD2, RSVD3),
  71 + PIN(DMIC1_DAT_PE1, DMIC1, I2S3, RSVD2, RSVD3),
  72 + PIN(DMIC2_CLK_PE2, DMIC2, I2S3, RSVD2, RSVD3),
  73 + PIN(DMIC2_DAT_PE3, DMIC2, I2S3, RSVD2, RSVD3),
  74 + PIN(DMIC3_CLK_PE4, DMIC3, I2S5A, RSVD2, RSVD3),
  75 + PIN(DMIC3_DAT_PE5, DMIC3, I2S5A, RSVD2, RSVD3),
  76 + PIN(GEN1_I2C_SCL_PJ1, I2C1, RSVD1, RSVD2, RSVD3),
  77 + PIN(GEN1_I2C_SDA_PJ0, I2C1, RSVD1, RSVD2, RSVD3),
  78 + PIN(GEN2_I2C_SCL_PJ2, I2C2, RSVD1, RSVD2, RSVD3),
  79 + PIN(GEN2_I2C_SDA_PJ3, I2C2, RSVD1, RSVD2, RSVD3),
  80 + PIN(GEN3_I2C_SCL_PF0, I2C3, RSVD1, RSVD2, RSVD3),
  81 + PIN(GEN3_I2C_SDA_PF1, I2C3, RSVD1, RSVD2, RSVD3),
  82 + PIN(CAM_I2C_SCL_PS2, I2C3, I2CVI, RSVD2, RSVD3),
  83 + PIN(CAM_I2C_SDA_PS3, I2C3, I2CVI, RSVD2, RSVD3),
  84 + PIN(PWR_I2C_SCL_PY3, I2CPMU, RSVD1, RSVD2, RSVD3),
  85 + PIN(PWR_I2C_SDA_PY4, I2CPMU, RSVD1, RSVD2, RSVD3),
  86 + PIN(UART1_TX_PU0, UARTA, RSVD1, RSVD2, RSVD3),
  87 + PIN(UART1_RX_PU1, UARTA, RSVD1, RSVD2, RSVD3),
  88 + PIN(UART1_RTS_PU2, UARTA, RSVD1, RSVD2, RSVD3),
  89 + PIN(UART1_CTS_PU3, UARTA, RSVD1, RSVD2, RSVD3),
  90 + PIN(UART2_TX_PG0, UARTB, I2S4A, SPDIF, UART),
  91 + PIN(UART2_RX_PG1, UARTB, I2S4A, SPDIF, UART),
  92 + PIN(UART2_RTS_PG2, UARTB, I2S4A, RSVD2, UART),
  93 + PIN(UART2_CTS_PG3, UARTB, I2S4A, RSVD2, UART),
  94 + PIN(UART3_TX_PD1, UARTC, SPI4, RSVD2, RSVD3),
  95 + PIN(UART3_RX_PD2, UARTC, SPI4, RSVD2, RSVD3),
  96 + PIN(UART3_RTS_PD3, UARTC, SPI4, RSVD2, RSVD3),
  97 + PIN(UART3_CTS_PD4, UARTC, SPI4, RSVD2, RSVD3),
  98 + PIN(UART4_TX_PI4, UARTD, UART, RSVD2, RSVD3),
  99 + PIN(UART4_RX_PI5, UARTD, UART, RSVD2, RSVD3),
  100 + PIN(UART4_RTS_PI6, UARTD, UART, RSVD2, RSVD3),
  101 + PIN(UART4_CTS_PI7, UARTD, UART, RSVD2, RSVD3),
  102 + PIN(DAP1_FS_PB0, I2S1, RSVD1, RSVD2, RSVD3),
  103 + PIN(DAP1_DIN_PB1, I2S1, RSVD1, RSVD2, RSVD3),
  104 + PIN(DAP1_DOUT_PB2, I2S1, RSVD1, RSVD2, RSVD3),
  105 + PIN(DAP1_SCLK_PB3, I2S1, RSVD1, RSVD2, RSVD3),
  106 + PIN(DAP2_FS_PAA0, I2S2, RSVD1, RSVD2, RSVD3),
  107 + PIN(DAP2_DIN_PAA2, I2S2, RSVD1, RSVD2, RSVD3),
  108 + PIN(DAP2_DOUT_PAA3, I2S2, RSVD1, RSVD2, RSVD3),
  109 + PIN(DAP2_SCLK_PAA1, I2S2, RSVD1, RSVD2, RSVD3),
  110 + PIN(DAP4_FS_PJ4, I2S4B, RSVD1, RSVD2, RSVD3),
  111 + PIN(DAP4_DIN_PJ5, I2S4B, RSVD1, RSVD2, RSVD3),
  112 + PIN(DAP4_DOUT_PJ6, I2S4B, RSVD1, RSVD2, RSVD3),
  113 + PIN(DAP4_SCLK_PJ7, I2S4B, RSVD1, RSVD2, RSVD3),
  114 + PIN(CAM1_MCLK_PS0, EXTPERIPH3, RSVD1, RSVD2, RSVD3),
  115 + PIN(CAM2_MCLK_PS1, EXTPERIPH3, RSVD1, RSVD2, RSVD3),
  116 + PIN(JTAG_RTCK, JTAG, RSVD1, RSVD2, RSVD3),
  117 + PIN(CLK_32K_IN, CLK, RSVD1, RSVD2, RSVD3),
  118 + PIN(CLK_32K_OUT_PY5, SOC, BLINK, RSVD2, RSVD3),
  119 + PIN(BATT_BCL, BCL, RSVD1, RSVD2, RSVD3),
  120 + PIN(CLK_REQ, SYS, RSVD1, RSVD2, RSVD3),
  121 + PIN(CPU_PWR_REQ, CPU, RSVD1, RSVD2, RSVD3),
  122 + PIN(PWR_INT_N, PMI, RSVD1, RSVD2, RSVD3),
  123 + PIN(SHUTDOWN, SHUTDOWN, RSVD1, RSVD2, RSVD3),
  124 + PIN(CORE_PWR_REQ, CORE, RSVD1, RSVD2, RSVD3),
  125 + PIN(AUD_MCLK_PBB0, AUD, RSVD1, RSVD2, RSVD3),
  126 + PIN(DVFS_PWM_PBB1, RSVD0, CLDVFS, SPI3, RSVD3),
  127 + PIN(DVFS_CLK_PBB2, RSVD0, CLDVFS, SPI3, RSVD3),
  128 + PIN(GPIO_X1_AUD_PBB3, RSVD0, RSVD1, SPI3, RSVD3),
  129 + PIN(GPIO_X3_AUD_PBB4, RSVD0, RSVD1, SPI3, RSVD3),
  130 + PIN(PCC7, RSVD0, RSVD1, RSVD2, RSVD3),
  131 + PIN(HDMI_CEC_PCC0, CEC, RSVD1, RSVD2, RSVD3),
  132 + PIN(HDMI_INT_DP_HPD_PCC1, DP, RSVD1, RSVD2, RSVD3),
  133 + PIN(SPDIF_OUT_PCC2, SPDIF, RSVD1, RSVD2, RSVD3),
  134 + PIN(SPDIF_IN_PCC3, SPDIF, RSVD1, RSVD2, RSVD3),
  135 + PIN(USB_VBUS_EN0_PCC4, USB, RSVD1, RSVD2, RSVD3),
  136 + PIN(USB_VBUS_EN1_PCC5, USB, RSVD1, RSVD2, RSVD3),
  137 + PIN(DP_HPD0_PCC6, DP, RSVD1, RSVD2, RSVD3),
  138 + PIN(WIFI_EN_PH0, RSVD0, RSVD1, RSVD2, RSVD3),
  139 + PIN(WIFI_RST_PH1, RSVD0, RSVD1, RSVD2, RSVD3),
  140 + PIN(WIFI_WAKE_AP_PH2, RSVD0, RSVD1, RSVD2, RSVD3),
  141 + PIN(AP_WAKE_BT_PH3, RSVD0, UARTB, SPDIF, RSVD3),
  142 + PIN(BT_RST_PH4, RSVD0, UARTB, SPDIF, RSVD3),
  143 + PIN(BT_WAKE_AP_PH5, RSVD0, RSVD1, RSVD2, RSVD3),
  144 + PIN(AP_WAKE_NFC_PH7, RSVD0, RSVD1, RSVD2, RSVD3),
  145 + PIN(NFC_EN_PI0, RSVD0, RSVD1, RSVD2, RSVD3),
  146 + PIN(NFC_INT_PI1, RSVD0, RSVD1, RSVD2, RSVD3),
  147 + PIN(GPS_EN_PI2, RSVD0, RSVD1, RSVD2, RSVD3),
  148 + PIN(GPS_RST_PI3, RSVD0, RSVD1, RSVD2, RSVD3),
  149 + PIN(CAM_RST_PS4, VGP1, RSVD1, RSVD2, RSVD3),
  150 + PIN(CAM_AF_EN_PS5, VIMCLK, VGP2, RSVD2, RSVD3),
  151 + PIN(CAM_FLASH_EN_PS6, VIMCLK, VGP3, RSVD2, RSVD3),
  152 + PIN(CAM1_PWDN_PS7, VGP4, RSVD1, RSVD2, RSVD3),
  153 + PIN(CAM2_PWDN_PT0, VGP5, RSVD1, RSVD2, RSVD3),
  154 + PIN(CAM1_STROBE_PT1, VGP6, RSVD1, RSVD2, RSVD3),
  155 + PIN(LCD_TE_PY2, DISPLAYA, RSVD1, RSVD2, RSVD3),
  156 + PIN(LCD_BL_PWM_PV0, DISPLAYA, PWM0, SOR0, RSVD3),
  157 + PIN(LCD_BL_EN_PV1, RSVD0, RSVD1, RSVD2, RSVD3),
  158 + PIN(LCD_RST_PV2, RSVD0, RSVD1, RSVD2, RSVD3),
  159 + PIN(LCD_GPIO1_PV3, DISPLAYB, RSVD1, RSVD2, RSVD3),
  160 + PIN(LCD_GPIO2_PV4, DISPLAYB, PWM1, RSVD2, SOR1),
  161 + PIN(AP_READY_PV5, RSVD0, RSVD1, RSVD2, RSVD3),
  162 + PIN(TOUCH_RST_PV6, RSVD0, RSVD1, RSVD2, RSVD3),
  163 + PIN(TOUCH_CLK_PV7, TOUCH, RSVD1, RSVD2, RSVD3),
  164 + PIN(MODEM_WAKE_AP_PX0, RSVD0, RSVD1, RSVD2, RSVD3),
  165 + PIN(TOUCH_INT_PX1, RSVD0, RSVD1, RSVD2, RSVD3),
  166 + PIN(MOTION_INT_PX2, RSVD0, RSVD1, RSVD2, RSVD3),
  167 + PIN(ALS_PROX_INT_PX3, RSVD0, RSVD1, RSVD2, RSVD3),
  168 + PIN(TEMP_ALERT_PX4, RSVD0, RSVD1, RSVD2, RSVD3),
  169 + PIN(BUTTON_POWER_ON_PX5, RSVD0, RSVD1, RSVD2, RSVD3),
  170 + PIN(BUTTON_VOL_UP_PX6, RSVD0, RSVD1, RSVD2, RSVD3),
  171 + PIN(BUTTON_VOL_DOWN_PX7, RSVD0, RSVD1, RSVD2, RSVD3),
  172 + PIN(BUTTON_SLIDE_SW_PY0, RSVD0, RSVD1, RSVD2, RSVD3),
  173 + PIN(BUTTON_HOME_PY1, RSVD0, RSVD1, RSVD2, RSVD3),
  174 + PIN(PA6, SATA, RSVD1, RSVD2, RSVD3),
  175 + PIN(PE6, RSVD0, I2S5A, PWM2, RSVD3),
  176 + PIN(PE7, RSVD0, I2S5A, PWM3, RSVD3),
  177 + PIN(PH6, RSVD0, RSVD1, RSVD2, RSVD3),
  178 + PIN(PK0, IQC0, I2S5B, RSVD2, RSVD3),
  179 + PIN(PK1, IQC0, I2S5B, RSVD2, RSVD3),
  180 + PIN(PK2, IQC0, I2S5B, RSVD2, RSVD3),
  181 + PIN(PK3, IQC0, I2S5B, RSVD2, RSVD3),
  182 + PIN(PK4, IQC1, RSVD1, RSVD2, RSVD3),
  183 + PIN(PK5, IQC1, RSVD1, RSVD2, RSVD3),
  184 + PIN(PK6, IQC1, RSVD1, RSVD2, RSVD3),
  185 + PIN(PK7, IQC1, RSVD1, RSVD2, RSVD3),
  186 + PIN(PL0, RSVD0, RSVD1, RSVD2, RSVD3),
  187 + PIN(PL1, SOC, RSVD1, RSVD2, RSVD3),
  188 + PIN(PZ0, VIMCLK2, RSVD1, RSVD2, RSVD3),
  189 + PIN(PZ1, VIMCLK2, SDMMC1, RSVD2, RSVD3),
  190 + PIN(PZ2, SDMMC3, CCLA, RSVD2, RSVD3),
  191 + PIN(PZ3, SDMMC3, RSVD1, RSVD2, RSVD3),
  192 + PIN(PZ4, SDMMC1, RSVD1, RSVD2, RSVD3),
  193 + PIN(PZ5, SOC, RSVD1, RSVD2, RSVD3),
  194 +};
  195 +const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra210_pingroups;
arch/arm/dts/tegra30-apalis.dts
Diff comments   View file @ b79dadf
... ... @@ -18,6 +18,10 @@
18 18 sdhci0 = "/sdhci@78000600";
19 19 sdhci1 = "/sdhci@78000400";
20 20 sdhci2 = "/sdhci@78000000";
  21 + spi0 = "/spi@7000d400";
  22 + spi1 = "/spi@7000dc00";
  23 + spi2 = "/spi@7000de00";
  24 + spi3 = "/spi@7000da00";
21 25 usb0 = "/usb@7d000000";
22 26 usb1 = "/usb@7d004000";
23 27 usb2 = "/usb@7d008000";
24 28  
... ... @@ -243,13 +247,15 @@
243 247 sdhci@78000000 {
244 248 status = "okay";
245 249 bus-width = <4>;
246   - cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>;
  250 + /* SD1_CD# */
  251 + cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_LOW>;
247 252 };
248 253  
249 254 sdhci@78000400 {
250 255 status = "okay";
251 256 bus-width = <8>;
252   - cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
  257 + /* MMC1_CD# */
  258 + cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
253 259 };
254 260  
255 261 sdhci@78000600 {
256 262  
... ... @@ -262,12 +268,14 @@
262 268 usb@7d000000 {
263 269 status = "okay";
264 270 dr_mode = "peripheral";
  271 + /* USBO1_EN */
265 272 nvidia,vbus-gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
266 273 };
267 274  
268 275 /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */
269 276 usb@7d004000 {
270 277 status = "okay";
  278 + /* USBH_EN */
271 279 nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
272 280 phy_type = "utmi";
273 281 };
... ... @@ -275,6 +283,7 @@
275 283 /* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */
276 284 usb@7d008000 {
277 285 status = "okay";
  286 + /* USBH_EN */
278 287 nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
279 288 };
280 289  
arch/arm/dts/tegra30-colibri.dts
Diff comments   View file @ b79dadf
... ... @@ -64,7 +64,7 @@
64 64 sdhci@78000200 {
65 65 status = "okay";
66 66 bus-width = <4>;
67   - cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
  67 + cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */
68 68 };
69 69  
70 70 sdhci@78000600 {
71 71  
... ... @@ -83,12 +83,14 @@
83 83 usb@7d004000 {
84 84 status = "okay";
85 85 phy_type = "utmi";
  86 + /* VBUS_LAN */
86 87 nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
87 88 };
88 89  
89 90 /* EHCI instance 2: USB3_DP/N -> USBH_P/N */
90 91 usb@7d008000 {
91 92 status = "okay";
  93 + /* USBH_PEN */
92 94 nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
93 95 };
94 96 };
arch/arm/include/asm/arch-orion5x/spl.h
Diff comments   View file @ b79dadf
  1 +/*
  2 + * (C) Copyright 2014 Albert ARIBAUD <albert.u.boot@aribaud.net>
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef _ASM_ARCH_SPL_H_
  8 +#define _ASM_ARCH_SPL_H_
  9 +
  10 +#define BOOT_DEVICE_NOR 1
arch/arm/include/asm/arch-tegra/ap.h
Diff comments   View file @ b79dadf
... ... @@ -74,4 +74,8 @@
74 74 {
75 75 }
76 76 #endif
  77 +
  78 +#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
  79 +bool tegra_cpu_is_non_secure(void);
  80 +#endif
arch/arm/include/asm/arch-tegra/pinmux.h
Diff comments   View file @ b79dadf
... ... @@ -23,40 +23,83 @@
23 23 PMUX_TRI_TRISTATE = 1,
24 24 };
25 25  
26   -#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
  26 +#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
27 27 enum pmux_pin_io {
28 28 PMUX_PIN_OUTPUT = 0,
29 29 PMUX_PIN_INPUT = 1,
30 30 PMUX_PIN_NONE,
31 31 };
  32 +#endif
32 33  
  34 +#ifdef TEGRA_PMX_PINS_HAVE_LOCK
33 35 enum pmux_pin_lock {
34 36 PMUX_PIN_LOCK_DEFAULT = 0,
35 37 PMUX_PIN_LOCK_DISABLE,
36 38 PMUX_PIN_LOCK_ENABLE,
37 39 };
  40 +#endif
38 41  
  42 +#ifdef TEGRA_PMX_PINS_HAVE_OD
39 43 enum pmux_pin_od {
40 44 PMUX_PIN_OD_DEFAULT = 0,
41 45 PMUX_PIN_OD_DISABLE,
42 46 PMUX_PIN_OD_ENABLE,
43 47 };
  48 +#endif
44 49  
  50 +#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
45 51 enum pmux_pin_ioreset {
46 52 PMUX_PIN_IO_RESET_DEFAULT = 0,
47 53 PMUX_PIN_IO_RESET_DISABLE,
48 54 PMUX_PIN_IO_RESET_ENABLE,
49 55 };
  56 +#endif
50 57  
51   -#ifdef TEGRA_PMX_HAS_RCV_SEL
  58 +#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
52 59 enum pmux_pin_rcv_sel {
53 60 PMUX_PIN_RCV_SEL_DEFAULT = 0,
54 61 PMUX_PIN_RCV_SEL_NORMAL,
55 62 PMUX_PIN_RCV_SEL_HIGH,
56 63 };
57   -#endif /* TEGRA_PMX_HAS_RCV_SEL */
58   -#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
  64 +#endif
59 65  
  66 +#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
  67 +enum pmux_pin_e_io_hv {
  68 + PMUX_PIN_E_IO_HV_DEFAULT = 0,
  69 + PMUX_PIN_E_IO_HV_NORMAL,
  70 + PMUX_PIN_E_IO_HV_HIGH,
  71 +};
  72 +#endif
  73 +
  74 +#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
  75 +/* Defines a pin group cfg's low-power mode select */
  76 +enum pmux_lpmd {
  77 + PMUX_LPMD_X8 = 0,
  78 + PMUX_LPMD_X4,
  79 + PMUX_LPMD_X2,
  80 + PMUX_LPMD_X,
  81 + PMUX_LPMD_NONE = -1,
  82 +};
  83 +#endif
  84 +
  85 +#if defined(TEGRA_PMX_PINS_HAVE_SCHMT) || defined(TEGRA_PMX_GRPS_HAVE_SCHMT)
  86 +/* Defines whether a pin group cfg's schmidt is enabled or not */
  87 +enum pmux_schmt {
  88 + PMUX_SCHMT_DISABLE = 0,
  89 + PMUX_SCHMT_ENABLE = 1,
  90 + PMUX_SCHMT_NONE = -1,
  91 +};
  92 +#endif
  93 +
  94 +#if defined(TEGRA_PMX_PINS_HAVE_HSM) || defined(TEGRA_PMX_GRPS_HAVE_HSM)
  95 +/* Defines whether a pin group cfg's high-speed mode is enabled or not */
  96 +enum pmux_hsm {
  97 + PMUX_HSM_DISABLE = 0,
  98 + PMUX_HSM_ENABLE = 1,
  99 + PMUX_HSM_NONE = -1,
  100 +};
  101 +#endif
  102 +
60 103 /*
61 104 * This defines the configuration for a pin, including the function assigned,
62 105 * pull up/down settings and tristate settings. Having set up one of these
63 106  
64 107  
65 108  
66 109  
67 110  
68 111  
69 112  
70 113  
... ... @@ -68,21 +111,37 @@
68 111 u32 func:8; /* function to assign PMUX_FUNC_... */
69 112 u32 pull:2; /* pull up/down/normal PMUX_PULL_...*/
70 113 u32 tristate:2; /* tristate or normal PMUX_TRI_... */
71   -#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
  114 +#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
72 115 u32 io:2; /* input or output PMUX_PIN_... */
  116 +#endif
  117 +#ifdef TEGRA_PMX_PINS_HAVE_LOCK
73 118 u32 lock:2; /* lock enable/disable PMUX_PIN... */
  119 +#endif
  120 +#ifdef TEGRA_PMX_PINS_HAVE_OD
74 121 u32 od:2; /* open-drain or push-pull driver */
  122 +#endif
  123 +#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
75 124 u32 ioreset:2; /* input/output reset PMUX_PIN... */
76   -#ifdef TEGRA_PMX_HAS_RCV_SEL
  125 +#endif
  126 +#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
77 127 u32 rcv_sel:2; /* select between High and Normal */
78 128 /* VIL/VIH receivers */
79 129 #endif
  130 +#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
  131 + u32 e_io_hv:2; /* select 3.3v tolerant receivers */
80 132 #endif
  133 +#ifdef TEGRA_PMX_PINS_HAVE_SCHMT
  134 + u32 schmt:2; /* schmitt enable */
  135 +#endif
  136 +#ifdef TEGRA_PMX_PINS_HAVE_HSM
  137 + u32 hsm:2; /* high-speed mode enable */
  138 +#endif
81 139 };
82 140  
83   -#if !defined(CONFIG_TEGRA20) && !defined(CONFIG_TEGRA30)
84   -/* Set the pinmux CLAMP_INPUTS_WHEN_TRISTATED bit */
  141 +#ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING
  142 +/* Set/clear the pinmux CLAMP_INPUTS_WHEN_TRISTATED bit */
85 143 void pinmux_set_tristate_input_clamping(void);
  144 +void pinmux_clear_tristate_input_clamping(void);
86 145 #endif
87 146  
88 147 /* Set the mux function for a pin group */
... ... @@ -97,7 +156,7 @@
97 156 /* Set a pin group to normal (non tristate) */
98 157 void pinmux_tristate_disable(enum pmux_pingrp pin);
99 158  
100   -#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
  159 +#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
101 160 /* Set a pin group as input or output */
102 161 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
103 162 #endif
... ... @@ -111,7 +170,7 @@
111 170 void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
112 171 int len);
113 172  
114   -#ifdef TEGRA_PMX_HAS_DRVGRPS
  173 +#ifdef TEGRA_PMX_SOC_HAS_DRVGRPS
115 174  
116 175 #define PMUX_SLWF_MIN 0
117 176 #define PMUX_SLWF_MAX 3
... ... @@ -129,29 +188,6 @@
129 188 #define PMUX_DRVDN_MAX 127
130 189 #define PMUX_DRVDN_NONE -1
131 190  
132   -/* Defines a pin group cfg's low-power mode select */
133   -enum pmux_lpmd {
134   - PMUX_LPMD_X8 = 0,
135   - PMUX_LPMD_X4,
136   - PMUX_LPMD_X2,
137   - PMUX_LPMD_X,
138   - PMUX_LPMD_NONE = -1,
139   -};
140   -
141   -/* Defines whether a pin group cfg's schmidt is enabled or not */
142   -enum pmux_schmt {
143   - PMUX_SCHMT_DISABLE = 0,
144   - PMUX_SCHMT_ENABLE = 1,
145   - PMUX_SCHMT_NONE = -1,
146   -};
147   -
148   -/* Defines whether a pin group cfg's high-speed mode is enabled or not */
149   -enum pmux_hsm {
150   - PMUX_HSM_DISABLE = 0,
151   - PMUX_HSM_ENABLE = 1,
152   - PMUX_HSM_NONE = -1,
153   -};
154   -
155 191 /*
156 192 * This defines the configuration for a pin group's pad control config
157 193 */
158 194  
159 195  
160 196  
... ... @@ -161,9 +197,15 @@
161 197 u32 slwr:3; /* rising edge slew */
162 198 u32 drvup:8; /* pull-up drive strength */
163 199 u32 drvdn:8; /* pull-down drive strength */
  200 +#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
164 201 u32 lpmd:3; /* low-power mode selection */
  202 +#endif
  203 +#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
165 204 u32 schmt:2; /* schmidt enable */
  205 +#endif
  206 +#ifdef TEGRA_PMX_GRPS_HAVE_HSM
166 207 u32 hsm:2; /* high-speed mode enable */
  208 +#endif
167 209 };
168 210  
169 211 /**
... ... @@ -175,7 +217,7 @@
175 217 void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
176 218 int len);
177 219  
178   -#endif /* TEGRA_PMX_HAS_DRVGRPS */
  220 +#endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */
179 221  
180 222 struct pmux_pingrp_desc {
181 223 u8 funcs[4];
arch/arm/include/asm/arch-tegra114/pinmux.h
Diff comments   View file @ b79dadf
... ... @@ -313,9 +313,17 @@
313 313 PMUX_FUNC_COUNT,
314 314 };
315 315  
316   -#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
317   -#define TEGRA_PMX_HAS_RCV_SEL
318   -#define TEGRA_PMX_HAS_DRVGRPS
  316 +#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
  317 +#define TEGRA_PMX_SOC_HAS_IO_CLAMPING
  318 +#define TEGRA_PMX_SOC_HAS_DRVGRPS
  319 +#define TEGRA_PMX_GRPS_HAVE_LPMD
  320 +#define TEGRA_PMX_GRPS_HAVE_SCHMT
  321 +#define TEGRA_PMX_GRPS_HAVE_HSM
  322 +#define TEGRA_PMX_PINS_HAVE_E_INPUT
  323 +#define TEGRA_PMX_PINS_HAVE_LOCK
  324 +#define TEGRA_PMX_PINS_HAVE_OD
  325 +#define TEGRA_PMX_PINS_HAVE_IO_RESET
  326 +#define TEGRA_PMX_PINS_HAVE_RCV_SEL
319 327 #include <asm/arch-tegra/pinmux.h>
320 328  
321 329 #endif /* _TEGRA114_PINMUX_H_ */
arch/arm/include/asm/arch-tegra124/pinmux.h
Diff comments   View file @ b79dadf
... ... @@ -335,9 +335,17 @@
335 335 PMUX_FUNC_COUNT,
336 336 };
337 337  
338   -#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
339   -#define TEGRA_PMX_HAS_RCV_SEL
340   -#define TEGRA_PMX_HAS_DRVGRPS
  338 +#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
  339 +#define TEGRA_PMX_SOC_HAS_IO_CLAMPING
  340 +#define TEGRA_PMX_SOC_HAS_DRVGRPS
  341 +#define TEGRA_PMX_GRPS_HAVE_LPMD
  342 +#define TEGRA_PMX_GRPS_HAVE_SCHMT
  343 +#define TEGRA_PMX_GRPS_HAVE_HSM
  344 +#define TEGRA_PMX_PINS_HAVE_E_INPUT
  345 +#define TEGRA_PMX_PINS_HAVE_LOCK
  346 +#define TEGRA_PMX_PINS_HAVE_OD
  347 +#define TEGRA_PMX_PINS_HAVE_IO_RESET
  348 +#define TEGRA_PMX_PINS_HAVE_RCV_SEL
341 349 #include <asm/arch-tegra/pinmux.h>
342 350  
343 351 #endif /* _TEGRA124_PINMUX_H_ */
arch/arm/include/asm/arch-tegra20/pinmux.h
Diff comments   View file @ b79dadf
... ... @@ -233,6 +233,7 @@
233 233 PMUX_FUNC_COUNT,
234 234 };
235 235  
  236 +#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
236 237 #include <asm/arch-tegra/pinmux.h>
237 238  
238 239 #endif /* _TEGRA20_PINMUX_H_ */
arch/arm/include/asm/arch-tegra210/pinmux.h
Diff comments   View file @ b79dadf
  1 +/*
  2 + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef _TEGRA210_PINMUX_H_
  8 +#define _TEGRA210_PINMUX_H_
  9 +
  10 +enum pmux_pingrp {
  11 + PMUX_PINGRP_SDMMC1_CLK_PM0,
  12 + PMUX_PINGRP_SDMMC1_CMD_PM1,
  13 + PMUX_PINGRP_SDMMC1_DAT3_PM2,
  14 + PMUX_PINGRP_SDMMC1_DAT2_PM3,
  15 + PMUX_PINGRP_SDMMC1_DAT1_PM4,
  16 + PMUX_PINGRP_SDMMC1_DAT0_PM5,
  17 + PMUX_PINGRP_SDMMC3_CLK_PP0 = (0x1c / 4),
  18 + PMUX_PINGRP_SDMMC3_CMD_PP1,
  19 + PMUX_PINGRP_SDMMC3_DAT0_PP5,
  20 + PMUX_PINGRP_SDMMC3_DAT1_PP4,
  21 + PMUX_PINGRP_SDMMC3_DAT2_PP3,
  22 + PMUX_PINGRP_SDMMC3_DAT3_PP2,
  23 + PMUX_PINGRP_PEX_L0_RST_N_PA0 = (0x38 / 4),
  24 + PMUX_PINGRP_PEX_L0_CLKREQ_N_PA1,
  25 + PMUX_PINGRP_PEX_WAKE_N_PA2,
  26 + PMUX_PINGRP_PEX_L1_RST_N_PA3,
  27 + PMUX_PINGRP_PEX_L1_CLKREQ_N_PA4,
  28 + PMUX_PINGRP_SATA_LED_ACTIVE_PA5,
  29 + PMUX_PINGRP_SPI1_MOSI_PC0,
  30 + PMUX_PINGRP_SPI1_MISO_PC1,
  31 + PMUX_PINGRP_SPI1_SCK_PC2,
  32 + PMUX_PINGRP_SPI1_CS0_PC3,
  33 + PMUX_PINGRP_SPI1_CS1_PC4,
  34 + PMUX_PINGRP_SPI2_MOSI_PB4,
  35 + PMUX_PINGRP_SPI2_MISO_PB5,
  36 + PMUX_PINGRP_SPI2_SCK_PB6,
  37 + PMUX_PINGRP_SPI2_CS0_PB7,
  38 + PMUX_PINGRP_SPI2_CS1_PDD0,
  39 + PMUX_PINGRP_SPI4_MOSI_PC7,
  40 + PMUX_PINGRP_SPI4_MISO_PD0,
  41 + PMUX_PINGRP_SPI4_SCK_PC5,
  42 + PMUX_PINGRP_SPI4_CS0_PC6,
  43 + PMUX_PINGRP_QSPI_SCK_PEE0,
  44 + PMUX_PINGRP_QSPI_CS_N_PEE1,
  45 + PMUX_PINGRP_QSPI_IO0_PEE2,
  46 + PMUX_PINGRP_QSPI_IO1_PEE3,
  47 + PMUX_PINGRP_QSPI_IO2_PEE4,
  48 + PMUX_PINGRP_QSPI_IO3_PEE5,
  49 + PMUX_PINGRP_DMIC1_CLK_PE0 = (0xa4 / 4),
  50 + PMUX_PINGRP_DMIC1_DAT_PE1,
  51 + PMUX_PINGRP_DMIC2_CLK_PE2,
  52 + PMUX_PINGRP_DMIC2_DAT_PE3,
  53 + PMUX_PINGRP_DMIC3_CLK_PE4,
  54 + PMUX_PINGRP_DMIC3_DAT_PE5,
  55 + PMUX_PINGRP_GEN1_I2C_SCL_PJ1,
  56 + PMUX_PINGRP_GEN1_I2C_SDA_PJ0,
  57 + PMUX_PINGRP_GEN2_I2C_SCL_PJ2,
  58 + PMUX_PINGRP_GEN2_I2C_SDA_PJ3,
  59 + PMUX_PINGRP_GEN3_I2C_SCL_PF0,
  60 + PMUX_PINGRP_GEN3_I2C_SDA_PF1,
  61 + PMUX_PINGRP_CAM_I2C_SCL_PS2,
  62 + PMUX_PINGRP_CAM_I2C_SDA_PS3,
  63 + PMUX_PINGRP_PWR_I2C_SCL_PY3,
  64 + PMUX_PINGRP_PWR_I2C_SDA_PY4,
  65 + PMUX_PINGRP_UART1_TX_PU0,
  66 + PMUX_PINGRP_UART1_RX_PU1,
  67 + PMUX_PINGRP_UART1_RTS_PU2,
  68 + PMUX_PINGRP_UART1_CTS_PU3,
  69 + PMUX_PINGRP_UART2_TX_PG0,
  70 + PMUX_PINGRP_UART2_RX_PG1,
  71 + PMUX_PINGRP_UART2_RTS_PG2,
  72 + PMUX_PINGRP_UART2_CTS_PG3,
  73 + PMUX_PINGRP_UART3_TX_PD1,
  74 + PMUX_PINGRP_UART3_RX_PD2,
  75 + PMUX_PINGRP_UART3_RTS_PD3,
  76 + PMUX_PINGRP_UART3_CTS_PD4,
  77 + PMUX_PINGRP_UART4_TX_PI4,
  78 + PMUX_PINGRP_UART4_RX_PI5,
  79 + PMUX_PINGRP_UART4_RTS_PI6,
  80 + PMUX_PINGRP_UART4_CTS_PI7,
  81 + PMUX_PINGRP_DAP1_FS_PB0,
  82 + PMUX_PINGRP_DAP1_DIN_PB1,
  83 + PMUX_PINGRP_DAP1_DOUT_PB2,
  84 + PMUX_PINGRP_DAP1_SCLK_PB3,
  85 + PMUX_PINGRP_DAP2_FS_PAA0,
  86 + PMUX_PINGRP_DAP2_DIN_PAA2,
  87 + PMUX_PINGRP_DAP2_DOUT_PAA3,
  88 + PMUX_PINGRP_DAP2_SCLK_PAA1,
  89 + PMUX_PINGRP_DAP4_FS_PJ4,
  90 + PMUX_PINGRP_DAP4_DIN_PJ5,
  91 + PMUX_PINGRP_DAP4_DOUT_PJ6,
  92 + PMUX_PINGRP_DAP4_SCLK_PJ7,
  93 + PMUX_PINGRP_CAM1_MCLK_PS0,
  94 + PMUX_PINGRP_CAM2_MCLK_PS1,
  95 + PMUX_PINGRP_JTAG_RTCK,
  96 + PMUX_PINGRP_CLK_32K_IN,
  97 + PMUX_PINGRP_CLK_32K_OUT_PY5,
  98 + PMUX_PINGRP_BATT_BCL,
  99 + PMUX_PINGRP_CLK_REQ,
  100 + PMUX_PINGRP_CPU_PWR_REQ,
  101 + PMUX_PINGRP_PWR_INT_N,
  102 + PMUX_PINGRP_SHUTDOWN,
  103 + PMUX_PINGRP_CORE_PWR_REQ,
  104 + PMUX_PINGRP_AUD_MCLK_PBB0,
  105 + PMUX_PINGRP_DVFS_PWM_PBB1,
  106 + PMUX_PINGRP_DVFS_CLK_PBB2,
  107 + PMUX_PINGRP_GPIO_X1_AUD_PBB3,
  108 + PMUX_PINGRP_GPIO_X3_AUD_PBB4,
  109 + PMUX_PINGRP_PCC7,
  110 + PMUX_PINGRP_HDMI_CEC_PCC0,
  111 + PMUX_PINGRP_HDMI_INT_DP_HPD_PCC1,
  112 + PMUX_PINGRP_SPDIF_OUT_PCC2,
  113 + PMUX_PINGRP_SPDIF_IN_PCC3,
  114 + PMUX_PINGRP_USB_VBUS_EN0_PCC4,
  115 + PMUX_PINGRP_USB_VBUS_EN1_PCC5,
  116 + PMUX_PINGRP_DP_HPD0_PCC6,
  117 + PMUX_PINGRP_WIFI_EN_PH0,
  118 + PMUX_PINGRP_WIFI_RST_PH1,
  119 + PMUX_PINGRP_WIFI_WAKE_AP_PH2,
  120 + PMUX_PINGRP_AP_WAKE_BT_PH3,
  121 + PMUX_PINGRP_BT_RST_PH4,
  122 + PMUX_PINGRP_BT_WAKE_AP_PH5,
  123 + PMUX_PINGRP_AP_WAKE_NFC_PH7,
  124 + PMUX_PINGRP_NFC_EN_PI0,
  125 + PMUX_PINGRP_NFC_INT_PI1,
  126 + PMUX_PINGRP_GPS_EN_PI2,
  127 + PMUX_PINGRP_GPS_RST_PI3,
  128 + PMUX_PINGRP_CAM_RST_PS4,
  129 + PMUX_PINGRP_CAM_AF_EN_PS5,
  130 + PMUX_PINGRP_CAM_FLASH_EN_PS6,
  131 + PMUX_PINGRP_CAM1_PWDN_PS7,
  132 + PMUX_PINGRP_CAM2_PWDN_PT0,
  133 + PMUX_PINGRP_CAM1_STROBE_PT1,
  134 + PMUX_PINGRP_LCD_TE_PY2,
  135 + PMUX_PINGRP_LCD_BL_PWM_PV0,
  136 + PMUX_PINGRP_LCD_BL_EN_PV1,
  137 + PMUX_PINGRP_LCD_RST_PV2,
  138 + PMUX_PINGRP_LCD_GPIO1_PV3,
  139 + PMUX_PINGRP_LCD_GPIO2_PV4,
  140 + PMUX_PINGRP_AP_READY_PV5,
  141 + PMUX_PINGRP_TOUCH_RST_PV6,
  142 + PMUX_PINGRP_TOUCH_CLK_PV7,
  143 + PMUX_PINGRP_MODEM_WAKE_AP_PX0,
  144 + PMUX_PINGRP_TOUCH_INT_PX1,
  145 + PMUX_PINGRP_MOTION_INT_PX2,
  146 + PMUX_PINGRP_ALS_PROX_INT_PX3,
  147 + PMUX_PINGRP_TEMP_ALERT_PX4,
  148 + PMUX_PINGRP_BUTTON_POWER_ON_PX5,
  149 + PMUX_PINGRP_BUTTON_VOL_UP_PX6,
  150 + PMUX_PINGRP_BUTTON_VOL_DOWN_PX7,
  151 + PMUX_PINGRP_BUTTON_SLIDE_SW_PY0,
  152 + PMUX_PINGRP_BUTTON_HOME_PY1,
  153 + PMUX_PINGRP_PA6,
  154 + PMUX_PINGRP_PE6,
  155 + PMUX_PINGRP_PE7,
  156 + PMUX_PINGRP_PH6,
  157 + PMUX_PINGRP_PK0,
  158 + PMUX_PINGRP_PK1,
  159 + PMUX_PINGRP_PK2,
  160 + PMUX_PINGRP_PK3,
  161 + PMUX_PINGRP_PK4,
  162 + PMUX_PINGRP_PK5,
  163 + PMUX_PINGRP_PK6,
  164 + PMUX_PINGRP_PK7,
  165 + PMUX_PINGRP_PL0,
  166 + PMUX_PINGRP_PL1,
  167 + PMUX_PINGRP_PZ0,
  168 + PMUX_PINGRP_PZ1,
  169 + PMUX_PINGRP_PZ2,
  170 + PMUX_PINGRP_PZ3,
  171 + PMUX_PINGRP_PZ4,
  172 + PMUX_PINGRP_PZ5,
  173 + PMUX_PINGRP_COUNT,
  174 +};
  175 +
  176 +enum pmux_drvgrp {
  177 + PMUX_DRVGRP_ALS_PROX_INT = (0x10 / 4),
  178 + PMUX_DRVGRP_AP_READY,
  179 + PMUX_DRVGRP_AP_WAKE_BT,
  180 + PMUX_DRVGRP_AP_WAKE_NFC,
  181 + PMUX_DRVGRP_AUD_MCLK,
  182 + PMUX_DRVGRP_BATT_BCL,
  183 + PMUX_DRVGRP_BT_RST,
  184 + PMUX_DRVGRP_BT_WAKE_AP,
  185 + PMUX_DRVGRP_BUTTON_HOME,
  186 + PMUX_DRVGRP_BUTTON_POWER_ON,
  187 + PMUX_DRVGRP_BUTTON_SLIDE_SW,
  188 + PMUX_DRVGRP_BUTTON_VOL_DOWN,
  189 + PMUX_DRVGRP_BUTTON_VOL_UP,
  190 + PMUX_DRVGRP_CAM1_MCLK,
  191 + PMUX_DRVGRP_CAM1_PWDN,
  192 + PMUX_DRVGRP_CAM1_STROBE,
  193 + PMUX_DRVGRP_CAM2_MCLK,
  194 + PMUX_DRVGRP_CAM2_PWDN,
  195 + PMUX_DRVGRP_CAM_AF_EN,
  196 + PMUX_DRVGRP_CAM_FLASH_EN,
  197 + PMUX_DRVGRP_CAM_I2C_SCL,
  198 + PMUX_DRVGRP_CAM_I2C_SDA,
  199 + PMUX_DRVGRP_CAM_RST,
  200 + PMUX_DRVGRP_CLK_32K_IN,
  201 + PMUX_DRVGRP_CLK_32K_OUT,
  202 + PMUX_DRVGRP_CLK_REQ,
  203 + PMUX_DRVGRP_CORE_PWR_REQ,
  204 + PMUX_DRVGRP_CPU_PWR_REQ,
  205 + PMUX_DRVGRP_DAP1_DIN,
  206 + PMUX_DRVGRP_DAP1_DOUT,
  207 + PMUX_DRVGRP_DAP1_FS,
  208 + PMUX_DRVGRP_DAP1_SCLK,
  209 + PMUX_DRVGRP_DAP2_DIN,
  210 + PMUX_DRVGRP_DAP2_DOUT,
  211 + PMUX_DRVGRP_DAP2_FS,
  212 + PMUX_DRVGRP_DAP2_SCLK,
  213 + PMUX_DRVGRP_DAP4_DIN,
  214 + PMUX_DRVGRP_DAP4_DOUT,
  215 + PMUX_DRVGRP_DAP4_FS,
  216 + PMUX_DRVGRP_DAP4_SCLK,
  217 + PMUX_DRVGRP_DMIC1_CLK,
  218 + PMUX_DRVGRP_DMIC1_DAT,
  219 + PMUX_DRVGRP_DMIC2_CLK,
  220 + PMUX_DRVGRP_DMIC2_DAT,
  221 + PMUX_DRVGRP_DMIC3_CLK,
  222 + PMUX_DRVGRP_DMIC3_DAT,
  223 + PMUX_DRVGRP_DP_HPD0,
  224 + PMUX_DRVGRP_DVFS_CLK,
  225 + PMUX_DRVGRP_DVFS_PWM,
  226 + PMUX_DRVGRP_GEN1_I2C_SCL,
  227 + PMUX_DRVGRP_GEN1_I2C_SDA,
  228 + PMUX_DRVGRP_GEN2_I2C_SCL,
  229 + PMUX_DRVGRP_GEN2_I2C_SDA,
  230 + PMUX_DRVGRP_GEN3_I2C_SCL,
  231 + PMUX_DRVGRP_GEN3_I2C_SDA,
  232 + PMUX_DRVGRP_PA6,
  233 + PMUX_DRVGRP_PCC7,
  234 + PMUX_DRVGRP_PE6,
  235 + PMUX_DRVGRP_PE7,
  236 + PMUX_DRVGRP_PH6,
  237 + PMUX_DRVGRP_PK0,
  238 + PMUX_DRVGRP_PK1,
  239 + PMUX_DRVGRP_PK2,
  240 + PMUX_DRVGRP_PK3,
  241 + PMUX_DRVGRP_PK4,
  242 + PMUX_DRVGRP_PK5,
  243 + PMUX_DRVGRP_PK6,
  244 + PMUX_DRVGRP_PK7,
  245 + PMUX_DRVGRP_PL0,
  246 + PMUX_DRVGRP_PL1,
  247 + PMUX_DRVGRP_PZ0,
  248 + PMUX_DRVGRP_PZ1,
  249 + PMUX_DRVGRP_PZ2,
  250 + PMUX_DRVGRP_PZ3,
  251 + PMUX_DRVGRP_PZ4,
  252 + PMUX_DRVGRP_PZ5,
  253 + PMUX_DRVGRP_GPIO_X1_AUD,
  254 + PMUX_DRVGRP_GPIO_X3_AUD,
  255 + PMUX_DRVGRP_GPS_EN,
  256 + PMUX_DRVGRP_GPS_RST,
  257 + PMUX_DRVGRP_HDMI_CEC,
  258 + PMUX_DRVGRP_HDMI_INT_DP_HPD,
  259 + PMUX_DRVGRP_JTAG_RTCK,
  260 + PMUX_DRVGRP_LCD_BL_EN,
  261 + PMUX_DRVGRP_LCD_BL_PWM,
  262 + PMUX_DRVGRP_LCD_GPIO1,
  263 + PMUX_DRVGRP_LCD_GPIO2,
  264 + PMUX_DRVGRP_LCD_RST,
  265 + PMUX_DRVGRP_LCD_TE,
  266 + PMUX_DRVGRP_MODEM_WAKE_AP,
  267 + PMUX_DRVGRP_MOTION_INT,
  268 + PMUX_DRVGRP_NFC_EN,
  269 + PMUX_DRVGRP_NFC_INT,
  270 + PMUX_DRVGRP_PEX_L0_CLKREQ_N,
  271 + PMUX_DRVGRP_PEX_L0_RST_N,
  272 + PMUX_DRVGRP_PEX_L1_CLKREQ_N,
  273 + PMUX_DRVGRP_PEX_L1_RST_N,
  274 + PMUX_DRVGRP_PEX_WAKE_N,
  275 + PMUX_DRVGRP_PWR_I2C_SCL,
  276 + PMUX_DRVGRP_PWR_I2C_SDA,
  277 + PMUX_DRVGRP_PWR_INT_N,
  278 + PMUX_DRVGRP_QSPI_SCK = (0x1bc / 4),
  279 + PMUX_DRVGRP_SATA_LED_ACTIVE,
  280 + PMUX_DRVGRP_SDMMC1,
  281 + PMUX_DRVGRP_SDMMC2,
  282 + PMUX_DRVGRP_SDMMC3 = (0x1dc / 4),
  283 + PMUX_DRVGRP_SDMMC4,
  284 + PMUX_DRVGRP_SHUTDOWN = (0x1f4 / 4),
  285 + PMUX_DRVGRP_SPDIF_IN,
  286 + PMUX_DRVGRP_SPDIF_OUT,
  287 + PMUX_DRVGRP_SPI1_CS0,
  288 + PMUX_DRVGRP_SPI1_CS1,
  289 + PMUX_DRVGRP_SPI1_MISO,
  290 + PMUX_DRVGRP_SPI1_MOSI,
  291 + PMUX_DRVGRP_SPI1_SCK,
  292 + PMUX_DRVGRP_SPI2_CS0,
  293 + PMUX_DRVGRP_SPI2_CS1,
  294 + PMUX_DRVGRP_SPI2_MISO,
  295 + PMUX_DRVGRP_SPI2_MOSI,
  296 + PMUX_DRVGRP_SPI2_SCK,
  297 + PMUX_DRVGRP_SPI4_CS0,
  298 + PMUX_DRVGRP_SPI4_MISO,
  299 + PMUX_DRVGRP_SPI4_MOSI,
  300 + PMUX_DRVGRP_SPI4_SCK,
  301 + PMUX_DRVGRP_TEMP_ALERT,
  302 + PMUX_DRVGRP_TOUCH_CLK,
  303 + PMUX_DRVGRP_TOUCH_INT,
  304 + PMUX_DRVGRP_TOUCH_RST,
  305 + PMUX_DRVGRP_UART1_CTS,
  306 + PMUX_DRVGRP_UART1_RTS,
  307 + PMUX_DRVGRP_UART1_RX,
  308 + PMUX_DRVGRP_UART1_TX,
  309 + PMUX_DRVGRP_UART2_CTS,
  310 + PMUX_DRVGRP_UART2_RTS,
  311 + PMUX_DRVGRP_UART2_RX,
  312 + PMUX_DRVGRP_UART2_TX,
  313 + PMUX_DRVGRP_UART3_CTS,
  314 + PMUX_DRVGRP_UART3_RTS,
  315 + PMUX_DRVGRP_UART3_RX,
  316 + PMUX_DRVGRP_UART3_TX,
  317 + PMUX_DRVGRP_UART4_CTS,
  318 + PMUX_DRVGRP_UART4_RTS,
  319 + PMUX_DRVGRP_UART4_RX,
  320 + PMUX_DRVGRP_UART4_TX,
  321 + PMUX_DRVGRP_USB_VBUS_EN0,
  322 + PMUX_DRVGRP_USB_VBUS_EN1,
  323 + PMUX_DRVGRP_WIFI_EN,
  324 + PMUX_DRVGRP_WIFI_RST,
  325 + PMUX_DRVGRP_WIFI_WAKE_AP,
  326 + PMUX_DRVGRP_COUNT,
  327 +};
  328 +
  329 +enum pmux_func {
  330 + PMUX_FUNC_DEFAULT,
  331 + PMUX_FUNC_AUD,
  332 + PMUX_FUNC_BCL,
  333 + PMUX_FUNC_BLINK,
  334 + PMUX_FUNC_CCLA,
  335 + PMUX_FUNC_CEC,
  336 + PMUX_FUNC_CLDVFS,
  337 + PMUX_FUNC_CLK,
  338 + PMUX_FUNC_CORE,
  339 + PMUX_FUNC_CPU,
  340 + PMUX_FUNC_DISPLAYA,
  341 + PMUX_FUNC_DISPLAYB,
  342 + PMUX_FUNC_DMIC1,
  343 + PMUX_FUNC_DMIC2,
  344 + PMUX_FUNC_DMIC3,
  345 + PMUX_FUNC_DP,
  346 + PMUX_FUNC_DTV,
  347 + PMUX_FUNC_EXTPERIPH3,
  348 + PMUX_FUNC_I2C1,
  349 + PMUX_FUNC_I2C2,
  350 + PMUX_FUNC_I2C3,
  351 + PMUX_FUNC_I2CPMU,
  352 + PMUX_FUNC_I2CVI,
  353 + PMUX_FUNC_I2S1,
  354 + PMUX_FUNC_I2S2,
  355 + PMUX_FUNC_I2S3,
  356 + PMUX_FUNC_I2S4A,
  357 + PMUX_FUNC_I2S4B,
  358 + PMUX_FUNC_I2S5A,
  359 + PMUX_FUNC_I2S5B,
  360 + PMUX_FUNC_IQC0,
  361 + PMUX_FUNC_IQC1,
  362 + PMUX_FUNC_JTAG,
  363 + PMUX_FUNC_PE,
  364 + PMUX_FUNC_PE0,
  365 + PMUX_FUNC_PE1,
  366 + PMUX_FUNC_PMI,
  367 + PMUX_FUNC_PWM0,
  368 + PMUX_FUNC_PWM1,
  369 + PMUX_FUNC_PWM2,
  370 + PMUX_FUNC_PWM3,
  371 + PMUX_FUNC_QSPI,
  372 + PMUX_FUNC_SATA,
  373 + PMUX_FUNC_SDMMC1,
  374 + PMUX_FUNC_SDMMC3,
  375 + PMUX_FUNC_SHUTDOWN,
  376 + PMUX_FUNC_SOC,
  377 + PMUX_FUNC_SOR0,
  378 + PMUX_FUNC_SOR1,
  379 + PMUX_FUNC_SPDIF,
  380 + PMUX_FUNC_SPI1,
  381 + PMUX_FUNC_SPI2,
  382 + PMUX_FUNC_SPI3,
  383 + PMUX_FUNC_SPI4,
  384 + PMUX_FUNC_SYS,
  385 + PMUX_FUNC_TOUCH,
  386 + PMUX_FUNC_UART,
  387 + PMUX_FUNC_UARTA,
  388 + PMUX_FUNC_UARTB,
  389 + PMUX_FUNC_UARTC,
  390 + PMUX_FUNC_UARTD,
  391 + PMUX_FUNC_USB,
  392 + PMUX_FUNC_VGP1,
  393 + PMUX_FUNC_VGP2,
  394 + PMUX_FUNC_VGP3,
  395 + PMUX_FUNC_VGP4,
  396 + PMUX_FUNC_VGP5,
  397 + PMUX_FUNC_VGP6,
  398 + PMUX_FUNC_VIMCLK,
  399 + PMUX_FUNC_VIMCLK2,
  400 + PMUX_FUNC_RSVD0,
  401 + PMUX_FUNC_RSVD1,
  402 + PMUX_FUNC_RSVD2,
  403 + PMUX_FUNC_RSVD3,
  404 + PMUX_FUNC_COUNT,
  405 +};
  406 +
  407 +#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x8d4
  408 +#define TEGRA_PMX_SOC_HAS_IO_CLAMPING
  409 +#define TEGRA_PMX_SOC_HAS_DRVGRPS
  410 +#define TEGRA_PMX_PINS_HAVE_E_INPUT
  411 +#define TEGRA_PMX_PINS_HAVE_LOCK
  412 +#define TEGRA_PMX_PINS_HAVE_OD
  413 +#define TEGRA_PMX_PINS_HAVE_E_IO_HV
  414 +#include <asm/arch-tegra/pinmux.h>
  415 +
  416 +#endif /* _TEGRA210_PINMUX_H_ */
arch/arm/include/asm/arch-tegra30/pinmux.h
Diff comments   View file @ b79dadf
... ... @@ -391,8 +391,15 @@
391 391 PMUX_FUNC_COUNT,
392 392 };
393 393  
394   -#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
395   -#define TEGRA_PMX_HAS_DRVGRPS
  394 +#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
  395 +#define TEGRA_PMX_SOC_HAS_DRVGRPS
  396 +#define TEGRA_PMX_GRPS_HAVE_LPMD
  397 +#define TEGRA_PMX_GRPS_HAVE_SCHMT
  398 +#define TEGRA_PMX_GRPS_HAVE_HSM
  399 +#define TEGRA_PMX_PINS_HAVE_E_INPUT
  400 +#define TEGRA_PMX_PINS_HAVE_LOCK
  401 +#define TEGRA_PMX_PINS_HAVE_OD
  402 +#define TEGRA_PMX_PINS_HAVE_IO_RESET
396 403 #include <asm/arch-tegra/pinmux.h>
397 404  
398 405 #endif /* _TEGRA30_PINMUX_H_ */
arch/arm/include/asm/macro.h
Diff comments   View file @ b79dadf
... ... @@ -74,6 +74,28 @@
74 74 .endm
75 75  
76 76 /*
  77 + * Branch if current processor is a Cortex-A57 core.
  78 + */
  79 +.macro branch_if_a57_core, xreg, a57_label
  80 + mrs \xreg, midr_el1
  81 + lsr \xreg, \xreg, #4
  82 + and \xreg, \xreg, #0x00000FFF
  83 + cmp \xreg, #0xD07 /* Cortex-A57 MPCore processor. */
  84 + b.eq \a57_label
  85 +.endm
  86 +
  87 +/*
  88 + * Branch if current processor is a Cortex-A53 core.
  89 + */
  90 +.macro branch_if_a53_core, xreg, a53_label
  91 + mrs \xreg, midr_el1
  92 + lsr \xreg, \xreg, #4
  93 + and \xreg, \xreg, #0x00000FFF
  94 + cmp \xreg, #0xD03 /* Cortex-A53 MPCore processor. */
  95 + b.eq \a53_label
  96 +.endm
  97 +
  98 +/*
77 99 * Branch if current processor is a slave,
78 100 * choose processor with all zero affinity value as the master.
79 101 */
arch/arm/lib/interrupts.c
Diff comments   View file @ b79dadf
... ... @@ -137,10 +137,15 @@
137 137  
138 138 flags = condition_codes (regs);
139 139  
140   - printf ("pc : [<%08lx>] lr : [<%08lx>]\n"
141   - "sp : %08lx ip : %08lx fp : %08lx\n",
142   - instruction_pointer (regs),
143   - regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
  140 + printf("pc : [<%08lx>] lr : [<%08lx>]\n",
  141 + instruction_pointer(regs), regs->ARM_lr);
  142 + if (gd->flags & GD_FLG_RELOC) {
  143 + printf("reloc pc : [<%08lx>] lr : [<%08lx>]\n",
  144 + instruction_pointer(regs) - gd->reloc_off,
  145 + regs->ARM_lr - gd->reloc_off);
  146 + }
  147 + printf("sp : %08lx ip : %08lx fp : %08lx\n",
  148 + regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
144 149 printf ("r10: %08lx r9 : %08lx r8 : %08lx\n",
145 150 regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
146 151 printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
arch/arm/mach-orion5x/Kconfig
Diff comments   View file @ b79dadf
... ... @@ -5,6 +5,7 @@
5 5  
6 6 config TARGET_EDMINIV2
7 7 bool "LaCie Ethernet Disk mini V2"
  8 + select SUPPORT_SPL
8 9  
9 10 endchoice
10 11  
arch/arm/mach-orion5x/cpu.c
Diff comments   View file @ b79dadf
... ... @@ -234,7 +234,9 @@
234 234 /* Enable and invalidate L2 cache in write through mode */
235 235 invalidate_l2_cache();
236 236  
  237 +#ifdef CONFIG_SPL_BUILD
237 238 orion5x_config_adr_windows();
  239 +#endif
238 240  
239 241 return 0;
240 242 }
arch/arm/mach-orion5x/include/mach/cpu.h
Diff comments   View file @ b79dadf
... ... @@ -86,7 +86,7 @@
86 86 #endif
87 87  
88 88 #if !defined (ORION5X_ADR_PCIE_IO_REMAP_LO)
89   -#define ORION5X_ADR_PCIE_IO_REMAP_LO 0x90000000
  89 +#define ORION5X_ADR_PCIE_IO_REMAP_LO 0xf0000000
90 90 #endif
91 91  
92 92 #if !defined (ORION5X_ADR_PCIE_IO_REMAP_HI)
arch/arm/mach-orion5x/lowlevel_init.S
Diff comments   View file @ b79dadf
... ... @@ -62,14 +62,16 @@
62 62 /*
63 63 * Low-level init happens right after start.S has switched to SVC32,
64 64 * flushed and disabled caches and disabled MMU. We're still running
65   - * from the boot chip select, so the first thing we should do is set
66   - * up RAM for us to relocate into.
  65 + * from the boot chip select, so the first thing SPL should do is to
  66 + * set up the RAM to copy U-Boot into.
67 67 */
68 68  
69 69 .globl lowlevel_init
70 70  
71 71 lowlevel_init:
72 72  
  73 +#ifdef CONFIG_SPL_BUILD
  74 +
73 75 /* Use 'r4 as the base for internal register accesses */
74 76 ldr r4, =ORION5X_REGS_PHY_BASE
75 77  
... ... @@ -272,6 +274,14 @@
272 274 ldr r2, [r3, #0x484]
273 275 orr r2, r2, r6
274 276 str r2, [r3, #0x484]
  277 +
  278 + /* enable for 2 GB DDR; detection should find out real amount */
  279 + sub r6, r6, r6
  280 + str r6, [r3, #0x500]
  281 + ldr r6, =0x7fff0001
  282 + str r6, [r3, #0x504]
  283 +
  284 +#endif /* CONFIG_SPL_BUILD */
275 285  
276 286 /* Return to U-boot via saved link register */
277 287 mov pc, lr
arch/arm/mach-tegra/board.c
Diff comments   View file @ b79dadf
... ... @@ -11,6 +11,7 @@
11 11 #include <asm/arch/funcmux.h>
12 12 #include <asm/arch/mc.h>
13 13 #include <asm/arch/tegra.h>
  14 +#include <asm/arch-tegra/ap.h>
14 15 #include <asm/arch-tegra/board.h>
15 16 #include <asm/arch-tegra/pmc.h>
16 17 #include <asm/arch-tegra/sys_proto.h>
17 18  
18 19  
19 20  
20 21  
21 22  
22 23  
... ... @@ -28,27 +29,66 @@
28 29 UART_COUNT = 5,
29 30 };
30 31  
  32 +#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
  33 +#if !defined(CONFIG_TEGRA124)
  34 +#error tegra_cpu_is_non_secure has only been validated on Tegra124
  35 +#endif
  36 +bool tegra_cpu_is_non_secure(void)
  37 +{
  38 + /*
  39 + * This register reads 0xffffffff in non-secure mode. This register
  40 + * only implements bits 31:20, so the lower bits will always read 0 in
  41 + * secure mode. Thus, the lower bits are an indicator for secure vs.
  42 + * non-secure mode.
  43 + */
  44 + struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
  45 + uint32_t mc_s_cfg0 = readl(&mc->mc_security_cfg0);
  46 + return (mc_s_cfg0 & 1) == 1;
  47 +}
  48 +#endif
  49 +
31 50 /* Read the RAM size directly from the memory controller */
32 51 unsigned int query_sdram_size(void)
33 52 {
34 53 struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE;
35   - u32 size_mb;
  54 + u32 emem_cfg, size_bytes;
36 55  
37   - size_mb = readl(&mc->mc_emem_cfg);
  56 + emem_cfg = readl(&mc->mc_emem_cfg);
38 57 #if defined(CONFIG_TEGRA20)
39   - debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", size_mb);
40   - size_mb = get_ram_size((void *)PHYS_SDRAM_1, size_mb * 1024);
  58 + debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", emem_cfg);
  59 + size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024);
41 60 #else
42   - debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", size_mb);
43   - size_mb = get_ram_size((void *)PHYS_SDRAM_1, size_mb * 1024 * 1024);
  61 + debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", emem_cfg);
  62 + /*
  63 + * If >=4GB RAM is present, the byte RAM size won't fit into 32-bits
  64 + * and will wrap. Clip the reported size to the maximum that a 32-bit
  65 + * variable can represent (rounded to a page).
  66 + */
  67 + if (emem_cfg >= 4096) {
  68 + size_bytes = U32_MAX & ~(0x1000 - 1);
  69 + } else {
  70 + /* RAM size EMC is programmed to. */
  71 + size_bytes = emem_cfg * 1024 * 1024;
  72 + /*
  73 + * If all RAM fits within 32-bits, it can be accessed without
  74 + * LPAE, so go test the RAM size. Otherwise, we can't access
  75 + * all the RAM, and get_ram_size() would get confused, so
  76 + * avoid using it. There's no reason we should need this
  77 + * validation step anyway.
  78 + */
  79 + if (emem_cfg <= (0 - PHYS_SDRAM_1) / (1024 * 1024))
  80 + size_bytes = get_ram_size((void *)PHYS_SDRAM_1,
  81 + size_bytes);
  82 + }
44 83 #endif
45 84  
46 85 #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
47 86 /* External memory limited to 2047 MB due to IROM/HI-VEC */
48   - if (size_mb == SZ_2G) size_mb -= SZ_1M;
  87 + if (size_bytes == SZ_2G)
  88 + size_bytes -= SZ_1M;
49 89 #endif
50 90  
51   - return size_mb;
  91 + return size_bytes;
52 92 }
53 93  
54 94 int dram_init(void)
arch/arm/mach-tegra/clock.c
Diff comments   View file @ b79dadf
... ... @@ -20,6 +20,7 @@
20 20 #include <asm/io.h>
21 21 #include <asm/arch/clock.h>
22 22 #include <asm/arch/tegra.h>
  23 +#include <asm/arch-tegra/ap.h>
23 24 #include <asm/arch-tegra/clk_rst.h>
24 25 #include <asm/arch-tegra/timer.h>
25 26 #include <div64.h>
... ... @@ -573,7 +574,10 @@
573 574 debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]);
574 575  
575 576 /* Do any special system timer/TSC setup */
576   - arch_timer_init();
  577 +#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
  578 + if (!tegra_cpu_is_non_secure())
  579 +#endif
  580 + arch_timer_init();
577 581 }
578 582  
579 583 static void set_avp_clock_source(u32 src)
arch/arm/mach-tegra/pinmux-common.c
Diff comments   View file @ b79dadf
... ... @@ -24,32 +24,60 @@
24 24 #define pmux_pin_tristate_isvalid(tristate) \
25 25 (((tristate) >= PMUX_TRI_NORMAL) && ((tristate) <= PMUX_TRI_TRISTATE))
26 26  
27   -#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
  27 +#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
28 28 /* return 1 if a pin_io_is in range */
29 29 #define pmux_pin_io_isvalid(io) \
30 30 (((io) >= PMUX_PIN_OUTPUT) && ((io) <= PMUX_PIN_INPUT))
  31 +#endif
31 32  
  33 +#ifdef TEGRA_PMX_PINS_HAVE_LOCK
32 34 /* return 1 if a pin_lock is in range */
33 35 #define pmux_pin_lock_isvalid(lock) \
34 36 (((lock) >= PMUX_PIN_LOCK_DISABLE) && ((lock) <= PMUX_PIN_LOCK_ENABLE))
  37 +#endif
35 38  
  39 +#ifdef TEGRA_PMX_PINS_HAVE_OD
36 40 /* return 1 if a pin_od is in range */
37 41 #define pmux_pin_od_isvalid(od) \
38 42 (((od) >= PMUX_PIN_OD_DISABLE) && ((od) <= PMUX_PIN_OD_ENABLE))
  43 +#endif
39 44  
  45 +#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
40 46 /* return 1 if a pin_ioreset_is in range */
41 47 #define pmux_pin_ioreset_isvalid(ioreset) \
42 48 (((ioreset) >= PMUX_PIN_IO_RESET_DISABLE) && \
43 49 ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
  50 +#endif
44 51  
45   -#ifdef TEGRA_PMX_HAS_RCV_SEL
  52 +#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
46 53 /* return 1 if a pin_rcv_sel_is in range */
47 54 #define pmux_pin_rcv_sel_isvalid(rcv_sel) \
48 55 (((rcv_sel) >= PMUX_PIN_RCV_SEL_NORMAL) && \
49 56 ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
50   -#endif /* TEGRA_PMX_HAS_RCV_SEL */
51   -#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
  57 +#endif
52 58  
  59 +#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
  60 +/* return 1 if a pin_e_io_hv is in range */
  61 +#define pmux_pin_e_io_hv_isvalid(e_io_hv) \
  62 + (((e_io_hv) >= PMUX_PIN_E_IO_HV_NORMAL) && \
  63 + ((e_io_hv) <= PMUX_PIN_E_IO_HV_HIGH))
  64 +#endif
  65 +
  66 +#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
  67 +#define pmux_lpmd_isvalid(lpm) \
  68 + (((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X))
  69 +#endif
  70 +
  71 +#if defined(TEGRA_PMX_PINS_HAVE_SCHMT) || defined(TEGRA_PMX_GRPS_HAVE_SCHMT)
  72 +#define pmux_schmt_isvalid(schmt) \
  73 + (((schmt) >= PMUX_SCHMT_DISABLE) && ((schmt) <= PMUX_SCHMT_ENABLE))
  74 +#endif
  75 +
  76 +#if defined(TEGRA_PMX_PINS_HAVE_HSM) || defined(TEGRA_PMX_GRPS_HAVE_HSM)
  77 +#define pmux_hsm_isvalid(hsm) \
  78 + (((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE))
  79 +#endif
  80 +
53 81 #define _R(offset) (u32 *)(NV_PA_APB_MISC_BASE + (offset))
54 82  
55 83 #if defined(CONFIG_TEGRA20)
56 84  
57 85  
58 86  
... ... @@ -78,15 +106,34 @@
78 106  
79 107 #endif /* CONFIG_TEGRA20 */
80 108  
81   -#define DRV_REG(group) _R(0x868 + ((group) * 4))
  109 +#define DRV_REG(group) _R(TEGRA_PMX_SOC_DRV_GROUP_BASE_REG + ((group) * 4))
82 110  
  111 +/*
  112 + * We could force arch-tegraNN/pinmux.h to define all of these. However,
  113 + * that's a lot of defines, and for now it's manageable to just put a
  114 + * special case here. It's possible this decision will change with future
  115 + * SoCs.
  116 + */
  117 +#ifdef CONFIG_TEGRA210
  118 +#define IO_SHIFT 6
  119 +#define LOCK_SHIFT 7
  120 +#ifdef TEGRA_PMX_PINS_HAVE_HSM
  121 +#define HSM_SHIFT 9
  122 +#endif
  123 +#define E_IO_HV_SHIFT 10
  124 +#define OD_SHIFT 11
  125 +#ifdef TEGRA_PMX_PINS_HAVE_SCHMT
  126 +#define SCHMT_SHIFT 12
  127 +#endif
  128 +#else
83 129 #define IO_SHIFT 5
84 130 #define OD_SHIFT 6
85 131 #define LOCK_SHIFT 7
86 132 #define IO_RESET_SHIFT 8
87 133 #define RCV_SEL_SHIFT 9
  134 +#endif
88 135  
89   -#if !defined(CONFIG_TEGRA20) && !defined(CONFIG_TEGRA30)
  136 +#ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING
90 137 /* This register/field only exists on Tegra114 and later */
91 138 #define APB_MISC_PP_PINMUX_GLOBAL_0 0x40
92 139 #define CLAMP_INPUTS_WHEN_TRISTATED 1
93 140  
94 141  
... ... @@ -94,12 +141,16 @@
94 141 void pinmux_set_tristate_input_clamping(void)
95 142 {
96 143 u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0);
97   - u32 val;
98 144  
99   - val = readl(reg);
100   - val |= CLAMP_INPUTS_WHEN_TRISTATED;
101   - writel(val, reg);
  145 + setbits_le32(reg, CLAMP_INPUTS_WHEN_TRISTATED);
102 146 }
  147 +
  148 +void pinmux_clear_tristate_input_clamping(void)
  149 +{
  150 + u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0);
  151 +
  152 + clrbits_le32(reg, CLAMP_INPUTS_WHEN_TRISTATED);
  153 +}
103 154 #endif
104 155  
105 156 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
... ... @@ -176,7 +227,7 @@
176 227 pinmux_set_tristate(pin, PMUX_TRI_NORMAL);
177 228 }
178 229  
179   -#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
  230 +#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
180 231 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
181 232 {
182 233 u32 *reg = REG(pin);
183 234  
... ... @@ -196,7 +247,9 @@
196 247 val &= ~(1 << IO_SHIFT);
197 248 writel(val, reg);
198 249 }
  250 +#endif
199 251  
  252 +#ifdef TEGRA_PMX_PINS_HAVE_LOCK
200 253 static void pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
201 254 {
202 255 u32 *reg = REG(pin);
203 256  
... ... @@ -221,7 +274,9 @@
221 274  
222 275 return;
223 276 }
  277 +#endif
224 278  
  279 +#ifdef TEGRA_PMX_PINS_HAVE_OD
225 280 static void pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
226 281 {
227 282 u32 *reg = REG(pin);
228 283  
... ... @@ -243,7 +298,9 @@
243 298  
244 299 return;
245 300 }
  301 +#endif
246 302  
  303 +#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
247 304 static void pinmux_set_ioreset(enum pmux_pingrp pin,
248 305 enum pmux_pin_ioreset ioreset)
249 306 {
250 307  
... ... @@ -266,8 +323,9 @@
266 323  
267 324 return;
268 325 }
  326 +#endif
269 327  
270   -#ifdef TEGRA_PMX_HAS_RCV_SEL
  328 +#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
271 329 static void pinmux_set_rcv_sel(enum pmux_pingrp pin,
272 330 enum pmux_pin_rcv_sel rcv_sel)
273 331 {
274 332  
... ... @@ -290,9 +348,83 @@
290 348  
291 349 return;
292 350 }
293   -#endif /* TEGRA_PMX_HAS_RCV_SEL */
294   -#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
  351 +#endif
295 352  
  353 +#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
  354 +static void pinmux_set_e_io_hv(enum pmux_pingrp pin,
  355 + enum pmux_pin_e_io_hv e_io_hv)
  356 +{
  357 + u32 *reg = REG(pin);
  358 + u32 val;
  359 +
  360 + if (e_io_hv == PMUX_PIN_E_IO_HV_DEFAULT)
  361 + return;
  362 +
  363 + /* Error check on pin and e_io_hv */
  364 + assert(pmux_pingrp_isvalid(pin));
  365 + assert(pmux_pin_e_io_hv_isvalid(e_io_hv));
  366 +
  367 + val = readl(reg);
  368 + if (e_io_hv == PMUX_PIN_E_IO_HV_HIGH)
  369 + val |= (1 << E_IO_HV_SHIFT);
  370 + else
  371 + val &= ~(1 << E_IO_HV_SHIFT);
  372 + writel(val, reg);
  373 +
  374 + return;
  375 +}
  376 +#endif
  377 +
  378 +#ifdef TEGRA_PMX_PINS_HAVE_SCHMT
  379 +static void pinmux_set_schmt(enum pmux_pingrp pin, enum pmux_schmt schmt)
  380 +{
  381 + u32 *reg = REG(grp);
  382 + u32 val;
  383 +
  384 + /* NONE means unspecified/do not change/use POR value */
  385 + if (schmt == PMUX_SCHMT_NONE)
  386 + return;
  387 +
  388 + /* Error check pad */
  389 + assert(pmux_pingrp_isvalid(pin));
  390 + assert(pmux_schmt_isvalid(schmt));
  391 +
  392 + val = readl(reg);
  393 + if (schmt == PMUX_SCHMT_ENABLE)
  394 + val |= (1 << SCHMT_SHIFT);
  395 + else
  396 + val &= ~(1 << SCHMT_SHIFT);
  397 + writel(val, reg);
  398 +
  399 + return;
  400 +}
  401 +#endif
  402 +
  403 +#ifdef TEGRA_PMX_PINS_HAVE_HSM
  404 +static void pinmux_set_hsm(enum pmux_pingrp pin, enum pmux_hsm hsm)
  405 +{
  406 + u32 *reg = REG(grp);
  407 + u32 val;
  408 +
  409 + /* NONE means unspecified/do not change/use POR value */
  410 + if (hsm == PMUX_HSM_NONE)
  411 + return;
  412 +
  413 + /* Error check pad */
  414 + assert(pmux_pingrp_isvalid(pin));
  415 + assert(pmux_hsm_isvalid(hsm));
  416 +
  417 + val = readl(reg);
  418 + if (hsm == PMUX_HSM_ENABLE)
  419 + val |= (1 << HSM_SHIFT);
  420 + else
  421 + val &= ~(1 << HSM_SHIFT);
  422 + writel(val, reg);
  423 +
  424 + return;
  425 +}
  426 +#endif
  427 +
296 428 static void pinmux_config_pingrp(const struct pmux_pingrp_config *config)
297 429 {
298 430 enum pmux_pingrp pin = config->pingrp;
299 431  
300 432  
301 433  
302 434  
303 435  
304 436  
... ... @@ -300,15 +432,30 @@
300 432 pinmux_set_func(pin, config->func);
301 433 pinmux_set_pullupdown(pin, config->pull);
302 434 pinmux_set_tristate(pin, config->tristate);
303   -#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
  435 +#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
304 436 pinmux_set_io(pin, config->io);
  437 +#endif
  438 +#ifdef TEGRA_PMX_PINS_HAVE_LOCK
305 439 pinmux_set_lock(pin, config->lock);
  440 +#endif
  441 +#ifdef TEGRA_PMX_PINS_HAVE_OD
306 442 pinmux_set_od(pin, config->od);
  443 +#endif
  444 +#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
307 445 pinmux_set_ioreset(pin, config->ioreset);
308   -#ifdef TEGRA_PMX_HAS_RCV_SEL
  446 +#endif
  447 +#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
309 448 pinmux_set_rcv_sel(pin, config->rcv_sel);
310 449 #endif
  450 +#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
  451 + pinmux_set_e_io_hv(pin, config->e_io_hv);
311 452 #endif
  453 +#ifdef TEGRA_PMX_PINS_HAVE_SCHMT
  454 + pinmux_set_schmt(pin, config->schmt);
  455 +#endif
  456 +#ifdef TEGRA_PMX_PINS_HAVE_HSM
  457 + pinmux_set_hsm(pin, config->hsm);
  458 +#endif
312 459 }
313 460  
314 461 void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
... ... @@ -320,7 +467,7 @@
320 467 pinmux_config_pingrp(&config[i]);
321 468 }
322 469  
323   -#ifdef TEGRA_PMX_HAS_DRVGRPS
  470 +#ifdef TEGRA_PMX_SOC_HAS_DRVGRPS
324 471  
325 472 #define pmux_drvgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PMUX_DRVGRP_COUNT))
326 473  
327 474  
328 475  
329 476  
... ... @@ -330,19 +477,31 @@
330 477 #define pmux_drv_isvalid(drv) \
331 478 (((drv) >= PMUX_DRVUP_MIN) && ((drv) <= PMUX_DRVUP_MAX))
332 479  
333   -#define pmux_lpmd_isvalid(lpm) \
334   - (((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X))
335   -
336   -#define pmux_schmt_isvalid(schmt) \
337   - (((schmt) >= PMUX_SCHMT_DISABLE) && ((schmt) <= PMUX_SCHMT_ENABLE))
338   -
339   -#define pmux_hsm_isvalid(hsm) \
340   - (((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE))
341   -
  480 +#ifdef TEGRA_PMX_GRPS_HAVE_HSM
342 481 #define HSM_SHIFT 2
  482 +#endif
  483 +#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
343 484 #define SCHMT_SHIFT 3
  485 +#endif
  486 +#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
344 487 #define LPMD_SHIFT 4
345 488 #define LPMD_MASK (3 << LPMD_SHIFT)
  489 +#endif
  490 +/*
  491 + * Note that the following DRV* and SLW* defines are accurate for many drive
  492 + * groups on many SoCs. We really need a per-group data structure to solve
  493 + * this, since the fields are in different positions/sizes in different
  494 + * registers (for different groups).
  495 + *
  496 + * On Tegra30/114/124, the DRV*_SHIFT values vary.
  497 + * On Tegra30, the SLW*_SHIFT values vary.
  498 + * On Tegra30/114/124/210, the DRV*_MASK values vary, although the values
  499 + * below are wide enough to cover the widest fields, and hopefully don't
  500 + * interfere with any other fields.
  501 + * On Tegra30, the SLW*_MASK values vary, but we can't use a value that's
  502 + * wide enough to cover all cases, since that would cause the field to
  503 + * overlap with other fields in the narrower cases.
  504 + */
346 505 #define DRVDN_SHIFT 12
347 506 #define DRVDN_MASK (0x7F << DRVDN_SHIFT)
348 507 #define DRVUP_SHIFT 20
... ... @@ -436,6 +595,7 @@
436 595 return;
437 596 }
438 597  
  598 +#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
439 599 static void pinmux_set_lpmd(enum pmux_drvgrp grp, enum pmux_lpmd lpmd)
440 600 {
441 601 u32 *reg = DRV_REG(grp);
442 602  
... ... @@ -456,7 +616,9 @@
456 616  
457 617 return;
458 618 }
  619 +#endif
459 620  
  621 +#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
460 622 static void pinmux_set_schmt(enum pmux_drvgrp grp, enum pmux_schmt schmt)
461 623 {
462 624 u32 *reg = DRV_REG(grp);
463 625  
... ... @@ -479,7 +641,9 @@
479 641  
480 642 return;
481 643 }
  644 +#endif
482 645  
  646 +#ifdef TEGRA_PMX_GRPS_HAVE_HSM
483 647 static void pinmux_set_hsm(enum pmux_drvgrp grp, enum pmux_hsm hsm)
484 648 {
485 649 u32 *reg = DRV_REG(grp);
... ... @@ -502,6 +666,7 @@
502 666  
503 667 return;
504 668 }
  669 +#endif
505 670  
506 671 static void pinmux_config_drvgrp(const struct pmux_drvgrp_config *config)
507 672 {
508 673  
509 674  
510 675  
... ... @@ -511,9 +676,15 @@
511 676 pinmux_set_drvdn_slwr(grp, config->slwr);
512 677 pinmux_set_drvup(grp, config->drvup);
513 678 pinmux_set_drvdn(grp, config->drvdn);
  679 +#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
514 680 pinmux_set_lpmd(grp, config->lpmd);
  681 +#endif
  682 +#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
515 683 pinmux_set_schmt(grp, config->schmt);
  684 +#endif
  685 +#ifdef TEGRA_PMX_GRPS_HAVE_HSM
516 686 pinmux_set_hsm(grp, config->hsm);
  687 +#endif
517 688 }
518 689  
519 690 void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
board/LaCie/edminiv2/config.mk
View file @ b79dadf
1   -#
2   -# Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
3   -#
4   -# (C) Copyright 2009
5   -# Marvell Semiconductor <www.marvell.com>
6   -# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
7   -#
8   -# SPDX-License-Identifier: GPL-2.0+
9   -#
10   -
11   -# TEXT_BASE must equal the intended FLASH location of u-boot.
12   -CONFIG_SYS_TEXT_BASE = 0xfff90000
board/LaCie/edminiv2/edminiv2.c
Diff comments   View file @ b79dadf
... ... @@ -12,59 +12,11 @@
12 12 #include <miiphy.h>
13 13 #include <asm/arch/orion5x.h>
14 14 #include "../common/common.h"
  15 +#include <spl.h>
  16 +#include <ns16550.h>
15 17  
16 18 DECLARE_GLOBAL_DATA_PTR;
17 19  
18   -/*
19   - * The ED Mini V2 is equipped with a Macronix MXLV400CB FLASH
20   - * which CFI does not properly detect, hence the LEGACY config.
21   - */
22   -#if defined(CONFIG_FLASH_CFI_LEGACY)
23   -#include <flash.h>
24   -ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
25   -{
26   - int sectsz[] = CONFIG_SYS_FLASH_SECTSZ;
27   - int sect;
28   -
29   - if (base != CONFIG_SYS_FLASH_BASE)
30   - return 0;
31   -
32   - info->size = 0;
33   - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
34   - /* set each sector's start address and size based */
35   - for (sect = 0; sect < CONFIG_SYS_MAX_FLASH_SECT; sect++) {
36   - info->start[sect] = base+info->size;
37   - info->size += sectsz[sect];
38   - }
39   - /* This flash must be accessed in 8-bits mode, no buffer. */
40   - info->flash_id = 0x01000000;
41   - info->portwidth = FLASH_CFI_8BIT;
42   - info->chipwidth = FLASH_CFI_BY8;
43   - info->buffer_size = 0;
44   - /* timings are derived from the Macronix datasheet. */
45   - info->erase_blk_tout = 1000;
46   - info->write_tout = 10;
47   - info->buffer_write_tout = 300;
48   - /* Commands and addresses are for AMD mode 8-bit access. */
49   - info->vendor = CFI_CMDSET_AMD_LEGACY;
50   - info->cmd_reset = 0xF0;
51   - info->interface = FLASH_CFI_X8;
52   - info->legacy_unlock = 0;
53   - info->ext_addr = 0;
54   - info->addr_unlock1 = 0x00000aaa;
55   - info->addr_unlock2 = 0x00000555;
56   - /* Manufacturer Macronix, device MX29LV400CB, CFI 1.3. */
57   - info->manufacturer_id = 0x22;
58   - info->device_id = 0xBA;
59   - info->device_id2 = 0;
60   - info->cfi_version = 0x3133;
61   - info->cfi_offset = 0x0000;
62   - info->name = "MX29LV400CB";
63   -
64   - return 1;
65   -}
66   -#endif /* CONFIG_SYS_FLASH_CFI */
67   -
68 20 int board_init(void)
69 21 {
70 22 /* arch number of board */
... ... @@ -83,4 +35,22 @@
83 35 mv_phy_88e1116_init("egiga0", 8);
84 36 }
85 37 #endif /* CONFIG_RESET_PHY_R */
  38 +
  39 +/*
  40 + * SPL serial setup and NOR boot device selection
  41 + */
  42 +
  43 +#ifdef CONFIG_SPL_BUILD
  44 +
  45 +void spl_board_init(void)
  46 +{
  47 + preloader_console_init();
  48 +}
  49 +
  50 +u32 spl_boot_device(void)
  51 +{
  52 + return BOOT_DEVICE_NOR;
  53 +}
  54 +
  55 +#endif /* CONFIG_SPL_BUILD */
board/nvidia/common/board.c
Diff comments   View file @ b79dadf
... ... @@ -21,6 +21,7 @@
21 21 #include <asm/arch/pwm.h>
22 22 #endif
23 23 #include <asm/arch/tegra.h>
  24 +#include <asm/arch-tegra/ap.h>
24 25 #include <asm/arch-tegra/board.h>
25 26 #include <asm/arch-tegra/clk_rst.h>
26 27 #include <asm/arch-tegra/pmc.h>
... ... @@ -179,6 +180,14 @@
179 180 #ifdef CONFIG_LCD
180 181 /* Make sure we finish initing the LCD */
181 182 tegra_lcd_check_next_stage(gd->fdt_blob, 1);
  183 +#endif
  184 +#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
  185 + if (tegra_cpu_is_non_secure()) {
  186 + printf("CPU is in NS mode\n");
  187 + setenv("cpu_ns_mode", "1");
  188 + } else {
  189 + setenv("cpu_ns_mode", "");
  190 + }
182 191 #endif
183 192 return 0;
184 193 }
board/nvidia/jetson-tk1/jetson-tk1.c
Diff comments   View file @ b79dadf
... ... @@ -22,7 +22,7 @@
22 22 */
23 23 void pinmux_init(void)
24 24 {
25   - pinmux_set_tristate_input_clamping();
  25 + pinmux_clear_tristate_input_clamping();
26 26  
27 27 gpio_config_table(jetson_tk1_gpio_inits,
28 28 ARRAY_SIZE(jetson_tk1_gpio_inits));
board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
Diff comments   View file @ b79dadf
1 1 /*
2   - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
  2 + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
3 3 *
4 4 * SPDX-License-Identifier: GPL-2.0+
5 5 */
6 6  
7 7  
8 8  
9 9  
10 10  
11 11  
12 12  
13 13  
14 14  
15 15  
16 16  
17 17  
18 18  
19 19  
20 20  
21 21  
22 22  
23 23  
... ... @@ -15,77 +15,47 @@
15 15  
16 16 static const struct tegra_gpio_config jetson_tk1_gpio_inits[] = {
17 17 /* gpio, init_val */
18   - GPIO_INIT(C7, IN),
19   - GPIO_INIT(G0, OUT0),
20   - GPIO_INIT(G1, OUT0),
  18 + GPIO_INIT(G0, IN),
  19 + GPIO_INIT(G1, IN),
21 20 GPIO_INIT(G2, IN),
22 21 GPIO_INIT(G3, IN),
  22 + GPIO_INIT(G4, IN),
23 23 GPIO_INIT(H2, OUT0),
24   - GPIO_INIT(H3, OUT0),
25 24 GPIO_INIT(H4, IN),
26   - GPIO_INIT(H5, OUT0),
27   - GPIO_INIT(H6, IN),
28   - GPIO_INIT(H7, OUT0),
  25 + GPIO_INIT(H7, IN),
29 26 GPIO_INIT(I0, OUT0),
30   - GPIO_INIT(I2, OUT0),
31   - GPIO_INIT(I4, OUT0),
32   - GPIO_INIT(I5, IN),
  27 + GPIO_INIT(I1, IN),
33 28 GPIO_INIT(I6, IN),
34 29 GPIO_INIT(J0, IN),
35   - GPIO_INIT(J2, IN),
36 30 GPIO_INIT(K1, OUT0),
37 31 GPIO_INIT(K2, IN),
38   - GPIO_INIT(K3, IN),
39 32 GPIO_INIT(K4, OUT0),
40   - GPIO_INIT(K5, OUT0),
41 33 GPIO_INIT(K6, OUT0),
42 34 GPIO_INIT(N7, IN),
43   - GPIO_INIT(O0, IN),
44 35 GPIO_INIT(O1, IN),
45   - GPIO_INIT(O2, IN),
46   - GPIO_INIT(O3, IN),
47 36 GPIO_INIT(O4, IN),
48   - GPIO_INIT(O5, IN),
49   - GPIO_INIT(O6, OUT0),
50   - GPIO_INIT(O7, IN),
51   - GPIO_INIT(P0, OUT0),
52   - GPIO_INIT(P1, OUT0),
53 37 GPIO_INIT(P2, OUT0),
54 38 GPIO_INIT(Q0, IN),
55   - GPIO_INIT(Q1, IN),
56   - GPIO_INIT(Q2, IN),
  39 + GPIO_INIT(Q3, IN),
57 40 GPIO_INIT(Q5, IN),
58   - GPIO_INIT(Q6, IN),
59   - GPIO_INIT(Q7, IN),
60 41 GPIO_INIT(R0, OUT0),
61   - GPIO_INIT(R1, OUT0),
62 42 GPIO_INIT(R2, OUT0),
63 43 GPIO_INIT(R4, IN),
64   - GPIO_INIT(R5, OUT0),
65 44 GPIO_INIT(R7, IN),
66   - GPIO_INIT(S0, IN),
67   - GPIO_INIT(S3, OUT0),
68   - GPIO_INIT(S4, OUT0),
69   - GPIO_INIT(S5, IN),
70   - GPIO_INIT(S6, OUT0),
  45 + GPIO_INIT(S7, IN),
71 46 GPIO_INIT(T0, OUT0),
72   - GPIO_INIT(T1, OUT0),
73   - GPIO_INIT(U0, OUT0),
  47 + GPIO_INIT(T1, IN),
  48 + GPIO_INIT(U0, IN),
74 49 GPIO_INIT(U1, IN),
75 50 GPIO_INIT(U2, IN),
76   - GPIO_INIT(U3, OUT0),
77   - GPIO_INIT(U4, OUT0),
  51 + GPIO_INIT(U3, IN),
  52 + GPIO_INIT(U4, IN),
78 53 GPIO_INIT(U5, IN),
79 54 GPIO_INIT(U6, IN),
80 55 GPIO_INIT(V0, IN),
81 56 GPIO_INIT(V1, IN),
82   - GPIO_INIT(W2, IN),
83   - GPIO_INIT(W3, IN),
84   - GPIO_INIT(X1, OUT0),
85   - GPIO_INIT(X3, IN),
86   - GPIO_INIT(X4, OUT0),
87   - GPIO_INIT(X5, IN),
88   - GPIO_INIT(X6, IN),
  57 + GPIO_INIT(X1, IN),
  58 + GPIO_INIT(X4, IN),
89 59 GPIO_INIT(X7, OUT0),
90 60 GPIO_INIT(BB3, OUT0),
91 61 GPIO_INIT(BB5, OUT0),
... ... @@ -93,10 +63,7 @@
93 63 GPIO_INIT(BB7, OUT0),
94 64 GPIO_INIT(CC1, IN),
95 65 GPIO_INIT(CC2, IN),
96   - GPIO_INIT(CC5, OUT0),
97   - GPIO_INIT(EE1, OUT0),
98   - GPIO_INIT(FF1, OUT0),
99   - GPIO_INIT(FF2, IN),
  66 + GPIO_INIT(EE2, OUT1),
100 67 };
101 68  
102 69 #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \
103 70  
104 71  
105 72  
106 73  
107 74  
108 75  
109 76  
110 77  
111 78  
112 79  
113 80  
114 81  
115 82  
116 83  
117 84  
118 85  
119 86  
120 87  
121 88  
122 89  
123 90  
124 91  
125 92  
126 93  
127 94  
... ... @@ -114,152 +81,152 @@
114 81  
115 82 static const struct pmux_pingrp_config jetson_tk1_pingrps[] = {
116 83 /* pingrp, mux, pull, tri, e_input, od, rcv_sel */
117   - PINCFG(CLK_32K_OUT_PA0, SOC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
118   - PINCFG(UART3_CTS_N_PA1, UARTC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
119   - PINCFG(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
120   - PINCFG(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
121   - PINCFG(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
122   - PINCFG(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
123   - PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  84 + PINCFG(CLK_32K_OUT_PA0, SOC, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
  85 + PINCFG(UART3_CTS_N_PA1, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  86 + PINCFG(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  87 + PINCFG(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  88 + PINCFG(DAP2_DIN_PA4, I2S1, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
  89 + PINCFG(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  90 + PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
124 91 PINCFG(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
125   - PINCFG(PB0, UARTD, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
126   - PINCFG(PB1, UARTD, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  92 + PINCFG(PB0, UARTD, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
  93 + PINCFG(PB1, UARTD, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
127 94 PINCFG(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
128 95 PINCFG(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
129 96 PINCFG(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
130 97 PINCFG(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
131   - PINCFG(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  98 + PINCFG(UART3_RTS_N_PC0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
132 99 PINCFG(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
133   - PINCFG(UART2_RXD_PC3, IRDA, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  100 + PINCFG(UART2_RXD_PC3, IRDA, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
134 101 PINCFG(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
135 102 PINCFG(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
136   - PINCFG(PC7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
137   - PINCFG(PG0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
138   - PINCFG(PG1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
139   - PINCFG(PG2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
140   - PINCFG(PG3, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
141   - PINCFG(PG4, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  103 + PINCFG(PC7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  104 + PINCFG(PG0, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
  105 + PINCFG(PG1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
  106 + PINCFG(PG2, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
  107 + PINCFG(PG3, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
  108 + PINCFG(PG4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
142 109 PINCFG(PG5, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
143 110 PINCFG(PG6, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
144   - PINCFG(PG7, SPI4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  111 + PINCFG(PG7, SPI4, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
145 112 PINCFG(PH0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
146 113 PINCFG(PH1, PWM1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
147 114 PINCFG(PH2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
148   - PINCFG(PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
149   - PINCFG(PH4, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
150   - PINCFG(PH5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
151   - PINCFG(PH6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
152   - PINCFG(PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  115 + PINCFG(PH3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  116 + PINCFG(PH4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
  117 + PINCFG(PH5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  118 + PINCFG(PH6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  119 + PINCFG(PH7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
153 120 PINCFG(PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
154   - PINCFG(PI1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
155   - PINCFG(PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  121 + PINCFG(PI1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
  122 + PINCFG(PI2, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
156 123 PINCFG(PI3, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
157   - PINCFG(PI4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
158   - PINCFG(PI5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
159   - PINCFG(PI6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  124 + PINCFG(PI4, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  125 + PINCFG(PI5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  126 + PINCFG(PI6, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
160 127 PINCFG(PI7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
161   - PINCFG(PJ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
162   - PINCFG(PJ2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
163   - PINCFG(UART2_CTS_N_PJ5, UARTB, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  128 + PINCFG(PJ0, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
  129 + PINCFG(PJ2, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  130 + PINCFG(UART2_CTS_N_PJ5, UARTB, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
164 131 PINCFG(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
165 132 PINCFG(PJ7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
166   - PINCFG(PK0, SOC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  133 + PINCFG(PK0, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
167 134 PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
168   - PINCFG(PK2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
169   - PINCFG(PK3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  135 + PINCFG(PK2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  136 + PINCFG(PK3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
170 137 PINCFG(PK4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
171   - PINCFG(SPDIF_OUT_PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  138 + PINCFG(SPDIF_OUT_PK5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
172 139 PINCFG(SPDIF_IN_PK6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
173 140 PINCFG(PK7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
174   - PINCFG(DAP1_FS_PN0, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
175   - PINCFG(DAP1_DIN_PN1, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
  141 + PINCFG(DAP1_FS_PN0, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  142 + PINCFG(DAP1_DIN_PN1, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
176 143 PINCFG(DAP1_DOUT_PN2, SATA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
177   - PINCFG(DAP1_SCLK_PN3, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
178   - PINCFG(USB_VBUS_EN0_PN4, USB, UP, NORMAL, INPUT, ENABLE, DEFAULT),
179   - PINCFG(USB_VBUS_EN1_PN5, USB, UP, NORMAL, INPUT, ENABLE, DEFAULT),
180   - PINCFG(HDMI_INT_PN7, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, NORMAL),
181   - PINCFG(ULPI_DATA7_PO0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
182   - PINCFG(ULPI_DATA0_PO1, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
183   - PINCFG(ULPI_DATA1_PO2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
184   - PINCFG(ULPI_DATA2_PO3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
185   - PINCFG(ULPI_DATA3_PO4, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
186   - PINCFG(ULPI_DATA4_PO5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
187   - PINCFG(ULPI_DATA5_PO6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
188   - PINCFG(ULPI_DATA6_PO7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
189   - PINCFG(DAP3_FS_PP0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
190   - PINCFG(DAP3_DIN_PP1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  144 + PINCFG(DAP1_SCLK_PN3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  145 + PINCFG(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
  146 + PINCFG(USB_VBUS_EN1_PN5, USB, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
  147 + PINCFG(HDMI_INT_PN7, DEFAULT, DOWN, TRISTATE, INPUT, DEFAULT, NORMAL),
  148 + PINCFG(ULPI_DATA7_PO0, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  149 + PINCFG(ULPI_DATA0_PO1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
  150 + PINCFG(ULPI_DATA1_PO2, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  151 + PINCFG(ULPI_DATA2_PO3, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  152 + PINCFG(ULPI_DATA3_PO4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
  153 + PINCFG(ULPI_DATA4_PO5, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  154 + PINCFG(ULPI_DATA5_PO6, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  155 + PINCFG(ULPI_DATA6_PO7, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  156 + PINCFG(DAP3_FS_PP0, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  157 + PINCFG(DAP3_DIN_PP1, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
191 158 PINCFG(DAP3_DOUT_PP2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
192 159 PINCFG(DAP3_SCLK_PP3, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
193   - PINCFG(DAP4_FS_PP4, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
194   - PINCFG(DAP4_DIN_PP5, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
195   - PINCFG(DAP4_DOUT_PP6, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
196   - PINCFG(DAP4_SCLK_PP7, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
197   - PINCFG(KB_COL0_PQ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
198   - PINCFG(KB_COL1_PQ1, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
199   - PINCFG(KB_COL2_PQ2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
200   - PINCFG(KB_COL3_PQ3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
201   - PINCFG(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
202   - PINCFG(KB_COL5_PQ5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
203   - PINCFG(KB_COL6_PQ6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
204   - PINCFG(KB_COL7_PQ7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  160 + PINCFG(DAP4_FS_PP4, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  161 + PINCFG(DAP4_DIN_PP5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  162 + PINCFG(DAP4_DOUT_PP6, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  163 + PINCFG(DAP4_SCLK_PP7, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  164 + PINCFG(KB_COL0_PQ0, DEFAULT, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
  165 + PINCFG(KB_COL1_PQ1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  166 + PINCFG(KB_COL2_PQ2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  167 + PINCFG(KB_COL3_PQ3, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
  168 + PINCFG(KB_COL4_PQ4, SDMMC3, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
  169 + PINCFG(KB_COL5_PQ5, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
  170 + PINCFG(KB_COL6_PQ6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  171 + PINCFG(KB_COL7_PQ7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
205 172 PINCFG(KB_ROW0_PR0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
206   - PINCFG(KB_ROW1_PR1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  173 + PINCFG(KB_ROW1_PR1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
207 174 PINCFG(KB_ROW2_PR2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
208   - PINCFG(KB_ROW3_PR3, SYS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
209   - PINCFG(KB_ROW4_PR4, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
210   - PINCFG(KB_ROW5_PR5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
211   - PINCFG(KB_ROW6_PR6, DISPLAYA_ALT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
212   - PINCFG(KB_ROW7_PR7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
213   - PINCFG(KB_ROW8_PS0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
214   - PINCFG(KB_ROW9_PS1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
215   - PINCFG(KB_ROW10_PS2, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
216   - PINCFG(KB_ROW11_PS3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
217   - PINCFG(KB_ROW12_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
218   - PINCFG(KB_ROW13_PS5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
219   - PINCFG(KB_ROW14_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
220   - PINCFG(KB_ROW15_PS7, SOC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  175 + PINCFG(KB_ROW3_PR3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  176 + PINCFG(KB_ROW4_PR4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
  177 + PINCFG(KB_ROW5_PR5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  178 + PINCFG(KB_ROW6_PR6, DISPLAYA_ALT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
  179 + PINCFG(KB_ROW7_PR7, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
  180 + PINCFG(KB_ROW8_PS0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  181 + PINCFG(KB_ROW9_PS1, UARTA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  182 + PINCFG(KB_ROW10_PS2, UARTA, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
  183 + PINCFG(KB_ROW11_PS3, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  184 + PINCFG(KB_ROW12_PS4, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  185 + PINCFG(KB_ROW13_PS5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  186 + PINCFG(KB_ROW14_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  187 + PINCFG(KB_ROW15_PS7, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
221 188 PINCFG(KB_ROW16_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
222   - PINCFG(KB_ROW17_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  189 + PINCFG(KB_ROW17_PT1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
223 190 PINCFG(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
224 191 PINCFG(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
225 192 PINCFG(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
226   - PINCFG(PU0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
227   - PINCFG(PU1, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
228   - PINCFG(PU2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
229   - PINCFG(PU3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
230   - PINCFG(PU4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
231   - PINCFG(PU5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
232   - PINCFG(PU6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
233   - PINCFG(PV0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
234   - PINCFG(PV1, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
235   - PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  193 + PINCFG(PU0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  194 + PINCFG(PU1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  195 + PINCFG(PU2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  196 + PINCFG(PU3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  197 + PINCFG(PU4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  198 + PINCFG(PU5, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  199 + PINCFG(PU6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  200 + PINCFG(PV0, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
  201 + PINCFG(PV1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
  202 + PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
236 203 PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
237 204 PINCFG(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
238 205 PINCFG(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
239   - PINCFG(GPIO_W2_AUD_PW2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
240   - PINCFG(GPIO_W3_AUD_PW3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  206 + PINCFG(GPIO_W2_AUD_PW2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  207 + PINCFG(GPIO_W3_AUD_PW3, SPI6, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
241 208 PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
242 209 PINCFG(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
243   - PINCFG(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
244   - PINCFG(UART3_RXD_PW7, UARTC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  210 + PINCFG(UART3_TXD_PW6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  211 + PINCFG(UART3_RXD_PW7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
245 212 PINCFG(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
246   - PINCFG(GPIO_X1_AUD_PX1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  213 + PINCFG(GPIO_X1_AUD_PX1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
247 214 PINCFG(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
248   - PINCFG(GPIO_X3_AUD_PX3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
249   - PINCFG(GPIO_X4_AUD_PX4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
250   - PINCFG(GPIO_X5_AUD_PX5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
251   - PINCFG(GPIO_X6_AUD_PX6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  215 + PINCFG(GPIO_X3_AUD_PX3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  216 + PINCFG(GPIO_X4_AUD_PX4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
  217 + PINCFG(GPIO_X5_AUD_PX5, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  218 + PINCFG(GPIO_X6_AUD_PX6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
252 219 PINCFG(GPIO_X7_AUD_PX7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
253 220 PINCFG(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
254   - PINCFG(ULPI_DIR_PY1, SPI1, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
  221 + PINCFG(ULPI_DIR_PY1, SPI1, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
255 222 PINCFG(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
256 223 PINCFG(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
257   - PINCFG(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
258   - PINCFG(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
259   - PINCFG(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
260   - PINCFG(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
261   - PINCFG(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
262   - PINCFG(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  224 + PINCFG(SDMMC1_DAT3_PY4, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  225 + PINCFG(SDMMC1_DAT2_PY5, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  226 + PINCFG(SDMMC1_DAT1_PY6, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  227 + PINCFG(SDMMC1_DAT0_PY7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  228 + PINCFG(SDMMC1_CLK_PZ0, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  229 + PINCFG(SDMMC1_CMD_PZ1, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
263 230 PINCFG(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
264 231 PINCFG(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
265 232 PINCFG(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
266 233  
267 234  
268 235  
269 236  
270 237  
271 238  
272 239  
... ... @@ -279,30 +246,30 @@
279 246 PINCFG(PBB6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
280 247 PINCFG(PBB7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
281 248 PINCFG(CAM_MCLK_PCC0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
282   - PINCFG(PCC1, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
283   - PINCFG(PCC2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
  249 + PINCFG(PCC1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  250 + PINCFG(PCC2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
284 251 PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
285   - PINCFG(CLK2_REQ_PCC5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  252 + PINCFG(CLK2_REQ_PCC5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
286 253 PINCFG(PEX_L0_RST_N_PDD1, PE0, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
287   - PINCFG(PEX_L0_CLKREQ_N_PDD2, PE0, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
288   - PINCFG(PEX_WAKE_N_PDD3, PE, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  254 + PINCFG(PEX_L0_CLKREQ_N_PDD2, PE0, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
  255 + PINCFG(PEX_WAKE_N_PDD3, PE, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
289 256 PINCFG(PEX_L1_RST_N_PDD5, PE1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
290   - PINCFG(PEX_L1_CLKREQ_N_PDD6, PE1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  257 + PINCFG(PEX_L1_CLKREQ_N_PDD6, PE1, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
291 258 PINCFG(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
292   - PINCFG(CLK3_REQ_PEE1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
293   - PINCFG(DAP_MCLK1_REQ_PEE2, SATA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
294   - PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
  259 + PINCFG(CLK3_REQ_PEE1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  260 + PINCFG(DAP_MCLK1_REQ_PEE2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  261 + PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
295 262 PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
296 263 PINCFG(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
297   - PINCFG(DP_HPD_PFF0, DP, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
298   - PINCFG(USB_VBUS_EN2_PFF1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
299   - PINCFG(PFF2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
  264 + PINCFG(DP_HPD_PFF0, DP, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
  265 + PINCFG(USB_VBUS_EN2_PFF1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  266 + PINCFG(PFF2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
300 267 PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
301   - PINCFG(CPU_PWR_REQ, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
302   - PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
303   - PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  268 + PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  269 + PINCFG(PWR_INT_N, PMI, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
  270 + PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
304 271 PINCFG(OWR, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, NORMAL),
305   - PINCFG(CLK_32K_IN, RSVD2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  272 + PINCFG(CLK_32K_IN, CLK, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
306 273 PINCFG(JTAG_RTCK, RTCK, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT),
307 274 };
308 275  
... ... @@ -360,6 +360,18 @@
360 360 /* Get the top of usable RAM */
361 361 __weak ulong board_get_usable_ram_top(ulong total_size)
362 362 {
  363 +#ifdef CONFIG_SYS_SDRAM_BASE
  364 + /*
  365 + * Detect whether we have so much RAM it goes past the end of our
  366 + * 32-bit address space. If so, clip the usable RAM so it doesn't.
  367 + */
  368 + if (gd->ram_top < CONFIG_SYS_SDRAM_BASE)
  369 + /*
  370 + * Will wrap back to top of 32-bit space when reservations
  371 + * are made.
  372 + */
  373 + return 0;
  374 +#endif
363 375 return gd->ram_top;
364 376 }
365 377  
configs/edminiv2_defconfig
Diff comments   View file @ b79dadf
1   -CONFIG_ARM=y
2   -CONFIG_ORION5X=y
3   -CONFIG_TARGET_EDMINIV2=y
  1 +CONFIG_SPL=y
  2 ++S:CONFIG_ARM=y
  3 ++S:CONFIG_ORION5X=y
  4 ++S:CONFIG_TARGET_EDMINIV2=y
include/configs/apalis_t30.h
Diff comments   View file @ b79dadf
1 1 /*
2   - * Copyright (c) 2014 Marcel Ziswiler
  2 + * Copyright (c) 2014-2015 Marcel Ziswiler
3 3 *
4 4 * SPDX-License-Identifier: GPL-2.0+
5 5 */
... ... @@ -22,8 +22,6 @@
22 22  
23 23 #define CONFIG_MACH_TYPE MACH_TYPE_APALIS_T30
24 24  
25   -#define CONFIG_BOARD_EARLY_INIT_F
26   -
27 25 /* I2C */
28 26 #define CONFIG_SYS_I2C_TEGRA
29 27 #define CONFIG_CMD_I2C
30 28  
... ... @@ -47,12 +45,8 @@
47 45 #define CONFIG_USB_STORAGE
48 46 #define CONFIG_CMD_USB
49 47  
50   -/* USB networking support */
51   -#define CONFIG_USB_HOST_ETHER
52   -#define CONFIG_USB_ETHER_ASIX
53   -
54 48 /* PCI host support */
55   -#undef CONFIG_PCI /* just define once Tegra PCIe support got merged */
  49 +#define CONFIG_PCI
56 50 #define CONFIG_PCI_TEGRA
57 51 #define CONFIG_PCI_PNP
58 52 #define CONFIG_CMD_PCI
59 53  
... ... @@ -60,11 +54,30 @@
60 54  
61 55 /* PCI networking support */
62 56 #define CONFIG_E1000
63   -#undef CONFIG_E1000_NO_NVM /* just define once E1000 driver got fixed */
  57 +#define CONFIG_E1000_NO_NVM
64 58  
65 59 /* General networking support */
66 60 #define CONFIG_CMD_NET
67 61 #define CONFIG_CMD_DHCP
  62 +
  63 +/* Miscellaneous commands */
  64 +#define CONFIG_CMD_SETEXPR
  65 +#define CONFIG_FAT_WRITE
  66 +
  67 +/* Increase console I/O buffer size */
  68 +#undef CONFIG_SYS_CBSIZE
  69 +#define CONFIG_SYS_CBSIZE 1024
  70 +
  71 +/* Increase arguments buffer size */
  72 +#undef CONFIG_SYS_BARGSIZE
  73 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  74 +
  75 +/* Increase print buffer size */
  76 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  77 +
  78 +/* Increase maximum number of arguments */
  79 +#undef CONFIG_SYS_MAXARGS
  80 +#define CONFIG_SYS_MAXARGS 32
68 81  
69 82 #include "tegra-common-usb-gadget.h"
70 83 #include "tegra-common-post.h"
include/configs/beaver.h
Diff comments   View file @ b79dadf
... ... @@ -36,8 +36,6 @@
36 36 #define MACH_TYPE_BEAVER 4597 /* not yet in mach-types.h */
37 37 #define CONFIG_MACH_TYPE MACH_TYPE_BEAVER
38 38  
39   -#define CONFIG_BOARD_EARLY_INIT_F
40   -
41 39 /* I2C */
42 40 #define CONFIG_SYS_I2C_TEGRA
43 41 #define CONFIG_CMD_I2C
include/configs/cardhu.h
Diff comments   View file @ b79dadf
... ... @@ -39,8 +39,6 @@
39 39  
40 40 #define CONFIG_MACH_TYPE MACH_TYPE_CARDHU
41 41  
42   -#define CONFIG_BOARD_EARLY_INIT_F
43   -
44 42 /* I2C */
45 43 #define CONFIG_SYS_I2C_TEGRA
46 44 #define CONFIG_CMD_I2C
include/configs/colibri_t20_iris.h
Diff comments   View file @ b79dadf
... ... @@ -18,8 +18,6 @@
18 18 #define CONFIG_TEGRA_UARTA_SDIO1
19 19 #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
20 20  
21   -#define CONFIG_BOARD_EARLY_INIT_F
22   -
23 21 /* SD/MMC support */
24 22 #define CONFIG_MMC
25 23 #define CONFIG_GENERIC_MMC
include/configs/colibri_t30.h
Diff comments   View file @ b79dadf
1 1 /*
2   - * Copyright (c) 2013-2014 Stefan Agner
  2 + * Copyright (c) 2013-2015 Stefan Agner
3 3 *
4 4 * SPDX-License-Identifier: GPL-2.0+
5 5 */
6 6  
7 7  
... ... @@ -11,18 +11,17 @@
11 11  
12 12 #include "tegra30-common.h"
13 13  
  14 +/* High-level configuration options */
14 15 #define V_PROMPT "Colibri T30 # "
15 16 #define CONFIG_TEGRA_BOARD_STRING "Toradex Colibri T30"
16 17  
17   -/* Board-specific config */
  18 +/* Board-specific serial config */
18 19 #define CONFIG_SERIAL_MULTI
19 20 #define CONFIG_TEGRA_ENABLE_UARTA
20 21 #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
21 22  
22 23 #define CONFIG_MACH_TYPE MACH_TYPE_COLIBRI_T30
23 24  
24   -#define CONFIG_BOARD_EARLY_INIT_F
25   -
26 25 /* I2C */
27 26 #define CONFIG_SYS_I2C_TEGRA
28 27 #define CONFIG_CMD_I2C
... ... @@ -53,6 +52,25 @@
53 52 /* General networking support */
54 53 #define CONFIG_CMD_NET
55 54 #define CONFIG_CMD_DHCP
  55 +
  56 +/* Miscellaneous commands */
  57 +#define CONFIG_CMD_SETEXPR
  58 +#define CONFIG_FAT_WRITE
  59 +
  60 +/* Increase console I/O buffer size */
  61 +#undef CONFIG_SYS_CBSIZE
  62 +#define CONFIG_SYS_CBSIZE 1024
  63 +
  64 +/* Increase arguments buffer size */
  65 +#undef CONFIG_SYS_BARGSIZE
  66 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  67 +
  68 +/* Increase print buffer size */
  69 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  70 +
  71 +/* Increase maximum number of arguments */
  72 +#undef CONFIG_SYS_MAXARGS
  73 +#define CONFIG_SYS_MAXARGS 32
56 74  
57 75 #include "tegra-common-usb-gadget.h"
58 76 #include "tegra-common-post.h"
include/configs/dalmore.h
Diff comments   View file @ b79dadf
... ... @@ -32,8 +32,6 @@
32 32  
33 33 #define CONFIG_MACH_TYPE MACH_TYPE_DALMORE
34 34  
35   -#define CONFIG_BOARD_EARLY_INIT_F
36   -
37 35 /* I2C */
38 36 #define CONFIG_SYS_I2C_TEGRA
39 37 #define CONFIG_CMD_I2C
include/configs/edminiv2.h
Diff comments   View file @ b79dadf
... ... @@ -12,7 +12,32 @@
12 12 #ifndef _CONFIG_EDMINIV2_H
13 13 #define _CONFIG_EDMINIV2_H
14 14  
  15 +/* general settings */
  16 +#define CONFIG_SYS_GENERIC_BOARD
  17 +
15 18 /*
  19 + * SPL
  20 + */
  21 +
  22 +#define CONFIG_SPL_FRAMEWORK
  23 +#define CONFIG_SPL_LIBGENERIC_SUPPORT
  24 +#define CONFIG_SPL_LIBCOMMON_SUPPORT
  25 +#define CONFIG_SPL_SERIAL_SUPPORT
  26 +#define CONFIG_SPL_NOR_SUPPORT
  27 +#define CONFIG_SPL_TEXT_BASE 0xffff0000
  28 +#define CONFIG_SPL_MAX_SIZE 0x0000fff0
  29 +#define CONFIG_SPL_STACK 0x00020000
  30 +#define CONFIG_SPL_BSS_START_ADDR 0x00020000
  31 +#define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff
  32 +#define CONFIG_SYS_SPL_MALLOC_START 0x00040000
  33 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff
  34 +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/orion5x/u-boot-spl.lds"
  35 +#define CONFIG_SPL_BOARD_INIT
  36 +#define CONFIG_SYS_UBOOT_BASE 0xfff90000
  37 +#define CONFIG_SYS_UBOOT_START 0x00800000
  38 +#define CONFIG_SYS_TEXT_BASE 0x00800000
  39 +
  40 +/*
16 41 * Version number information
17 42 */
18 43  
19 44  
... ... @@ -89,13 +114,9 @@
89 114  
90 115 #define CONFIG_SYS_FLASH_CFI
91 116 #define CONFIG_FLASH_CFI_DRIVER
92   -#define CONFIG_FLASH_CFI_LEGACY
93 117 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
94 118 #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */
95 119 #define CONFIG_SYS_FLASH_BASE 0xfff80000
96   -#define CONFIG_SYS_FLASH_SECTSZ \
97   - {16384, 8192, 8192, 32768, \
98   - 65536, 65536, 65536, 65536, 65536, 65536, 65536}
99 120  
100 121 /* auto boot */
101 122 #define CONFIG_BOOTDELAY 3 /* default enable autoboot */
include/configs/harmony.h
Diff comments   View file @ b79dadf
... ... @@ -27,9 +27,6 @@
27 27  
28 28 #define CONFIG_MACH_TYPE MACH_TYPE_HARMONY
29 29  
30   -#define CONFIG_BOARD_EARLY_INIT_F
31   -#define CONFIG_BOARD_LATE_INIT /* Make sure LCD init is complete */
32   -
33 30 /* SD/MMC */
34 31 #define CONFIG_MMC
35 32 #define CONFIG_GENERIC_MMC
include/configs/jetson-tk1.h
Diff comments   View file @ b79dadf
... ... @@ -24,8 +24,6 @@
24 24 #define CONFIG_TEGRA_ENABLE_UARTD
25 25 #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
26 26  
27   -#define CONFIG_BOARD_EARLY_INIT_F
28   -
29 27 /* I2C */
30 28 #define CONFIG_SYS_I2C_TEGRA
31 29 #define CONFIG_CMD_I2C
include/configs/ls2085a_common.h
Diff comments   View file @ b79dadf
... ... @@ -15,6 +15,10 @@
15 15 #define CONFIG_GICV3
16 16 #define CONFIG_FSL_TZPC_BP147
17 17  
  18 +/* Errata fixes */
  19 +#define CONFIG_ARM_ERRATA_828024
  20 +#define CONFIG_ARM_ERRATA_826974
  21 +
18 22 /* Link Definitions */
19 23 #define CONFIG_SYS_TEXT_BASE 0x30001000
20 24  
include/configs/medcom-wide.h
Diff comments   View file @ b79dadf
... ... @@ -20,9 +20,6 @@
20 20 #define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */
21 21 #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
22 22  
23   -#define CONFIG_BOARD_EARLY_INIT_F
24   -#define CONFIG_BOARD_LATE_INIT
25   -
26 23 /* SD/MMC */
27 24 #define CONFIG_MMC
28 25 #define CONFIG_GENERIC_MMC
include/configs/nyan-big.h
Diff comments   View file @ b79dadf
... ... @@ -21,8 +21,6 @@
21 21 #define CONFIG_TEGRA_ENABLE_UARTA
22 22 #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
23 23  
24   -#define CONFIG_BOARD_EARLY_INIT_F
25   -
26 24 /* I2C */
27 25 #define CONFIG_SYS_I2C_TEGRA
28 26 #define CONFIG_CMD_I2C
include/configs/paz00.h
Diff comments   View file @ b79dadf
... ... @@ -30,9 +30,6 @@
30 30  
31 31 #define CONFIG_MACH_TYPE MACH_TYPE_PAZ00
32 32  
33   -#define CONFIG_BOARD_EARLY_INIT_F
34   -#define CONFIG_BOARD_LATE_INIT
35   -
36 33 /* SD/MMC */
37 34 #define CONFIG_MMC
38 35 #define CONFIG_GENERIC_MMC
include/configs/plutux.h
Diff comments   View file @ b79dadf
... ... @@ -20,9 +20,6 @@
20 20 #define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */
21 21 #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
22 22  
23   -#define CONFIG_BOARD_EARLY_INIT_F
24   -#define CONFIG_BOARD_LATE_INIT
25   -
26 23 /* SD/MMC */
27 24 #define CONFIG_MMC
28 25 #define CONFIG_GENERIC_MMC
include/configs/seaboard.h
Diff comments   View file @ b79dadf
... ... @@ -32,9 +32,6 @@
32 32  
33 33 #define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD
34 34  
35   -#define CONFIG_BOARD_EARLY_INIT_F
36   -#define CONFIG_BOARD_LATE_INIT /* Make sure LCD init is complete */
37   -
38 35 /* I2C */
39 36 #define CONFIG_SYS_I2C_TEGRA
40 37 #define CONFIG_CMD_I2C
include/configs/tec-ng.h
Diff comments   View file @ b79dadf
... ... @@ -19,8 +19,6 @@
19 19 #define CONFIG_TEGRA_ENABLE_UARTD
20 20 #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
21 21  
22   -#define CONFIG_BOARD_EARLY_INIT_F
23   -
24 22 /* I2C */
25 23 #define CONFIG_SYS_I2C_TEGRA
26 24 #define CONFIG_CMD_I2C
include/configs/tec.h
Diff comments   View file @ b79dadf
... ... @@ -20,9 +20,6 @@
20 20 #define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */
21 21 #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
22 22  
23   -#define CONFIG_BOARD_EARLY_INIT_F
24   -#define CONFIG_BOARD_LATE_INIT
25   -
26 23 /* SD/MMC */
27 24 #define CONFIG_MMC
28 25 #define CONFIG_GENERIC_MMC
include/configs/tegra-common.h
Diff comments   View file @ b79dadf
... ... @@ -150,6 +150,8 @@
150 150 #define CONFIG_SPL_GPIO_SUPPORT
151 151  
152 152 #define CONFIG_SYS_GENERIC_BOARD
  153 +#define CONFIG_BOARD_EARLY_INIT_F
  154 +#define CONFIG_BOARD_LATE_INIT
153 155  
154 156 /* Misc utility code */
155 157 #define CONFIG_BOUNCE_BUFFER
include/configs/trimslice.h
Diff comments   View file @ b79dadf
... ... @@ -22,8 +22,6 @@
22 22  
23 23 #define CONFIG_MACH_TYPE MACH_TYPE_TRIMSLICE
24 24  
25   -#define CONFIG_BOARD_EARLY_INIT_F
26   -
27 25 /* SPI */
28 26 #define CONFIG_TEGRA20_SFLASH
29 27 #define CONFIG_SPI_FLASH
include/configs/venice2.h
Diff comments   View file @ b79dadf
... ... @@ -21,8 +21,6 @@
21 21 #define CONFIG_TEGRA_ENABLE_UARTA
22 22 #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
23 23  
24   -#define CONFIG_BOARD_EARLY_INIT_F
25   -
26 24 /* I2C */
27 25 #define CONFIG_SYS_I2C_TEGRA
28 26 #define CONFIG_CMD_I2C
include/configs/ventana.h
Diff comments   View file @ b79dadf
... ... @@ -21,9 +21,6 @@
21 21  
22 22 #define CONFIG_MACH_TYPE MACH_TYPE_VENTANA
23 23  
24   -#define CONFIG_BOARD_EARLY_INIT_F
25   -#define CONFIG_BOARD_LATE_INIT /* Make sure LCD init is complete */
26   -
27 24 /* SD/MMC */
28 25 #define CONFIG_MMC
29 26 #define CONFIG_GENERIC_MMC
include/configs/whistler.h
Diff comments   View file @ b79dadf
... ... @@ -22,8 +22,6 @@
22 22  
23 23 #define CONFIG_MACH_TYPE MACH_TYPE_WHISTLER
24 24  
25   -#define CONFIG_BOARD_EARLY_INIT_F
26   -
27 25 /* I2C */
28 26 #define CONFIG_SYS_I2C_TEGRA
29 27 #define CONFIG_CMD_I2C