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Commit ba650e9b5263bfc7579e6775676441eeeca2edc4

Authored by Masahiro Yamada
Committed by Tom Rini
1 parent 247161b816
Exists in v2017.01-smarct4x and in 48 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

m68k: Remove M5271EVB and idmr board support 

CONFIG_SYS_HZ must be always 1000, but M5271EVB.h defines it
as 1000000 and idmr.h defines it as (50000000 / 64).

When compiling these two boards, a warning message is displayed:

  time.c:14:2: warning: #warning "CONFIG_SYS_HZ must be 1000
  and should not be defined by platforms" [-Wcpp]

There are no board maintainers for them so this commit just
deletes them.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Jason Jin <Jason.jin@freescale.com>

Showing 13 changed files with 9 additions and 1293 deletions Side-by-side Diff

board/freescale/m5271evb/Makefile
View file @ ba650e9
1   -#
2   -# (C) Copyright 2000-2006
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# SPDX-License-Identifier: GPL-2.0+
6   -#
7   -
8   -obj-y = m5271evb.o
board/freescale/m5271evb/config.mk
View file @ ba650e9
1   -#
2   -# (C) Copyright 2000-2006
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
5   -#
6   -# SPDX-License-Identifier: GPL-2.0+
7   -#
8   -
9   -CONFIG_SYS_TEXT_BASE = 0xffe00000
board/freescale/m5271evb/m5271evb.c
View file @ ba650e9
1   -/*
2   - * (C) Copyright 2000-2006
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <common.h>
9   -#include <asm/immap.h>
10   -
11   -int checkboard (void) {
12   - puts ("Board: Freescale M5271EVB\n");
13   - return 0;
14   -};
15   -
16   -phys_size_t initdram (int board_type) {
17   -
18   - int i;
19   -
20   - /* Enable Address lines 23-21 and lower 16bits of data path */
21   - mbar_writeByte(MCF_GPIO_PAR_AD, MCF_GPIO_AD_ADDR23 |
22   - MCF_GPIO_AD_ADDR22 | MCF_GPIO_AD_ADDR21 |
23   - MCF_GPIO_AD_DATAL);
24   -
25   - /* Set CS2 pin to be SD_CS0 */
26   - mbar_writeByte(MCF_GPIO_PAR_CS, mbar_readByte(MCF_GPIO_PAR_CS)
27   - | MCF_GPIO_PAR_CS_PAR_CS2);
28   -
29   - /* Configure SDRAM Control Pin Assignemnt Register */
30   - mbar_writeByte(MCF_GPIO_PAR_SDRAM, MCF_GPIO_SDRAM_CSSDCS_00 |
31   - MCF_GPIO_SDRAM_SDWE | MCF_GPIO_SDRAM_SCAS |
32   - MCF_GPIO_SDRAM_SRAS | MCF_GPIO_SDRAM_SCKE |
33   - MCF_GPIO_SDRAM_SDCS_11);
34   - asm(" nop");
35   -
36   - /*
37   - * Check to see if the SDRAM has already been initialized
38   - * by a run control tool
39   - */
40   - if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE)) {
41   - /* Initialize DRAM Control Register: DCR */
42   - mbar_writeShort(MCF_SDRAMC_DCR,
43   - MCF_SDRAMC_DCR_RTIM(2)
44   - | MCF_SDRAMC_DCR_RC(0x2E));
45   - asm(" nop");
46   -
47   - /*
48   - * Initialize DACR0
49   - *
50   - * CASL: 01
51   - * CBM: cmd at A20, bank select bits 21 and up
52   - * PS: 32bit port size
53   - */
54   - mbar_writeLong(MCF_SDRAMC_DACR0,
55   - MCF_SDRAMC_DACRn_BA(CONFIG_SYS_SDRAM_BASE>>18)
56   - | MCF_SDRAMC_DACRn_CASL(1)
57   - | MCF_SDRAMC_DACRn_CBM(3)
58   - | MCF_SDRAMC_DACRn_PS(0));
59   - asm(" nop");
60   -
61   - /* Initialize DMR0 */
62   - mbar_writeLong(MCF_SDRAMC_DMR0,
63   - MCF_SDRAMC_DMRn_BAM_16M
64   - | MCF_SDRAMC_DMRn_V);
65   - asm(" nop");
66   -
67   - /* Set IP bit in DACR */
68   - mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
69   - | MCF_SDRAMC_DACRn_IP);
70   - asm(" nop");
71   -
72   - /* Wait at least 20ns to allow banks to precharge */
73   - for (i = 0; i < 5; i++)
74   - asm(" nop");
75   -
76   - /* Write to this block to initiate precharge */
77   - *(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
78   - asm(" nop");
79   -
80   - /* Set RE bit in DACR */
81   - mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
82   - | MCF_SDRAMC_DACRn_RE);
83   -
84   - /* Wait for at least 8 auto refresh cycles to occur */
85   - for (i = 0; i < 2000; i++)
86   - asm(" nop");
87   -
88   - /* Finish the configuration by issuing the MRS */
89   - mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
90   - | MCF_SDRAMC_DACRn_MRS);
91   - asm(" nop");
92   -
93   - /*
94   - * Write to the SDRAM Mode Register A0-A11 = 0x400
95   - *
96   - * Write Burst Mode = Programmed Burst Length
97   - * Op Mode = Standard Op
98   - * CAS Latency = 2
99   - * Burst Type = Sequential
100   - * Burst Length = 1
101   - */
102   - *(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xa5a5a5a5;
103   - asm(" nop");
104   - }
105   -
106   - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
107   -};
108   -
109   -int testdram (void) {
110   -
111   - /* TODO: XXX XXX XXX */
112   - printf ("DRAM test not implemented!\n");
113   -
114   - return (0);
115   -}
board/freescale/m5271evb/u-boot.lds
View file @ ba650e9
1   -/*
2   - * (C) Copyright 2000
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -OUTPUT_ARCH(m68k)
9   -
10   -SECTIONS
11   -{
12   - .text :
13   - {
14   - arch/m68k/cpu/mcf52x2/start.o (.text*)
15   -
16   - . = DEFINED(env_offset) ? env_offset : .;
17   - common/env_embedded.o (.ppcenv)
18   -
19   - *(.text*)
20   - }
21   - _etext = .;
22   - PROVIDE (etext = .);
23   - .rodata :
24   - {
25   - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
26   - }
27   -
28   - /* Read-write section, merged into data segment: */
29   - . = (. + 0x00FF) & 0xFFFFFF00;
30   - _erotext = .;
31   - PROVIDE (erotext = .);
32   -
33   - .reloc :
34   - {
35   - __got_start = .;
36   - KEEP(*(.got))
37   - __got_end = .;
38   - _GOT2_TABLE_ = .;
39   - KEEP(*(.got2))
40   - _FIXUP_TABLE_ = .;
41   - KEEP(*(.fixup))
42   - }
43   - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
44   - __fixup_entries = (. - _FIXUP_TABLE_)>>2;
45   -
46   - .data :
47   - {
48   - *(.data*)
49   - *(.sdata*)
50   - }
51   - _edata = .;
52   - PROVIDE (edata = .);
53   -
54   - . = .;
55   -
56   - . = ALIGN(4);
57   - .u_boot_list : {
58   - KEEP(*(SORT(.u_boot_list*)));
59   - }
60   -
61   - . = .;
62   - __start___ex_table = .;
63   - __ex_table : { *(__ex_table) }
64   - __stop___ex_table = .;
65   -
66   - . = ALIGN(256);
67   - __init_begin = .;
68   - .text.init : { *(.text.init) }
69   - .data.init : { *(.data.init) }
70   - . = ALIGN(256);
71   - __init_end = .;
72   -
73   - __bss_start = .;
74   - .bss (NOLOAD) :
75   - {
76   - _sbss = .;
77   - *(.bss*)
78   - *(.sbss*)
79   - *(COMMON)
80   - . = ALIGN(4);
81   - _ebss = .;
82   - }
83   - __bss_end = . ;
84   - PROVIDE (end = .);
85   -}
board/idmr/Makefile
View file @ ba650e9
1   -#
2   -# (C) Copyright 2000-2006
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# SPDX-License-Identifier: GPL-2.0+
6   -#
7   -
8   -obj-y = idmr.o flash.o
board/idmr/config.mk
View file @ ba650e9
1   -#
2   -# (C) Copyright 2000-2006
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
5   -#
6   -# SPDX-License-Identifier: GPL-2.0+
7   -#
8   -
9   -CONFIG_SYS_TEXT_BASE = 0xff800000
board/idmr/flash.c
View file @ ba650e9
1   -/*
2   - * (C) Copyright 2000-2006
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <common.h>
9   -
10   -#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
11   -#define FLASH_BANK_SIZE 0x800000
12   -#define EN29LV640 0x227e227e
13   -
14   -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
15   -
16   -void flash_print_info (flash_info_t * info)
17   -{
18   - int i;
19   -
20   - switch (info->flash_id & FLASH_VENDMASK) {
21   - case (AMD_MANUFACT & FLASH_VENDMASK):
22   - printf ("AMD: ");
23   - break;
24   - default:
25   - printf ("Unknown Vendor ");
26   - break;
27   - }
28   -
29   - switch (info->flash_id & FLASH_TYPEMASK) {
30   - case (EN29LV640 & FLASH_TYPEMASK):
31   - printf ("EN29LV640 (16Mbit)\n");
32   - break;
33   - default:
34   - printf ("Unknown Chip Type\n");
35   - goto Done;
36   - break;
37   - }
38   -
39   - printf (" Size: %ld MB in %d Sectors\n",
40   - info->size >> 20, info->sector_count);
41   -
42   - printf (" Sector Start Addresses:");
43   - for (i = 0; i < info->sector_count; i++) {
44   - if ((i % 5) == 0) {
45   - printf ("\n ");
46   - }
47   - printf (" %08lX%s", info->start[i],
48   - info->protect[i] ? " (RO)" : " ");
49   - }
50   - printf ("\n");
51   -
52   - Done:
53   - return;
54   -}
55   -
56   -
57   -unsigned long flash_init (void)
58   -{
59   - int i, j;
60   - ulong size = 0;
61   -
62   - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
63   - ulong flashbase = 0;
64   -
65   - flash_info[i].flash_id =
66   - (AMD_MANUFACT & FLASH_VENDMASK) |
67   - (EN29LV640 & FLASH_TYPEMASK);
68   - flash_info[i].size = FLASH_BANK_SIZE;
69   - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
70   - memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
71   - if (i == 0)
72   - flashbase = PHYS_FLASH_1;
73   - else
74   - panic ("configured to many flash banks!\n");
75   -
76   - for (j = 0; j < flash_info[i].sector_count; j++) {
77   - flash_info[i].start[j] = flashbase + 0x10000 * j;
78   - }
79   - size += flash_info[i].size;
80   - }
81   -
82   - flash_protect (FLAG_PROTECT_SET,
83   - CONFIG_SYS_FLASH_BASE,
84   - CONFIG_SYS_FLASH_BASE + 0x2ffff, &flash_info[0]);
85   -
86   - return size;
87   -}
88   -
89   -
90   -#define CMD_READ_ARRAY 0x00F0
91   -#define CMD_UNLOCK1 0x00AA
92   -#define CMD_UNLOCK2 0x0055
93   -#define CMD_ERASE_SETUP 0x0080
94   -#define CMD_ERASE_CONFIRM 0x0030
95   -#define CMD_PROGRAM 0x00A0
96   -#define CMD_UNLOCK_BYPASS 0x0020
97   -
98   -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555<<1)))
99   -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA<<1)))
100   -
101   -#define BIT_ERASE_DONE 0x0080
102   -#define BIT_RDY_MASK 0x0080
103   -#define BIT_PROGRAM_ERROR 0x0020
104   -#define BIT_TIMEOUT 0x80000000 /* our flag */
105   -
106   -#define READY 1
107   -#define ERR 2
108   -#define TMO 4
109   -
110   -
111   -int flash_erase (flash_info_t * info, int s_first, int s_last)
112   -{
113   - ulong result;
114   - int iflag, prot, sect;
115   - int rc = ERR_OK;
116   - int chip1;
117   - ulong start;
118   -
119   - /* first look for protection bits */
120   -
121   - if (info->flash_id == FLASH_UNKNOWN)
122   - return ERR_UNKNOWN_FLASH_TYPE;
123   -
124   - if ((s_first < 0) || (s_first > s_last)) {
125   - return ERR_INVAL;
126   - }
127   -
128   - if ((info->flash_id & FLASH_VENDMASK) !=
129   - (AMD_MANUFACT & FLASH_VENDMASK)) {
130   - return ERR_UNKNOWN_FLASH_VENDOR;
131   - }
132   -
133   - prot = 0;
134   - for (sect = s_first; sect <= s_last; ++sect) {
135   - if (info->protect[sect]) {
136   - prot++;
137   - }
138   - }
139   - if (prot)
140   - return ERR_PROTECTED;
141   -
142   - /*
143   - * Disable interrupts which might cause a timeout
144   - * here. Remember that our exception vectors are
145   - * at address 0 in the flash, and we don't want a
146   - * (ticker) exception to happen while the flash
147   - * chip is in programming mode.
148   - */
149   - iflag = disable_interrupts ();
150   -
151   - printf ("\n");
152   -
153   - /* Start erase on unprotected sectors */
154   - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
155   - printf ("Erasing sector %2d ... ", sect);
156   -
157   - /* arm simple, non interrupt dependent timer */
158   - start = get_timer(0);
159   -
160   - if (info->protect[sect] == 0) { /* not protected */
161   - volatile u16 *addr =
162   - (volatile u16 *) (info->start[sect]);
163   -
164   - MEM_FLASH_ADDR1 = CMD_UNLOCK1;
165   - MEM_FLASH_ADDR2 = CMD_UNLOCK2;
166   - MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
167   -
168   - MEM_FLASH_ADDR1 = CMD_UNLOCK1;
169   - MEM_FLASH_ADDR2 = CMD_UNLOCK2;
170   - *addr = CMD_ERASE_CONFIRM;
171   -
172   - /* wait until flash is ready */
173   - chip1 = 0;
174   -
175   - do {
176   - result = *addr;
177   -
178   - /* check timeout */
179   - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT * CONFIG_SYS_HZ / 1000) {
180   - MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
181   - chip1 = TMO;
182   - break;
183   - }
184   -
185   - if (!chip1
186   - && (result & 0xFFFF) & BIT_ERASE_DONE)
187   - chip1 = READY;
188   -
189   - } while (!chip1);
190   -
191   - MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
192   -
193   - if (chip1 == ERR) {
194   - rc = ERR_PROG_ERROR;
195   - goto outahere;
196   - }
197   - if (chip1 == TMO) {
198   - rc = ERR_TIMOUT;
199   - goto outahere;
200   - }
201   -
202   - printf ("ok.\n");
203   - } else { /* it was protected */
204   -
205   - printf ("protected!\n");
206   - }
207   - }
208   -
209   - if (ctrlc ())
210   - printf ("User Interrupt!\n");
211   -
212   - outahere:
213   - /* allow flash to settle - wait 10 ms */
214   - printf("Waiting 10 ms...");
215   - udelay (10000);
216   -
217   -/* for (i = 0; i < 10 * 1000 * 1000; ++i)
218   - asm(" nop");
219   -*/
220   -
221   - printf("done\n");
222   - if (iflag)
223   - enable_interrupts ();
224   -
225   -
226   - return rc;
227   -}
228   -
229   -static int write_word (flash_info_t * info, ulong dest, ulong data)
230   -{
231   - volatile u16 *addr = (volatile u16 *) dest;
232   - ulong result;
233   - int rc = ERR_OK;
234   - int iflag;
235   - int chip1;
236   - ulong start;
237   -
238   - /*
239   - * Check if Flash is (sufficiently) erased
240   - */
241   - result = *addr;
242   - if ((result & data) != data)
243   - return ERR_NOT_ERASED;
244   -
245   -
246   - /*
247   - * Disable interrupts which might cause a timeout
248   - * here. Remember that our exception vectors are
249   - * at address 0 in the flash, and we don't want a
250   - * (ticker) exception to happen while the flash
251   - * chip is in programming mode.
252   - */
253   - iflag = disable_interrupts ();
254   -
255   - MEM_FLASH_ADDR1 = CMD_UNLOCK1;
256   - MEM_FLASH_ADDR2 = CMD_UNLOCK2;
257   - MEM_FLASH_ADDR1 = CMD_PROGRAM;
258   - *addr = data;
259   -
260   - /* arm simple, non interrupt dependent timer */
261   - start = get_timer(0);
262   -
263   - /* wait until flash is ready */
264   - chip1 = 0;
265   - do {
266   - result = *addr;
267   -
268   - /* check timeout */
269   - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT * CONFIG_SYS_HZ / 1000) {
270   - chip1 = ERR | TMO;
271   - break;
272   - }
273   - if (!chip1 && ((result & 0x80) == (data & 0x80)))
274   - chip1 = READY;
275   -
276   - } while (!chip1);
277   -
278   - *addr = CMD_READ_ARRAY;
279   -
280   - if (chip1 == ERR || *addr != data)
281   - rc = ERR_PROG_ERROR;
282   -
283   - if (iflag)
284   - enable_interrupts ();
285   -
286   - return rc;
287   -}
288   -
289   -
290   -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
291   -{
292   - ulong wp, data;
293   - int rc;
294   -
295   - if (addr & 1) {
296   - printf ("unaligned destination not supported\n");
297   - return ERR_ALIGN;
298   - }
299   -
300   -#if 0
301   - if (cnt & 1) {
302   - printf ("odd transfer sizes not supported\n");
303   - return ERR_ALIGN;
304   - }
305   -#endif
306   -
307   - wp = addr;
308   -
309   - if (addr & 1) {
310   - data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *)
311   - src);
312   - if ((rc = write_word (info, wp - 1, data)) != 0) {
313   - return (rc);
314   - }
315   - src += 1;
316   - wp += 1;
317   - cnt -= 1;
318   - }
319   -
320   - while (cnt >= 2) {
321   - data = *((volatile u16 *) src);
322   - if ((rc = write_word (info, wp, data)) != 0) {
323   - return (rc);
324   - }
325   - src += 2;
326   - wp += 2;
327   - cnt -= 2;
328   - }
329   -
330   - if (cnt == 1) {
331   - data = (*((volatile u8 *) src) << 8) |
332   - *((volatile u8 *) (wp + 1));
333   - if ((rc = write_word (info, wp, data)) != 0) {
334   - return (rc);
335   - }
336   - src += 1;
337   - wp += 1;
338   - cnt -= 1;
339   - }
340   -
341   - return ERR_OK;
342   -}
board/idmr/idmr.c
View file @ ba650e9
1   -/*
2   - * (C) Copyright 2000-2006
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <common.h>
9   -#include <asm/immap.h>
10   -
11   -int checkboard (void) {
12   - puts ("Board: iDMR\n");
13   - return 0;
14   -};
15   -
16   -phys_size_t initdram (int board_type) {
17   - int i;
18   -
19   - /*
20   - * After reset, CS0 is configured to cover entire address space. We
21   - * need to configure it to its proper values, so that writes to
22   - * CONFIG_SYS_SDRAM_BASE and vicinity during SDRAM controller setup below do
23   - * now fall under CS0 (see 16.3.1 of the MCF5271 Reference Manual).
24   - */
25   -
26   - /* Flash chipselect, CS0 */
27   - /* ;CSAR0: Flash at 0xFF800000 */
28   - mbar_writeShort(0x0080, 0xFF80);
29   -
30   - /* CSCR0: Flash 6 waits, 16bit */
31   - mbar_writeShort(0x008A, 0x1980);
32   -
33   - /* CSMR0: Flash 8MB, R/W, valid */
34   - mbar_writeLong(0x0084, 0x007F0001);
35   -
36   -
37   - /*
38   - * SDRAM configuration proper
39   - */
40   -
41   - /*
42   - * Address/Data Pin Assignment Reg.: enable address lines 23-21; do
43   - * not enable data pins D[15:0], as we have 16 bit port to SDRAM
44   - */
45   - mbar_writeByte(MCF_GPIO_PAR_AD,
46   - MCF_GPIO_AD_ADDR23 |
47   - MCF_GPIO_AD_ADDR22 |
48   - MCF_GPIO_AD_ADDR21);
49   -
50   - /* No need to configure BS pins - reset values are OK */
51   -
52   - /* Chip Select Pin Assignment Reg.: set CS[1-7] to GPIO */
53   - mbar_writeByte(MCF_GPIO_PAR_CS, 0x00);
54   -
55   - /* SDRAM Control Pin Assignment Reg. */
56   - mbar_writeByte(MCF_GPIO_PAR_SDRAM,
57   - MCF_GPIO_SDRAM_CSSDCS_00 | /* no matter: PAR_CS=0 */
58   - MCF_GPIO_SDRAM_SDWE |
59   - MCF_GPIO_SDRAM_SCAS |
60   - MCF_GPIO_SDRAM_SRAS |
61   - MCF_GPIO_SDRAM_SCKE |
62   - MCF_GPIO_SDRAM_SDCS_01);
63   -
64   - /*
65   - * Wait 100us. We run the bus at 50MHz, one cycle is 20ns. So 5
66   - * iterations will do, but we do 10 just to be safe.
67   - */
68   - for (i = 0; i < 10; ++i)
69   - asm(" nop");
70   -
71   -
72   - /* 1. Initialize DRAM Control Register: DCR */
73   - mbar_writeShort(MCF_SDRAMC_DCR,
74   - MCF_SDRAMC_DCR_RTIM(0x10) | /* 65ns */
75   - MCF_SDRAMC_DCR_RC(0x60)); /* 1562 cycles */
76   -
77   -
78   - /*
79   - * 2. Initialize DACR0
80   - *
81   - * CL: 11 (CL=3: 0x03, 0x02; CL=2: 0x1)
82   - * CBM: cmd at A20, bank select bits 21 and up
83   - * PS: 16 bit
84   - */
85   - mbar_writeLong(MCF_SDRAMC_DACR0,
86   - MCF_SDRAMC_DACRn_BA(CONFIG_SYS_SDRAM_BASE>>18) |
87   - MCF_SDRAMC_DACRn_BA(0x00) |
88   - MCF_SDRAMC_DACRn_CASL(0x03) |
89   - MCF_SDRAMC_DACRn_CBM(0x03) |
90   - MCF_SDRAMC_DACRn_PS(0x03));
91   -
92   - /* Initialize DMR0 */
93   - mbar_writeLong(MCF_SDRAMC_DMR0,
94   - MCF_SDRAMC_DMRn_BAM_16M |
95   - MCF_SDRAMC_DMRn_V);
96   -
97   -
98   - /* 3. Set IP bit in DACR to initiate PALL command */
99   - mbar_writeLong(MCF_SDRAMC_DACR0,
100   - mbar_readLong(MCF_SDRAMC_DACR0) |
101   - MCF_SDRAMC_DACRn_IP);
102   -
103   - /* Write to this block to initiate precharge */
104   - *(volatile u16 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5;
105   -
106   - /*
107   - * Wait at least 20ns to allow banks to precharge (t_RP = 20ns). We
108   - * wait a wee longer, just to be safe.
109   - */
110   - for (i = 0; i < 5; ++i)
111   - asm(" nop");
112   -
113   -
114   - /* 4. Set RE bit in DACR */
115   - mbar_writeLong(MCF_SDRAMC_DACR0,
116   - mbar_readLong(MCF_SDRAMC_DACR0) |
117   - MCF_SDRAMC_DACRn_RE);
118   -
119   - /*
120   - * Wait for at least 8 auto refresh cycles to occur, i.e. at least
121   - * 781 bus cycles.
122   - */
123   - for (i = 0; i < 1000; ++i)
124   - asm(" nop");
125   -
126   - /* Finish the configuration by issuing the MRS */
127   - mbar_writeLong(MCF_SDRAMC_DACR0,
128   - mbar_readLong(MCF_SDRAMC_DACR0) |
129   - MCF_SDRAMC_DACRn_MRS);
130   -
131   - /*
132   - * Write to the SDRAM Mode Register A0-A11 = 0x400
133   - *
134   - * Write Burst Mode = Programmed Burst Length
135   - * Op Mode = Standard Op
136   - * CAS Latency = 3
137   - * Burst Type = Sequential
138   - * Burst Length = 1
139   - */
140   - *(volatile u32 *)(CONFIG_SYS_SDRAM_BASE + 0x1800) = 0xa5a5a5a5;
141   -
142   - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
143   -};
144   -
145   -
146   -int testdram (void) {
147   -
148   - /* TODO: XXX XXX XXX */
149   - printf ("DRAM test not implemented!\n");
150   -
151   - return (0);
152   -}
board/idmr/u-boot.lds
View file @ ba650e9
1   -/*
2   - * (C) Copyright 2000
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -OUTPUT_ARCH(m68k)
9   -
10   -SECTIONS
11   -{
12   - .text :
13   - {
14   - arch/m68k/cpu/mcf52x2/start.o (.text*)
15   -
16   - *(.text*)
17   - }
18   - _etext = .;
19   - PROVIDE (etext = .);
20   - .rodata :
21   - {
22   - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
23   - }
24   -
25   - /* Read-write section, merged into data segment: */
26   - . = (. + 0x00FF) & 0xFFFFFF00;
27   - _erotext = .;
28   - PROVIDE (erotext = .);
29   -
30   - .reloc :
31   - {
32   - __got_start = .;
33   - KEEP(*(.got))
34   - __got_end = .;
35   - _GOT2_TABLE_ = .;
36   - KEEP(*(.got2))
37   - _FIXUP_TABLE_ = .;
38   - KEEP(*(.fixup))
39   - }
40   - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
41   - __fixup_entries = (. - _FIXUP_TABLE_)>>2;
42   -
43   - .data :
44   - {
45   - *(.data*)
46   - *(.sdata*)
47   - }
48   - _edata = .;
49   - PROVIDE (edata = .);
50   -
51   - . = .;
52   -
53   - . = ALIGN(4);
54   - .u_boot_list : {
55   - KEEP(*(SORT(.u_boot_list*)));
56   - }
57   -
58   - . = .;
59   - __start___ex_table = .;
60   - __ex_table : { *(__ex_table) }
61   - __stop___ex_table = .;
62   -
63   - . = ALIGN(256);
64   - __init_begin = .;
65   - .text.init : { *(.text.init) }
66   - .data.init : { *(.data.init) }
67   - . = ALIGN(256);
68   - __init_end = .;
69   -
70   - __bss_start = .;
71   - .bss (NOLOAD) :
72   - {
73   - _sbss = .;
74   - *(.bss*)
75   - *(.sbss*)
76   - *(COMMON)
77   - . = ALIGN(4);
78   - _ebss = .;
79   - }
80   - __bss_end = . ;
81   - PROVIDE (end = .);
82   -}
... ... @@ -453,7 +453,6 @@
453 453 Active m68k mcf5227x - freescale m52277evb M52277EVB_stmicro M52277EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x43E00000 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
454 454 Active m68k mcf523x - freescale m5235evb M5235EVB M5235EVB:SYS_TEXT_BASE=0xFFE00000 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
455 455 Active m68k mcf523x - freescale m5235evb M5235EVB_Flash32 M5235EVB:NORFLASH_PS32BIT,SYS_TEXT_BASE=0xFFC00000 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
456   -Active m68k mcf52x2 - - - idmr - -
457 456 Active m68k mcf52x2 - - cobra5272 cobra5272 - -
458 457 Active m68k mcf52x2 - BuS eb_cpu5282 eb_cpu5282 eb_cpu5282:SYS_TEXT_BASE=0xFF000000,SYS_MONITOR_BASE=0xFF000400 Jens Scharsig <esw@bus-elektronik.de>
459 458 Active m68k mcf52x2 - BuS eb_cpu5282 eb_cpu5282_internal eb_cpu5282:SYS_TEXT_BASE=0xF0000000,SYS_MONITOR_BASE=0xF0000418 Jens Scharsig <esw@bus-elektronik.de>
... ... @@ -462,7 +461,6 @@
462 461 Active m68k mcf52x2 - freescale m5249evb M5249EVB - -
463 462 Active m68k mcf52x2 - freescale m5253demo M5253DEMO - TsiChung Liew <Tsi-Chung.Liew@freescale.com>
464 463 Active m68k mcf52x2 - freescale m5253evbe M5253EVBE - Hayden Fraser <Hayden.Fraser@freescale.com>
465   -Active m68k mcf52x2 - freescale m5271evb M5271EVB - -
466 464 Active m68k mcf52x2 - freescale m5272c3 M5272C3 - -
467 465 Active m68k mcf52x2 - freescale m5275evb M5275EVB - -
468 466 Active m68k mcf52x2 - freescale m5282evb M5282EVB - -
doc/README.scrapyard
Diff comments   View file @ ba650e9
... ... @@ -11,13 +11,15 @@
11 11  
12 12 Board Arch CPU Commit Removed Last known maintainer/contact
13 13 =================================================================================================
14   -dvl_host arm ixp - 2014-01-28 Michael Schwingen <michael@schwingen.org>
15   -actux4 arm ixp - 2014-01-28 Michael Schwingen <michael@schwingen.org>
16   -actux3 arm ixp - 2014-01-28 Michael Schwingen <michael@schwingen.org>
17   -actux2 arm ixp - 2014-01-28 Michael Schwingen <michael@schwingen.org>
18   -actux1 arm ixp - 2014-01-28 Michael Schwingen <michael@schwingen.org>
19   -mx1ads arm arm920t - 2014-01-13
20   -mini2440 arm arm920t - 2014-01-13 Gabriel Huau <contact@huau-gabriel.fr>
  14 +idmr m68k mcf52x2 - 2014-01-28
  15 +M5271EVB m68k mcf52x2 - 2014-01-28
  16 +dvl_host arm ixp e317de6b 2014-01-28 Michael Schwingen <michael@schwingen.org>
  17 +actux4 arm ixp 6ff7aafa 2014-01-28 Michael Schwingen <michael@schwingen.org>
  18 +actux3 arm ixp 38da33f3 2014-01-28 Michael Schwingen <michael@schwingen.org>
  19 +actux2 arm ixp 13e0ee7f 2014-01-28 Michael Schwingen <michael@schwingen.org>
  20 +actux1 arm ixp 373ee048 2014-01-28 Michael Schwingen <michael@schwingen.org>
  21 +mx1ads arm arm920t e570aca9 2014-01-13
  22 +mini2440 arm arm920t af5b9b1f 2014-01-13 Gabriel Huau <contact@huau-gabriel.fr>
21 23 omap730p2 arm arm926ejs 79c5c08d 2013-11-11
22 24 pn62 powerpc mpc824x 649acfe1 2013-11-11 Wolfgang Grandegger <wg@grandegger.com>
23 25 pdnb3 arm ixp 304db0b 2013-09-24 Stefan Roese <sr@denx.de>
include/configs/M5271EVB.h
View file @ ba650e9
1   -/*
2   - * Configuation settings for the Freescale M5271EVB
3   - *
4   - * Based on MC5272C3 and r5200 board configs
5   - * (C) Copyright 2006 Lab X Technologies <zachary.landau@labxtechnologies.com>
6   - * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
7   - *
8   - * SPDX-License-Identifier: GPL-2.0+
9   - */
10   -
11   -/*
12   - * board/config.h - configuration options, board specific
13   - */
14   -
15   -#ifndef _M5271EVB_H
16   -#define _M5271EVB_H
17   -
18   -/*
19   - * High Level Configuration Options (easy to change)
20   - */
21   -#define CONFIG_MCF52x2 /* define processor family */
22   -#define CONFIG_M5271 /* define processor type */
23   -#define CONFIG_M5271EVB /* define board type */
24   -
25   -#define CONFIG_MCFTMR
26   -
27   -#define CONFIG_MCFUART
28   -#define CONFIG_SYS_UART_PORT (0)
29   -#define CONFIG_BAUDRATE 115200
30   -
31   -#undef CONFIG_WATCHDOG /* disable watchdog */
32   -
33   -/* Configuration for environment
34   - * Environment is embedded in u-boot in the second sector of the flash
35   - */
36   -#ifndef CONFIG_MONITOR_IS_IN_RAM
37   -#define CONFIG_ENV_OFFSET 0x4000
38   -#else
39   -#define CONFIG_ENV_ADDR 0xffe04000
40   -#endif
41   -#define CONFIG_ENV_SECT_SIZE 0x2000
42   -#define CONFIG_ENV_IS_IN_FLASH 1
43   -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
44   -
45   -/*
46   - * BOOTP options
47   - */
48   -#define CONFIG_BOOTP_BOOTFILESIZE
49   -#define CONFIG_BOOTP_BOOTPATH
50   -#define CONFIG_BOOTP_GATEWAY
51   -#define CONFIG_BOOTP_HOSTNAME
52   -
53   -/*
54   - * Command line configuration.
55   - */
56   -#include <config_cmd_default.h>
57   -
58   -#define CONFIG_CMD_CACHE
59   -#define CONFIG_CMD_PING
60   -#define CONFIG_CMD_NET
61   -#define CONFIG_CMD_MII
62   -#define CONFIG_CMD_ELF
63   -#define CONFIG_CMD_FLASH
64   -#define CONFIG_CMD_I2C
65   -#define CONFIG_CMD_MEMORY
66   -#define CONFIG_CMD_MISC
67   -
68   -#undef CONFIG_CMD_LOADS
69   -#define CONFIG_CMD_LOADB
70   -#define CONFIG_CMDLINE_EDITING 1 /* enables command line history */
71   -#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
72   -
73   -#define CONFIG_MCFFEC
74   -#ifdef CONFIG_MCFFEC
75   -# define CONFIG_MII 1
76   -# define CONFIG_MII_INIT 1
77   -# define CONFIG_SYS_DISCOVER_PHY
78   -# define CONFIG_SYS_RX_ETH_BUFFER 8
79   -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
80   -
81   -# define CONFIG_SYS_FEC0_PINMUX 0
82   -# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
83   -# define MCFFEC_TOUT_LOOP 50000
84   -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
85   -# ifndef CONFIG_SYS_DISCOVER_PHY
86   -# define FECDUPLEX FULL
87   -# define FECSPEED _100BASET
88   -# else
89   -# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
90   -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
91   -# endif
92   -# endif /* CONFIG_SYS_DISCOVER_PHY */
93   -#endif
94   -
95   -/* I2C */
96   -#define CONFIG_SYS_I2C
97   -#define CONFIG_SYS_I2C_FSL
98   -#define CONFIG_SYS_FSL_I2C_SPEED 80000
99   -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
100   -#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
101   -#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
102   -
103   -#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */
104   -#define CONFIG_BOOTFILE "u-boot.bin"
105   -#ifdef CONFIG_MCFFEC
106   -# define CONFIG_NET_RETRY_COUNT 5
107   -# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
108   -# define CONFIG_IPADDR 192.162.1.2
109   -# define CONFIG_NETMASK 255.255.255.0
110   -# define CONFIG_SERVERIP 192.162.1.1
111   -# define CONFIG_GATEWAYIP 192.162.1.1
112   -# define CONFIG_OVERWRITE_ETHADDR_ONCE
113   -#endif /* FEC_ENET */
114   -
115   -#define CONFIG_HOSTNAME M5271EVB
116   -#define CONFIG_EXTRA_ENV_SETTINGS \
117   - "netdev=eth0\0" \
118   - "loadaddr=10000\0" \
119   - "uboot=u-boot.bin\0" \
120   - "load=tftp $loadaddr $uboot\0" \
121   - "upd=run load; run prog\0" \
122   - "prog=prot off ffe00000 ffe3ffff;" \
123   - "era ffe00000 ffe3ffff;" \
124   - "cp.b $loadaddr ffe00000 $filesize;" \
125   - "save\0" \
126   - ""
127   -
128   -#define CONFIG_SYS_LONGHELP /* undef to save memory */
129   -
130   -#if defined(CONFIG_CMD_KGDB)
131   -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
132   -#else
133   -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
134   -#endif
135   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
136   -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
137   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
138   -
139   -#define CONFIG_SYS_LOAD_ADDR 0x00100000
140   -
141   -#define CONFIG_SYS_MEMTEST_START 0x400
142   -#define CONFIG_SYS_MEMTEST_END 0x380000
143   -
144   -#define CONFIG_SYS_HZ 1000000
145   -
146   -/* Clock configuration
147   - * The external oscillator is a 25.000 MHz
148   - * CONFIG_SYS_CLK for ColdFire V2 sets cpu_clk (not bus_clk)
149   - * bus_clk = (cpu_clk/2) (fixed ratio)
150   - *
151   - * If CONFIG_SYS_CLK is changed. the CONFIG_SYS_MCF_SYNCR must be updated to
152   - * match the new clock speed. Max cpu_clk is 150 MHz.
153   - */
154   -#define CONFIG_SYS_CLK 100000000
155   -#define CONFIG_SYS_MCF_SYNCR (MCF_SYNCR_MFD_4X | MCF_SYNCR_RFD_DIV1)
156   -
157   -/*
158   - * Low Level Configuration Settings
159   - * (address mappings, register initial values, etc.)
160   - * You should know what you are doing if you make changes here.
161   - */
162   -
163   -#define CONFIG_SYS_MBAR 0x40000000 /* Register Base Addrs */
164   -
165   -/*
166   - * Definitions for initial stack pointer and data area (in DPRAM)
167   - */
168   -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
169   -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
170   -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
171   -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
172   -
173   -/*
174   - * Start addresses for the final memory configuration
175   - * (Set up by the startup code)
176   - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
177   - */
178   -#define CONFIG_SYS_SDRAM_BASE 0x00000000
179   -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
180   -#define CONFIG_SYS_FLASH_BASE 0xffe00000
181   -
182   -#ifdef CONFIG_MONITOR_IS_IN_RAM
183   -#define CONFIG_SYS_MONITOR_BASE 0x20000
184   -#else
185   -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
186   -#endif
187   -
188   -#define CONFIG_SYS_MONITOR_LEN 0x40000
189   -#define CONFIG_SYS_MALLOC_LEN (256 << 10)
190   -#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
191   -
192   -/*
193   - * For booting Linux, the board info and command line data
194   - * have to be in the first 8 MB of memory, since this is
195   - * the maximum mapped by the Linux kernel during initialization ??
196   - */
197   -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
198   -
199   -/* FLASH organization */
200   -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
201   -#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
202   -#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
203   -
204   -#define CONFIG_SYS_FLASH_CFI 1
205   -#define CONFIG_FLASH_CFI_DRIVER 1
206   -#define CONFIG_SYS_FLASH_SIZE 0x200000
207   -
208   -/* Cache Configuration */
209   -#define CONFIG_SYS_CACHELINE_SIZE 16
210   -
211   -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
212   - CONFIG_SYS_INIT_RAM_SIZE - 8)
213   -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
214   - CONFIG_SYS_INIT_RAM_SIZE - 4)
215   -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
216   -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
217   - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
218   - CF_ACR_EN | CF_ACR_SM_ALL)
219   -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
220   - CF_CACR_DISD | CF_CACR_INVI | \
221   - CF_CACR_CEIB | CF_CACR_DCM | \
222   - CF_CACR_EUSP)
223   -
224   -/* Chip Select 0 : Boot Flash */
225   -#define CONFIG_SYS_CS0_BASE 0xFFE00000
226   -#define CONFIG_SYS_CS0_MASK 0x001F0001
227   -#define CONFIG_SYS_CS0_CTRL 0x00001980
228   -
229   -/* Chip Select 1 : External SRAM */
230   -#define CONFIG_SYS_CS1_BASE 0x30000000
231   -#define CONFIG_SYS_CS1_MASK 0x00070001
232   -#define CONFIG_SYS_CS1_CTRL 0x00001900
233   -
234   -#endif /* _M5271EVB_H */
include/configs/idmr.h
View file @ ba650e9
1   -/*
2   - * Configuration settings for the iDMR board
3   - *
4   - * Based on MC5272C3, r5200 and M5271EVB board configs
5   - * (C) Copyright 2006 Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6   - * (C) Copyright 2006 Lab X Technologies <zachary.landau@labxtechnologies.com>
7   - * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
8   - *
9   - * SPDX-License-Identifier: GPL-2.0+
10   - */
11   -
12   -#ifndef _IDMR_H
13   -#define _IDMR_H
14   -
15   -
16   -/*
17   - * High Level Configuration Options (easy to change)
18   - */
19   -
20   -#define CONFIG_MCF52x2 /* define processor family */
21   -#define CONFIG_M5271 /* define processor type */
22   -#define CONFIG_IDMR /* define board type */
23   -
24   -#undef CONFIG_WATCHDOG /* disable watchdog */
25   -
26   -/*
27   - * Default environment settings
28   - */
29   -#define CONFIG_BOOTCOMMAND "run net_nfs"
30   -#define CONFIG_BOOTDELAY 5
31   -#define CONFIG_MCFUART
32   -#define CONFIG_SYS_UART_PORT (0)
33   -#define CONFIG_BAUDRATE 19200
34   -#define CONFIG_ETHADDR 00:06:3b:01:41:55
35   -#define CONFIG_ETHPRIME
36   -#define CONFIG_IPADDR 192.168.30.1
37   -#define CONFIG_SERVERIP 192.168.1.1
38   -#define CONFIG_ROOTPATH ""
39   -#define CONFIG_GATEWAYIP 192.168.1.1
40   -#define CONFIG_NETMASK 255.255.0.0
41   -#define CONFIG_HOSTNAME idmr
42   -#define CONFIG_BOOTFILE "/tftpboot/idmr/uImage"
43   -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root " \
44   - "filesystem over NFS; echo"
45   -
46   -#define CONFIG_MCFTMR
47   -
48   -#define CONFIG_EXTRA_ENV_SETTINGS \
49   - "netdev=eth0\0" \
50   - "ramargs=setenv bootargs root=/dev/ram rw\0" \
51   - "addip=setenv bootargs $(bootargs) " \
52   - "ip=$(ipaddr):$(serverip):$(gatewayip):" \
53   - "$(netmask):$(hostname):$(netdev):off panic=1\0" \
54   - "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \
55   - "flash_self=run ramargs addip;bootm $(kernel_addr) " \
56   - "$(ramdisk_addr)\0" \
57   - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
58   - "nfsargs=setenv bootargs root=/dev/nfs rw " \
59   - "nfsroot=$(serverip):$(rootpath)\0" \
60   - "ethact=FEC\0 " \
61   - "update=prot off ff800000 ff81ffff; era ff800000 ff81ffff; " \
62   - "cp.b 200000 ff800000 $(filesize);" \
63   - "prot on ff800000 ff81ffff\0" \
64   - "load=tftp 200000 $(u-boot)\0" \
65   - "u-boot=/tftpboot/idmr/u-boot.bin\0" \
66   - ""
67   -
68   -
69   -/*
70   - * BOOTP options
71   - */
72   -#define CONFIG_BOOTP_BOOTFILESIZE
73   -#define CONFIG_BOOTP_BOOTPATH
74   -#define CONFIG_BOOTP_GATEWAY
75   -#define CONFIG_BOOTP_HOSTNAME
76   -
77   -
78   -/*
79   - * Command line configuration.
80   - */
81   -#include <config_cmd_default.h>
82   -
83   -#define CONFIG_CMD_PING
84   -#define CONFIG_CMD_JFFS2
85   -#define CONFIG_CMD_NET
86   -
87   -#undef CONFIG_CMD_LOADS
88   -#undef CONFIG_CMD_LOADB
89   -
90   -
91   -/*
92   - * Low Level Configuration Settings
93   - * (address mappings, register initial values, etc.)
94   - * You should know what you are doing if you make changes here.
95   - */
96   -
97   -/*
98   - * Configuration for environment, which occupies third sector in flash.
99   - */
100   -#ifndef CONFIG_MONITOR_IS_IN_RAM
101   -#define CONFIG_ENV_ADDR 0xff820000
102   -#define CONFIG_ENV_SECT_SIZE 0x10000
103   -#define CONFIG_ENV_SIZE 0x2000
104   -#define CONFIG_ENV_IS_IN_FLASH
105   -#else /* CONFIG_MONITOR_IS_IN_RAM */
106   -#define CONFIG_ENV_OFFSET 0x4000
107   -#define CONFIG_ENV_SECT_SIZE 0x2000
108   -#define CONFIG_ENV_IS_IN_FLASH
109   -#endif /* !CONFIG_MONITOR_IS_IN_RAM */
110   -
111   -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
112   -
113   -#define CONFIG_SYS_LONGHELP /* undef to save memory */
114   -
115   -#if defined(CONFIG_CMD_KGDB)
116   -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
117   -#else
118   -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
119   -#endif
120   -
121   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
122   -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
123   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
124   -
125   -#define CONFIG_SYS_LOAD_ADDR 0x00100000
126   -
127   -#define CONFIG_SYS_MEMTEST_START 0x400
128   -#define CONFIG_SYS_MEMTEST_END 0x380000
129   -
130   -#define CONFIG_SYS_HZ (50000000 / 64)
131   -#define CONFIG_SYS_CLK 100000000
132   -
133   -#define CONFIG_SYS_MBAR 0x40000000 /* Register Base Addrs */
134   -
135   -/*
136   - * Ethernet
137   - */
138   -#define CONFIG_MCFFEC
139   -#ifdef CONFIG_MCFFEC
140   -# define CONFIG_MII 1
141   -# define CONFIG_MII_INIT 1
142   -# define CONFIG_SYS_DISCOVER_PHY
143   -# define CONFIG_SYS_RX_ETH_BUFFER 8
144   -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
145   -
146   -# define CONFIG_SYS_FEC0_PINMUX 0
147   -# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
148   -# define MCFFEC_TOUT_LOOP 50000
149   -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
150   -# ifndef CONFIG_SYS_DISCOVER_PHY
151   -# define FECDUPLEX FULL
152   -# define FECSPEED _100BASET
153   -# else
154   -# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
155   -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
156   -# endif
157   -# endif /* CONFIG_SYS_DISCOVER_PHY */
158   -#endif
159   -
160   -/*
161   - * Definitions for initial stack pointer and data area (in DPRAM)
162   - */
163   -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
164   -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
165   -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
166   -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
167   -
168   -/*
169   - * Start addresses for the final memory configuration
170   - * (Set up by the startup code)
171   - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
172   - */
173   -#define CONFIG_SYS_SDRAM_BASE 0x00000000
174   -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
175   -#define CONFIG_SYS_FLASH_BASE 0xff800000
176   -
177   -#ifdef CONFIG_MONITOR_IS_IN_RAM
178   -#define CONFIG_SYS_MONITOR_BASE 0x20000
179   -#else /* !CONFIG_MONITOR_IS_IN_RAM */
180   -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
181   -#endif /* CONFIG_MONITOR_IS_IN_RAM */
182   -
183   -#define CONFIG_SYS_MONITOR_LEN 0x20000
184   -#define CONFIG_SYS_MALLOC_LEN (256 << 10)
185   -#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
186   -
187   -/*
188   - * For booting Linux, the board info and command line data
189   - * have to be in the first 8 MB of memory, since this is
190   - * the maximum mapped by the Linux kernel during initialization ??
191   - */
192   -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
193   -
194   -/* FLASH organization */
195   -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
196   -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
197   -#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
198   -
199   -#define CONFIG_SYS_FLASH_SIZE 0x800000
200   -/*
201   - * #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
202   - */
203   -
204   -/* Cache Configuration */
205   -#define CONFIG_SYS_CACHELINE_SIZE 16
206   -
207   -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
208   - CONFIG_SYS_INIT_RAM_SIZE - 8)
209   -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
210   - CONFIG_SYS_INIT_RAM_SIZE - 4)
211   -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
212   -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
213   - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
214   - CF_ACR_EN | CF_ACR_SM_ALL)
215   -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
216   - CF_CACR_DISD | CF_CACR_INVI | \
217   - CF_CACR_CEIB | CF_CACR_DCM | \
218   - CF_CACR_EUSP)
219   -
220   -/* Port configuration */
221   -#define CONFIG_SYS_FECI2C 0xF0
222   -
223   -
224   -/* Dynamic MTD partition support */
225   -#define CONFIG_CMD_MTDPARTS
226   -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
227   -#define CONFIG_FLASH_CFI_MTD
228   -#define MTDIDS_DEFAULT "nor0=idmr-0"
229   -
230   -#define MTDPARTS_DEFAULT "mtdparts=idmr-0:128k(u-boot)," \
231   - "64k(env)," \
232   - "640k(kernel)," \
233   - "2m(rootfs)," \
234   - "-(user)";
235   -
236   -#if defined(CONFIG_CMD_MII)
237   -#error "MII commands don't work on iDMR board and should not be enabled."
238   -#endif
239   -
240   -#endif /* _IDMR_H */