Eric Lee / smarc-uboot

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Commit bcdbe240bb2a97d38ba30dd244a51ece87662b06

Authored by Robby Cai
1 parent fd8fbf7fa0
Exists in smarc-rel_imx_4.1.15_2.0.0_ga

MLK-12929 imx6ull: support splash screen for epdc 

add splash screen feature for epdc.
it's tested on imx6ull arm2 board.

Signed-off-by: Robby Cai <robby.cai@nxp.com>

Showing 7 changed files with 322 additions and 1 deletions Side-by-side Diff

arch/arm/cpu/armv7/mx6/clock.c
Diff comments   View file @ bcdbe24
... ... @@ -1372,6 +1372,35 @@
1372 1372 }
1373 1373 }
1374 1374  
  1375 +#if defined(CONFIG_MXC_EPDC) && defined(CONFIG_MX6ULL)
  1376 +void enable_epdc_clock(void)
  1377 +{
  1378 + u32 reg = 0;
  1379 +
  1380 + /* disable the clock gate first */
  1381 + clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_EPDC_CLK_ENABLE_MASK);
  1382 +
  1383 + /* PLL3_PFD2 */
  1384 + reg = readl(&imx_ccm->chsccdr);
  1385 + reg &= ~MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_MASK;
  1386 + reg |= 5 << MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_OFFSET;
  1387 + writel(reg, &imx_ccm->chsccdr);
  1388 +
  1389 + reg = readl(&imx_ccm->chsccdr);
  1390 + reg &= ~MXC_CCM_CHSCCDR_EPDC_PODF_MASK;
  1391 + reg |= 7 << MXC_CCM_CHSCCDR_EPDC_PODF_OFFSET;
  1392 + writel(reg, &imx_ccm->chsccdr);
  1393 +
  1394 + reg = readl(&imx_ccm->chsccdr);
  1395 + reg &= ~MXC_CCM_CHSCCDR_EPDC_CLK_SEL_MASK;
  1396 + reg |= 0 <<MXC_CCM_CHSCCDR_EPDC_CLK_SEL_OFFSET;
  1397 + writel(reg, &imx_ccm->chsccdr);
  1398 +
  1399 + /* enable the clock gate */
  1400 + setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_EPDC_CLK_ENABLE_MASK);
  1401 +}
  1402 +#endif
  1403 +
1375 1404 /***************************************************/
1376 1405  
1377 1406 U_BOOT_CMD(
arch/arm/include/asm/arch-mx6/clock.h
Diff comments   View file @ bcdbe24
... ... @@ -72,6 +72,7 @@
72 72 int enable_lvds_bridge(u32 lcd_base_addr);
73 73 void enable_qspi_clk(int qspi_num);
74 74 void enable_thermal_clk(void);
  75 +void enable_epdc_clock(void);
75 76 void mxs_set_lcdclk(u32 base_addr, u32 freq);
76 77 void mxs_set_vadcclk(void);
77 78 #endif /* __ASM_ARCH_CLOCK_H */
arch/arm/include/asm/arch-mx6/mx6ull_pins.h
Diff comments   View file @ bcdbe24
... ... @@ -430,6 +430,7 @@
430 430 MX6_PAD_ENET2_RX_DATA0__GPIO2_IO08 = IOMUX_PAD(0x0370, 0x00E4, 5, 0x0000, 0, 0),
431 431 MX6_PAD_ENET2_RX_DATA0__KPP_ROW04 = IOMUX_PAD(0x0370, 0x00E4, 6, 0x0000, 0, 0),
432 432 MX6_PAD_ENET2_RX_DATA0__USB_OTG1_PWR = IOMUX_PAD(0x0370, 0x00E4, 8, 0x0000, 0, 0),
  433 + MX6_PAD_ENET2_RX_DATA0__EPDC_SDDO08 = IOMUX_PAD(0x0370, 0x00E4, 9, 0x0000, 0, 0),
433 434  
434 435 MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 = IOMUX_PAD(0x0374, 0x00E8, 0, 0x0000, 0, 0),
435 436 MX6_PAD_ENET2_RX_DATA1__UART6_DCE_RX = IOMUX_PAD(0x0374, 0x00E8, 1, 0x064C, 2, 0),
... ... @@ -440,6 +441,7 @@
440 441 MX6_PAD_ENET2_RX_DATA1__GPIO2_IO09 = IOMUX_PAD(0x0374, 0x00E8, 5, 0x0000, 0, 0),
441 442 MX6_PAD_ENET2_RX_DATA1__KPP_COL04 = IOMUX_PAD(0x0374, 0x00E8, 6, 0x0000, 0, 0),
442 443 MX6_PAD_ENET2_RX_DATA1__USB_OTG1_OC = IOMUX_PAD(0x0374, 0x00E8, 8, 0x0664, 1, 0),
  444 + MX6_PAD_ENET2_RX_DATA1__EPDC_SDDO09 = IOMUX_PAD(0x0374, 0x00E8, 9, 0x0000, 0, 0),
443 445  
444 446 MX6_PAD_ENET2_RX_EN__ENET2_RX_EN = IOMUX_PAD(0x0378, 0x00EC, 0, 0x0000, 0, 0),
445 447 MX6_PAD_ENET2_RX_EN__UART7_DCE_TX = IOMUX_PAD(0x0378, 0x00EC, 1, 0x0000, 0, 0),
... ... @@ -450,6 +452,7 @@
450 452 MX6_PAD_ENET2_RX_EN__GPIO2_IO10 = IOMUX_PAD(0x0378, 0x00EC, 5, 0x0000, 0, 0),
451 453 MX6_PAD_ENET2_RX_EN__KPP_ROW05 = IOMUX_PAD(0x0378, 0x00EC, 6, 0x0000, 0, 0),
452 454 MX6_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M = IOMUX_PAD(0x0378, 0x00EC, 8, 0x0000, 0, 0),
  455 + MX6_PAD_ENET2_RX_EN__EPDC_SDDO10 = IOMUX_PAD(0x0378, 0x00EC, 9, 0x0000, 0, 0),
453 456  
454 457 MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 = IOMUX_PAD(0x037C, 0x00F0, 0, 0x0000, 0, 0),
455 458 MX6_PAD_ENET2_TX_DATA0__UART7_DCE_RX = IOMUX_PAD(0x037C, 0x00F0, 1, 0x0654, 1, 0),
... ... @@ -459,6 +462,7 @@
459 462 MX6_PAD_ENET2_TX_DATA0__EIM_EB_B02 = IOMUX_PAD(0x037C, 0x00F0, 4, 0x0000, 0, 0),
460 463 MX6_PAD_ENET2_TX_DATA0__GPIO2_IO11 = IOMUX_PAD(0x037C, 0x00F0, 5, 0x0000, 0, 0),
461 464 MX6_PAD_ENET2_TX_DATA0__KPP_COL05 = IOMUX_PAD(0x037C, 0x00F0, 6, 0x0000, 0, 0),
  465 + MX6_PAD_ENET2_TX_DATA0__EPDC_SDDO11 = IOMUX_PAD(0x037C, 0x00F0, 9, 0x0000, 0, 0),
462 466  
463 467 MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 = IOMUX_PAD(0x0380, 0x00F4, 0, 0x0000, 0, 0),
464 468 MX6_PAD_ENET2_TX_DATA1__UART8_DCE_TX = IOMUX_PAD(0x0380, 0x00F4, 1, 0x0000, 0, 0),
... ... @@ -469,6 +473,7 @@
469 473 MX6_PAD_ENET2_TX_DATA1__GPIO2_IO12 = IOMUX_PAD(0x0380, 0x00F4, 5, 0x0000, 0, 0),
470 474 MX6_PAD_ENET2_TX_DATA1__KPP_ROW06 = IOMUX_PAD(0x0380, 0x00F4, 6, 0x0000, 0, 0),
471 475 MX6_PAD_ENET2_TX_DATA1__USB_OTG2_PWR = IOMUX_PAD(0x0380, 0x00F4, 8, 0x0000, 0, 0),
  476 + MX6_PAD_ENET2_TX_DATA1__EPDC_SDDO12 = IOMUX_PAD(0x0380, 0x00F4, 9, 0x0000, 0, 0),
472 477  
473 478 MX6_PAD_ENET2_TX_EN__ENET2_TX_EN = IOMUX_PAD(0x0384, 0x00F8, 0, 0x0000, 0, 0),
474 479 MX6_PAD_ENET2_TX_EN__UART8_DCE_RX = IOMUX_PAD(0x0384, 0x00F8, 1, 0x065C, 1, 0),
... ... @@ -479,6 +484,7 @@
479 484 MX6_PAD_ENET2_TX_EN__GPIO2_IO13 = IOMUX_PAD(0x0384, 0x00F8, 5, 0x0000, 0, 0),
480 485 MX6_PAD_ENET2_TX_EN__KPP_COL06 = IOMUX_PAD(0x0384, 0x00F8, 6, 0x0000, 0, 0),
481 486 MX6_PAD_ENET2_TX_EN__USB_OTG2_OC = IOMUX_PAD(0x0384, 0x00F8, 8, 0x0660, 1, 0),
  487 + MX6_PAD_ENET2_TX_EN__EPDC_SDDO13 = IOMUX_PAD(0x0384, 0x00F8, 9, 0x0000, 0, 0),
482 488  
483 489 MX6_PAD_ENET2_TX_CLK__ENET2_TX_CLK = IOMUX_PAD(0x0388, 0x00FC, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0),
484 490 MX6_PAD_ENET2_TX_CLK__UART8_DCE_CTS = IOMUX_PAD(0x0388, 0x00FC, 1, 0x0000, 0, 0),
... ... @@ -489,6 +495,7 @@
489 495 MX6_PAD_ENET2_TX_CLK__GPIO2_IO14 = IOMUX_PAD(0x0388, 0x00FC, 5, 0x0000, 0, 0),
490 496 MX6_PAD_ENET2_TX_CLK__KPP_ROW07 = IOMUX_PAD(0x0388, 0x00FC, 6, 0x0000, 0, 0),
491 497 MX6_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID = IOMUX_PAD(0x0388, 0x00FC, 8, 0x04BC, 1, 0),
  498 + MX6_PAD_ENET2_TX_CLK__EPDC_SDDO14 = IOMUX_PAD(0x0388, 0x00FC, 9, 0x0000, 0, 0),
492 499  
493 500 MX6_PAD_ENET2_RX_ER__ENET2_RX_ER = IOMUX_PAD(0x038C, 0x0100, 0, 0x0000, 0, 0),
494 501 MX6_PAD_ENET2_RX_ER__UART8_DCE_RTS = IOMUX_PAD(0x038C, 0x0100, 1, 0x0658, 1, 0),
... ... @@ -499,6 +506,7 @@
499 506 MX6_PAD_ENET2_RX_ER__GPIO2_IO15 = IOMUX_PAD(0x038C, 0x0100, 5, 0x0000, 0, 0),
500 507 MX6_PAD_ENET2_RX_ER__KPP_COL07 = IOMUX_PAD(0x038C, 0x0100, 6, 0x0000, 0, 0),
501 508 MX6_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY = IOMUX_PAD(0x038C, 0x0100, 8, 0x0000, 0, 0),
  509 + MX6_PAD_ENET2_RX_ER__EPDC_SDDO15 = IOMUX_PAD(0x038C, 0x0100, 9, 0x0000, 0, 0),
502 510  
503 511 MX6_PAD_LCD_CLK__LCDIF_CLK = IOMUX_PAD(0x0390, 0x0104, 0, 0x0000, 0, 0),
504 512 MX6_PAD_LCD_CLK__LCDIF_WR_RWN = IOMUX_PAD(0x0390, 0x0104, 1, 0x0000, 0, 0),
... ... @@ -508,6 +516,7 @@
508 516 MX6_PAD_LCD_CLK__EIM_CS2_B = IOMUX_PAD(0x0390, 0x0104, 4, 0x0000, 0, 0),
509 517 MX6_PAD_LCD_CLK__GPIO3_IO00 = IOMUX_PAD(0x0390, 0x0104, 5, 0x0000, 0, 0),
510 518 MX6_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x0390, 0x0104, 8, 0x0000, 0, 0),
  519 + MX6_PAD_LCD_CLK__EPDC_SDCLK = IOMUX_PAD(0x0390, 0x0104, 9, 0x0000, 0, 0),
511 520  
512 521 MX6_PAD_LCD_ENABLE__LCDIF_ENABLE = IOMUX_PAD(0x0394, 0x0108, 0, 0x0000, 0, 0),
513 522 MX6_PAD_LCD_ENABLE__LCDIF_RD_E = IOMUX_PAD(0x0394, 0x0108, 1, 0x0000, 0, 0),
... ... @@ -517,6 +526,7 @@
517 526 MX6_PAD_LCD_ENABLE__EIM_CS3_B = IOMUX_PAD(0x0394, 0x0108, 4, 0x0000, 0, 0),
518 527 MX6_PAD_LCD_ENABLE__GPIO3_IO01 = IOMUX_PAD(0x0394, 0x0108, 5, 0x0000, 0, 0),
519 528 MX6_PAD_LCD_ENABLE__ECSPI2_RDY = IOMUX_PAD(0x0394, 0x0108, 8, 0x0000, 0, 0),
  529 + MX6_PAD_LCD_ENABLE__EPDC_SDLE = IOMUX_PAD(0x0394, 0x0108, 9, 0x0000, 0, 0),
520 530  
521 531 MX6_PAD_LCD_HSYNC__LCDIF_HSYNC = IOMUX_PAD(0x0398, 0x010C, 0, 0x05DC, 0, 0),
522 532 MX6_PAD_LCD_HSYNC__LCDIF_RS = IOMUX_PAD(0x0398, 0x010C, 1, 0x0000, 0, 0),
... ... @@ -526,6 +536,7 @@
526 536 MX6_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB = IOMUX_PAD(0x0398, 0x010C, 4, 0x0000, 0, 0),
527 537 MX6_PAD_LCD_HSYNC__GPIO3_IO02 = IOMUX_PAD(0x0398, 0x010C, 5, 0x0000, 0, 0),
528 538 MX6_PAD_LCD_HSYNC__ECSPI2_SS1 = IOMUX_PAD(0x0398, 0x010C, 8, 0x0000, 0, 0),
  539 + MX6_PAD_LCD_HSYNC__EPDC_SDOE = IOMUX_PAD(0x0398, 0x010C, 9, 0x0000, 0, 0),
529 540  
530 541 MX6_PAD_LCD_VSYNC__LCDIF_VSYNC = IOMUX_PAD(0x039C, 0x0110, 0, 0x0000, 0, 0),
531 542 MX6_PAD_LCD_VSYNC__LCDIF_BUSY = IOMUX_PAD(0x039C, 0x0110, 1, 0x05DC, 1, 0),
... ... @@ -535,6 +546,7 @@
535 546 MX6_PAD_LCD_VSYNC__WDOG2_WDOG_B = IOMUX_PAD(0x039C, 0x0110, 4, 0x0000, 0, 0),
536 547 MX6_PAD_LCD_VSYNC__GPIO3_IO03 = IOMUX_PAD(0x039C, 0x0110, 5, 0x0000, 0, 0),
537 548 MX6_PAD_LCD_VSYNC__ECSPI2_SS2 = IOMUX_PAD(0x039C, 0x0110, 8, 0x0000, 0, 0),
  549 + MX6_PAD_LCD_VSYNC__EPDC_SDCE0 = IOMUX_PAD(0x039C, 0x0110, 9, 0x0000, 0, 0),
538 550  
539 551 MX6_PAD_LCD_RESET__LCDIF_RESET = IOMUX_PAD(0x03A0, 0x0114, 0, 0x0000, 0, 0),
540 552 MX6_PAD_LCD_RESET__LCDIF_CS = IOMUX_PAD(0x03A0, 0x0114, 1, 0x0000, 0, 0),
... ... @@ -543,6 +555,7 @@
543 555 MX6_PAD_LCD_RESET__WDOG1_WDOG_ANY = IOMUX_PAD(0x03A0, 0x0114, 4, 0x0000, 0, 0),
544 556 MX6_PAD_LCD_RESET__GPIO3_IO04 = IOMUX_PAD(0x03A0, 0x0114, 5, 0x0000, 0, 0),
545 557 MX6_PAD_LCD_RESET__ECSPI2_SS3 = IOMUX_PAD(0x03A0, 0x0114, 8, 0x0000, 0, 0),
  558 + MX6_PAD_LCD_RESET__EPDC_GDOE = IOMUX_PAD(0x03A0, 0x0114, 9, 0x0000, 0, 0),
546 559  
547 560 MX6_PAD_LCD_DATA00__LCDIF_DATA00 = IOMUX_PAD(0x03A4, 0x0118, 0, 0x0000, 0, 0),
548 561 MX6_PAD_LCD_DATA00__PWM1_OUT = IOMUX_PAD(0x03A4, 0x0118, 1, 0x0000, 0, 0),
... ... @@ -551,6 +564,7 @@
551 564 MX6_PAD_LCD_DATA00__GPIO3_IO05 = IOMUX_PAD(0x03A4, 0x0118, 5, 0x0000, 0, 0),
552 565 MX6_PAD_LCD_DATA00__SRC_BT_CFG00 = IOMUX_PAD(0x03A4, 0x0118, 6, 0x0000, 0, 0),
553 566 MX6_PAD_LCD_DATA00__SAI1_MCLK = IOMUX_PAD(0x03A4, 0x0118, 8, 0x05E0, 1, 0),
  567 + MX6_PAD_LCD_DATA00__EPDC_SDDO00 = IOMUX_PAD(0x03A4, 0x0118, 9, 0x0000, 0, 0),
554 568  
555 569 MX6_PAD_LCD_DATA01__LCDIF_DATA01 = IOMUX_PAD(0x03A8, 0x011C, 0, 0x0000, 0, 0),
556 570 MX6_PAD_LCD_DATA01__PWM2_OUT = IOMUX_PAD(0x03A8, 0x011C, 1, 0x0000, 0, 0),
... ... @@ -559,6 +573,7 @@
559 573 MX6_PAD_LCD_DATA01__GPIO3_IO06 = IOMUX_PAD(0x03A8, 0x011C, 5, 0x0000, 0, 0),
560 574 MX6_PAD_LCD_DATA01__SRC_BT_CFG01 = IOMUX_PAD(0x03A8, 0x011C, 6, 0x0000, 0, 0),
561 575 MX6_PAD_LCD_DATA01__SAI1_TX_SYNC = IOMUX_PAD(0x03A8, 0x011C, 8, 0x05EC, 0, 0),
  576 + MX6_PAD_LCD_DATA01__EPDC_SDDO01 = IOMUX_PAD(0x03A8, 0x011C, 9, 0x0000, 0, 0),
562 577  
563 578 MX6_PAD_LCD_DATA02__LCDIF_DATA02 = IOMUX_PAD(0x03AC, 0x0120, 0, 0x0000, 0, 0),
564 579 MX6_PAD_LCD_DATA02__PWM3_OUT = IOMUX_PAD(0x03AC, 0x0120, 1, 0x0000, 0, 0),
... ... @@ -567,6 +582,7 @@
567 582 MX6_PAD_LCD_DATA02__GPIO3_IO07 = IOMUX_PAD(0x03AC, 0x0120, 5, 0x0000, 0, 0),
568 583 MX6_PAD_LCD_DATA02__SRC_BT_CFG02 = IOMUX_PAD(0x03AC, 0x0120, 6, 0x0000, 0, 0),
569 584 MX6_PAD_LCD_DATA02__SAI1_TX_BCLK = IOMUX_PAD(0x03AC, 0x0120, 8, 0x05E8, 0, 0),
  585 + MX6_PAD_LCD_DATA02__EPDC_SDDO02 = IOMUX_PAD(0x03AC, 0x0120, 9, 0x0000, 0, 0),
570 586  
571 587 MX6_PAD_LCD_DATA03__LCDIF_DATA03 = IOMUX_PAD(0x03B0, 0x0124, 0, 0x0000, 0, 0),
572 588 MX6_PAD_LCD_DATA03__PWM4_OUT = IOMUX_PAD(0x03B0, 0x0124, 1, 0x0000, 0, 0),
... ... @@ -575,6 +591,7 @@
575 591 MX6_PAD_LCD_DATA03__GPIO3_IO08 = IOMUX_PAD(0x03B0, 0x0124, 5, 0x0000, 0, 0),
576 592 MX6_PAD_LCD_DATA03__SRC_BT_CFG03 = IOMUX_PAD(0x03B0, 0x0124, 6, 0x0000, 0, 0),
577 593 MX6_PAD_LCD_DATA03__SAI1_RX_DATA = IOMUX_PAD(0x03B0, 0x0124, 8, 0x05E4, 0, 0),
  594 + MX6_PAD_LCD_DATA03__EPDC_SDDO03 = IOMUX_PAD(0x03B0, 0x0124, 9, 0x0000, 0, 0),
578 595  
579 596 MX6_PAD_LCD_DATA04__LCDIF_DATA04 = IOMUX_PAD(0x03B4, 0x0128, 0, 0x0000, 0, 0),
580 597 MX6_PAD_LCD_DATA04__UART8_DCE_CTS = IOMUX_PAD(0x03B4, 0x0128, 1, 0x0000, 0, 0),
... ... @@ -584,6 +601,7 @@
584 601 MX6_PAD_LCD_DATA04__GPIO3_IO09 = IOMUX_PAD(0x03B4, 0x0128, 5, 0x0000, 0, 0),
585 602 MX6_PAD_LCD_DATA04__SRC_BT_CFG04 = IOMUX_PAD(0x03B4, 0x0128, 6, 0x0000, 0, 0),
586 603 MX6_PAD_LCD_DATA04__SAI1_TX_DATA = IOMUX_PAD(0x03B4, 0x0128, 8, 0x0000, 0, 0),
  604 + MX6_PAD_LCD_DATA04__EPDC_SDDO04 = IOMUX_PAD(0x03B4, 0x0128, 9, 0x0000, 0, 0),
587 605  
588 606 MX6_PAD_LCD_DATA05__LCDIF_DATA05 = IOMUX_PAD(0x03B8, 0x012C, 0, 0x0000, 0, 0),
589 607 MX6_PAD_LCD_DATA05__UART8_DCE_RTS = IOMUX_PAD(0x03B8, 0x012C, 1, 0x0658, 3, 0),
... ... @@ -593,6 +611,7 @@
593 611 MX6_PAD_LCD_DATA05__GPIO3_IO10 = IOMUX_PAD(0x03B8, 0x012C, 5, 0x0000, 0, 0),
594 612 MX6_PAD_LCD_DATA05__SRC_BT_CFG05 = IOMUX_PAD(0x03B8, 0x012C, 6, 0x0000, 0, 0),
595 613 MX6_PAD_LCD_DATA05__ECSPI1_SS1 = IOMUX_PAD(0x03B8, 0x012C, 8, 0x0000, 0, 0),
  614 + MX6_PAD_LCD_DATA05__EPDC_SDDO05 = IOMUX_PAD(0x03B8, 0x012C, 9, 0x0000, 0, 0),
596 615  
597 616 MX6_PAD_LCD_DATA06__LCDIF_DATA06 = IOMUX_PAD(0x03BC, 0x0130, 0, 0x0000, 0, 0),
598 617 MX6_PAD_LCD_DATA06__UART7_DCE_CTS = IOMUX_PAD(0x03BC, 0x0130, 1, 0x0000, 0, 0),
... ... @@ -602,6 +621,7 @@
602 621 MX6_PAD_LCD_DATA06__GPIO3_IO11 = IOMUX_PAD(0x03BC, 0x0130, 5, 0x0000, 0, 0),
603 622 MX6_PAD_LCD_DATA06__SRC_BT_CFG06 = IOMUX_PAD(0x03BC, 0x0130, 6, 0x0000, 0, 0),
604 623 MX6_PAD_LCD_DATA06__ECSPI1_SS2 = IOMUX_PAD(0x03BC, 0x0130, 8, 0x0000, 0, 0),
  624 + MX6_PAD_LCD_DATA06__EPDC_SDDO06 = IOMUX_PAD(0x03BC, 0x0130, 9, 0x0000, 0, 0),
605 625  
606 626 MX6_PAD_LCD_DATA07__LCDIF_DATA07 = IOMUX_PAD(0x03C0, 0x0134, 0, 0x0000, 0, 0),
607 627 MX6_PAD_LCD_DATA07__UART7_DCE_RTS = IOMUX_PAD(0x03C0, 0x0134, 1, 0x0650, 3, 0),
... ... @@ -611,6 +631,7 @@
611 631 MX6_PAD_LCD_DATA07__GPIO3_IO12 = IOMUX_PAD(0x03C0, 0x0134, 5, 0x0000, 0, 0),
612 632 MX6_PAD_LCD_DATA07__SRC_BT_CFG07 = IOMUX_PAD(0x03C0, 0x0134, 6, 0x0000, 0, 0),
613 633 MX6_PAD_LCD_DATA07__ECSPI1_SS3 = IOMUX_PAD(0x03C0, 0x0134, 8, 0x0000, 0, 0),
  634 + MX6_PAD_LCD_DATA07__EPDC_SDDO07 = IOMUX_PAD(0x03C0, 0x0134, 9, 0x0000, 0, 0),
614 635  
615 636 MX6_PAD_LCD_DATA08__LCDIF_DATA08 = IOMUX_PAD(0x03C4, 0x0138, 0, 0x0000, 0, 0),
616 637 MX6_PAD_LCD_DATA08__SPDIF_IN = IOMUX_PAD(0x03C4, 0x0138, 1, 0x0618, 2, 0),
... ... @@ -667,6 +688,7 @@
667 688 MX6_PAD_LCD_DATA14__GPIO3_IO19 = IOMUX_PAD(0x03DC, 0x0150, 5, 0x0000, 0, 0),
668 689 MX6_PAD_LCD_DATA14__SRC_BT_CFG14 = IOMUX_PAD(0x03DC, 0x0150, 6, 0x0000, 0, 0),
669 690 MX6_PAD_LCD_DATA14__USDHC2_DATA4 = IOMUX_PAD(0x03DC, 0x0150, 8, 0x068C, 0, 0),
  691 + MX6_PAD_LCD_DATA14__EPDC_SDSHR = IOMUX_PAD(0x03DC, 0x0150, 9, 0x0000, 0, 0),
670 692  
671 693 MX6_PAD_LCD_DATA15__LCDIF_DATA15 = IOMUX_PAD(0x03E0, 0x0154, 0, 0x0000, 0, 0),
672 694 MX6_PAD_LCD_DATA15__SAI3_TX_DATA = IOMUX_PAD(0x03E0, 0x0154, 1, 0x0000, 0, 0),
... ... @@ -675,6 +697,7 @@
675 697 MX6_PAD_LCD_DATA15__GPIO3_IO20 = IOMUX_PAD(0x03E0, 0x0154, 5, 0x0000, 0, 0),
676 698 MX6_PAD_LCD_DATA15__SRC_BT_CFG15 = IOMUX_PAD(0x03E0, 0x0154, 6, 0x0000, 0, 0),
677 699 MX6_PAD_LCD_DATA15__USDHC2_DATA5 = IOMUX_PAD(0x03E0, 0x0154, 8, 0x0690, 0, 0),
  700 + MX6_PAD_LCD_DATA15__EPDC_GDRL = IOMUX_PAD(0x03E0, 0x0154, 9, 0x0000, 0, 0),
678 701  
679 702 MX6_PAD_LCD_DATA16__LCDIF_DATA16 = IOMUX_PAD(0x03E4, 0x0158, 0, 0x0000, 0, 0),
680 703 MX6_PAD_LCD_DATA16__UART7_DCE_TX = IOMUX_PAD(0x03E4, 0x0158, 1, 0x0000, 0, 0),
... ... @@ -684,6 +707,7 @@
684 707 MX6_PAD_LCD_DATA16__GPIO3_IO21 = IOMUX_PAD(0x03E4, 0x0158, 5, 0x0000, 0, 0),
685 708 MX6_PAD_LCD_DATA16__SRC_BT_CFG24 = IOMUX_PAD(0x03E4, 0x0158, 6, 0x0000, 0, 0),
686 709 MX6_PAD_LCD_DATA16__USDHC2_DATA6 = IOMUX_PAD(0x03E4, 0x0158, 8, 0x0694, 0, 0),
  710 + MX6_PAD_LCD_DATA16__EPDC_GDCLK = IOMUX_PAD(0x03E4, 0x0158, 9, 0x0000, 0, 0),
687 711  
688 712 MX6_PAD_LCD_DATA17__LCDIF_DATA17 = IOMUX_PAD(0x03E8, 0x015C, 0, 0x0000, 0, 0),
689 713 MX6_PAD_LCD_DATA17__UART7_DCE_RX = IOMUX_PAD(0x03E8, 0x015C, 1, 0x0654, 3, 0),
... ... @@ -693,6 +717,7 @@
693 717 MX6_PAD_LCD_DATA17__GPIO3_IO22 = IOMUX_PAD(0x03E8, 0x015C, 5, 0x0000, 0, 0),
694 718 MX6_PAD_LCD_DATA17__SRC_BT_CFG25 = IOMUX_PAD(0x03E8, 0x015C, 6, 0x0000, 0, 0),
695 719 MX6_PAD_LCD_DATA17__USDHC2_DATA7 = IOMUX_PAD(0x03E8, 0x015C, 8, 0x0698, 0, 0),
  720 + MX6_PAD_LCD_DATA17__EPDC_GDSP = IOMUX_PAD(0x03E8, 0x015C, 9, 0x0000, 0, 0),
696 721  
697 722 MX6_PAD_LCD_DATA18__LCDIF_DATA18 = IOMUX_PAD(0x03EC, 0x0160, 0, 0x0000, 0, 0),
698 723 MX6_PAD_LCD_DATA18__PWM5_OUT = IOMUX_PAD(0x03EC, 0x0160, 1, 0x0000, 0, 0),
... ... @@ -731,6 +756,7 @@
731 756 MX6_PAD_LCD_DATA21__GPIO3_IO26 = IOMUX_PAD(0x03F8, 0x016C, 5, 0x0000, 0, 0),
732 757 MX6_PAD_LCD_DATA21__SRC_BT_CFG29 = IOMUX_PAD(0x03F8, 0x016C, 6, 0x0000, 0, 0),
733 758 MX6_PAD_LCD_DATA21__USDHC2_DATA1 = IOMUX_PAD(0x03F8, 0x016C, 8, 0x0680, 1, 0),
  759 + MX6_PAD_LCD_DATA21__EPDC_SDCE1 = IOMUX_PAD(0x03F8, 0x016C, 9, 0x0000, 0, 0),
734 760  
735 761 MX6_PAD_LCD_DATA22__LCDIF_DATA22 = IOMUX_PAD(0x03FC, 0x0170, 0, 0x0000, 0, 0),
736 762 MX6_PAD_LCD_DATA22__MQS_RIGHT = IOMUX_PAD(0x03FC, 0x0170, 1, 0x0000, 0, 0),
board/freescale/mx6ull_ddr3_arm2/mx6ull_ddr3_arm2.c
Diff comments   View file @ bcdbe24
... ... @@ -29,6 +29,10 @@
29 29 #include "../common/pfuze.h"
30 30 #include <usb.h>
31 31 #include <usb/ehci-fsl.h>
  32 +#if defined(CONFIG_MXC_EPDC)
  33 +#include <lcd.h>
  34 +#include <mxc_epdc_fb.h>
  35 +#endif
32 36 #include <asm/imx-common/video.h>
33 37  
34 38 DECLARE_GLOBAL_DATA_PTR;
... ... @@ -80,6 +84,8 @@
80 84 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
81 85 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
82 86  
  87 +#define EPDC_PAD_CTRL 0x010b1
  88 +
83 89 #ifdef CONFIG_SYS_I2C_MXC
84 90 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
85 91 /* I2C1 for PMIC and EEPROM */
... ... @@ -546,6 +552,216 @@
546 552 size_t display_count = ARRAY_SIZE(displays);
547 553 #endif
548 554  
  555 +#ifdef CONFIG_MXC_EPDC
  556 +static iomux_v3_cfg_t const epdc_enable_pads[] = {
  557 + MX6_PAD_ENET2_RX_DATA0__EPDC_SDDO08 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  558 + MX6_PAD_ENET2_RX_DATA1__EPDC_SDDO09 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  559 + MX6_PAD_ENET2_RX_EN__EPDC_SDDO10 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  560 + MX6_PAD_ENET2_TX_DATA0__EPDC_SDDO11 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  561 + MX6_PAD_ENET2_TX_DATA1__EPDC_SDDO12 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  562 + MX6_PAD_ENET2_TX_EN__EPDC_SDDO13 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  563 + MX6_PAD_ENET2_TX_CLK__EPDC_SDDO14 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  564 + MX6_PAD_ENET2_RX_ER__EPDC_SDDO15 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  565 + MX6_PAD_LCD_CLK__EPDC_SDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  566 + MX6_PAD_LCD_ENABLE__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  567 + MX6_PAD_LCD_HSYNC__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  568 + MX6_PAD_LCD_VSYNC__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  569 + MX6_PAD_LCD_DATA00__EPDC_SDDO00 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  570 + MX6_PAD_LCD_DATA01__EPDC_SDDO01 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  571 + MX6_PAD_LCD_DATA02__EPDC_SDDO02 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  572 + MX6_PAD_LCD_DATA03__EPDC_SDDO03 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  573 + MX6_PAD_LCD_DATA04__EPDC_SDDO04 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  574 + MX6_PAD_LCD_DATA05__EPDC_SDDO05 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  575 + MX6_PAD_LCD_DATA06__EPDC_SDDO06 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  576 + MX6_PAD_LCD_DATA07__EPDC_SDDO07 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  577 + MX6_PAD_LCD_DATA14__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  578 + MX6_PAD_LCD_DATA15__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  579 + MX6_PAD_LCD_DATA16__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  580 + MX6_PAD_LCD_DATA17__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  581 + MX6_PAD_LCD_RESET__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  582 +};
  583 +
  584 +static iomux_v3_cfg_t const epdc_disable_pads[] = {
  585 + MX6_PAD_ENET2_RX_DATA0__GPIO2_IO08,
  586 + MX6_PAD_ENET2_RX_DATA1__GPIO2_IO09,
  587 + MX6_PAD_ENET2_RX_EN__GPIO2_IO10,
  588 + MX6_PAD_ENET2_TX_DATA0__GPIO2_IO11,
  589 + MX6_PAD_ENET2_TX_DATA1__GPIO2_IO12,
  590 + MX6_PAD_ENET2_TX_EN__GPIO2_IO13,
  591 + MX6_PAD_ENET2_TX_CLK__GPIO2_IO14,
  592 + MX6_PAD_ENET2_RX_ER__GPIO2_IO15,
  593 + MX6_PAD_LCD_CLK__GPIO3_IO00,
  594 + MX6_PAD_LCD_ENABLE__GPIO3_IO01,
  595 + MX6_PAD_LCD_HSYNC__GPIO3_IO02,
  596 + MX6_PAD_LCD_VSYNC__GPIO3_IO03,
  597 + MX6_PAD_LCD_DATA00__GPIO3_IO05,
  598 + MX6_PAD_LCD_DATA01__GPIO3_IO06,
  599 + MX6_PAD_LCD_DATA02__GPIO3_IO07,
  600 + MX6_PAD_LCD_DATA03__GPIO3_IO08,
  601 + MX6_PAD_LCD_DATA04__GPIO3_IO09,
  602 + MX6_PAD_LCD_DATA05__GPIO3_IO10,
  603 + MX6_PAD_LCD_DATA06__GPIO3_IO11,
  604 + MX6_PAD_LCD_DATA07__GPIO3_IO12,
  605 + MX6_PAD_LCD_DATA14__GPIO3_IO19,
  606 + MX6_PAD_LCD_DATA15__GPIO3_IO20,
  607 + MX6_PAD_LCD_DATA16__GPIO3_IO21,
  608 + MX6_PAD_LCD_DATA17__GPIO3_IO22,
  609 + MX6_PAD_LCD_RESET__GPIO3_IO04,
  610 +};
  611 +
  612 +vidinfo_t panel_info = {
  613 + .vl_refresh = 85,
  614 + .vl_col = 1024,
  615 + .vl_row = 758,
  616 + .vl_pixclock = 40000000,
  617 + .vl_left_margin = 12,
  618 + .vl_right_margin = 76,
  619 + .vl_upper_margin = 4,
  620 + .vl_lower_margin = 5,
  621 + .vl_hsync = 12,
  622 + .vl_vsync = 2,
  623 + .vl_sync = 0,
  624 + .vl_mode = 0,
  625 + .vl_flag = 0,
  626 + .vl_bpix = 3,
  627 + .cmap = 0,
  628 +};
  629 +
  630 +struct epdc_timing_params panel_timings = {
  631 + .vscan_holdoff = 4,
  632 + .sdoed_width = 10,
  633 + .sdoed_delay = 20,
  634 + .sdoez_width = 10,
  635 + .sdoez_delay = 20,
  636 + .gdclk_hp_offs = 524,
  637 + .gdsp_offs = 327,
  638 + .gdoe_offs = 0,
  639 + .gdclk_offs = 19,
  640 + .num_ce = 1,
  641 +};
  642 +
  643 +static void setup_epdc_power(void)
  644 +{
  645 + /* Setup epdc voltage */
  646 +
  647 + /* EPDC_PWRSTAT - GPIO3[16] for PWR_GOOD status */
  648 + imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA11__GPIO3_IO16 |
  649 + MUX_PAD_CTRL(EPDC_PAD_CTRL));
  650 + gpio_direction_input(IMX_GPIO_NR(3, 16));
  651 +
  652 + /* EPDC_VCOM0 - GPIO3[24] for VCOM control */
  653 + imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA19__GPIO3_IO24 |
  654 + MUX_PAD_CTRL(EPDC_PAD_CTRL));
  655 +
  656 + /* Set as output */
  657 + gpio_direction_output(IMX_GPIO_NR(3, 24), 1);
  658 +
  659 + /* EPDC_PWRWAKEUP - GPIO3[14] for EPD PMIC WAKEUP */
  660 + imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA09__GPIO3_IO14 |
  661 + MUX_PAD_CTRL(EPDC_PAD_CTRL));
  662 + /* Set as output */
  663 + gpio_direction_output(IMX_GPIO_NR(3, 14), 1);
  664 +
  665 + /* EPDC_PWRCTRL0 - GPIO3[17] for EPD PWR CTL0 */
  666 + imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA12__GPIO3_IO17 |
  667 + MUX_PAD_CTRL(EPDC_PAD_CTRL));
  668 + /* Set as output */
  669 + gpio_direction_output(IMX_GPIO_NR(3, 17), 1);
  670 +}
  671 +
  672 +static void epdc_enable_pins(void)
  673 +{
  674 + /* epdc iomux settings */
  675 + imx_iomux_v3_setup_multiple_pads(epdc_enable_pads,
  676 + ARRAY_SIZE(epdc_enable_pads));
  677 +}
  678 +
  679 +static void epdc_disable_pins(void)
  680 +{
  681 + /* Configure MUX settings for EPDC pins to GPIO and drive to 0 */
  682 + imx_iomux_v3_setup_multiple_pads(epdc_disable_pads,
  683 + ARRAY_SIZE(epdc_disable_pads));
  684 +}
  685 +
  686 +static void setup_epdc(void)
  687 +{
  688 + /*** epdc Maxim PMIC settings ***/
  689 +
  690 + /* EPDC_PWRSTAT - GPIO3[16] for PWR_GOOD status */
  691 + imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA11__GPIO3_IO16 |
  692 + MUX_PAD_CTRL(EPDC_PAD_CTRL));
  693 +
  694 + /* EPDC_VCOM0 - GPIO3[24] for VCOM control */
  695 + imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA19__GPIO3_IO24 |
  696 + MUX_PAD_CTRL(EPDC_PAD_CTRL));
  697 +
  698 + /* EPDC_PWRWAKEUP - GPIO3[14] for EPD PMIC WAKEUP */
  699 + imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA09__GPIO3_IO14 |
  700 + MUX_PAD_CTRL(EPDC_PAD_CTRL));
  701 +
  702 + /* EPDC_PWRCTRL0 - GPIO3[17] for EPD PWR CTL0 */
  703 + imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA12__GPIO3_IO17 |
  704 + MUX_PAD_CTRL(EPDC_PAD_CTRL));
  705 +
  706 + /* Set pixel clock rates for EPDC in clock.c */
  707 +
  708 + panel_info.epdc_data.wv_modes.mode_init = 0;
  709 + panel_info.epdc_data.wv_modes.mode_du = 1;
  710 + panel_info.epdc_data.wv_modes.mode_gc4 = 3;
  711 + panel_info.epdc_data.wv_modes.mode_gc8 = 2;
  712 + panel_info.epdc_data.wv_modes.mode_gc16 = 2;
  713 + panel_info.epdc_data.wv_modes.mode_gc32 = 2;
  714 +
  715 + panel_info.epdc_data.epdc_timings = panel_timings;
  716 +
  717 + setup_epdc_power();
  718 +}
  719 +
  720 +void epdc_power_on(void)
  721 +{
  722 + unsigned int reg;
  723 + struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO3_BASE_ADDR;
  724 +
  725 + /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
  726 + gpio_set_value(IMX_GPIO_NR(3, 17), 1);
  727 + udelay(1000);
  728 +
  729 + /* Enable epdc signal pin */
  730 + epdc_enable_pins();
  731 +
  732 + /* Set PMIC Wakeup to high - enable Display power */
  733 + gpio_set_value(IMX_GPIO_NR(3, 14), 1);
  734 +
  735 + /* Wait for PWRGOOD == 1 */
  736 + while (1) {
  737 + reg = readl(&gpio_regs->gpio_psr);
  738 + if (!(reg & (1 << 16)))
  739 + break;
  740 +
  741 + udelay(100);
  742 + }
  743 +
  744 + /* Enable VCOM */
  745 + gpio_set_value(IMX_GPIO_NR(3, 24), 1);
  746 +
  747 + udelay(500);
  748 +}
  749 +
  750 +void epdc_power_off(void)
  751 +{
  752 + /* Set PMIC Wakeup to low - disable Display power */
  753 + gpio_set_value(IMX_GPIO_NR(3, 14), 0);
  754 +
  755 + /* Disable VCOM */
  756 + gpio_set_value(IMX_GPIO_NR(3, 24), 0);
  757 +
  758 + epdc_disable_pins();
  759 +
  760 + /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
  761 + gpio_set_value(IMX_GPIO_NR(3, 17), 0);
  762 +}
  763 +#endif
  764 +
549 765 #ifdef CONFIG_FEC_MXC
550 766 int board_eth_init(bd_t *bis)
551 767 {
... ... @@ -751,6 +967,11 @@
751 967  
752 968 #ifdef CONFIG_SYS_USE_QSPI
753 969 board_qspi_init();
  970 +#endif
  971 +
  972 +#ifdef CONFIG_MXC_EPDC
  973 + enable_epdc_clock();
  974 + setup_epdc();
754 975 #endif
755 976  
756 977 return 0;
configs/mx6ull_14x14_ddr3_arm2_epdc_defconfig
Diff comments   View file @ bcdbe24
  1 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ull_ddr3_arm2/imximage.cfg,MXC_EPDC"
  2 +CONFIG_ARM=y
  3 +CONFIG_ARCH_MX6=y
  4 +CONFIG_TARGET_MX6ULL_DDR3_ARM2=y
  5 +CONFIG_CMD_GPIO=y
include/configs/mx6ull_ddr3_arm2.h
Diff comments   View file @ bcdbe24
... ... @@ -87,5 +87,44 @@
87 87 #define CONFIG_FEC_DMA_MINALIGN 64
88 88 #endif
89 89  
  90 +#ifdef CONFIG_VIDEO
  91 +#define CONFIG_CFB_CONSOLE
  92 +#define CONFIG_VIDEO_MXS
  93 +#define CONFIG_VIDEO_LOGO
  94 +#define CONFIG_VIDEO_SW_CURSOR
  95 +#define CONFIG_VGA_AS_SINGLE_DEVICE
  96 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV
  97 +#define CONFIG_SPLASH_SCREEN
  98 +#define CONFIG_SPLASH_SCREEN_ALIGN
  99 +#define CONFIG_CMD_BMP
  100 +#define CONFIG_BMP_16BPP
  101 +#define CONFIG_VIDEO_BMP_RLE8
  102 +#define CONFIG_VIDEO_BMP_LOGO
  103 +#define CONFIG_IMX_VIDEO_SKIP
  104 +#endif
  105 +
  106 +/* #define CONFIG_SPLASH_SCREEN*/
  107 +/* #define CONFIG_MXC_EPDC*/
  108 +
  109 +/*
  110 + * SPLASH SCREEN Configs
  111 + */
  112 +#if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_MXC_EPDC)
  113 +/*
  114 + * Framebuffer and LCD
  115 + */
  116 +#define CONFIG_CFB_CONSOLE
  117 +#define CONFIG_CMD_BMP
  118 +#define CONFIG_LCD
  119 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV
  120 +
  121 +#undef LCD_TEST_PATTERN
  122 +/* #define CONFIG_SPLASH_IS_IN_MMC 1 */
  123 +#define LCD_BPP LCD_MONOCHROME
  124 +/* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */
  125 +
  126 +#define CONFIG_WAVEFORM_BUF_SIZE 0x400000
  127 +#endif
  128 +
90 129 #endif
include/mxc_epdc_fb.h
Diff comments   View file @ bcdbe24
... ... @@ -193,7 +193,7 @@
193 193 #define EPDC_PIGEON_16_0 0xC00
194 194 #define EPDC_PIGEON_16_1 0xC10
195 195 #define EPDC_PIGEON_16_2 0xC20
196   -#ifdef CONFIG_MX7
  196 +#if defined(CONFIG_MX7) || defined(CONFIG_MX6ULL)
197 197 #define EPDC_WB_ADDR_TCE 0x010
198 198 #else
199 199 #define EPDC_WB_ADDR_TCE 0xC10